SLLS318D − NOVEMBER 1998 − REVISED NOVEMBER 2007
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D3:21 Data Channel Expansion at up to
178.5 Mbytes/s Throughput
DSuited for SVGA, XGA, or SXGA Display
Data Transmission From Controller to
Display With Very Low EMI
DThree Data Channels and Clock
Low-Voltage Differential Channels In and
21 Data and Clock Low-Voltage TTL
Channels Out
DOperates From a Single 3.3-V Supply
DTolerates 4-kV HBM ESD
DPackaged in Thin Shrink Small-Outline
Package (TSSOP) With 20-Mil Terminal
Pitch
DConsumes Less Than 1 mW When Disabled
DWide Phase-Lock Input Frequency Range
of 31 MHz to 68 MHz
DNo External Components Required for PLL
DInputs Meet or Exceed the Standard
Requirements of ANSI EIA/TIA-644
Standard
DImproved Replacement for the DS90C364
and SN75LVDS86
DImproved Jitter Tolerance
DSee SN65LVDS86A-Q1 Data Sheet for
Information About the Automotive
Qualified Version
description
The SN65LVDS86A/SN75LVDS86A FlatLinkt receiver contains three serial-in 7-bit parallel-out shift registers
and four low-voltage differential signaling (LVDS) line receivers in a single integrated circuit. These functions
allow receipt of synchronous data from a compatible transmitter, such as the SN75LVDS81, ’83, ’84, or ’85, over
four balanced-pair conductors and expansion to 21 bits of single-ended low-voltage LVTTL synchronous data
at a lower transfer rate.
When receiving, the high-speed LVDS data is received and loaded into registers at seven times the LVDS input
clock (CLKIN) rate. The data is then unloaded to a 21-bit-wide LVTTL parallel bus at the CLKIN rate. The
’LVDS86A presents valid data on the falling edge of the output clock (CLKOUT).
The ’ LVDS86A requires only four line-termination resistors for the differential inputs and little or no control. The
data bus appears the same at the input to the transmitter and output of the receiver with the data transmission
transparent to the user(s). The only user intervention is the possible use of the shutdown/clear (SHTDN)
active-low input to inhibit the clock and shut off the LVDS receivers for lower power consumption. A low level
on this signal clears all internal registers to a low level.
The SN75LVDS86A is characterized for operation over ambient free-air temperatures of 0_C to 70_C. The
SN65LVDS86A is characterized for operation over the full Automotive temperature range of −40°C to 125°C.
Copyright 2007, Texas Instruments Incorporated
!"# $"%! &#'
&"! ! $#!! $# (# # #) "#
&& *+' &"! $!#, &# #!#+ !"&#
#, $##'
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
FlatLink is a trademark of Texas Instruments Incorporated.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
D17
D18
GND
D19
D20
NC
LVDSGND
A0M
A0P
A1M
A1P
LVDSVCC
LVDSGND
A2M
A2P
CLKINM
CLKINP
LVDSGND
PLLGND
PLLVCC
PLLGND
SHTDN
CLKOUT
D0
VCC
D16
D15
D14
GND
D13
VCC
D12
D11
D10
GND
D9
VCC
D8
D7
D6
GND
D5
D4
D3
VCC
D2
D1
GND
DGG PACKAGE
(TOP VIEW)
NC − Not connected
SLLS318D − NOVEMBER 1998 − REVISED NOVEMBER 2007
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functional block diagram
Serial In
CLK
Serial-In/Parallel-
Out Shift Register
Serial In
CLK
Serial In
CLK
Control Logic
CLK
Clock In
Clock Generator
SHTDN
CLKINP
A2P
A2M
A1P
A1M
A0P
A0M
CLKOUT
CLKINM
D14
D15
D16
D17
D18
D19
D20
D7
D8
D9
D10
D11
D12
D13
D0
D1
D2
D3
D4
D5
D6
A, B, ...G
Clock Out
A, B, ...G
A, B, ...G
Serial-In/Parallel-
Out Shift Register
Serial-In/Parallel-
Out Shift Register
Input Bus
SLLS318D − NOVEMBER 1998 − REVISED NOVEMBER 2007
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ÇÇ
ÇÇ
CLKOUT
CLKIN
D0
A0
A1
A2
D0−1 D6 D4 D3 D2 D1 D0 D6+1
D7−1 D13 D12 D11 D10 D9 D8 D7 D13+1
D14−1 D20 D19 D18 D17 D16 D15 D14 D20+1
ÉÉÉ
ÉÉÉ
ÉÉ
ÉÉ
ÇÇ
ÇÇ
Current CyclePrevious Cycle Next Cycle
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÉÉÉ
ÉÉÉ
ÇÇ
ÇÇ
ÉÉ
ÉÉ
ÇÇÇ
ÇÇÇ
Dn − 1 Dn Dn + 1
D5
Figure 1. SN65LVDS86A/SN75LVDS86A Load and Shift Timing Sequences
equivalent input and output schematic diagrams
VCC
50 Ω
7 V
SHTDN
VCC
7 V
5 Ω
D Output
INPUT
OUTPUT
VCC
300 kΩ
AnM
7 V 7 V
300 kΩ
AnP
INPUT
100 Ω
100 Ω
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absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC (see Note 1) −0.5 V to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range at any terminal −0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrostatic discharge (see Note 2): All pins (Class 3A) 4 KV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
All pins (Class 2B) 200 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating virtual junction temperature range, TJ−40_C to 150_C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65_C to 150_C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 in) from case for 10 s 260_C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to the GND terminals unless otherwise noted.
2. This rating is measured using MIL-STD-883C Method, 3015.7.
DISSIPATION RATING TABLE
PACKAGE TA ≤ 25°C
POWER RATING DERATING FACTOR‡
ABOVE TA = 25°CTA = 70°C
POWER RATING TA = 125°C
POWER RATING
DGG 1637 mW 13.1 mW/°C1048 mW 327 mW
‡This is the inverse of the junction-to-ambient thermal resistance when board mounted and with no air flow.
recommended operating conditions (see Figure 2)
MIN NOM MAX UNIT
Supply voltage, VCC 3 3.3 3.6 V
High-level input voltage, VIH (SHTDN) 2 V
Low-level input voltage, VIL (SHTDN) 0.8 V
Magnitude differential input voltage, |VID| 0.1 0.6 V
Common-mode input voltage, VIC |VID|
22.4 *
|VID|
2V
Operating free-air temperature, TA
SN75LVDS86A 0 70
°C
Operating free-air temperature, TASN65LVDS86A −40 125 °C
timing requirements
MIN NOM MAX UNIT
Cycle time, input clock, tc§14.7 tc32.4 ns
§Parameter tc is defined as the mean duration of a minimum of 32000 clock cycles.
SLLS318D − NOVEMBER 1998 − REVISED NOVEMBER 2007
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electrical characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
VIT+ Positive-going differential input threshold voltage 100 mV
VIT− Negative-going differential input threshold voltage‡−100 mV
VOH High-level output voltage IOH = −4 mA 2.4 V
VOL Low-level output voltage IOL = 4 mA 0.4 V
Disabled, All inputs to GND 280 µA
Enabled,
AnM = 1.4 V, AnP = 1 V,
tc = 15.38 ns 33 40
ICC Quiescent current (average) Enabled, CL = 8 pF,
Grayscale pattern (see Figure 3),
tc = 15.38 ns 43 mA
Enabled, CL = 8 pF,
Worst-case pattern (see Figure 4)
tc = 15.38 ns 68
IIH High-level input current (SHTDN) VIH = VCC ±20 µA
IIL
Low-level input current (SHTDN)
VIL = 0
SN75LVDS86A ±20
A
IIL Low-level input current (SHTDN)V
IL = 0 SN65LVDS86A ±25 µA
IIInput current A inputs 0 ≤ VI ≤ 2.4 V ±20 µA
IOZ High-impedance output current VO = 0 or VCC ±10 µA
†All typical values are at VCC = 3.3 V, TA = 25°C.
‡The algebraic convention, in which the less-positive (more-negative) limit is designated minimum, is used in this data sheet for the negative-going
input voltage threshold only.
switching characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
tsu Setup time, D0–D20 to CLKOUT↓
CL = 8 pF, See Figure 5
5 ns
thData hold time, CLKOUT↓ to D0–D20 CL = 8 pF, See Figure 5 5 ns
t(RSKM) Receiver input skew margin§ (see Figure 7) tc = 15.38 ns (±0.2%),
|Input clock jitter| < 50 ps¶,550 700 ps
tdDelay time, CLKIN↑ to CLKOUT↓(see Figure 7) VCC = 3.3 V,
tc = 15.38 ns (±0.2%), TA = 25°C3 5 7 ns
ten Enable time, SHTDN to phase lock See Figure 7 1 ms
tdis Disable time, SHTDN to off state See Figure 8 400 ns
ttTransition time, output (10% to 90% tr or tf) (data only) CL = 8 pF 3 ns
ttTransition time, output (10% to 90% tr or tf) (clock only) CL = 8 pF 1.5 ns
twPulse duration, output clock 0.50 tcns
†All typical values are at VCC = 3.3 V, TA = 25°C.
§The parameter t(RSKM) is the timing margin available to allocate to the transmitter and interconnection skews and clock jitter. The value of this
parameter at clock periods other than 15.38 ns can be calculated from tRSKM = tc/14 – 550 ps.
¶|Input clock jitter| is the magnitude of the change in input clock period.
SLLS318D − NOVEMBER 1998 − REVISED NOVEMBER 2007
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PARAMETER MEASUREMENT INFORMATION
VID
AP
AM
VIAM
VIAP
VIC
(VIAP + VIAM)/2
Figure 2. Voltage Definitions
CLKIN/CLKOUT
D0, D6, D12
D1, D7, D13
D2, D8, D14
D3, D9, D15
D18, D19, D20
ALL OTHERS
NOTE A: The 16-grayscale test-pattern test device power consumption for a typical display pattern.
Figure 3. 16-Grayscale Test-Pattern Waveforms
tc
NOTE A: The worst-case test pattern produces nearly the maximum switching frequency for all of the LVTTL outputs.
CLKIN/CLKOUT
Even Dn
Odd Dn
Figure 4. Worst-Case Test-Pattern Waveforms
SLLS318D − NOVEMBER 1998 − REVISED NOVEMBER 2007
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PARAMETER MEASUREMENT INFORMATION
D0−D20
tsu
CLKOUT
th
70% VOH
70% VOH
30% VOH
30% VOH
Figure 5. Setup and Hold Time Waveforms
SLLS318D − NOVEMBER 1998 − REVISED NOVEMBER 2007
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PARAMETER MEASUREMENT INFORMATION
Device
Under
Test
(DUT)
CLKIN
Tektronix
HFS9003/HFS9DG1
Stimulus System
(repeating patterns of
1110111 and 0001000)
Tektronix
Microwave Logic
Multi-BERT-100RX
Word Error Detector
An D0 − D20
CLKOUT
An
CLKIN
t
c
CLKOUT
td
0 V
≈300 mV
≈−300 mV
90%
10%
tr < 1 ns
VOL
VOH
1.4 V
td
ÇÇÇ
ÇÇÇ
ÉÉ
ÉÉ
ÇÇÇ
ÇÇÇ
ÉÉ
ÉÉ
ÉÉÉ
ÉÉÉ
ÇÇ
ÇÇ
ÉÉÉ
ÉÉÉ
ÇÇ
ÇÇ
3
7tct(RSKM)
th1
tsu1
4
7tct(RSKM)
and An
CLKIN
or An
CLKOUT
tW
tW
±
±
(see Note A)
(see Note A)
NOTE A: CLKIN is advanced or delayed with respect to data until errors are observed at the receiver outputs. The advance or delay is then
reduced until there are no data errors observed. The magnitude of the advance or delay is t
(RSKM)
.
Internal Strobing Position
Figure 6. Receiver Input Skew Margin, Setup/Hold Time, and Delay Time Definitions
SLLS318D − NOVEMBER 1998 − REVISED NOVEMBER 2007
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
CLKIN
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ten
SHTDN
An
Dn ValidInvalid
Figure 7. Enable Time Waveforms
CLKIN
CLKOUT
tdis
SHTDN
Figure 8. Disable Time Waveforms
SLLS318D − NOVEMBER 1998 − REVISED NOVEMBER 2007
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
CLOCK FREQUENCY
55
45
40
30
30 40 50 60 70
fclk − Clock Frequency − MHz
VCC = 3 V
VCC = 3.6 V
− Supply Current − mA
ICC
25
35
50
60
80 90
Grayscale Data Pattern
CL = 8 pF
TA = 25°C
VCC = 3.3 V
Figure 9. RMS Grayscale ICC vs Clock Frequency
SLLS318D − NOVEMBER 1998 − REVISED NOVEMBER 2007
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
RED0 RED0
RED1 RED1
RED2 RED2
RED3 RED3
NA RED4
NA RED5
GREEN0 GREEN0
GREEN1 GREEN1
GREEN2 GREEN2
GREEN3 GREEN3
NA GREEN4
NA GREEN5
BLUE0 BLUE0
BLUE1 BLUE1
BLUE2 BLUE2
BLUE3 BLUE3
NA BLUE4
NA BLUE5
H_SYNC H_SYNC
V_SYNC V_SYNC
ENABLE ENABLE
CLOCK CLOCK
12-BIT 18-BIT
Graphics Controller
SN75LVDS86A/
SN65LVDS86A
SN75LVDS84/5
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
CLKOUT
24
26
27
29
30
31
33
34
35
37
39
40
41
43
45
46
47
1
2
4
5
23
100 Ω
8
9
41
40
100 Ω
10
11
39
38
100 Ω
14
15
35
34
100 Ω
16
17
33
32
Cable Flat Panel DisplayHost
Y0M
Y0P
Y1M
Y1P
Y2M
Y2P
CLKOUTM
CLKOUTP
A0M
A0P
A1M
A1P
A2M
A2P
CLKINM
CLKINP
NOTES: A. The four 100-Ω terminating resistors are recommended to be 0603 types.
B. NA - not applicable, these unused inputs should be left open.
Figure 10. 18-Bit Color Host to Flat Panel Display Application
SLLS318D − NOVEMBER 1998 − REVISED NOVEMBER 2007
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
SN75LVDS86A/
SN65LVDS86A
SN75LVDS81/83
100 Ω
8
9
48
47
100 Ω
10
11
46
45
100 Ω
14
15
42
41
16
17
100 Ω
40
39
Cable Flat Panel DisplayHost
Y0M
Y0P
Y1M
Y1P
Y2M
Y2P
CLKOUTM
CLKOUTP
A0M
A0P
A1M
A1P
A2M
A2P
CLKINM
CLKINP
RED0 RED0
RED1 RED1
RED2 RED2
RED3 RED3
NA RED4
NA RED5
GREEN0 GREEN0
GREEN1 GREEN1
GREEN2 GREEN2
GREEN3 GREEN3
NA GREEN4
NA GREEN5
BLUE0 BLUE0
BLUE1 BLUE1
BLUE2 BLUE2
BLUE3 BLUE3
NA BLUE4
NA BLUE5
H_SYNC H_SYNC
V_SYNC V_SYNC
ENABLE ENABLE
CLOCK CLOCK
12-BIT 18-BIT
Graphics Controller
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
CLKOUT
24
26
27
29
30
31
33
34
35
37
39
40
41
43
45
46
47
1
2
4
5
23
38
37
Y3M
Y3P
NOTES: A. The four 100-Ω terminating resistors are recommended to be 0603 types.
B. NA - not applicable, these unused inputs should be left open.
Figure 11. 24-Bit Color Host to 18-Bit Color LCD Panel Display Application
See the FlatLinkt Designer’s Guide (SLLA012) for more application information.
PACKAGE OPTION ADDENDUM
www.ti.com 16-Jan-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
SN65LVDS86AQDGG ACTIVE TSSOP DGG 48 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
SN65LVDS86AQDGGR ACTIVE TSSOP DGG 48 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
SN75LVDS86ADGG ACTIVE TSSOP DGG 48 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
SN75LVDS86ADGGG4 ACTIVE TSSOP DGG 48 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
SN75LVDS86ADGGR ACTIVE TSSOP DGG 48 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
SN75LVDS86ADGGRG4 ACTIVE TSSOP DGG 48 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
PACKAGE OPTION ADDENDUM
www.ti.com 16-Jan-2012
Addendum-Page 2
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN65LVDS86A :
•Automotive: SN65LVDS86A-Q1
NOTE: Qualified Version Definitions:
•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN65LVDS86AQDGGR TSSOP DGG 48 2000 330.0 24.4 8.6 15.8 1.8 12.0 24.0 Q1
SN75LVDS86ADGGR TSSOP DGG 48 2000 330.0 24.4 8.6 15.8 1.8 12.0 24.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN65LVDS86AQDGGR TSSOP DGG 48 2000 367.0 367.0 45.0
SN75LVDS86ADGGR TSSOP DGG 48 2000 367.0 367.0 45.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUAR Y 1998
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
4040078/F 12/97
48 PINS SHOWN
0,25
0,15 NOM
Gage Plane
6,00
6,20 8,30
7,90
0,75
0,50
Seating Plane
25
0,27
0,17
24
A
48
1
1,20 MAX
M
0,08
0,10
0,50
0°–8°
56
14,10
13,90
48
DIM
A MAX
A MIN
PINS **
12,40
12,60
64
17,10
16,90
0,15
0,05
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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