CY62158H MoBL®
8-Mbit (1M words × 8-bit) Static RAM
with Error-Correcting Code (ECC)
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 001-96968 Rev. *E Revised April 4, 2018
8-Mbit (1M wor ds × 8-bit) Static RA M with Err or-Correcting Code (ECC)
Features
■Ultra-low standby power
❐Typical standby current: 5.5 A
❐Maximum standby current: 16 A
■High speed: 45 ns
■Embedded error-correcting code (ECC) for single-bit error
correction[1, 2]
■Operating voltage range: 4.5 V to 5.5 V
■1.0-V data retention
■Transistor-transistor logic (TTL) compatible inputs and outputs
■Available in Pb-free 44-pin TSOP II package
Functional Description
CY62158H is a high-performance CMOS low-power (MoBL)
SRAM device with embedded ECC.
Device is accessed by asserting both chip enable inputs – CE1
as LOW and CE2 as HIGH.
Write to the device is performed by taking Chip Enable 1 (CE1)
LOW and Chip Enable 2 (CE2) HIGH and the Write Enable (WE)
input LOW. Data on the eight I/O pins (I/O0 through I/O7) is then
written into the location specified on the address pins (A0 through
A19).
Read from the device is performed by taking Chip Enable 1 (CE1)
and Output Enable (OE) LOW and Chip Enable 2 (CE2) HIGH
while forcing Write Enable (WE) HIGH. Under these conditions,
the contents of the memory location specified by the address
pins will appear on the I/O pins.
The eight input and output pins (I/O0 through I/O7) are placed in
a high-impedance state when the device is deselected (CE1
HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or a
write operation is in progress (CE1 LOW and CE2 HIGH and WE
LOW). See the Truth Table – CY62158H on page 11 for a
complete description of read and write modes.
Logic Block Diagram – CY62158H
1Mx8
RAMARRAY
ROWDECODER
A1
A2
A3
A4
A5
A6
A7
A8
A9
A0
COLUMN
DECODER
A10
SENSE
AMPLIFIERS
ECCDECODER
A11
A12
A13
A14
A15
A16
A17
A18
A19
ECCENCODER DATAIN
DRIVERS
I/O0‐I/O7
WE
OE
CE2
CE1
Notes
1. This device does not support automatic write-back on error detection.
2. SER FIT Rate <0.1 FIT/Mb. Refer AN88889 for details.
Document Number: 001-96968 Rev. *E Page 2 of 16
CY62158H MoBL®
Contents
Product Portfolio .............................................................. 3
Pin Configurations – CY62158H ......................................3
Maximum Ratings ............................................................. 4
Operating Range ............................................................... 4
DC Electrical Characteristics .......................................... 4
Capacitance ...................................................................... 5
Thermal Resistance .......................................................... 5
AC Test Loads and Waveforms ....................................... 5
Data Retention Characteristics ....................................... 6
Data Retention Waveform ................................................ 6
Switching Characteristics ................................................ 7
Switching Waveforms ...................................................... 8
Truth Table – CY62158H ................................................ 11
Ordering Information ...................................................... 12
Ordering Code Definitions ......................................... 12
Package Diagram ............................................................ 13
Acronyms ........................................................................ 14
Document Conventions ................................................. 14
Units of Measure ....................................................... 14
Document History Page ................................................. 15
Sales, Solutions, and Legal Information ...................... 16
Worldwide Sales and Design Support ....................... 16
Products .................................................................... 16
PSoC® Solutions ...................................................... 16
Cypress Developer Community ................................. 16
Technical Support ..................................................... 16
Document Number: 001-96968 Rev. *E Page 3 of 16
CY62158H MoBL®
Product Portfolio
Product Features and Options (see Pin
Configurations – CY62158H)Range VCC Range
(V)
Speed
(ns)
Power Dissipation
Operating ICC (mA) Standby ISB2 (µA)
f = fmax
Typ[3] Max Typ[3] Max
CY62158H Dual Chip Enable Industrial 4.5 V–5.5 V 45 29 36 5.5 16
Pin Configurations – CY62158H
Figure 1. 44-pin TSOP II Pinout [4]
1
2
3
4
5
6
7
8
9
11
14 31
32
36
35
34
33
37
40
39
38
12
13
41
44
43
42
16
15
29
30
A
5
18
17
20
19
23
28
25
24
22
21
27
26
A
6
A
7
A
4
A
3
A
2
A
1
A
0
A
17
A
18
A
10
A
11
A
12
A
13
A
15
A
16
A
14
OE
CE
2
A
8
CE
1
WE
NC
NC
I/O
0
I/O
1
I/O
2
I/O
3
NC
NC NC
NC
I/O
4
I/O
5
I/O
6
I/O
7
NC
NC
V
CC
V
CC
V
SS
V
SS
A
9
10
A
19
Notes
3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = 5 V (for VCC range of 4.5 V–5.5 V), TA = 25 °C.
4. NC pins are not connected internally to the die and are typically used for address expansion to a higher-density device. Refer to the respective datasheets for pin
configuration.
Document Number: 001-96968 Rev. *E Page 4 of 16
CY62158H MoBL®
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage temperature ............................... –65 °C to + 150 °C
Ambient temperature
with power applied .................................. –55 °C to + 125 °C
Supply voltage to ground potential ..... –0.5 V to VCC + 0.5 V
DC voltage applied to outputs
in High Z state[5] .................................. –0.5 V to VCC + 0.5 V
DC input voltage[5] .............................. –0.5 V to VCC + 0.5 V
Output current into outputs (LOW) ............................. 20 mA
Static discharge voltage
(MIL-STD-883, Method 3015) ................................. >2001 V
Latch-up current ..................................................... >140 mA
Operating Range
Grade Ambient Temperature VCC[6]
Industrial –40 C to +85 C 4.5 V to 5.5 V
DC Electrical Characteristics
Over the Operating Range of –40 C to 85 C
Parameter Description Test Conditions 45 ns Unit
Min Typ[7] Max
VOH Output HIGH
voltage 4.5 V to 5.5 V VCC = Min, IOH = –1.0 mA 2.4 – – V
4.5 V to 5.5 V VCC = Min, IOH = –0.1 mA VCC – 0.4[8] ––
VOL Output LOW
voltage 4.5 V to 5.5 V VCC = Min, IOL = 2.1 mA – – 0.4 V
VIH[5] Input HIGH
voltage 4.5 V to 5.5 V – 2.2 – VCC + 0.5 V
VIL[5] Input LOW
voltage 4.5 V to 5.5 V – –0.5 – 0.8 V
IIX Input leakage current GND < VIN < VCC –1.0 – +1.0 A
IOZ Output leakage current GND < VOUT < VCC, Output disabled –1.0 – +1.0 A
ICC VCC operating supply current VCC = Max, IOUT = 0 mA,
CMOS levels f = 22.22 MHz
(45 ns) – 29.0 36.0 mA
f = 1 MHz – 7.0 9.0
ISB1[9] Automatic power down current –
CMOS inputs;
VCC = 4.5 to 5.5 V
CE1 > VCC – 0.2 V or CE2 < 0.2 V,
VIN > VCC – 0.2 V, VIN < 0.2 V,
f = fmax (address and data only),
f = 0 (OE, and WE), VCC = VCC(max)
– 5.5 16.0 A
ISB2[9] Automatic power down current –
CMOS inputs;
VCC = 4.5 to 5.5 V
CE1 > VCC – 0.2 V or
CE2 < 0.2 V, or
VIN > VCC – 0.2 V or
VIN < 0.2 V,
f = 0, VCC = VCC(max)
25 °C[10] –5.56.5A
40 °C[10] –6.38.0
70 °C[10] – 8.4 12.0
85 °C – 12.0[10] 16.0
Notes
5. VIL(min) = –2.0 V and VIH(max) = VCC + 2 V for pulse durations of less than 20 ns.
6. Full Device AC operation assumes a 100 µs ramp time from 0 to VCC(min) and 200 µs wait time after VCC stabilization.
7. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = 5 V (for VCC range of 4.5 V–5.5 V), TA = 25 °C.
8. This parameter is guaranteed by design and not tested.
9. Chip enables (CE1 and CE2) must be tied to CMOS levels to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating.
10. The ISB2 limits at 25 °C, 40 °C, 70 °C and typical limit at 85 °C are guaranteed by design and not 100% tested.
Document Number: 001-96968 Rev. *E Page 5 of 16
CY62158H MoBL®
Capacitance
Parameter[11] Description Test Conditions Max Unit
CIN Input capacitance TA = 25 °C, f = 1 MHz, VCC = VCC(typ) 10 pF
COUT Output capacitance 10 pF
Thermal Resistance
Parameter[11] Description Test Conditions 44-pin TSOP II Unit
JA Thermal resistance
(junction to ambient) Still air, soldered on a 3 × 4.5 inch, four-layer printed circuit
board 66.93 °C/W
JC Thermal resistance
(junction to case) 13.09 °C/W
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms
V
HIGH
V
CC
OUTPUT
R2
30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10% 90%
10%
Rise Time = 1 V/ns Fall Time = 1 V/ns
OUTPUT V
TH
Equivalent to: THÉVENIN EQUIVALENT
ALL INPUT PULSES
R
TH
R1
Parameters 5.0 V Unit
R1 1800
R2 990
RTH 639
VTH 1.77 V
VHIGH 5.0 V
Note
11. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 001-96968 Rev. *E Page 6 of 16
CY62158H MoBL®
Data Retention Characteristics
Over the Operating Range
Parameter Description Conditions Min Typ[12] Max Unit
VDR VCC for data retention 1.0 – – V
ICCDR[13, 14] Data retention current 1.2 V < VCC < 2.2 V,
CE1 > VCC 0.2 V or CE2 < 0.2 V,
VIN > VCC 0.2 V or VIN < 0.2 V
– 7.0 26.0 A
2.2 V < VCC < 3.6 V or
4.5 V < VCC < 5.5 V,
CE1 > VCC 0.2 V or CE2 < 0.2 V,
VIN > VCC 0.2 V or VIN < 0.2 V
– 5.5 16.0 A
tCDR[15] Chip deselect to data retention
time 0–––
tR[15, 16] Operation recovery time 45 – – ns
Data Retention Waveform
Figure 3. Data Retention Waveform
tCDR tR
VDR=1 .0 V
DATARETENTIONM ODE
VCC(m in) VCC(m in)
VCC
CE2
(or)
CE1
Notes
12. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = 1.8 V (for VCC range of 1.65 V–2.2 V), VCC =3V
(for VCC range of 2.2 V–3.6 V), and VCC = 5 V (for VCC range of 4.5 V–5.5 V), TA = 25 °C.
13. Chip enables (CE1 and CE2) must be tied to CMOS levels to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating.
14. ICCDR is guaranteed only after device is first powered up to VCC(min) and brought down to VDR.
15. These parameters are guaranteed by design.
16. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s.
Document Number: 001-96968 Rev. *E Page 7 of 16
CY62158H MoBL®
Switching Characteristics
Parameter [17] Description 45 ns Unit
Min Max
Read Cycle
tRC Read cycle time 45.0 –ns
tAA Address to data valid –45.0 ns
tOHA Data hold from address change 10.0 –ns
tACE CE1 LOW and CE2 HIGH to data valid / CE LOW to ERR valid –45.0 ns
tDOE OE LOW to data valid / OE LOW to ERR valid –22.0 ns
tLZOE OE LOW to Low Z[18, 19, 20] 5.0 –ns
tHZOE OE HIGH to High Z[18, 19, 20, 21] –18.0 ns
tLZCE CE1 LOW and CE2 HIGH to Low Z[18, 19, 20] 10.0 –ns
tHZCE CE1 HIGH and CE2 LOW to High Z[18, 19, 20, 21] –18.0 ns
tPU CE1 LOW and CE2 HIGH to power-up[20] 0 – ns
tPD CE1 HIGH and CE2 LOW to power-down[20] –45.0 ns
Write Cycle[22, 23]
tWC Write cycle time 45.0 –ns
tSCE CE1 LOW and CE2 HIGH to write end 35.0 –ns
tAW Address setup to write end 35.0 –ns
tHA Address hold from write end 0 – ns
tSA Address setup to write start 0 – ns
tPWE WE pulse width 35.0 –ns
tSD Data setup to write end 25.0 –ns
tHD Data hold from write end 0 – ns
tHZWE WE LOW to High Z[18, 19, 20, 21] –18.0 ns
tLZWE WE HIGH to Low Z[18, 19, 20] 10.0 –ns
Notes
17. Test conditions assume signal transition time (rise/fall) of 3 ns or less, timing reference levels of 1.5 V (for VCC > 3 V) and VCC/2 (for VCC < 3 V), and input pulse levels
of 0 to 3 V (for VCC > 3 V) and 0 to VCC (for VCC < 3V). Test conditions for the read cycle use output loading shown in AC Test Loads and Waveforms section, unless specified
otherwise.
18. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device.
19. Tested initially and after any design or process changes that may affect these parameters.
20. These parameters are guaranteed by design and are not tested.
21. tHZOE, tHZCE, and tHZWE transitions are measured when the outputs enter a high impedance state.
22. The internal write time of the memory is defined by the overlap of WE = VIL, CE1 = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these
signals can terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that terminates the write.
23. The minimum write cycle pulse width for Write cycle No. 2 (WE Controlled, OE Low) should be equal to he sum of tHZWE and tSD.
Document Number: 001-96968 Rev. *E Page 8 of 16
CY62158H MoBL®
Switching Waveforms
Figure 4. Read Cycle No. 1 (Address Transition Controlled)[24, 25]
Figure 5. Read Cycle No. 2 (OE Controlled)[25, 26, 27]
ADDRESS
DATA I/O PREVIOUS DATAOUT
VALID DATAOUT VALID
tRC
tOHA
tAA
tRC
tHZCE
tPD
tACE
tDOE
tLZOE
tLZCE
tPU
HIGH IMPEDANCE DATA
OUT VALID HIGH
IMPEDANCE
ADDRESS
CE
OE
DATA I/O
VCC
SUPPLY
CURRENT
tHZOE
ISB
Notes
24. The device is continuously selected. OE = VIL, CE = VIL.
25. WE is HIGH for read cycle.
26. For all dual chip enable devices, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW,
CE is HIGH.
27. Address valid prior to or coincident with CE LOW transition.
Document Number: 001-96968 Rev. *E Page 9 of 16
CY62158H MoBL®
Figure 6. Write Cycle No. 1 (WE Controlled)[28, 29, 30]
Switching Waveforms (continued)
ADDRESS
CE
WE
D A TA I/O
OE
tWC
tSCE
tAW
tSA tPWE
tHA
tHD
tHZOE tSD
DATAIN V A L ID
Note 31
Notes
28. For all dual chip enable devices, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW,
CE is HIGH.
29. The internal write time of the memory is defined by the overlap of WE = VIL, CE1 = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these
signals can terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that terminates the write.
30. Data I/O is in the high-impedance state if CE = VIH, or OE = VIH.
31. During this period, the I/Os are in output state. Do not apply input signals.
Document Number: 001-96968 Rev. *E Page 10 of 16
CY62158H MoBL®
Figure 7. Write Cycle No. 2 (WE Controlled, OE Low)[32, 33, 34, 35]
Figure 8. Write Cycle No. 3 (CE Controlled)[32, 33, 34]
Switching Waveforms (continued)
Note 36
ADDRESS
CE
WE
DATA I/O
OE
tWC
tSCE
tAW
tSA
tPWE
tHA
tHD
tHZOE tSD
DATA
IN VALID
Note 36
Notes
32. For all dual chip enable devices, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW,
CE is HIGH.
33. The internal write time of the memory is defined by the overlap of WE = VIL, CE1 = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these
signals can terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that terminates the write.
34. Data I/O is in high impedance state if CE = VIH, or OE = VIH.
35. The minimum write cycle pulse width should be equal to the sum of the tHZWE and tSD.
36. During this period I/O are in the output state. Do not apply input signals.
Document Number: 001-96968 Rev. *E Page 11 of 16
CY62158H MoBL®
Truth Table – CY62158H
CE1CE2WE OE I/Os Mode Power
HX
[37] X[37] X[37] High Z Deselect /
Power down Standby (ISB2)
X[37] LX
[37] X[37] High Z Deselect /
Power down
Standby (ISB2)
LHHLData Out
(I/O0–I/O7)
Read Active (ICC)
L H H H High Z Output disabled Active (ICC)
LHLXData In
(I/O0–I/O7)
Write Active (ICC)
Note
37. The ‘X’ (Don’t care) state for the chip enables refer to the logic state (either HIGH or LOW). Intermediate voltage levels on these pins is not permitted.
Document Number: 001-96968 Rev. *E Page 12 of 16
CY62158H MoBL®
Ordering Code Definitions
Ordering Information
Speed
(ns) Ordering Code
Package
Diagram Package Type (all Pb-free) Operating
Range
45 CY62158H-45ZSXI 51-85087 44-pin TSOP II (Pb-free) Industrial
CY62158H-45ZSXIT
X = blank or T
blank = Bulk; T = Tape and Reel
Temperature Grade: I = Industrial
Pb-free
Package Type:
ZS = 44-pin TSOP II
Speed Grade: 45 ns
Voltage Range: XX = No character or 18 or 30
No character = 5 V typ; 30 = 3 V typ; 18 = 1.8 V typ
Process Technology: H = 65 nm
Bus width: 8 = × 8
Density: 5 = 8-Mbit
Family Code: MoBL SRAM family
Company ID: CY = Cypress
CY 45 ZS
621 58HX
-I
XX T
Document Number: 001-96968 Rev. *E Page 13 of 16
CY62158H MoBL®
Package Diagram
Figure 9. 44-pin TSOP Z44-II Package Outline, 51-85087
51-85087 *E
Document Number: 001-96968 Rev. *E Page 14 of 16
CY62158H MoBL®
Acronyms Document Conventions
Units of Measure
Table 1. Acronyms Used in this Document
Acronym Description
CE Chip Enable
CMOS Complementary Metal Oxide Semiconductor
I/O Input/Output
OE Output Enable
SRAM Static Random Access Memory
VFBGA Very Fine-Pitch Ball Grid Array
WE Write Enable
ECC Error Correcting Code
Table 2. Units of Measure
Symbol Unit of Measure
°C degree Celsius
MHz megahertz
Amicroampere
smicrosecond
mA milliampere
mm millimeter
ns nanosecond
ohm
%percent
pF picofarad
Vvolt
Document Number: 001-96968 Rev. *E Page 15 of 16
CY62158H MoBL®
Document History Page
Document Title: CY62158H MoBL®, 8-Mbit (1M words × 8-bit) Static RAM with Error-Correcting Code (ECC)
Document Number: 001-96968
Rev. ECN No. Orig. of
Change
Submission
Date Description of Change
*B 5258628 NILE 05/06/2016 Changed status from Preliminary to Final.
*C 5430402 VINI 09/13/2016 Updated DC Electrical Characteristics:
Updated Note 5 (Replaced 2 ns with 20 ns).
Updated Ordering Information:
Updated part numbers.
Updated to new template.
*D 5980470 AESATMP8 11/30/2017 Updated logo and Copyright.
*E 6122301 NILE 04/04/2018 Updated Features:
Referred Note 1 in “Embedded error-correcting code (ECC) for single-bit
error correction”.
Added Note 2 and referred the same note in “Embedded error-correcting
code (ECC) for single-bit error correction”.
Updated to new template.
Completing Sunset Review.
Document Number: 001-96968 Rev. *E Revised April 4, 2018 Page 16 of 16
© Cypress Semiconductor Corporation, 2015-2018. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC (“Cypress”). This document,
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CY62158H MoBL®
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