PRM® Regulator
Page 1 of 22
Rev 1.1
7/2015
vicorpower.com
800 927.9474
PRM® Regulator
PRM48BH480T200B00
S
C NRTL US
High Efficiency Remote Sense PRM Converter
FEATURES DESCRIPTION
•
45 V (38 to 55 V
IN
), non-isolated ZVS buck-boost
The VI Chip
®
PRM®
Regulator is a high efficiency
regulator
•
5 to 55 V adjustable output range
•
Building block for high efficiency DC-DC systems
•
200 W Output Power in 0.57 in
2
footprint
•
97% typical efficiency, at full load
•
1,300 W/in
3
(81 W/cm
3
) Power Density
•
Enables a 48 V to 1.5 V, 130 A isolated, regulated
solution with total footprint of 1.7 in
2
(11 cm
2
)
•
Flexible “Remote Sense” architecture optimizes
regulation / feedback loop design to fit application
requirements
•
Current Feedback signal allows dynamic adjustment of
current limit setpoint
•
4.93 MHrs MTBF (MIL-HDBK-217Plus Parts Count)
TYPICAL APPLICATIONS
•
High Efficiency Server Processor and Memory Power
•
High Density ATE system DC-DC power
•
Telecom NPU and ASIC core power
•
LED drivers
•
High Density Power Supply DC-DC rail outputs
•
Non-isolated power converters
converter, operating from a 38 to 55 Vdc input to generate
a regulated 5 to 55 Vdc output. The ZVS Buck – Boost
topology enables high switching frequency (~1 MHz)
operation with high conversion efficiency. High switching
frequency reduces the size of reactive components
enabling power density up to 1,300 W/in
3
.
The half VI Chip package is compatible with standard pick-
and-place and surface mount assembly processes with a
planar thermal interface area and superior thermal
conductivity.
In a Factorized Power Architecture™ system, the
PRM48BH480T200B00 and downstream VTM
®
transformer minimize distribution and conversion losses in
a high power solution.
An external control loop and current sensor maintain
regulation and enable flexibility both in the design of
voltage and current compensation loops to control of
output voltages and currents.
48 V to 1.2 V, 130A Voltage Regulator
Voltage
Control
Feedback
Enable/
Disable
Voltage
Reference
PC
+IN
PR TM
+OUT
+IN
IM PC TM
+OUT1
+OUT2
38 to 55
Vdc Input
-IN
PRM
-OUT
-IN
VTM
-OUT1
Load
IF RE SG VC VC -OUT2
Current
Sense
PRM® Regulator
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800 927.9474
PRM48BH480T200B00
1.0 ABSOLUTE MAXIMUM RATINGS
The ABSOLUTE MAXIMUM ratings below are stress ratings only. Operation at or beyond these maximum ratings can cause
permanent damage to device. Electrical specifications do not apply when operating beyond rated operating conditions. All
voltages are specified relative to SG unless otherwise noted. Positive pin current represents current flowing out of the pin.
Min Max
Unit
PR ………………………………………………………………………..
PC ………………………………………………………………………..
TM ………………………………………………………………………..
+IN to –IN ……………………………………………………………………………
VS ………………………………………………………………………..
SG ……………………………………………………………………………
IF ……………………………………………………………………………
RE ……………………………………………………………………………
-0.3 10.5 V
±10 mA
-0.3 5.7 V
±10 mA
-0.3 5.7 V
±1 mA
-1 62 V
-0.5 10.5 V
±100 mA
±100 mA
-0.5 5.7 V
-0.3 5 V
VC to –OUT
………………………………………………………………………..
-0.5 18 V
±1.8 A
+OUT to –OUT ……………………………………………………………………………
Output Current ……………………………………………………………………………
Operating Analog IC Junction Temperature ……………………………………………………………………………
Storage Temperature ……………………………………………………………………………
-1 62 V
±5.5 A
-40 125 ºC
-40 125 ºC
2.0 ELECTRICAL CHARACTERISTICS
Specifications apply over all line and load conditions, T
J
= 25 ºC and output voltage from 20 V to 55 V, unless otherwise
noted.
Boldface specifications apply over the temperature range of -40 ºC < TJ < 125 ºC (T-grade).
Att
r
ibute S
y
mbol Conditions
/
Note s Min T
y
p Max Unit
POWER INPUT SPECIFICATION
Input Voltage range
V
IN 38 45 55
V
VIN Slew
R
ate d
V
IN
/
dt 0 < VIN < 18 V 0.001 1000
V
/
ms
No Load Power Dissipation PNL PC High, VIN = 45 V 2.6 4 W
Input Quiescent current IQC PC Low, VIN = 45 V 4.5 8.5 mA
Input Current
I
IN_DC
IOUT = 4.17 A, VIN = 38 V, VOUT =48V
5.5 5.7
A
Input Capacitance (Internal) CIN_INT Effecti
v
e
v
alue, VIN = 45 V (see Fig. 20) 2 µF
Input Capacitance (Internal) ESR
R
Cin 3 mΩ
POWER OUTPUT SPECIFICATION
Output Voltage range
V
OUT 5 48 55
V
Output Current IOUT See Fig.16, SOA 4.17
A
Output Power POUT See Fig.16, SOA 200 W
Output Turn-ON Delay TON From PC pin
r
elease to VOUT,V
IN p
r
e
-
applied and TOFF al
r
ead
y
expi
r
ed 20 µs
TOFF + TON From VIN applied to VOUT, PC floating 18.02 ms
Current Sharing accuracy
I
OUT_PS
Equal input, output and PR
v
oltage at full load; VIN =45V,V
OUT =48V,exclusi
v
eofcur
r
ent limi
t
±10 %
Equal input, output and PR voltage at full load;
Over line, trim, and temperature; exclusive of current limit See sec 10.6 %
Efficiency
η
Nominal line, full load, VOUT = 48V 95.7 96.9 %
50% load and VOUT = 48 V; o
v
e
r
tempe
r
atu
r
e 94.5 %
50% load; over temperature 88.5 %
Output Discharge current IOD Section 4.0 0.5 mA
Output Voltage Ripple
V
OUT_PP COUT_EXT = 0 F, IOUT = 4.17 A, VIN =45V,V
OUT =48V,20MHzBW
1020 1500 mV
Output Inductance (Parasitic)
L
OUT_PAR
Frequency @ 1 MHz, Simulated J-Lead model 2.5 nH
Output Capacitance (Internal) COUT_INT Effecti
v
e
v
alue, VOUT = 48 V (see Fig. 20) 2 µF
Output Capacitance (Internal) ESR
R
Cout 3 mΩ
POWERTRAIN PROTECTIONS
Input Undervoltage Turn-ON
V
IN_UVLO+ Instantanous powe
r
t
r
ain shutdown, latched afte
r
TBLANK 35.75 37.13
V
Input Undervoltage Turn-OFF
V
IN_UVLO- 31.97 33.56
V
Input Overvoltage Turn-ON
V
IN_OVLO+ Instantanous powe
r
t
r
ain shutdown, latched afte
r
TBLANK 55.91 57.24
V
Input Overvoltage Turn-OFF
V
IN_OVLO- 58.44 59.91
V
Overcurrent (IF) and Input
Over/Undervoltage Blanking Time TBLANK 50 120 150 µs
Output Overvoltage Threshold
V
OUT_OVLO+
Instantaneous, latched shutdown 55.25 56.57 59.04
V
Thermal Shutdown Setpoint TJ_OTP Instantaneous, latched shutdown; gua
r
anteed b
y
design, not p
r
oduction tested; V TM =4.03V
130 ºC
Overtemperature, Output Overvoltage
and PC Shutdown Response Time TPROT
2 µs
Short Circuit Vout Threshold
V
SC_VOUT 3.0
V
Short Circuit Vout Recovery Threshold
V
SC_VOUTR
4.0
V
Short Circuit Vpr Threshold
V
SC_VPR 7.2
V
Short Circuit Vpr Recovery Threshold
V
SC_VPRR 7.1
V
Short Circuit Timeout TSC Sho
r
t Ci
r
cuit faul
t
latched afte
r
VSC_VOUT and VSC_VPR th
r
esholds pe
r
sist fo
r
this time 20 ms
Short Circuit Fault Recovery Time TSCR 0.1 ms
Output Power Limit PPROT 200 W
PRM48BH480T200B00
PRM® Regulator
Page 3 of 22
Rev 1.1
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800 927. 9474
3.0 SIGNAL CHARACTERISTICS
Specifications apply over all line and load conditions, T
J
= 25 ºC and Output Voltage from 20 V to 55 V, unless otherwise
noted.
Boldface specifications apply over the temperature range of -40 ºC < TJ < 125 ºC (T-grade).
P
r
ima
r
y
Cont
r
ol PC
•
The PC pin enables and disables the PRM
•
In PRM array configurations, PC pins should be connected in order to synchronize startup.
•
It is a weak pull-down during any fault mode excluding short circuit. PC is a strong pull-down to SG if a Short Circuit fault is latched.
Signal T
y
pe State Att
r
ibute S
y
mbol Conditions
/
Notes Min T
y
p Max Unit
Analog Output
Regular
Operation
PC Voltage VPC 4.7 5.3 V
PC Available Current
I
PC_OP
1.8 mA
Startup PC Source Current
I
PC_EN
After TOFF 90 µA
Minimum Time to Start TOFF Section 5.0 10.0 18.0 30.0 ms
Digital Input / Output
Startup PC Enable Threshold VPC_EN 2.50 3.20 V
Standby PC Disable Threshold VPC_DIS 1.75 2.40 V
PC Resistance to disable
R
PC_EXT Max Resistance to SG required to disable the PRM 300 Ω
Digital Output [Short Circuit Fault] Fault PC Sink Current to SG
I
PC_SC
Short circuit, PC Voltage 1 V or above 25 mA
Digital Output [All other Faults] Fault PC Sink Current to ~1V
I
PC_FAULT
Temperature, Over- and Under-Voltage, Overcurrent 10
µΑ
V
oltage Sou
r
c
e
V
S
• Intended to power feedback components and/or auxiliary circuits.
Signal T
y
pe State Att
r
ibute S
y
mbol Conditions
/
Notes Min T
y
p Max Unit
Analog Output
Regular
Operation
VS Voltage VVS 8.55 9.00 9.45 V
VS Available Current
I
VS
5 mA
VS Voltage Ripple
V
VS_PP
Iout = 0A, Cvs_ext=0. Maximum specification
includes powertrain operation in burst mode. 100 400 mV
Transition VS Capacitance (External)
C
VS_EXT
0.04 µF
VS Fault Response Time
T
FR_VS
From fault recognition to VS = 1.5 V 30 µs
R
efe
r
en
c
e Enable RE
• RE signals successful startup and powertrain ready to operate
• Regulated, delayed voltage source intended to power the feedback circuit voltage reference and current monitor
Signal T
y
pe State Att
r
ibute S
y
mbol Conditions
/
Notes Min T
y
p Max Unit
Analog Output
Regular
Operation
RE Voltage VRE 3.0 3.3 3.6 V
RE Available Current IRE 8.0 mA
RE Regulation %
RE across load and temperature ±2.5 %
RE Voltage Ripple VRE_PP includes powertrain in burst mode 100 mV
Transition
PC to RE Delay TPC_RE Fault detected 100 µs
RE Capacitance (External) CRE_EXT 0.1 µF
VS to RE Delay TVS_RE VS = 8.1 V to RE high, VIN > VIN_UVLO- 1 ms
Cont
r
ol Node PR
• Modulator control node input
• Sinks constant current when externally driven
• Sources current when pulled below active range
Signal T
y
pe State Att
r
ibute S
y
mbol Conditions
/
Notes Min T
y
p Max Unit
Analog Input
Regular
Operation
PR Voltage Active Range VPR 0.79 7.40 V
PR Source Current
I
PR
VPR ≤0.79V 2 mA
PR Sink Current
I
PR_Low
VPR >0.79V 250 500 750 µA
PR Resistance to SG (Internal) RPR 93.3 kΩ
Cur
r
ent Feedba
c
k IF
• A voltage proportional to the PRM output current must be supplied externally to the IF pin in order for the device to properly protect overcurrent events and to enable output current limit (clamp)
• Overcurrent protection trip will cause instantaneous powertrain disable, latched after TBLANK
Signal T
y
pe State Att
r
ibute S
y
mbol Conditions
/
Notes Min T
y
p Max Unit
Analog Input
Regular
Operation
Current Limit (clamp) Threshold
V
IF_IL
VIN = 45 V; TJ = 25 °C 1.90 2.00 2.10
V
Overcurrent Protection Threshold
V
IF_OC
Not Production Tested; Guaranteed by Design;
TJ = 25 °C 2.58 2.69 2.80
IF Input Impedance RIF 2.11 2.13 2.15 kΩ
Current Limit Bandwidth BWIL 2 kHz
PRM48BH480T200B00
PRM® Regulator
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Rev 1.1
7/2015
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800 927. 9474
Tempe
r
atu
r
e Monito
r
TM
• The TM pin monitors the internal temperature of the PRM analog control IC.
• "Power Good" flag to verify that the PRM is operating
Signal T
y
pe State Att
r
ibute S
y
mbol Conditions
/
Notes Min T
y
p Max Unit
Analog Output
Regular
Operation
TM Voltage VTM Full temperature range 2.12 4.04 V
TM Voltage reference VTM_ AMB TJ = 27 °C 2.94 3.00 3.06 V
TM Voltage Ripple VVS_PP powertrain in burst mode 350 mV
TM Available Current ITM 100 µ
A
TM Gain ATM 10 mV/°C
Digital Output [Fault Flag] Fault or
Standby TM Disabled Current I DC state with TM Voltage +/- 0.5V. This is a high
impedance state. 0.0 mA
TM_ D IS
Signal G
r
ound SG
• All control signals must be referenced to this pin, with the exception of VC
• SG is internally connected to -IN and -OUT
Signal T
y
pe State
A
tt
r
ibute S
y
mbol Conditions
/
Notes Min T
y
p Max Unit
Analog Input / Output Any Maximum Allowable Current
I
SG
-100 100 mA
V
TM Cont
r
ol
V
C
• Pulsed voltage source used to power and synchronize start up of downstream VTM
• If not used, must be resistively terminated to -OUT
Signal T
y
pe State
A
tt
r
ibute S
y
mbol Conditions
/
Notes Min T
y
p Max Unit
Analog Output
Startup
VC Voltage VVC RVC = 68
Ω
13 V
VC Current Limit
I
VC
VC = 14 V, VIN > 20 V 200 500 mA
VC duration TVC 7 10 16 ms
VC Slew Rate dVC/dt RVC = 1k
Ω
20 V/µs
PRM48BH480T200B00
PRM® Regulator
Page 5 of 22
Rev 1.1
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800 927. 9474
-Vout
4.0 FUNCTIONAL BLOCK DIAGRAM
+Vin
Internal
Vcc
Vcc
3.3V
Linear
Regulator
3.3V
PC PR Vout
Cin
Q1 Q3
Cout
+Vout
Vcc
Regulator
RE uC 8051 L
-Vin
16V
PR
9V
8.2V
+Vout
Output
Discharge
(OD)
Q2 Q4
PR Modulator
93.3kW
100uA
Vcc
0.5m
A
Q SET S
2.5mA Min
T
OFF
delay
Var. Vclamp
Enable
Fault Logic
VTM Vc Start up pulse
14V VC
10ms
RE RE
Q CLR R
Instant
latch
Latch after
120us
3.3V
R
3V
5V
2mA max
Vout
(OV)
Vin
(OV, UV)
Vs
9V 0.01uF
PC Enable
PC
10uA
TM
3 V @ 27°C
VPC_EN
Temperature
dependent voltage
source
Vref
(130°C)
Overtemperature
Protection
Current Limit
Overcurrent
Protection
V
IF_IL
V
IF_OC
SG
IF
2130
W
PRM48BH480T200B00
PRM® Regulator
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5.0 HIGH LEVEL FUNCTIONAL STATE DIAGRAM
Conditions that cause state transitions are shown along arrows. Sub-sequence activities listed inside the state bubbles.
Application of
Vin
PC HIGH
and
Toff expiry
STANDBY
SEQUENCE
PC: 10uA to LOW
Toff Timeout
PC: 90uA to HIGH
Powertrain Stopped
T
BLNK
Fault
Overtemp or Output
OVP
PC HIGH
and
Ton expiry
STARTUP
SEQUENCE
PC: 1.8mA to HIGH
Ton timeout;
VC Pulse;
Powertrain Active
Delayed RE
expiry removed
BLANKING
PC: 1.8mA to HIGH
T
BLNK
Timeout
Powertrain Paused
Input OVP,
Input UVP,
or
OverCurrent Prot
SUSTAINED
OPERATION
PC: 1.8mA to HIGH
Powertrain Active
Short Circuit:
Vout < VSC_Vout
and
Vpr > VSC_Vpr
Vout < 1 V
And
TSCR expiry
PC
falling
edge
Short Removed:
Vout > VSC_VOUTR
or
Vpr < VSC_VPR_R
SHORT
CIRCUIT
PC: 1.8mA to HIGH
T
SC
Timeout
Powertrain Active
OUTPUT DISCHARGE
PC: pulsed 25mA drive
LOW
T
SCR
Timeout
Powertrain Stopped
I
OD
Output Discharge
T
SC
expiry
PC
falling
edge
PRM48BH480T200B00
PRM® Regulator
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Rev 1.1
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800 927. 9474
IF
Input
/
Output
Input Output
PC
V
RE
6.0 TIMING DIAGRAMS
Module Inputs are shown in blue; Module Outputs are shown in brown; Timing diagrams assumes the following:
Single PRM (no array)
VS powers error amplifier
RE powers voltage reference and output current transducer
I
OUT
is sensed, scaled, and fed back to IF pin such that IF = 2.00 V at full load
1 2 3 4 5 6 7 8
Start up with
1.2V/ms < dVIN/dt < maximum
Quick OC Input OV
(t<TBLNK)
Input OV
recovery
PC
disable
PC
release
Full load
applied
Load release and
Output OV (slow f/b)
V
IN
OV
UV
T
OFF
TON
18 V
Vpr_max
PR
TBLNK
Vpr_min
VIF_OC
VIF_IL
t < TBLNK
Vpc
T
BLNK
T
OFF
TOFF
T
PROT
TON
Vpc_en
VC
Vvc
TVC
OV
OUT
TPROT
1 V
T
VS_RE
T
PC_RE
TPC_RE TPC_RE
Vre_amb
Vvs_amb
VS
TM
OT
TBLNK
Vtm_amb
PRM48BH480T200B00
PRM® Regulator
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800 927. 9474
IF
Input Output Input
/
Output
PC
V
9
Start up with
minimum < dVIN/dt < 1.2V/ms
T
OFF
10
Output short
circuit
(Output Short fault
conditions satisfied)
(Output Short fault
11
Output Power
limit Protection
12
Current limit
event
13
Input UV
V
IN
OV
UV
timer expired)
18 V
Vpr_max
PR
TBLNK
Vpr_min
VIF_OC
VIF_IL
Vpc
TSC
TSCR+TOFF
Vpc_en
VC
Vvc
OV
OUT
<TBLNK
Vsc_vpr
1 V
RE
Vre_amb
Vvs_amb
VS
TM
OT
Vtm_amb
PRM48BH480T200B00
PRM® Regulator
Page 9 of 22
Rev 1.1
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800 927. 9474
Efficiency
[%]
Power
Dissipation
[W]
Power
Dissipation
[W]
Power
Dissipation
[W]
Efficiency
[%]
Power
Dissipation
[W]
7.0 APPLICATIONS CHARACTERISTICS
The following figures present typical performance at T
C
= 25º C, unless otherwise noted. See associated figures for general
trend data.
No Load Power Dissipation vs. Line
Module Enabled - Nominal V
OUT
6
No Load Power Dissipation vs. Line
Module Disabled, PC=Low
1
5 0.8
4
0.6
3
0.4
2
1 0.2
0
38 40 42 44 46 48 50 52 54
Input Voltage [V]
0
38 40 42 44 46 48 50 52 54
Input Voltage [V]
TCASE: -40 ºC 25 ºC 100 ºC TCASE: -40 ºC 25 ºC 100 ºC
Figure 1
- No load power dissipation vs. V
IN
, module
enabled
Figure 2
- No load power dissipation vs. V
IN
, module
disabled
Efficiency & Power Dissipation
V
OUT
= 20 V T
CASE
= -40 ºC
98 16
96
94 14
92
90 12
88
86 10
84
82 8
80
78 6
76
74 4
72
70 2
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5
Load Current [A]
Efficiency & Power Dissipation
V
OUT
= 48 V T
CASE
= -40 ºC
98 16
96
94 14
92
90 12
88
86 10
84
82 8
80
78 6
76
74 4
72
70 2
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5
Load Current [A]
VIN: 38 45 55 38 45 55 VIN: 38 45 55 38 45 55
Figure 3
– Total efficiency and power dissipation vs. V
IN
and
I
OUT
, V
OUT
= 20 V, T
CASE
= -40ºC
Figure 4
– Total efficiency and power dissipation vs. V
IN
and
I
OUT
, V
OUT
= 48 V, T
CASE
= -40ºC
PRM48BH480T200B00
PRM® Regulator
Page 10 of 22
Rev 1.1
7/2015
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800 927. 9474
Efficiency
[%]
Efficiency
[%]
Efficiency
[%]
Power
Dissipation
[W]
Power
Dissipation
[W]
Power
Dissipation
[W]
Efficiency
[%]
Efficiency
[%]
Efficiency
[%]
Power
Dissipation
[W]
Power
Dissipation
[W]
Power
Dissipation
[W]
Efficiency & Power Dissipation
V
OUT
= 55 V T
CASE
= -40 ºC
98 16
96
94 14
92
90 12
88
86 10
84
82 8
80
78 6
76
74 4
72
70 2
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5
Load Current [A]
Efficiency & Power Dissipation
V
OUT
= 20 V T
CASE
= 25 ºC
98 16
96
94 14
92
90 12
88
86 10
84
82 8
80
78 6
76
74 4
72
70 2
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5
Load Current [A]
VIN: 38 45 55 38 45 55 VIN: 38 45 55 38 45 55
Figure 5
– Total efficiency and power dissipation vs. V
IN
and
I
OUT
, V
OUT
= 55 V, T
CASE
= -40ºC
Figure 6
– Total efficiency and power dissipation vs. V
IN
and
I
OUT
, V
OUT
= 20 V, T
CASE
= 25ºC
Efficiency & Power Dissipation
V
OUT
= 48 V T
CASE
= 25 ºC
98 16
96
94 14
92
90 12
88
86 10
84
82 8
80
78 6
76
74 4
72
70 2
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5
Load Current [A]
Efficiency & Power Dissipation
V
OUT
= 55 V T
CASE
= 25 ºC
98 16
96
94 14
92
90 12
88
86 10
84
82 8
80
78 6
76
74 4
72
70 2
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5
Load Current [A]
VIN: 38 45 55 38 45 55 VIN: 38 45 55 38 45 55
Figure 7
– Total efficiency and power dissipation vs. V
IN
and
I
OUT
, V
OUT
= 48 V, T
CASE
= 25ºC
Figure 8
– Total efficiency and power dissipation vs. V
IN
and
I
OUT
, V
OUT
= 55 V, T
CASE
= 25ºC
Efficiency & Power Dissipation
V
OUT
= 20 V T
CASE
= 100 ºC
98 16
96
94 14
92
90 12
88
86 10
84
82 8
80
78 6
76
74 4
72
70 2
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5
Load Current [A]
Efficiency & Power Dissipation
V
OUT
= 48 V T
CASE
= 100 ºC
98 16
96
94 14
92
90 12
88
86 10
84
82 8
80
78 6
76
74 4
72
70 2
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5
Load Current [A]
VIN: 38 45 55 38 45 55 VIN: 38 45 55 38 45 55
Figure 9
– Total efficiency and power dissipation vs. V
IN
and
I
OUT
, V
OUT
= 20 V, T
CASE
= 100ºC
Figure 10
– Total efficiency and power dissipation vs. V
IN
and I
OUT
, V
OUT
= 48 V, T
CASE
= 100ºC
PRM48BH480T200B00
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f
SW
[kHz]
Efficiency
[%]
Total
input
charge
per
switching
cycle
[
µ
C]
Power
Dissipation
[W]
f
SW
[kHz]
Output
Current
[A]
V
PR
[V]
Total
output
charge
per
switching
cycle
[
µ
C]
Output
Power
[W]
Efficiency & Power Dissipation
V
OUT
= 55 V T
CASE
= 100 ºC
98 16
96
94 14
92
90 12
88
86 10
84
82 8
80
78 6
76
74 4
72
70 2
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5
Load Current [A]
6.5
6
5.5
5
4.5
4
V
PR
vs. Case Temperature
V
IN
= 45 V; V
OUT
= 48 V
6.12 6.21 6.04
4.57 4.62
4.47
-40 -20 0 20 40 60 80 100
Temperature [ºC]
VIN: 38 45 55 38 45 55 IOUT: 2.08 4.17
Figure 11
– Total efficiency and power dissipation vs. V
IN
and I
OUT
, V
OUT
= 55 V, T
CASE
= 100ºC
Figure 12
– Typical control node voltage vs. T
CASE
, I
OUT
; V
IN
= 45 V, V
OUT
= 48 V
Powertrain switching frequency and periodic
output charge vs. input voltage - Full load
1025
1000
975
950
925
900
875
850
825
800
18
f
sw
16
14
12
10
8
6
µC
4
2
0
38 40 42 44 46 48 50 52 54 56
Input Voltage [V]
Figure 13
– Typical output voltage ripple waveform, T
CASE
=
VOUT 55 20 48 55 20 48
30ºC, V
IN
= 45 V, V
OUT
= 48 V, I
OUT
= 4.17 A, no external
capacitance.
Figure 14
– Powertrain switching frequency and periodic
output charge vs. V
IN
, V
OUT
; I
OUT
= 4.17 A
Powertrain switching frequency and periodic
input charge vs. input voltage - Full load
1025 18
fsw
1000 16
975 14
950 12
925 10
900 8
5.21
4.17
3.13
2.08
DC Safe Operating Area
200
160
120
80
875
850
825
800
6
µC
4
2
0
38 40 42 44 46 48 50 52 54 56
Input Voltage [V]
1.04
0.00
40
0
5 10 15 20 25 30 35 40 45 50 55 60
Output Voltage [V]
Current Power
VOUT 55 20 48 55 20 48
Figure 15
– Powertrain switching frequency and periodic
input charge vs. V
IN
, V
OUT
; I
OUT
= 4.17 A
Figure 16
– DC Output Safe Operating Area
PRM48BH480T200B00
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G
p
r
req_out
G
PR
[d
B
]
G
PR
[d
B
]
Output
Power
[W]
r
eq_out
[
Ω
]
r
eq_out
[
Ω
]
µ
Effective
capacitance
[
F]
G
PR
[d
B
]
r
[
Ω
]
IN
r
eq_out
[
Ω
]
DC modulator gain and powertrain equivalent
output resistance vs. output current - VOUT = 55V
DC modulator gain and powertrain equivalent
output resistance vs. output current - VOUT = 20V
4
2
0
-2
-4
-6
-8
-10
Gpr
req_out
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5
Output Current [A]
490
420
350
280
210
140
70
0
8 49
6 42
4 35
2 28
0 21
-2 14
-4 7
-6 0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5
Output Current [A]
VIN
: 38 45 55 38 45 55 VIN
: 38 45 55 38 45 55
Figure 17
– Powertrain characteristics vs. I
OUT;
Resistive load, V
OUT
= 55 V, various V
IN
Figure 18
– Powertrain characteristics vs. I
OUT;
Resistive load, V
OUT
= 20 V, various V
IN
6
4
2
0
-2
-4
-6
-8
VIN
:
DC modulator gain and powertrain equivalent
output resistance vs. output current - VOUT = 48V
210
180
150
Gpr
120
90
60
r
eq_out
30
0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5
Output Current [A]
38 45 55 38 45 55
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
Effective internal input (C
IN_INT
) and output
(C
OUT_INT
) capacitance vs. applied voltage
0 5 10 15 20 25 30 35 40 45 50 55
Voltage [V]
Figure 19
– Powertrain characteristics vs. I
OUT;
Resistive load, V
OUT
= 48 V, various V
IN
Figure 20
– Effective internal input and output capacitance
vs. voltage – ceramic type
200
180
160
140
120
100
80
60
40
20
0
Output Power vs. V
PR
V
IN
= 45V, V
OUT
= 48V, T
C
=25ºC
Typical min
Nominal
Typical max
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
PR Voltage [V]
Powertrain equivalent input resistance
vs. output current - V
OUT
= 55V
32
28
24
20
16
12
8
4
0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5
Output Current [A]
VIN: 38 45 55
Figure 21
– Output Power vs. V
PR
; V
IN
= 45 V, V
OUT
= 48 V,
T
CASE
= 25ºC
Figure 22
– Magnitude of powertrain dynamic input
impedance vs. V
IN
, I
OUT
; V
OUT
= 55 V
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Att
r
ibute S
y
mbol Conditions
/
Note s Min T
y
p Max Unit
MECHANIC
A
L
Length L 21.8 / [0.86] 22.0 / [0.87] 22.3 / [0.88] mm / [in]
Width W 16.3 / [0.64] 16.5 / [0.65] 16.8 / [0.66] mm / [in]
Height H 6.48 / [0.255] 6.73 / [0.265] 6.98 / [0.275] mm / [in]
Volume Vol No Heatsink 2.44 / [0.15] cm3 / [in3]
Weight W 7 g
Lead Finish Nickel 0.51 2.03
µm
Palladium 0.02 0.15
Gold 0.003 0.050
THE
R
M
A
L
Operating and Storage Junction
Temperature T
-40 125 ºC
Operating Case Temperature TC Any operating condition -40 100 ºC
Thermal Capacity 5 Ws/ºC
A
SSEMBLY
Peak Compressive Force Applied to
Case (Z-axis) Supported by J-Lead only 3 lbs
5.33 lbs / in
2
Storage Temperature TST -40 125 ºC
ESD Rating ESDHBM Human Body Model, "JEDEC JESD 22-A114C.01" 1000 V
ESDCDM Charged Device Model, "JEDEC JESD 22-C101D" 400
SOLDE
R
ING
Peak Temperature During Reflow MSL 4 (Datecode 1528 and later) 245 ºC
Maximum Time Above [217] ºC 150 s
Peak Heating Rate During Reflow 1.5 2 ºC / s
Peak Cooling Rate Post Reflow 2.5 3 ºC / s
S
A
FETY and
R
ELIABILITY
MTBF Telcordia Issue 2 - Method I Case 1; Ground Benign, Controlled 2.51 MHrs
MIL-HDBK-217Plus Parts Count - 25C Ground Benign, Stationary, Indoors / Computer Profile 4.93 MHrs
Agency Approvals / Standards CTUV US
CE Mark
ROHS 6 of 6
r
IN
[
Ω
]
r
IN
[
Ω
]
180
160
140
120
100
80
60
40
20
0
Powertrain equivalent input resistance
vs. output current - V
OUT
= 20V
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5
Powertrain equivalent input resistance
vs. output current - V
OUT
= 48V
40
35
30
25
20
15
10
5
0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5
Output Current [A] Output Current [A]
VIN: 38 45 55 VIN: 38 45 55
Figure 23
– Magnitude of powertrain dynamic input
impedance vs. V
IN
, I
OUT
; V
OUT
= 20 V
Figure 24
– Magnitude of powertrain dynamic input
impedance vs. V
IN
, I
OUT
; V
OUT
= 48 V
8.0 GENERAL CHARACTERISTICS
Specifications apply over all line and load conditions, T
J
= 25 ºC and Output Voltage from 20 V to 55 V, unless otherwise
noted.
Boldface specifications apply over the temperature range of -40 ºC < TJ < 125 ºC (T-grade).
J
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9.0 PRODUCT OUTLINE DRAWING AND RECOMMENDED PCB FOOTPRINT
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10.1
PRODUCT DETAILS AND DESIGN GUIDELINES
10.2
Control pins description and characteristics
Control node (PR)
is the input to the control node which
determines the powertrain timing and ultimately the
module output power (Figure 21). An internal 0.5mA
current sink is always active. The bi-directional buffer
between PR and the control node has two states. In
normal operation, PR will be above the 0.79 V switching
threshold, and will drive the control node through the
buffer. An internal 7.4 V clamp determines the maximum
output power that can be requested of the modulator.
When PR falls below 0.79 V, the converter will stop
switching. An internal circuit clamps the modulator input
control node to 0.79 V, and a buffer will source up to
2.5 mA out of the pin at that clamp level. For this reason,
the output impedance of the amplifier driving PR must be
taken into account. A rail-to-rail operational amplifier with
low output impedance is always recommended.
The powertrain small signal (plant) response consists of a
single pole determined by the load resistance, the
powertrain equivalent output resistance, and the total
output capacitance (internal and external to the module).
Both the modulator gain and the equivalent output
resistance vary as a function of line, load and output
voltage, as shown in Figures 17, 18 and 19. As the load
increases, the powertrain pole moves to higher frequency.
As a result, the closed loop crossover frequency will be the
highest at full load and lowest at minimum load. Figure 25
shows a reference AC small-signal model.
Current feedback (IF)
is the input for the module output
overcurrent protection and current limit features (see
functional block diagram in section 4.0). A voltage
proportional to the powertrain output current must be
applied to IF in order for overcurrent protection to operate
properly.
If the IF voltage exceeds the IF pin’s overcurrent
protection threshold, the powertrain will stop switching. If
the IF voltage falls below the overcurrent protection
threshold within T
BLANK
time, then the powertrain will
immediately resumes switching. Otherwise a fault is
latched.
The current limit threshold for the IF pin is set lower than
the protection threshold. When the IF pin average voltage
exceeds the current limit threshold, an internal integrator
will activate a clamp amplifier which overrides the
modulator input maximum level. This causes the
powertrain to maintain a constant output current.
The bandwidth of this current limit integrator is significantly
slower than that of the PR control node input. Therefore
this current limit can not be used in lieu of properly
compensating the (external) PR control loop to avoid
exceeding maximum current or power ratings for the
device.
If the IF pin is not driven, it must be resistively terminated
to SG. A 1 kΩ resistor to SG is recommended in this case.
+
VIN
rEQ_IN
C
IN_INT
-
+
VPR
RPR
+
VPR · GPR COUT_INT
r
IPR_Low
-
EQ_OUT
-
Figure 25
– PRM48BH480T200B00 AC small signal model
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VTM Control (VC)
pin supplies an initial V
CC
voltage to
downstream VTMs, enabling them and synchronizing their
startup with the PRM. The V
CC
voltage is a pulse, typically
10 ms duration at 14 V.
If VC is not loaded by a VTM, it must be terminated with a
1 kΩ resistor to –V
OUT
.
Primary Control (PC)
is both an input and an output. It
can provide the following features:
•
Delayed start: upon application of voltage (>UVLO) to the
module power input and after T
OFF
, the PC pin will source
a constant 90 µA current.
•
Output disable: PC may be pulled down externally in
order to disable the module. Pull down resistance should
be less than 300 Ω to SG.
•
Fault detection flag: The PC 5 V voltage source is
internally turned off when a fault condition is latched. Note
that aside from the Short Circuit fault condition, PC does
not have significant current sinking capability. Therefore in
the case of an array of PRMs with interconnected PC pins,
PC does not in general reflect the fault state of all PRMs.
The common PC line will not disable neighboring modules
when a fault is detected except for a latched Output Short
Circuit fault. Conversely any unit in the array latching a
Short Circuit fault will disable the array for T
SCR
.
Temperature Monitor (TM)
pin outputs a voltage
proportional to the absolute temperature of the converter
analog control IC. It can be used to accomplish the
following functions:
•
Monitor the control IC temperature: The gain and setpoint
of TM are such that the temperature, in Kelvin, of the PRM
controller IC is equal to the voltage on the TM pin scaled
by 100. (i.e. 3.0 V = 300 K = 27 ºC).
•
Closed loop thermal management at the system
level
(e.g. variable speed fans or coolant flow)
•
Fault detection flag: The TM voltage source is turned off
as soon as a fault is detected. For system monitoring
purposes (microcontroller interface) faults are detected on
falling edges of TM.
Reference Enable (RE)
pin outputs a regulated 3.3 V,
8 mA voltage source. It is enabled only after successful
startup of the PRM powertrain (see chapters 5.0 and 6.0.)
RE is intended to power the output current transducer and
also the voltage reference for the control loop. Powering
the reference generator with RE helps provide a controlled
startup, since the output voltage of the system is able to
track the reference level as it comes up.
Voltage Source (VS)
pin outputs a gated (e.g. mirrors PC
status), non-isolated, regulated 9 V, 5 mA voltage source.
It can be used to power external control circuitry; it always
leads RE.
Signal Ground (SG)
pin provides a Kelvin connection to
the PRM’s internal signal ground. It should be used as the
reference for PR, TM, IF, and should return all PC, VS and
RE pin currents. In array configurations with common
ground control circuits, a series resistor (~1 Ω) is
recommended in order to decouple power and signal
current returns.
10.2
Control circuit requirements and design procedure
The PRM48BH480T200B00 is an intelligent powertrain
module designed to fully exploit external output voltage
feedback and current sensing sub-circuits. These two
external circuits are illustrated in Figure 26, which shows
an example of the PRM in a standalone application with
local voltage feedback and high side current sensing.
In general, these circuits include a precision voltage
reference, an operational amplifier which provides closed
loop feedback compensation, and a high side current
sense circuit which includes a shunt and current sense IC.
The following design procedures refer to the circuit shown
in Figure 26.
10.2.1
Setting the output voltage level
The output voltage setpoint is a function of the voltage
reference and the output voltage sense ratio. With
reference to Fig. 26, R1 and R2 form the output voltage
sensing divider which provides the scaled output voltage
to the negative input of the error amplifier; a dedicated
reference IC provides the reference voltage to the positive
input of the error amplifier. Under normal operation, the
error amplifier will keep the voltages at the inverting and
non-inverting inputs equal, and therefore the output
voltage is defined by:
V
=
V
⋅
R
1
+
R
2
OUT ref R2
Note that the component R1 will also factor into the
compensation as described in a later section.
It is important to apply proper slew rate to the reference
voltage rise when the control loop is initially enabled. The
recommended range for reference rise time is 1 ms to 9
ms. The lower rise time limit will ensure optimized
modulator timing performance during startup, and to allow
the current limit feature (through IF pin) to fully protect the
device during power-up. The upper rise time limit is
needed to guarantee a sufficient factorized bus voltage is
provided to any downstream VTM input before the end of
the VC pulse.
PRM48BH480T200B00
PRM® Regulator
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C
3
R
G
R
G
3
10.2.2
Setting the output current limit and overcurrent
protection level
The current limit and overcurrent protection set points are
linked, and scale together against the current sense shunt,
and the gain of the current sense amplifier. The output of
the current sense IC provides the IF voltage which has
V
IF_IL
and V
IF_OC
thresholds for the two functions
respectively. The set points are therefore defined by:
I = VIF _ IL
Internal output capacitance: see Figure 20
External output capacitance value
In the case of ceramic capacitors, the ESR can be
considered low enough to push the associated zero well
above the frequency of interest. Applications with high
ESR capacitor may require a different type of
compensation, or cascade control.
The system poles and zeros of the closed loop can then
be defined as follows:
Powertrain pole, assuming the external capacitor
ESR can be neglected:
IL
S
⋅
CS
r
EQ
_
OUT
⋅
R
LOAD
and
I = VIF _ OC
R OUT _ EXT
<<
rEQ _ OUT
+
R
LOAD
OC
S
⋅
CS
Main pole frequency:
where G
CS
is the gain of the current sense amplifier.
1
F
≈
10.2.3
Control loop compensation requirements
In order to properly compensate the control loop, all
components which contribute to the closed loop frequency
P
2 π
⋅
rEQ _ OUT
rEQ _ OUT
·
RLOAD
+ RLOAD
·
(
C
OUT
INT
+ COUT
EXT
)
response should be identified and understood. Figure 25
shows the AC small signal model for the module.
Modulator DC transconductance gain (G
PR
) and powertrain
Compensation Mid-Band Gain:
R
equivalent resistance (r
EQ_OUT
) are shown.
These
modeling parameters will support a design cut-off
frequency up to 50 kHz.
GMB = 20 log
R1
[1]
Standard Bode analysis should be used for calculating the
error amplifier compensation and analyzing the closed
loop stability. The recommended stability criteria are as
follows:
Compensation Zero:
F = 1 [2]
1)
Phase Margin > 45º : for the closed loop response, the
Z1 2 π⋅ R
3
⋅
C
1
phase should be greater than 45º where the gain crosses
0dB.
2)
Gain Margin > 10dB : The closed loop gain should
be
Compensation Pole:
lower than -10dB where the phase crosses 0º.
3)
Gain Slope = -20dB / decade : The closed loop gain
should have a slope of -20dB / decade at the crossover
FP 2
=
2 π
⋅
1
R
3
⋅
C
1
⋅
C
2
frequency.
The compensation characteristics must be selected to
meet these stability criteria. Refer to Figure 27 for a local
sense, voltage-mode control example based on the
configuration in Figure 26. In this example, it is assumed
C1 + C2
and for FP2>>FZ1 (C1 + C2 ≈ C1):
F
≈
1
that the maximum crossover frequency (F
CMAX
) has been
selected to occur between B and C. Type-2 compensation
(Curve IJKL) is sufficient in this case.
The following data must be gathered in order to proceed:
Modulator Gain GPR: See Figures 17, 18, 19
Powertrain equivalent resistance r
EQ
: See Figures
17, 18, 19
P
2
2
π
⋅
R
⋅
C
2
[3]
PRM48BH480T200B00
PRM® Regulator
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10.2.4
Midband Gain Design
(R1,R3):
With reference to Figure 27: curve ABC is the:
minimum output voltage in the application
maximum input voltage expected in the application
maximum load
PRM open loop response, and is where the maximum
crossover frequency occurs. In order for the maximum
crossover frequency to occur at the design choice F
CMAX
,
the compensation gain must be equal and opposite of the
powertrain gain at this frequency. For stability purposes,
the compensation should be in the Mid-band (J-K) at the
crossover. Using Equation [1], the mid-band gain can be
selected appropriately.
10.2.5
Compensation Zero
Design (C1):
With reference to Figure 27: curve EFG is the:
maximum output voltage in the application
minimum input voltage expected in the application
minimum load in the application
PRM open loop response, and is where the minimum
crossover frequency F
CMIN
occurs. Based on stability
criteria, the compensation must be in the mid-band at the
minimum crossover frequency, therefore F
CMIN
will occur
where EFG is equal and opposite of G
MB
. C1 can be
selected using Equation [2] so that F
Z1
occurs prior to
F
CMIN
.
C2
C1 R3
-
+ Vref
R2
R1
F1
+IN
VS
PR
RS
+OUT
CIN_EXT
PRM
CIN_INT COUT_INT COUT_EXT
-IN IF RE SG -OUT
Vref
Vref IC
I sense
IC
Figure 26
– Control circuit example
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Gain (dB)
Open Loop Gain vs. Frequency
80
60 I
Compensation Gain
Application's op-amp G·BW
40
E F
PRM Open Loop Min Load
A B
20 PRM Open Loop Max Load
J K
L
FCMIN
0 FCMAX
-20
-40
C
G
Frequency, Log scale
(y-intercept is application specific)
Figure 27
– Reference asymptotic Bode plot for the considered system
10.2.6
High Frequency Pole
Design (C2):
Using Equation [3], C2 should be selected so that F
P2
is at
least one decade above F
CMAX
and prior to the gain
bandwidth product of the operational amplifier (10 MHz for
this example). For applications with a higher desired
crossover frequency the use of a high gain bandwidth
product amplifier may be necessary to ensure that the real
pole can be set at least one decade above the maximum
crossover frequency.
10.2.7
Verifying
Stability:
based on the ratio of the “kick” to “droop” (as defined in
Fig. 28).
k
Vout
d
The preferred method for verifying stability is to use a
network analyzer, measuring the closed loop response
across various lines and load conditions.
In the absence of a network analyzer, a load step transient
response can be used in order to estimate stability.
Figure 28 illustrates an example of a load step response.
Iou
t
time
time
Equation [4] can be used to predict the phase margin
Figure 28
– load step response example and “droop”
vs. “kick” definition
PRM48BH480T200B00
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d
d
2
m 100
ln
k
2
[4]
Figure 20 provides the effective internal capacitance of the
module. A conservative estimate of input and output peak-
peak voltage ripple at nominal line and trim is provided by
equation [5]:
ln
k
+
2
Δ
V
=
QTO T
I
⋅
0.4
FL
fSW
[5]
10.3
Burst Mode
Operation:
At light loads, the PRM will operate in a burst mode due to
minimum timing constraints. An example burst operation
waveform is illustrated in Figure 29.
For very light loads, and also for higher input voltages, the
minimum time power switching cycle from the powertrain
will exceed the power required by the load. In this case the
external error amplifier will periodically drive PR below the
switching threshold in order to maintain regulation.
Switching will cease momentarily until the error amplifier
once again drives PR voltage above the threshold.
CINT + CEXT
Q
TOT
is the total input (Fig. 15) or output (Fig. 14) charge
per switching cycle at full load, while C
INT
is the module
internal effective capacitance at the considered voltage
(Fig. 20) and C
EXT
is the external effective capacitance at
the considered voltage.
10.5 Input filter stability
The PRM can provide very high dynamic transients. It is
therefore very important to verify that the voltage supply
source as well as the interconnecting line are stable and
do not oscillate. For this purpose, the converter dynamic
input impedance magnitude
r
EQ
_
IN
is provided in Figures
22, 23, 24. It is recommended to provide adequate design
margin with respect to the stability conditions illustrated in
10.5.1 and 10.5.2.
10.5.1 Inductive source and local, external input
decoupling capacitance with negligible ESR (i.e.: ceramic
type)
Figure 29
– light load burst mode of operation
Note that during the bursts of switching, the powertrain
frequency is constant, but the number of pulses as well as
the time between bursts is variable. The variability
The voltage source impedance can be modeled as a
series R
line
L
line
circuit. The high performance ceramic
decoupling capacitors will not significantly damp the
network because of their low ESR; therefore in order to
guarantee stability the following conditions must be
verified:
depends on many factors including input voltage, output
voltages, load impedance, and external error amplifier
R
line
>
(C
Lline
+
C
)
⋅
r
[6]
output impedance.
In burst mode, the gain of the PR input to the plant which
is modeled in the previous sections is time varying.
Therefore the small signal analysis can not be directly
IN INT IN EXT EQ IN
applied to burst mode operation.
R
line
<<
r
EQ
_
IN
[7]
10.4 Input and Output filter design
Figures 14 and 15 provide the total input and output
charge per cycle, as well as switching frequency, of the
PRM at full load under various input and output voltages
conditions.
It is critical that the line source impedance be at least an
octave lower than the converter’s dynamic input
resistance, [7]. However, R
line
cannot be made arbitrarily
low otherwise equation [6] is violated and the system will
show instability, due to under-damped RLC input network.
PRM48BH480T200B00
PRM® Regulator
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>
C
10.5.2 Inductive source and local, external input
decoupling capacitance with significant R
CIN_EXT
ESR (i.e.:
electrolytic type)
In order to simplify the analysis in this case, the voltage
source impedance can be modeled as a simple inductor
L
line
. Notice that, the high performance ceramic capacitors
C
IN_INT
within the PRM should be included in the external
electrolytic capacitance value for this purpose. The
stability criteria will be
temperature differences among PRMs, Vin
variations, and error terms in the buffering of the
error amplifier output to the PR pins.
Control loop compensation procedures above will
hold for an array, in general, although many
parameters must be scaled against the number of
PRMs in the system.
Please contact Vicor Applications for assistance.
10.7 Input Fuse Recommendations
r
EQ
_
IN
R
IN
_
EXT
[8]
A fuse should be incorporated at the input to each PRM, in
series with the +IN pin. A 10 A or smaller input fuse
Lline < r [9] (Littelfuse® NANO2®
451/453 Series, or equivalent) is
C
IN
_
EXT
⋅
R
C
IN _ EXT
EQ _ IN
required to safety agency conditions of acceptability.
Always ascertain and observe the safety, regulatory, or
other agency specifications that apply to your specific
Equation [9] shows that if the aggregate ESR is too small
– for example by using very high quality input capacitors
(C
IN_EXT
) – the system will be under-damped and may even
become destabilized. Again, an octave of design margin in
satisfying [8] should be considered the minimum.
10.6 Arrays
Up to ten PRMs of the same type may be placed in
parallel to expand the power capacity of the system. The
following high-level guidelines must be followed in order
for the resultant system to start up and operate properly,
and to avoid overstress or exceeding any absolute
maximum ratings.
–IN pins of all PRMs must be connected together.
Both inductance and resistance from the common
power source to each PRM should be minimized,
and matched.
Input voltage to all PRMs must be the same.
Independent fuses for each PRM are
recommended.
PC pins must be connected together for
synchronization and proper fault response.
Reference supply to the control loop voltage
reference and current sense circuitry must be
enabled when all modules’ RE pins have reached
their operational voltage levels.
There must be one single external voltage control
loop. The control loop must drive each PR pin
relative to each module’s SG pin, and the local PR
voltage must be the same across all modules.
Each PRM must have its own local current shunt
and current sense circuitry to drive its IF pin.
The number of PRMs required to achieve a given
array capacity must consider all sources of
mismatch to avoid overstress of any PRM in the
array. Imbalances in sharing are not only due to
current sharing accuracy specifications, but also
application.
10.8 Layout considerations
Application Note AN:005 details board layout using
VI Chip components. Additional consideration must be
given to the external control circuit components.
The current sense shunt signal voltage is highly sensitive
to noise. As such, current sensing circuitry should be
located close to the shunt to minimize the length of the
sense signals. A Kelvined connection at the shunt is
recommended for best results.
The control signal from a remote voltage sense circuit to
the PRM should be shielded. Avoid routing this, or other
control signals directly underneath the PRM, if possible.
Components that tie directly to the PRM should be located
close to their respective pins. It is also critical that all
control components be referenced to SG, and that SG not
be tied to any other ground in the system, including –IN or
–OUT of the PRM.
PRM48BH480T200B00
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Information furnished by Vicor is believed to be accurate and reliable. However, no responsibility is assumed by Vicor for
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The products described on this data sheet are protected by the following U.S. Patents Numbers:
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