HYMP512S64CP8-C4 - SK Hynix - Datasheet.Directory

This document is a general product description and is subject t o change without notice. Hynix Semiconductor do es not assume any

responsibility for use of circuits described. No patent licenses are implied.

Rev. 0.6 / Dec. 2008 1

200pin Unbuffered DDR2 SDRAM SO-DIMMs based on 512 Mb C ver.

This Hynix unbuffered Small Outline Dual In-Line Memory Module (DIMM) series consists of 512Mb C ver. DDR2

SDRAMs in Fine Ball Grid Array (FBGA) packages on a 200pin glass-epoxy substrate. This Hynix 512Mb C ver. based

Unbuffered D DR2 SO-DIMM series provide a high perf ormance 8 byte interf ace in 67.60mm width form fa ctor of indus-

try standard. It is suitable for easy interchange and addition.

FEATURES

ORDERING INFORMATION

Notes:

1. All Hynix’ DDR2 Lead-free parts are compliant to RoHS.

Part Name Density Organization # of

DRAMs # of

ranks Materials Power

Consumption

HYMP532S64CP6-E3/C4/Y5 256MB 32Mx64 4 1 Lead free* Normal

HYMP564S64CP6-E3/C4/Y5 512MB 64Mx64 8 2 Lead free Normal

HYMP512S64CP8-E3/C4/Y5 1GB 128Mx64 16 2 Lead free Normal

HYMP532S64CLP6-E3/C4/Y5 256MB 32Mx64 4 1 Lead free Low

HYMP564S64CLP6-E3/C4/Y5 512MB 64Mx64 8 2 Lead free Low

HYMP512S64CLP8-E3/C4/Y5 1GB 128Mx64 16 2 Lead free Low

• JEDEC standard Double Data Rate2 Synchronous

DRAMs (DDR2 SDRAMs) with 1.8V +/- 0.1V Power

Supply

• All inputs and outputs are compatible with SS TL_1.8

interface

•Posted CAS

• Programmable CAS Latency 3, 4, 5, 6

• OCD (Off-Chip Driver Impedance Adjustment) and

ODT (On-Die Termination)

• Fully differential clock operations (CK & CK)

• Programmable Burst Length 4 / 8 with both sequen-

tial and interleave mode

• Auto refresh and self refresh supported

• 8192 refresh cycles / 64ms

• Serial presence detect with EEPROM

• DDR2 SDRAM Package: 60ball(x8), 84ball(x16)

FBGA

• 67.60 x 30.00 mm form factor

• Lead-free Products are RoHS compliant

Rev. 0.6 / Dec. 2008 2

1200pin Unbuffered DDR2 SDRAM SO-DIMMs

SPEED GRADE & KEY PARAMETERS

ADDRESS TABLE

E3

(DDR2-400) C4

(DDR2-533) Y5

(DDR2-667) S6

(DDR2-800) S5

(DDR2-800) Unit

Speed @CL3 400 533 400 - - Mbps

Speed @CL4 533 533 533 533 533 Mbps

Speed @CL5 - - 667 667 800 Mbps

Speed @CL6 - - - 800 - Mbps

CL-tRCD-tRP 3-3-3 4-4-4 5-5-5 5-5-5 5-5-5 tCK

Density Organization Ranks SDRAMs # of

DRAMs # of row/bank/column Address Refresh

Method

256MB 32M x 64 1 32Mb x 16 4 13(A0~A12)/2(BA0~BA1)/10(A0~A9) 8K / 64ms

512MB 64M x 64 2 32Mb x 16 8 13(A0~A12)/2(BA0~BA1)/10(A0~A9) 8K / 64ms

1GB 128M x 64 2 64Mb x 8 16 14(A0~A13)/2(BA0~BA1)/10(A0~A9) 8K / 64ms

Rev. 0.6 / Dec. 2008 3

1200pin Unbuffered DDR2 SDRAM SO-DIMMs

PIN DESCRIPTION

Symbol Type Polarity Pin Description

CK[1:0], CK[1:0] Input Cross

Point

The system clock inputs. All address and commands lines are sampled on the cross point

of the rising edge of CK and fall ing edge of CK. A Dela y Lock ed Loop (DLL) ci rcuit is driv en

from the clock inputs and outp ut timing for read operations is synchronized to the input

clock.

CKE[1:0] Input Active

High

Activates the DDR2 SD RA M CK signal when hig h and deactivates the CK signal when low.

By deactivating the clocks, CKE low initiates the Power Down mode or the Self Refresh

mode.

S[1:0] Input Active

Low

Enables the associated DDR2 SDRAM command decoder when low and disables the com-

mand decoder when high. When the command decoder is disabled, new commands are

ignored but previous operations continue. Rank 0 is s e lec ted by S0; Rank 1 is selected by

S1

RAS, CAS, WE Input Active

Low When sampled at the c ross poi nt of the rising ed ge of CK and falling ed ge of CK, CAS, RAS

and WE define the operation to be executed by the SDRAM.

BA[1:0] Input Selects which DDR2 SDRAM internal bank of four is activated.

ODT[1:0] Input Active

High Asserts on-die terminat ion for DQ, DM, DQS and DQS signals if enabled via the DDR2

SDRAM mode register.

A[9:0], A10/AP,

A[15:11] Input

During a Bank Activate command cycle, defines the row address when sampled at the

cross point of the rising edge of CK and falling edge of CK. During a Read or Write com-

mand cycle, defi nes the column add ress when sampled at the cross p oint of the rising

edge of CK and falling edge of CK. In addition to the co lumn addr ess, AP is us ed to in vo ke

autoprecharge operation at the end of the burst read or write cycle. If AP is high. , autopre-

charge is selected and BA0-BAn defines the bank to be precharged. If AP is low, autopre-

charge is disabled. During a Precharge command cycle., AP is used in conjunction with

BA0-BAn to contr ol whic h bank(s) to pr echarg e. If AP is high, all banks will be pr echar ged

regardless of the state of BA0-BAn inputs. If AP is low, then BA0-BAn are used to define

which bank to precharge.

DQ[63:0] In/Out Data Input/Output pins.

DM[7:0] Input Active

High

The data write masks, asso ciated with one data b yte. In Write mode, DM operates as a

byte mask by allowing input data to be written if it is low but blocks the write operation if

it is high. In Read mode, DM lines have no effect.

DQS[7:0], DQS[7:0] In/Out Cross

point

The data strobe, associated with one data byte, sourced whit data transfers. In Write

mode, the data strobe is sourced by the controller and is centered in the data window. In

Read mode, the data strobe is sourced by the DDR2 SDRAMs and is sent at leading edge

of the data window . DQS signals ar e complements, and timing is r elativ e to the cro sspoi nt

of respective DQS and DQS. If the module is to be operated in single ended strobe mode,

all DQS signals m ust be tied on the system boar d to VS S and DDR2 SDRAM mode registers

progr a mmed appropriately.

VDD, VDDSPD,VSS Supply Power supplies for core, I/O, Seria l P resense Detect, and g rou nd for the module.

SDA In/Out This is a bidirectional pin used to transfer data into or out of the SPD EEPROM. A resister

must be connected to VDD to act as a pull up.

SCL Input This signals is used to clock data into and out of the SPD EEPROM. A resistor may be con-

nected from SCL to VDD to act as a pull up.

SA[1:0] Input Address pi ns used to select the Serial Presence Detect base address.

TEST In/Out The TEST pin is reserved for bus analysis tools and is not connected on normal memory

modules (SODIMMs).

Rev. 0.6 / Dec. 2008 4

1200pin Unbuffered DDR2 SDRAM SO-DIMMs

PIN ASSIGNMENT

Pin Location

NO. Front

Side Pin

NO. Back

Side Pin

NO. Front

Side Pin

NO. Back

Side Pin

NO. Front

Side Pin

NO. Back

Side Pin

NO. Front

Side Pin

NO. Back

Side

1 VREF 2 VSS 51 DQS2 52 DM2 101 A1 102 A0 151 DQ42 152 DQ46

3 VSS 4 DQ4 53 VSS 54 VSS 103 VDD 104 VDD 153 DQ43 154 DQ47

5 DQ0 6 DQ5 55 DQ18 56 DQ22 105 A10/AP 106 BA1 155 VSS 156 VSS

7 DQ1 8 VSS 57 DQ19 58 DQ23 107 BA0 108 RAS 157 DQ48 158 DQ52

9 VSS 10 DM0 59 VSS 60 VSS 109 WE 110 S0 159 DQ49 160 DQ53

11 DQS0 12 VSS 61 DQ24 62 DQ28 111 VDD 112 VDD 161 VSS 162 VSS

13 DQS0 14 DQ6 63 DQ25 64 DQ29 113 CAS 114 ODT0 163 NC,TEST 164 CK1

15 VSS 16 DQ7 65 VSS 66 VSS 115 NC/S1 116 A13 165 VSS 166 CK1

17 DQ2 18 VSS 67 DM3 68 DQS3 117 VDD 118 VDD 167 DQS6 168 VSS

19 DQ3 20 DQ12 69 NC 70 DQS3 119 NC/ODT1 120 NC 169 DQS6 170 DM6

21 VSS 22 DQ13 71 VSS 72 VSS 121 VSS 122 VSS 171 VSS 172 VSS

23 DQ8 24 VSS 73 DQ26 74 DQ30 123 DQ32 124 DQ36 173 DQ50 174 DQ54

25 DQ9 26 DM1 75 DQ27 76 DQ31 125 DQ33 126 DQ37 175 DQ51 176 DQ55

27 VSS 28 VSS 77 VSS 78 VSS 127 VSS 128 VSS 177 VSS 178 VSS

29 DQS1 30 CK0 79 CKE0 80 NC/CKE1 129 DQS4 130 DM4 179 DQ56 180 DQ60

31 DQS1 32 CK0 81 VDD 82 VDD 131 DQS4 132 VSS 181 DQ57 182 DQ61

33 VSS 34 VSS 83 NC 84 NC/A15 133 VSS 134 DQ38 183 VSS 184 VSS

35 DQ10 36 DQ14 85 BA2 86 NC/A14 135 DQ34 136 DQ39 185 DM7 186 DQS7

37 DQ11 38 DQ15 87 VDD 88 VDD 137 DQ35 138 VSS 187 VSS 188 DQS7

39 VSS 40 VSS 89 A12 90 A11 139 VSS 140 DQ44 189 DQ58 190 VSS

41 VSS 42 VSS 91 A9 92 A7 141 DQ40 142 DQ45 191 DQ59 192 DQ62

43 DQ16 44 DQ20 93 A8 94 A6 143 DQ41 144 VSS 193 VSS 194 DQ63

45 DQ17 46 DQ21 95 VDD 96 VDD 145 VSS 146 DQS5 195 SDA 196 VSS

47 VSS 48 VSS 97 A5 98 A4 147 DM5 148 DQS5 197 SCL 198 SA0

49 DQS2 50 NC 99 A3 100 A2 149 VSS 150 VSS 199 VDDSPD 200 SA1

Front Back

139 41 199

240 200

42

Rev. 0.6 / Dec. 2008 5

1200pin Unbuffered DDR2 SDRAM SO-DIMMs

FUNCTIONAL BLOCK DIAGRAM

256MB(32Mbx64): HYMP532S64C(L)P6

CKE0

/S0

ODT0

D0

/C S O DT CKE

DQS0 LDQS

/DQS0 /UDQS

DM0 LDM

DQ0 I/O 0

DQ1 I/O 1

DQ2 I/O 2

DQ3 I/O 3

DQ4 I/O 4

DQ5 I/O 5

DQ6 I/O 6

I/O 7

DQ7

DQS1 UDQS

/DQS1 /UDQ S

DM1 UDM

DQ8

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

D1

/C S O DT CKE

DQS2 LDQS

/DQS2 /LDQS

DM2 LDM

DQ16 I/O 0

DQ17 I/O 1

DQ18 I/O 2

DQ19 I/O 3

DQ20 I/O 4

DQ21 I/O 5

DQ22 I/O 6

I/O 7

DQ23

DQS3 UDQS

/DQS3 /U DQ S

DM3 UDM

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

SCL SDA

A0

A1

A2

Serial PD

SCL SDA

WP

SA0

SA1

DQS5

/DQS5

DM5 DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

D3

/C S O DT CKE

DQS6 LDQS

/DQS6 /LDQS

DM6 LDM

DQ48 I/O 0

DQ49 I/O 1

DQ50 I/O 2

DQ51 I/O 3

DQ52 I/O 4

DQ53 I/O 5

DQ54 I/O 6

I/O 7

DQ55

DQS7 UDQS

/DQS7 /UDQS

DM7 UDM

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

D2

/C S O DT CKE

DQS4 LDQS

/DQS4 /LD Q S

DM4 LDM

DQ32 I/O 0

DQ33 I/O 1

DQ34 I/O 2

DQ35 I/O 3

DQ36 I/O 4

DQ37 I/O 5

DQ38 I/O 6

I/O 7

DQ39

/S1 N.C.

ODT1 N.C.

CKE1 N.C.

3Ω+/− 5%

BA0-BA1

3Ω +/- 5%

A0-AN

/RAS

/CAS

/W E

SDRAMS D0-3

2 loads

CK0

/CK0

2 loads

CK1

/CK1

I/O 8

I/O 9

I/O 1 0

I/O 1 1

I/O 1 2

I/O 1 3

I/O 1 4

I/O 1 5

I/O 8

I/O 9

I/O 1 0

I/O 1 1

I/O 1 2

I/O 1 3

I/O 1 4

I/O 1 5

I/O 8

I/O 9

I/O 1 0

I/O 1 1

I/O 1 2

I/O 1 3

I/O 1 4

I/O 1 5

UDQS

/UD QS

UDM

I/O 8

I/O 9

I/O 1 0

I/O 1 1

I/O 1 2

I/O 1 3

I/O 1 4

I/O 1 5

VDD SPD

VDD

VREF

VSS

Serial PD

SDRAMS DO-D3

SDRAMS DO-D3, VDD and VDDQ

SDR AMS DO -D3, SPD

1. Resistor values are 22 Ohm +/- 5%

Notes :

Rev. 0.6 / Dec. 2008 6

1200pin Unbuffered DDR2 SDRAM SO-DIMMs

FUNCTIONAL BLOCK DIAGRAM

512MB(64Mbx64): HYMP564S64C(L)P6

CKE0

/S0

/S1

DQS0

/DQS0

DM0 DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQS1

/DQS1

DM1

DQ8

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQS2

/DQS2

DM2 DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQS3

/DQS3

DM3 DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

SCL SDA

A0

A1

A2

Serial PD

SCL SDA

WP

SA0

SA1

DQS5

/DQS5

DM5

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DQS6

/DQS6

DM6 DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DQS7

/DQS7

DM7 DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

DQS4

/DQS4

DM4 DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

3Ω+/− 5%

BA0 - BA1 3Ω +/- 5%

A0-AN

/RAS

/CAS

/WE

SDRAMS D 0 -7

VDD SPD

VDD

VREF

VSS

Serial PD

SDRAMS DO-D3

SDRAMS DO-D3, VDD a nd VDDQ

SDRAMS DO-D3, SPD

4 loads

CK0

/CK0

4 loads

CK1

/CK1

D0

/CS

LDQS

/UDQS

LDM

I/ O 0

I/ O 1

I/ O 2

I/ O 3

I/ O 4

I/ O 5

I/ O 6

I/O 7

UDQS

/UDQS

UDM

D1

LDQS

/LDQS

LDM

I/ O 0

I/ O 1

I/ O 2

I/ O 3

I/ O 4

I/ O 5

I/ O 6

I/ O 7

UDQS

/UDQS

UDM

I/ O 8

I/ O 9

I/ O 10

I/ O 11

I/ O 12

I/ O 13

I/ O 14

I/ O 15

I/ O 8

I/ O 9

I/ O 10

I/ O 11

I/ O 12

I/ O 13

I/ O 14

I/ O 15

CKE

ODT

/CS

CKE

ODT

D4

/CS

LDQS

/UDQS

LDM

I/ O 0

I/ O 1

I/ O 2

I/ O 3

I/ O 4

I/ O 5

I/ O 6

I/ O 7

UDQS

/UDQS

UDM

I/ O 8

I/ O 9

I/ O 10

I/ O 11

I/ O 12

I/ O 13

I/ O 14

I/ O 15

CKE

ODT

D5

/CS

LDQS

/UDQS

LDM

I/ O 0

I/ O 1

I/ O 2

I/ O 3

I/ O 4

I/ O 5

I/ O 6

I/ O 7

UDQS

/UDQS

UDM

I/ O 8

I/ O 9

I/ O 10

I/ O 11

I/ O 12

I/ O 13

I/ O 14

I/ O 15

CKE

ODT

D2

/CS

LDQS

/UDQS

LDM

I/ O 0

I/ O 1

I/ O 2

I/ O 3

I/ O 4

I/ O 5

I/ O 6

I/ O 7

UDQS

/UDQS

UDM

D3

LDQS

/LDQS

LDM

I/ O 0

I/ O 1

I/ O 2

I/ O 3

I/ O 4

I/ O 5

I/ O 6

I/ O 7

UDQS

/UDQS

UDM

I/ O 8

I/ O 9

I/ O 10

I/ O 11

I/ O 12

I/ O 13

I/ O 14

I/ O 15

I/ O 8

I/ O 9

I/ O 10

I/ O 11

I/ O 12

I/ O 13

I/ O 14

I/ O 15

CKE

ODT

/CS

CKE

ODT

D6

/CS

LDQS

/UDQS

LDM

I/ O 0

I/ O 1

I/ O 2

I/ O 3

I/ O 4

I/ O 5

I/ O 6

I/ O 7

UDQS

/UDQS

UDM

I/ O 8

I/ O 9

I/ O 10

I/ O 11

I/ O 12

I/ O 13

I/ O 14

I/ O 15

CKE

ODT

D7

/CS

LDQS

/UDQS

LDM

I/ O 0

I/ O 1

I/ O 2

I/ O 3

I/ O 4

I/ O 5

I/ O 6

I/ O 7

UDQS

/UDQS

UDM

I/ O 8

I/ O 9

I/ O 10

I/ O 11

I/ O 12

I/ O 13

I/ O 14

I/ O 15

CKE

ODT

CKE1

ODT0

ODT1

1. Resistor values are 22 Ohm +/- 5%

Notes :

Rev. 0.6 / Dec. 2008 7

1200pin Unbuffered DDR2 SDRAM SO-DIMMs

FUNCTIONAL BLOCK DIAGRAM

1GB(128Mbx64): HYMP512S64C(L)P8

CKE0

S0

S1

SA0 SDA

A0

A1

A2

Serial Presense

Detect (SPD)

SCL

Event/WP

3 Ω +/- 5%

BA0 - BA2

10 Ω +/-5%

A0-AN SD RAMS

VDD SPD

VDD

VREF

SPD

SDRAMS DO -D15

, VDD and VDDQ

, SPD

8loads

CK0

/CK0

8loads

CK1

/CK1

ODT1

CKE

ODT1

1

0

DM0 DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

D1

CS0

DQS

DM

I/ O 0

I/ O 1

I/ O 2

I/ O 3

I/ O 4

I/ O 5

I/ O 6

I/ O 7

DQS1

DM1 DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

ODT0 CKE0

D10

CS0

DQS

DM

I/ O 0

I/ O 1

I/ O 2

I/ O 3

I/ O 4

I/ O 5

I/ O 6

I/ O 7

DQS2

DM2 DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

ODT0 CKE0

D11

CS0

DQS

DM

I/ O 0

I/ O 1

I/ O 2

I/ O 3

I/ O 4

I/ O 5

I/ O 6

I/ O 7

DQS3

DM3 DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

ODT0 CKE0

D0

DQS

DM

I/ O 0

I/ O 1

I/ O 2

I/ O 3

I/ O 4

I/ O 5

I/ O 6

I/ O 7

ODT0 CKE0

D8

CS1

DQS

DM

I/ O 0

I/ O 1

I/ O 2

I/ O 3

I/ O 4

I/ O 5

I/ O 6

I/ O 7

ODT1 CKE1

D9

CS1

DQS

DM

I/ O 0

I/ O 1

I/ O 2

I/ O 3

I/ O 4

I/ O 5

I/ O 6

I/ O 7

ODT1 CKE1

D2

CS1

DQS

DM

I/ O 0

I/ O 1

I/ O 2

I/ O 3

I/ O 4

I/ O 5

I/ O 6

I/ O 7

ODT1 CKE1

D3

CS1

DQS

DM

I/ O 0

I/ O 1

I/ O 2

I/ O 3

I/ O 4

I/ O 5

I/ O 6

I/ O 7

ODT1 CKE1

DQS4

DM4

D5

CS0

DQS

DM

I/ O 0

I/ O 1

I/ O 2

I/ O 3

I/ O 4

I/ O 5

I/ O 6

I/ O 7

DQS5

DM5 DQ

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

ODT0 CKE0

D14

CS0

DQS

DM

I/ O 0

I/ O 1

I/ O 2

I/ O 3

I/ O 4

I/ O 5

I/ O 6

I/ O 7

DQS6

DM6 DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

ODT0 CKE0

D15

CS0

DQS

DM

I/ O 0

I/ O 1

I/ O 2

I/ O 3

I/ O 4

I/ O 5

I/ O 6

I/ O 7

DQS7

DM7 DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

ODT0 CKE0

D4

CS0

DQS

DM

I/ O 0

I/ O 1

I/ O 2

I/ O 3

I/ O 4

I/ O 5

I/ O 6

I/ O 7

ODT0 CKE0

D12

CS1

DQS

DM

I/ O 0

I/ O 1

I/ O 2

I/ O 3

I/ O 4

I/ O 5

I/ O 6

I/ O 7

ODT1 CKE1

D13

CS1

DQS

DM

I/ O 0

I/ O 1

I/ O 2

I/ O 3

I/ O 4

I/ O 5

I/ O 6

I/ O 7

ODT1 CKE1

D6

CS1

DQS

DM

I/ O 0

I/ O 1

I/ O 2

I/ O 3

I/ O 4

I/ O 5

I/ O 6

I/ O 7

ODT1 CKE1

D7

CS1

DQS

DM

I/ O 0

I/ O 1

I/ O 2

I/ O 3

I/ O 4

I/ O 5

I/ O 6

I/ O 7

ODT1 CKE1

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DQ41

40

/

////

//

/

/DQS0

DQS

/RAS

/CAS

/WE

D0-D15

SDRAMS D0-D15

/DQS /CS0

/

//

/

///

////

/

/////

/

SDRAMS DO -D15

SA1

SA2

Notes:

For normal operation only R(WP) is placed.

For the SPD temperture sensor option

only R(Event) is placed.

#Unless otherwise note d, resistor val ues

are 22 Ω⎣+/- 5% DQ wiring may differ from

that described in this draw in g;described

in this drawing; howev er, DQ/D M/D Q S/DQS

relationships are maintain ed as shown

WP

Event

R(WP) = 0Ω

R(Event) = 0Ω

5.6 pF

Rev. 0.6 / Dec. 2008 8

1200pin Unbuffered DDR2 SDRAM SO-DIMMs

ABSOLUTE MAXIMUM RATINGS

Notes:

1. Stress greater than those listed may cause permanent dama ge to the device. This is a stress r ating only, and device

functional operation at or above the conditions indicated is not implied. Exposure to absolute maximum rating con

ditions for extended periods may affect reliability.

OPERATING CONDITIONS

Notes:

1. Up to 9850 ft.

2. If the DRAM case temperature is Above 85oC, the Auto-Refresh command interval has to be reduced to

tREFI=3.9us. For Measurement conditions of TCASE, please refer to the JEDEC document JESD51-2.

DC OPERATING CONDITIONS (SSTL_1.8)

Notes:

1. VDDQ must be less than or equal to VDD.

2. Peak to peak ac noise on VREF may not exceed +/-2% VREF(dc)

3. VTT of transmitting device must track VREF of receiving device.

Parameter Symbol Value Unit Note

Voltage on VDD pin relative to Vss VDD - 1.0 ~ 2.3 V 1

Voltage on VDDL pin relative to Vss VDDL -0.5 ~ 2.3 V 1

Voltage on VDDQ pin relative to Vss VDDQ - 0.5 ~ 2.3 V 1

Voltage on any pin relative to Vss VIN, VOUT - 0.5 ~ 2.3 V 1

Storage Temperature TSTG -50 ~ +100 oC1

Storage Humidity (without condensation) HSTG 5 ~ 95 % 1

Parameter Symbol Rating Units Notes

DIMM Operating temperature (ambient) TOPR 0 ~ +55 oC

DIMM Barometric Pressure (operating & storage) PBAR 105 ~ 69 K Pascal 1

DRAM Component Case Temperature Range TCASE 0 ~+95 oC2

Parameter Symbol Min Max Unit Note

Power Supply Voltage

VDD 1.7 1.9 V

VDDL 1.7 1.9 V

VDDQ 1.7 1.9 V 1

Input Reference Voltage VREF 0.49 x VDDQ 0.51 x VDDQ V2

EEPROM Supply Voltage VDDSPD 1.7 3.6 V

Termination Voltage VTT VREF-0.04 VREF+0.04 V 3

Rev. 0.6 / Dec. 2008 9

1200pin Unbuffered DDR2 SDRAM SO-DIMMs

INPUT DC LOGIC LEVEL

INPUT AC LOGIC LEVEL

AC INPUT TEST CONDITIONS

Notes:

1. Input waveform timing is referenced to the input signal crossing through the VREF level applied to the device

under test.

2. The input signal minimum slew rate is to be maintained over the range from VREF to VIH(ac) min for rising edges

and the range from VREF to VIL(ac) max for falling edges as shown in the below figure.

3. AC timings are referenced with input waveforms switching from VIL (ac) to VIH (ac) on the positive transitions

and VIH (ac) to VIL (ac) on the negative transitions.

Parameter Symbol Min Max Unit Note

Input High Voltage VIH(DC) VREF + 0.125 VDDQ + 0.3 V

Input Low Voltage VIL(DC) -0.30 VREF - 0.125 V

Parameter Symbol DDR2 400/533 DDR2 667/800 Unit

Min Max Min Max

AC Input logic High VIH(AC) VREF + 0.250 - VREF + 0.200 - V

AC Input logic Low VIL(AC) -V

REF - 0.250 - VREF - 0.200 V

Symbol Condition Value Units Notes

VREF Input reference voltage 0.5 * VDDQ V1

VSWING(MAX) Input signal maximum peak to peak swing 1.0 V 1

SLEW Input signal minimum slew rate 1.0 V/ns 2, 3

VDDQ

VIH(ac) min

VIH(dc) min

VREF

VIL(dc) max

VIL(ac) max

VSS

V

SWING(MAX)

delta TRdelta TF

VREF

-

VIL

(ac)

max

delta TF

Falling Slew = Rising Slew =

VIH

(ac)

min

- V

REF

delta TR

< Figure: AC Input Test Signal Waveform>

Rev. 0.6 / Dec. 2008 10

1200pin Unbuffered DDR2 SDRAM SO-DIMMs

Differential Input AC logic Level

1. VIN(DC) specifies the allowable DC execution of each input of differential pair such as CK, CK, DQS, DQS, LDQS,

LDQS, UDQS and UDQS.

2. VID(DC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input

(such as CK, DQS, LDQS or UDQS) level and VCP is the complementary input (such as CK, DQS, LDQS or UDQS) level.

The minimum value is equal to VIH(DC) - VIL(DC).

Notes:

1. VID(AC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input signal

(such as CK, DQS, LDQS or UDQS) and VCP is the complementary input signal (such as CK, DQS, LDQS or UDQS).

The minimum value is equal to V IH(AC) - VIL(AC).

2. The typical value of VIX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VIX(AC) is expected to

track variations in VDDQ. VIX(AC) indicates the voltage at which differential input signals must cross.

DIFFERENTIAL AC OUTPUT PARAMETERS

Notes:

1. The typical v a lue of V OX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VOX(AC) is expected to

track variations in VDDQ. VOX(AC) indicates the voltage at which differential output signals must cross.

Symbol Parameter Min. Max. Units Note

VID (ac) ac differential input voltage 0.5 VDDQ + 0.6 V 1

VIX (ac) ac differential cross point voltage 0.5 * VDDQ - 0.175 0.5 * VDDQ + 0.175 V 2

Symbol Parameter Min. Max. Units Note

VOX (ac) ac differential cross point voltage 0.5 * VDDQ - 0.125 0.5 * VDDQ + 0.125 V 1

VDDQ

Crossing point

VSSQ

VTR

VCP

VID VIX or VOX

< Differential signal levels >

Rev. 0.6 / Dec. 2008 11

1200pin Unbuffered DDR2 SDRAM SO-DIMMs

OUTPUT BUFFER LEVELS

OUTPUT AC TEST CONDITIONS

Notes:

1. The VDDQ of the device under test is referenced.

OUTPUT DC CURRENT DRIVE

Notes:

1. VDDQ = 1.7 V; VOUT = 1420 mV. (VOUT - VDDQ)/IOH must be less than 21 ohm for values of VOUT between VDDQ and

VDDQ - 280 mV.

2. VDDQ = 1.7 V; VOUT = 280 mV. VOUT/IOL must be less than 21 ohm for values of VOUT between 0 V and 280 mV.

3. The dc value of VREF applied to the receiving device is set to VTT

4. The values of IOH(dc) and IOL(dc) are based on the conditions given in Notes 1 and 2. They are used to test device

drive current capability to ensure VIH min plus a noise margin and VIL max minus a noise margin are delivered to an

SSTL_18 receiver.

The actual current values are derived by shifting the desired driver oper at ing point alon g a 21 oh m load line to def ine

a convenient driver current for measurement.

Symbol Parameter SSTl_18 Units Notes

VOTR Output Timing Measurement Reference Level 0.5 * VDDQ V1

Symbol Parameter SSTl_18 Units Notes

IOH(dc) Output Minimum Source DC Current - 13.4 mA 1, 3, 4

IOL(dc) Output Minimum Sink DC Current 13.4 mA 2, 3, 4

Rev. 0.6 / Dec. 2008 12

1200pin Unbuffered DDR2 SDRAM SO-DIMMs

PIN Capacitance (VDD=1.8V,VDDQ=1.8V, TA=25℃. f=1MHz)

256MB: HYMP532S64C[L]P6

512MB: HYMP564S64C[L]P6

1GB: HYMP512S64C[L]P8

Notes:

1. Pins not under test are tied to GND.

2. These values are guaranteed by design and tested on a sample basis only.

Pin Symbol Min Max Unit

CK, CK CCK 12 15 pF

CKE, ODT,CS CI1 27 30 pF

Address, RAS, CAS, WE CI2 25 32 pF

DQ, DM, DQS, DQS CIO 6.0 7.5 pF

Pin Symbol Min Max Unit

CK, CK CCK 17 20 pF

CKE, ODT,CS CI1 22 25 pF

Address, RAS, CAS, WE CI2 28.5 37.0 pF

DQ, DM, DQS, DQS CIO 10.0 12.0 pF

Pin Symbol Min Max Unit

CK, CK CCK 25 49 pF

CKE, ODT,CS CI1 32 58 pF

Address, RAS, CAS, WE CI2 47 96 pF

DQ, DM, DQS, DQS CIO 16 20 pF

Rev. 0.6 / Dec. 2008 13

1200pin Unbuffered DDR2 SDRAM SO-DIMMs

IDD SPECIFICATIONS (TCASE: 0 to 95oC)

256MB, 32M x 64 SO- DIMM: HYMP532S64C[L]P6

512MB, 64M x 64 SO - DIMM: HYMP564S64C[L]P6

Notes:

1. IDD6 current values are guaranteed up to Tcase of 85℃ max.

Symbol E3

(DDR 400@CL 3) C4

(DDR 533@CL 4) Y5

(DDR 667@CL 5) S5

(DDR 800@CL 5) Unit note

IDD0 400 400 400 480 mA

IDD1 440 440 480 520 mA

IDD2P 32 32 32 32 mA

IDD2Q 120 120 160 160 mA

IDD2N 120 160 160 200 mA

IDD3P(F) 120 120 120 140 mA

IDD3P(S) 48 48 48 48 mA

IDD3N 160 200 200 240 mA

IDD4W 520 680 800 960 mA

IDD4R 440 600 680 800 mA

IDD5B 600 600 640 660 mA

IDD6 32 32 32 32 mA 1

IDD6(L) 16 16 16 16 mA 1

IDD7 1280 1280 1280 1360 mA

Symbol E3

(DDR 400@CL 3) C4

(DDR 533@CL 4) Y5

(DDR 667@CL 5) S5

(DDR 800@CL 5) Unit note

IDD0 560 600 640 720 mA

IDD1 600 640 680 760 mA

IDD2P 64 64 64 64 mA

IDD2Q 240 240 320 320 mA

IDD2N 240 320 320 400 mA

IDD3P(F) 240 240 240 280 mA

IDD3P(S) 96 96 96 96 mA

IDD3N 320 400 400 480 mA

IDD4W 680 880 1000 1200 mA

IDD4R 600 800 880 1040 mA

IDD5B 760 800 840 900 mA

IDD6 64 64 64 64 mA 1

IDD6(L) 32 32 32 32 mA 1

IDD7 1440 1480 1480 1600 mA

Rev. 0.6 / Dec. 2008 14

1200pin Unbuffered DDR2 SDRAM SO-DIMMs

1GB, 128M x 64 SO - DIMM: HYMP512S64C[L]P8

Notes:

1. IDD6 current values are guaranteed up to Tcase of 85℃ max.

Symbol E3

(DDR 400@CL 3) C4

(DDR 533@CL 4) Y5

(DDR 667@CL 5) S5

(DDR 800@CL 5) Unit note

IDD0 960 1040 1120 1280 mA

IDD1 960 1120 1120 1280 mA

IDD2P 128 128 128 128 mA

IDD2Q 480 480 640 640 mA

IDD2N 480 640 640 800 mA

IDD3P(F) 480 480 480 560 mA

IDD3P(S) 192 192 192 192 mA

IDD3N 640 800 800 960 mA

IDD4W 1120 1440 1600 1920 mA

IDD4R 1040 1280 1520 1760 mA

IDD5B 1520 1600 1680 1800 mA

IDD6 128 128 128 128 mA 1

IDD6(L) 64 64 64 64 mA 1

IDD7 2000 2080 2160 2320 mA

Rev. 0.6 / Dec. 2008 15

1200pin Unbuffered DDR2 SDRAM SO-DIMMs

IDD Measurement Conditions

Notes:

1. IDD specifications are tested after the device is properly initialized

2. Input slew rate is specified by AC Parametric Test Condition

3. IDD parameters are specified with ODT disabled.

4. Data bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS, and UDQS . IDD values must be met with all combinations

of EMRS bits 10 and 11.

5. Definiti ons for IDD

LOW is defined as Vin ≤ VILAC (max)

HIGH is defined as Vin ≥ VIHAC (min)

STABLE is defined as inputs stable at a HIGH or LOW level

FLOATING is defined as in puts at VREF = VDDQ/2

SWITCHING is defined as: inputs changing between HIGH and LOW every other clock cycle (once per two clocks) for address and

control signals, and inputs changing between HIGH and LOW every other data transfer (once per clock)

for DQ signals not including masks or strobes.

Symbol Conditions Units

IDD0 Operating one bank active-precharge current; tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin

(IDD);CKE is HIGH, CS is HIGH between val id commands; Addr ess bus inputs ar e SWIT CHING; Data bus inputs

are SWITCHING mA

IDD1 Operating one bank active-read-precharge current; IOUT = 0mA;BL = 4, CL = CL(IDD), AL = 0;

tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin (IDD), tRCD = tRCD(IDD); CKE is HIGH, CS is HIGH

between valid command s; A d dress bus inputs are SWITCHING; Data pattern is same as IDD4W mA

IDD2P Precharge power-down current; All banks idle; tCK = tCK(IDD); CKE is LOW ; Other co ntrol and address bus

inputs are STABLE; Data bus inputs are FLOATING mA

IDD2Q Precharge quiet standby current; All ba nks idle; tCK = tCK(IDD);CKE is HIGH, CS is HIGH; Other control

and address bus inputs are STABLE; Data bus inputs are FLOATING mA

IDD2N Precharge standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH, CS is HIGH; Othe r co ntrol and

address bus inputs are SWITCHING; Data bus inputs are SWITCHING mA

IDD3P Active power-down current; All banks open; tCK = tCK(IDD); CKE is LOW;

Other control and address bus inputs are STABLE; Data bus inputs are FLOAT-

ING

Fast PDN Exit MRS(12) = 0 mA

Slow PDN Exit MRS(12) = 1 mA

IDD3N Active standby current; All banks open; tCK = tCK(IDD), tRAS = tRASmax (IDD), tRP =tRP(IDD); CKE is

HIGH, CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus

inputs are SWITCHING mA

IDD4W Operating burst write current; All banks open, Continuo us bur st wr ites ; BL = 4 , CL = CL(ID D), AL = 0; tCK

= tCK(IDD), tRAS = tRASmax (IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands;

Address bus inputs are SWITCHING; Data bus inputs are SWITCHING mA

IDD4R Operating burst read current; All bank s open, Cont inuou s burst r eads, IOUT = 0mA; BL = 4, CL = CL(IDD),

AL = 0; tCK = tCK(IDD), tRAS = tRASmax (IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid com-

mands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W mA

IDD5B Burst refresh current; tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH, CS is

HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are

SWITCHING mA

IDD6 Self refresh current; CK and CK at 0V; CKE ≤ 0.2V ; Other cont rol and addr ess bus inputs are FL OATING; Data

bus inputs are FLOATING. IDD6 current values are guaranteed up to Tcase of 85℃ max. mA

IDD7

Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD),

AL = tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD), tRCD = 1*tCK(IDD); CKE is

HIGH, CS is HIGH between v alid c ommands; Addr ess bus inputs are STABLE during DESELECTs; Data pattern is

same as IDD4R; - Refer to the following page for detailed timing conditions

mA

Rev. 0.6 / Dec. 2008 16

1200pin Unbuffered DDR2 SDRAM SO-DIMMs

Electrical Characteristics & AC Timings

Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin

AC Timing Parameters by Spe ed Grade

Speed DDR2-800 DDR2-800 DDR2-667 DDR2-533 DDR2-400 Unit

Bin (CL-tRCD-tRP) 6-6-6 5-5-5 5-5-5 3-3-3 4-4-4

Parameter min min min min min

CAS Latency 65535

tCK

tRCD 15 12.5 15 11.25 15 ns

tRP 15 12.5 15 11.25 15 ns

tRAS 45 45 45 45 40 ns

tRC 60 57.25 60 56.25 55 ns

Parameter Symbol DDR2-400 DDR2-533 Unit Note

Min Max Min Max

Data-Out edge to Cl ock edge Skew tAC -600 +600 -500 500 ps

DQS-Out edge to Clock edge Skew tDQSCK -500 +500 -500 450 ns

Clock High Level Width tCH 0.45 0.55 0.45 0.55 CK

Clock Low Level Width tCL 0.45 0.55 0.45 0.55 CK

Clock Half Period tHP min(tCL,tCH) -min

(tCL, tCH) -ns

System Clock Cycle Time tCK 5000 8000 3750 8000 ps

DQ and DM input setup time(differential strobe) tDS 150 - 100 -ps 1

DQ and DM input hold time(differential strobe) tDH 275 - 225 -ps 1

DQ and DM input setup time(single ended strobe) tDS1 25 --25-ps 1

DQ and DM input hold time(single ended strobe) tDH1 25 --25-ps 1

Control & Address input Pulse Width for each input tIPW 0.6 -0.6 - tCK

DQ and DM input pulse width for each inp ut tDIPW 0.35 -0.35 - tCK

Data-out high-impedance window from CK, /CK tHZ -tAC max

-tAC max

ps

DQS low-impedance time from CK/CK tLZ(DQS) tAC min tAC max tAC min tAC max ps

DQ low-impedance time from CK/CK tLZ(DQ) 2*tAC min tAC max 2*tAC min tAC max ps

DQS-DQ skew for DQS and associated DQ signals tDQSQ - 350 - 300 ps

DQ hold skew factor tQHS - 450 - 400 ps

DQ/DQS output hold time from DQS tQH tHP - tQHS -tHP - tQHS -ps

First DQS latching transition to associated clock edge tDQSS -0.25 + 0.25 -0.25 + 0.25 tCK

DQS input high pulse width tDQSH 0.35 -0.35 -tCK

DQS input low pulse width tDQSL 0.35 -0.35 -tCK

Rev. 0.6 / Dec. 2008 17

1200pin Unbuffered DDR2 SDRAM SO-DIMMs

- continued -

Parameter Symbol DDR2-400 DDR2-533 Unit Note

Min Max Min Max

DQS falling edge to CK setup time tDSS 0.2 -0.2 -tCK

DQS falling edge hold time from CK tDSH 0.2 -0.2 -tCK

Mode register set command cycle time tMRD 2 - 2 - tCK

Write postamble tWPST 0.4 0.6 0.4 0.6 tCK

Write preamble tWPRE 0.35 -0.35 -tCK

Address and control input setup ti me tIS 350 -250-ps

Address and control input hold time tIH 475 -375-ps

Read pre amble tRPRE 0.9 1.1 0.9 1.1 tCK

Read postamb le tRPST 0.4 0.6 0.4 0.6 tCK

Auto-Refresh to Active/Auto-Refresh command

period tRFC 105 -105 -ns

Row Active to Row Active Delay for 1KB page size tRRD 7.5 -7.5 - ns

Row Active to Row Active Delay for 2KB page size tRRD 10 -10 - ns

Four Activate Window for 1KB page size tFAW 37.5 -37.5 - ns

Four Activate Window for 2KB page size tFAW 50 -50 - ns

CAS to CAS command delay tCCD 2 2 tCK

Write recovery time tWR 15 -15-ns

Auto Precharge Write Recovery + Precharge Time tDAL WR+tRP -tWR + tRP - tCK

Write to Read Command Delay tWTR 10 -7.5-ns

Internal read to precharge command delay tRTP 7.5 7.5 ns

Exit self refre sh to a non-read command tXSNR tRFC + 10 tRFC + 10 ns

Exit self refre sh to a read command tXSRD 200 -200 -tCK

Exit precharge power down to an y non-read

command tXP 2 - 2 - tCK

Exit active power down to read command tXARD 2 2 tCK

Exit active power down to read command

(Slow exit, Lower power) tXARDS 6 - AL 6 - AL tCK

CKE minimum pulse width

(high and low pulse width) tCKE 3 3 tCK

ODT turn-on delay tAOND 2222

tCK

ODT turn-on tAON tAC (min) tAC(max)+1 tAC (min) tAC(max)+1 ns

ODT turn-on (Power-Down mode) tAONPD tAC(min)+2 2tCK+

tAC(max)+1 tAC(min)+2 2tCK+tAC(m

ax)+1 ns

ODT turn-off delay tAOFD 2.5 2.5 2.5 2.5 tCK

ODT turn-off tAOF tAC (min) tAC(max)+0

.6 tAC (min) tAC (max)+

0.6 ns

ODT turn-off (Power-Down mode) tAOFPD 2.5 2.5 tAC(min)+2 2.5tCK+tAC(

max)+1 ns

Rev. 0.6 / Dec. 2008 18

1200pin Unbuffered DDR2 SDRAM SO-DIMMs

- continued -

Note:

1. For details and notes, please refer to the relevant Hynix component datasheet(HY5PS128(16)21C[L]FP).

2. 0°C ≤ TCASE ≤ 85°C

3. 85°C ＜ TCASE ≤ 95°C

Parameter Symbol DDR2-400 DDR2-533 Unit Note

Min Max Min Max

ODT to power down entry latency tANPD tAC (min) tAC(max)+0.

63tCK

ODT power down exit latency tAXPD tAC(min)+2 2.5tCK+

tAC(max)+1 8tCK

OCD drive mode output delay tOIT 3012

ns

Minimum time clocks remains ON after

CKE asynchronously drops LOW tDelay 8 tIS + tCK + tIH ns

Average periodic Refresh Interval tREFI -7.8-7.8us 2

tREFI -3.9 -3.9 us 3

Rev. 0.6 / Dec. 2008 19

1200pin Unbuffered DDR2 SDRAM SO-DIMMs

Parameter Symbol DDR2-667 DDR2-800 Unit Note

min max min max

DQ output access time from CK/CK tAC -450 +450 -400 +400 ps

DQS output access time from CK/CK tDQSCK -400 +400 -350 +350 ps

CK high-level width tCH 0.45 0.55 0.45 0.55 tCK

CK low-level width tCL 0.45 0.55 0.45 0.55 tCK

CK half period tHP min(tCL,

tCH) -min(tCL,

tCH) -ps

Clock cycle time, CL=x tCK 3000 8000 2500 ps

DQ and DM inpu t setup time

(differen t ial strobe ) tDS 100 - 50 -ps 1

DQ and DM input hold time

(differen t ial strobe ) tDH 175 - 125 -ps 1

Control & Address input pulse width for each

input tIPW 0.6 - 0.6 -tCK

DQ and DM input pulse width for each input tDIPW 0.35 - 0.35 -tCK

Data-out high-impe dan ce time from CK/CK tHZ - tAC max - tAC max ps

DQS low-impedance time from CK/C K tLZ(DQS) tAC min tAC max tAC min tAC max ps

DQ low-impedance time from CK/CK tLZ(DQ) 2*tAC min tAC max 2*tAC min tAC max ps

DQS-DQ skew for DQS and associated DQ

signals tDQSQ - 240 -200ps

DQ hold skew factor tQHS - 340 -300ps

DQ/DQS output hold time from DQS tQH tHP - tQHS -tHP - tQHS -ps

First DQS latching transition to associated

clock edge tDQSS - 0.25 + 0.25 - 0.25 + 0.25 tCK

DQS input high pulse width tDQSH 0.35 -0.35 -tCK

DQS input low pulse width tDQSL 0.35 -0.35 -tCK

DQS falling edge to CK setup time tDSS 0.2 -0.2 -tCK

DQS falling edge hold time from CK tDSH 0.2 -0.2 -tCK

Mode register set com mand cycle time tMRD 2 - 2 - tCK

Write postamble tWPST 0.4 0.6 0.4 0.6 tCK

Write preamble tWPRE 0.35 -0.35 -tCK

Address and control input setup time tIS 200 - 175 -ps

Address and control input hold time tIH 275 - 250 -ps

Read pr eambl e tRPRE 0.9 1.1 0.9 1.1 tCK

Read postamble tRPST 0.4 0.6 0.4 0.6 tCK

Activate to precharge command tRAS 45 70000 45 70000 ns

Active to active command period for 1KB page

size products tRRD 7.5 -7.5-ns

Active to active command period for 2KB page

size products tRRD 10 -10-ns

Four Active Window for 1KB page size

products tFAW 37.5 -35 -ns

Four Active Window for 2KB page size

products tFAW 50 -45 -ns

Rev. 0.6 / Dec. 2008 20

1200pin Unbuffered DDR2 SDRAM SO-DIMMs

- continued -

Note:

1. For details and notes, please refer to the relevant Hynix component datasheet(HY5PS128(16)21C[L]FP).

2. 0°C ≤ TCASE ≤ 85°C

3. 85°C ＜ TCASE ≤ 95°C

Parameter Symbol DDR2-667 DDR2-800 Unit Note

min max min max

CAS to CAS command delay tCCD 2 2 tCK

Write recovery time tWR 15 -15-ns

Auto precharge write recovery +

precharge time tDAL WR+tRP -WR+tRP -tCK

Internal write to read command delay tWTR 7.5 -7.5-ns

Internal read to precharge command

delay tRTP 7.5 7.5 ns

Exit self refresh to a non-read command tXSNR tRFC + 10 tRFC + 10 ns

Exit self refresh to a read command tXSRD 200 -200 -tCK

Exit precharge power down to any non-

read command tXP 2 - 2 - tCK

Exit active power down to read command tXARD 2 2 tCK

Exit active power down to read command

(Slow exit, Lower power) tXARDS 7 - AL 8 - AL tCK

CKE minimum pulse width (high and low

pulse width) tCKE 33tCK

ODT turn-on delay tAOND 2222tCK

ODT turn-on tAON tAC (min) tAC(max)+0.7 tAC (min) tAC(max)+0.7 ns

ODT turn-on (Power-Down mode) tAONPD tAC(min)+2 2tCK+

tAC(max)+1 tAC(min)+2 2tCK+

tAC(max)+1 ns

ODT turn-off delay tAOFD 2.5 2.5 2.5 2.5 tCK

ODT turn-off tAOF tAC (min) tAC (max)+

0.6 tAC (min) tAC(max)+0.6 ns

ODT turn-off (Power-Down mode) tAOFPD tAC(min)+2 2.5tCK+

tAC(max)+1 tAC (min)

+2 2.5tCK+

tAC(max)+1 ns

ODT to power down entry latency tANPD 3 3 tCK

ODT power down exit latency tAXPD 8 8 tCK

OCD drive mode output delay tOIT 0 12 0 12 ns

Minimum time clocks remains ON after

CKE asynchronously drops LOW tDelay tIS + tCK +

tIH tIS + tCK +

tIH ns

Average periodic Refresh Interval tREFI - 7.8 - 7.8 us 2

tREFI -3.9 -3.9 us 3

Rev. 0.6 / Dec. 2008 21

1200pin Unbuffered DDR2 SDRAM SO-DIMMs

PACKAGE OUTLINE

32Mx64 - HYMP532S64C[L]P6

Front

67.60

2.00 Min

4.00±0.10

PIN 1 PIN 39 PIN 41 PIN 199

4.20

47.40

20.00

6.00

30.00

2.45 11.40 47.40

PIN 2 PIN 40 PIN 42 PIN 200

Back

3.8 max

1.00 ± 0.10

Side

note:

1 . A l l d imensio n s a r e in millimeters.

2 . A l l o u t lin e d ime n s io ns and tolera nce s fo llo w th e J E D EC sta ndard.

0.45±0.03

0.60

0.20±0.15

De ta il of C o n tac ts A

2.55

D eta il o f C o n ta c ts B (Fro n t)

1.0±0.05

4.00±0.10

4.20

2.70±0.10

Detail-A

Detail-B

4.20

2.40±0.10 1.80

1.50

De ta il of C o n tac ts B (Ba ck )

1.80±0.10

2.15

1.50±0.10

11.40

Rev. 0.6 / Dec. 2008 22

1200pin Unbuffered DDR2 SDRAM SO-DIMMs

PACKAGE OUTLINE

64Mx64 - HYMP564S64C[L]P6

Front

67.60

2.00 Min

4.00±0.10

PIN 1 PIN 39 PIN 41 PIN 199

11.40

1.80±0.10

4.20

47.40

20.00

6.00

30.00

2.45 11.40 47.40

PIN 2 PIN 40 PIN 42 PIN 200

Back

note:

1. All dimensions are in millimeters.

2. All outline dimensions and tolerances follow the JEDEC standard.

0.45±0.03

0.60

0.20±0.15

Detail of C ontacts A

2.55

Detail of Contacts B (Front)

1.0±0.05

4.00±0.10

4.20

2.70±0.10

4.20

2.40±0.10 1.80

1.50

Detail of Contacts B (Back)

Detail-B

Detail-A

3.8 max

1.00 ± 0.10

Side

2.15

1.50±0.10

Rev. 0.6 / Dec. 2008 23

1200pin Unbuffered DDR2 SDRAM SO-DIMMs

PACKAGE OUTLINE

128Mx64 - HYMP512S64C[L]P8

Front

67.60

2.00 Min

4.00 +/-0.10

PIN 1 PIN 39 PIN 41 PIN 199

4.20

47.40

20.00

6.00

30.00

2.45 11.40 47.40

PIN 2 PIN 200

Back

3.8 ma x

1.00 ± 0.10

Side

note:

1 . A ll dim e n s io ns a re in millimeters.

2 . A ll outline d imen s ions a n d t o le r a n c e s fo ll o w t h e J E DEC s tanda r d.

0.45±0.03

0.60

0.20±0.15

D eta il o f C o n ta cts A

2.55

De tail o f Co nta c ts B (Fron t)

1.0±0.05

4.00±0.10

4.20

2.70±0.10

Detail-B

4.20

2.40±0.10 1.80

1.50

D eta il o f C o n ta cts B (B a c k)

Detail-A

Detail-B

PIN 40 PIN 42

2.15 11.40

1.80±0.10

1.50±0.10

Rev. 0.6 / Dec. 2008 24

1200pin Unbuffered DDR2 SDRAM SO-DIMMs

REVISION HISTORY

Revision History Date Remark

0.1 First Version Release Jul. 2006

0.2 Added IDD Spec for S5(800Mhz part) Aug. 2006

0.3 Updated IDD3P-S value Aug. 2006

0.4 Corrected DIMM Outline & Added Speed S6 Jul. 2007

0.5 Editorial Correction Sep. 2008

0.6 Modified Block diagram Dec. 2008