LT4294 IEEE 802.3bt PD Interface Controller FEATURES DESCRIPTION IEEE 802.3af/at/bt (Draft 3.7) Powered Device (PD) Controller nn Supports Up to 71.3W PDs nn 5-Event Classification Sensing nn Superior Surge Protection (100V Absolute Maximum) nn Wide Junction Temperature Range (-40C to 125C) nn Overtemperature Protection nn Integrated Signature Resistor nn External Hot Swap N-Channel MOSFET for Lowest Power Dissipation and Highest System Efficiency nn Configurable Aux Power Support as Low as 9V nn Easy Migration Between LTPoE++(R) PDs and IEEE 802.3bt PDs nn Pin Compatible with LT4275A/B/C nn Available in 10-Lead MSOP and 3mm x 3mm DFN Packages The LT(R)4294 is an IEEE 802.3af/at/bt (Draft 3.7)-compliant powered device (PD) interface controller. The T2P output indicates the number of classification events received during IEEE 802.3bt-compliant mutual identification and negotiation of available power. nn The LT4294 utilizes an external, low RDS(ON) N-channel hot swap MOSFET and supports the LT4320/LT4321 ideal diode bridges, to extend the end-to-end power delivery efficiency and eliminate costly heat sinks. The LT4294 also includes a power good output, onboard signature resistor, undervoltage lockout, and thermal protection. Start-up inrush current is adjustable with an external capacitor. Auxiliary power override is supported as low as 9V with the AUX pin. The LT4294 can be configured to support all possible 802.3bt, 802.3at and 802.3af power levels with external component changes. Pin-for-pin compatibility with the LT4275 family of PD Interface Controllers enables easy migration between LTPoE++ PDs and IEEE 802.3btcompliant PDs. APPLICATIONS High Power Wireless Data Systems Outdoor Security Camera Equipment nn Commercial and Public Information Displays nn High Temperature Industrial Applications nn nn All registered trademarks and trademarks are the property of their respective owners. TYPICAL APPLICATION IEEE 802.3bt Single-Signature Powered Device Interface VAUX (9V TO 60V) DATA PAIR SPARE PAIR ~ ~ ~ ~ + CPORT PSMN040-100MSE + - Single-Signature Power Classification VPORT CPD 0.1F 3.3k VIN 47nF + VPORT HSGATE - PWRGD AUX RCLASS RCLASS++ RCLS RCLS++ HSSRC ISOLATED POWER SUPPLY RUN + VOUT - LT4294 GND T2P OPTO 4294 TA01a PSE TYPE (TO P) CLASS AVAILABLE POWER AT PD INPUT 0 13W 1 3.84W 2 6.49W 3 13W 4 25.5W 5 40W 6 51W 7 62W 8 71.3W Rev. A Document Feedback For more information www.analog.com 1 LT4294 ABSOLUTE MAXIMUM RATINGS (Notes 1, 3) VPORT, HSSRC Voltages.......................... -0.3V to 100V HSGATE Current.................................................. 20mA RCLASS, RCLASS++ Voltages........................... -0.3V to 8V (and VPORT) AUX Current......................................................... 1.4mA T2P, PWRGD Voltage................................ -0.3V to 100V T2P, PWRGD Current................................................5mA Operating Junction Temperature Range (Note 4) LT4294I.................................................-40C to 85C LT4294H............................................. -40C to 125C Storage Temperature Range................... -65C to 150C Lead Temperature (Soldering, 10 sec.)................... 300C PIN CONFIGURATION TOP VIEW GND 1 AUX 2 RCLASS 3 RCLASS++ 4 GND 5 TOP VIEW 10 VPORT 11 GND GND AUX RCLASS RCLASS++ GND 9 HSGATE 8 HSSRC 7 PWRGD 6 T2P 1 2 3 4 5 10 9 8 7 6 VPORT HSGATE HSSRC PWRGD T2P MS PACKAGE 10-LEAD PLASTIC MSOP TJMAX = 150C, JC = 45C/W DD PACKAGE 10-LEAD (3mm x 3mm) PLASTIC DFN TJMAX = 150C, JC = 5C/W EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB GND ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PACKAGE DESCRIPTION TEMPERATURE RANGE LT4294IDD#PBF LT4294IDD#TRPBF PART MARKING* LHBX 10-Lead (3mm x 3mm) Plastic DFN -40C to 85C LT4294HDD#PBF LT4294HDD#TRPBF LHBX 10-Lead (3mm x 3mm) Plastic DFN -40C to 125C LT4294IMS#PBF LT4294IMS#TRPBF LTHBW 10-Lead Plastic MSOP -40C to 85C LT4294HMS#PBF LT4294HMS#TRPBF LTHBW 10-Lead Plastic MSOP -40C to 125C Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix. ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 3) SYMBOL PARAMETER CONDITIONS MIN VPORT Operating Input Voltage At VPORT Pin l VSIG VPORT Signature Range At VPORT Pin l VCLASS VPORT Classification Range At VPORT Pin l VMARK VPORT Mark Range At VPORT Pin, Preceded by VCLASS l 2 TYP MAX UNITS 60 V 1.5 10 V 12.5 21 V 5.6 10 V Rev. A For more information www.analog.com LT4294 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 3) SYMBOL PARAMETER VPORT Aux Mode Range CONDITIONS MIN At VPORT Pin, AUX > VAUXT Signature/Class Hysteresis Window At VPORT Pin, Preceded by VCLASS l 8 l 1.0 l 2.6 VRESET Reset Threshold VHSON Hot Swap Turn-On Voltage l VHSOFF Hot Swap Turn-Off Voltage l 30 Hot Swap On/Off Hysteresis Window l 3 TYP MAX 60 UNITS V V 35 5.6 V 37 V 31 V V Supply Current Supply Current VVPORT = VHSSRC = 57V l Supply Current During Classification VVPORT = 17.5V, RCLASS and RCLASS++ Open l 0.4 Supply Current During Mark Event VVPORT = VMARK After 1st Classification Event l 0.5 Detection Signature Resistance VSIG (Note 2) l 23.7 Resistance During Mark Event RCLASS/RCLASS++ Operating Voltage VMARK (Note 2) l 5.8 -10mA IRCLASS -36mA, VCLASS l 1.32 Classification Signature Stability Time VVPORT Step to 17.5V, 34.8 from RCLASS or RCLASS++ to GND l 2 mA 0.9 mA 2.2 mA 25.2 k 8.3 11 k 1.40 1.43 0.7 Detection and Classification Signature 24.4 2 V ms Analog/Digital Interface VAUXT AUX Threshold l 6.1 6.3 6.5 V IAUXH AUX Pin Hysteresis Current VAUX = 6.1V l 3.2 5 7 A T2P Output Low 1mA Load l 0.8 V PWRGD Output Low 1mA Load l 0.8 V PWRGD Leakage Current VPWRGD = 60V l 5 A T2P Leakage Current T2P = 60V l 5 A -18 A 18 V Hot Swap Control IGPU HSGATE Pull-Up Current VHSGATE - VHSSRC = 5V (Note 6) l -27 VGOC HSGATE Open Circuit Voltage -10A Load, with Respect to HSSRC l 10 HSGATE Pull-Down Current VHSGATE - VHSSRC = 5V l 200 T2P Frequency After PWRGD Valid, if IEEE802.3bt PSE Is Mutually Identified l 690 -22 A Timing fT2P T2P Duty Cycle in PoE Operation (Note 5) After 4-Event Classification After 5-Event Classification (RCLASS++ Has Resistor to GND) T2P Duty Cycle in Auxiliary VAUX > VAUXT, and RCLASS++ Has Resistor to GND Supply Operation (Note 5) Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: Signature resistance specifications do not include resistance added by the external diode bridge which can add as much as 1.1k to the port resistance. Note 3: All voltages with respect to GND unless otherwise noted. Positive currents are into pins; negative currents are out of pins unless otherwise noted. 840 990 Hz 50 25 % % 25 % Note 4: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 150C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability. Note 5: Specified as the percentage of the period which T2P is low impedance with respect to GND. Note 6: IGPU available in PoE powered operation. That is, available after VVPORT > VHSON and VAUX < VAUXT, over the range where VVPORT is between VHSOFF and 60V. Rev. A For more information www.analog.com 3 LT4294 TYPICAL PERFORMANCE CHARACTERISTICS Input Current vs Input Voltage 25k Detection Signature Range VPORT VOLTAGE (V) 0.2 35 34 33 32 0.1 2 4 6 VPORT VOLTAGE (V) 8 30 -50 10 -25 0 25 50 75 TEMPERATURE (C) 4294 G01 100 35 40 24.75 24.25 1 3 5 7 VPORT VOLTAGE (V) 4.6 4.1 3.6 2.6 -50 9 -25 0 25 50 75 TEMPERATURE (C) T = -40C T = 25C T = 75C T = 125C 940 T2P FREQUENCY (Hz) VOLTAGE (V) VPORT VOLTAGE (V) 1 2 3 CURRENT (mA) 11.5 11.0 4 5 10.0 -50 890 840 790 740 -25 0 25 50 75 TEMPERATURE (C) 100 125 4294 G07 4294 G06 4 T2P Frequency DETECT OR MARK TO CLASS CLASS TO MARK 10.5 0 125 990 12.0 1 100 4294 G05 VPORT Classification Thresholds 12.5 2 0 60 3.1 PWRGD, T2P Output Low Voltage vs Current 3 55 4294 G03 4294 G04 4 45 50 VPORT VOLTAGE (V) 5.1 VPORT VOLTAGE (V) SIGNATURE RESISTANCE (k) 0 125 Reset Threshold 25.25 23.75 0.5 5.6 T = -40C T = 25C T = 75C T = 125C 25.75 1.0 4294 G02 Detection Signature Resistance vs Input Voltage 26.25 1.5 Hot Swap OFF 31 0 T = -40C T = 25C T = 75C T = 125C Hot Swap ON 36 0.3 0 Supply Current During Power-On 2.0 37 T = -40C T = 25C T = 75C T = 125C 0.4 VPORT CURRENT (mA) VPORT Hot Swap Thresholds SUPPLY CURRENT (mA) 0.5 690 -50 -25 0 25 50 75 TEMPERATURE (C) 100 125 4294 G08 Rev. A For more information www.analog.com LT4294 PIN FUNCTIONS GND (Pins 1, 5, DFN Exposed Pad Pin 11): Device Ground. Exposed Pad must be electrically and thermally connected to pin 5 and PCB GND. AUX (Pin 2): Auxiliary Sense. A resistive divider from the auxiliary power input to AUX sets the voltage at which the auxiliary supply takes over. In auxiliary power operation, HSGATE pulls down, the signature resistor disconnects, classification is disabled, the PWRGD pin is high impedance and T2P indicates max available power. The AUX pin sinks IAUXH when below its threshold voltage of VAUXT to provide hysteresis. Connect to GND when not used. RCLASS (Pin 3): Configurable PoE Classification Resistor. See Table 2. RCLASS++ (Pin 4): Configurable PoE Classification Resistor. See Table 2. T2P (Pin 6): PSE Type Indicator, Open-Drain Output. See the Applications Information section for pin behavior. PWRGD (Pin 7): Power Good Indicator, Open-Drain Output. Pulls to GND during VCLASS and inrush. HSSRC (Pin 8): External Hot Swap MOSFET Source. Connect to source of the external MOSFET. HSGATE (Pin 9): External Hot Swap MOSFET Gate Control, Output. Connect to gate of the external MOSFET. VPORT (Pin 10): PD interface upper power rail and external Hot Swap MOSFET drain connection. Rev. A For more information www.analog.com 5 LT4294 BLOCK DIAGRAM VPORT VPORT VOLTAGE AND CURRENT REFERENCES PWRGD CONTROL LOGIC HSGATE CHARGE PUMP ON VGOC AUX ~6.5V 6.3V + - OVERTEMP VPORT 1.4V + EN - CLASSIFICATION LOGIC HSSRC T2P VPORT RCLASS EN + - 1.4V RCLASS++ GND 4294 BD 6 Rev. A For more information www.analog.com LT4294 APPLICATIONS INFORMATION OVERVIEW POWER ON The LT4294 is an IEEE 802.3bt (Draft 3.7)-compliant PD interface controller, and allows up to 71.3W operation while maintaining backwards compatibility with existing PSE systems. The T2P output indicates the number of classification events received during IEEE 802.3bt-compliant mutual identification and negotiation of available power. The LT4294 controls a low RDS(ON) N-channel MOSFET to maximize efficiency and delivered power. Analog Devices also provides the LT4295, an IEEE 802.3btcompliant PD with an integrated switching regulator to service applications that require a more compact and integrated solution. IEEE 802.3bt vs LTPoE++ Available Power The LT4294 supports IEEE 802.3bt PD power levels up to 71.3W. The LT4275 and LT4276 are available to support PD power levels up to 90W under the LTPoE++ standard. See the Related Parts section for a list of LTPoE++ products. MODES OF OPERATION VHSOFF 1ST CLASS VVPORT Power over Ethernet (PoE) continues to gain popularity as products take advantage of DC power and high speed data available from a single RJ45 connector. Powered device (PD) equipment vendors are running into the 25.5W power limit established by the IEEE 802.3at standard. VHSON VCLASSMIN VMARKMAX VRESET DETECT 1ST MARK VSIGMIN 4294 F01 Figure 1. Type 3 or 4 PSE, 1-Event Class Sequence smaller than 25k to compensate for the additional series resistance introduced by the IEEE required bridge or the LT4321-based ideal diode bridge. IEEE 802.3bt Single-Signature vs Dual-Signature PDs IEEE 802.3bt defines two PD topologies: single-signature and dual-signature. The LT4294 primarily targets singlesignature PD topologies, eliminating the need for a second PD controller. All PD descriptions and IEEE 802.3 standard references in this data sheet are limited in scope to singlesignature PDs. The LT4294 may be deployed in dual-signature PD applications. For more information, contact Analog Devices Applications. Classification Signature and Mark Detection Signature During detection, the PSE looks for a 25k signature resistor which identifies the device as a PD. The PSE will apply two voltages in the range of 2.7V to 10.1V and measure the corresponding currents. Figure 1 shows the detection voltages. The PSE calculates the signature resistance using a V/I measurement technique. The classification/mark process varies depending on the PSE type. A PSE, after a successful detection, may apply a classification probe voltage of 14.5V to 20.5V and measure the PD classification signature current. Once the PSE applies a classification probe voltage, the PSE returns the PD voltage to the mark voltage range before applying another classification probe voltage, or powering up the PD. The LT4294 presents its precision, temperature-compensated 24.4k resistor between the VPORT and GND pins, allowing the PSE to recognize a PD is present and requesting power to be applied. The LT4294 signature resistor is An example of 1-Event classification is shown in Figure 1. In 2-Event classification, a PSE probes for power classification twice as shown in Figure 2. An IEEE 802.3bt PSE may apply as many as 5 events before powering up the PD. Rev. A For more information www.analog.com 7 LT4294 APPLICATIONS INFORMATION POWER ON VHSON IEEE 802.3bt defines physical classification to allow a PD to request a power allocation from the connected PSE and to allow the PSE to inform the PD of the PSE's available power. Demotion is provided if the PD requested power level is not available at the PSE. If demoted, the PD must operate in a lower power state. VHSOFF VPORT 1ST CLASS 2ND CLASS VCLASSMIN VMARKMAX DETECT VRESET 1ST MARK The number of class/mark events issued by the PSE directly indicates the power allocated to the PD and is summarized in Table 1. 2ND MARK VSIGMIN 4294 F02 Figure 2. Type 2 PSE, 2-Event Class Sequence POWER ON PD REQUESTED CLASS 1ST CLASS 2ND CLASS 3RD CLASS VPORT IEEE 802.3bt provides nine PD classes and four PD types, as shown in Table 2. The LT4294 class is configured by setting the RCLS and RCLS++ resistor values. Table 1. PSE Allocated Class Power VHSON VHSOFF VCLASSMIN VMARKMAX IEEE 802.3bt Physical Classification and Demotion DETECT VRESET 1ST MARK 2ND MARK 3RD MARK VSIGMIN 4294 F03 Figure 3. Type 3 or 4 PSE, 3-Event Class Sequence NUMBER OF PSE CLASS/MARK EVENTS 1 2 3 4 0 13W 1 3.84W 2 6.49W 3 13W 4 13W 5 25.5W 5 13W 25.5W 40W 6 13W 25.5W 51W 7 13W 25.5W 51W 62W 8 13W 25.5W 51W 71.3W Note: Bold indicates the PD has been demoted. Table 2. Single-Signature Classification Codes, Power Levels and Resistor Selection PD REQUESTED CLASS 0 1 2 3 4 5 6 7 8 8 PD POWER AVAILABLE 13W 3.84W 6.49W 13W 25.5W 40W 51W 62W 71.3W PD TYPE Type 1 Type 1 or 3 Type 1 or 3 Type 1 or 3 Type 2 or 3 Type 3 Type 3 Type 4 Type 4 NOMINAL CLASS CURRENT 2.5mA 10.5mA 18.5mA 28mA 40mA 40mA/2.5mA 40mA/10.5mA 40mA/18.5mA 40mA/28mA RESISTOR (1%) RCLS RCLS++ 1.00k Open 140 Open 76.8 Open 49.9 Open 34.8 Open 1.00k 37.4 140 46.4 76.8 64.9 49.9 118 Rev. A For more information www.analog.com LT4294 APPLICATIONS INFORMATION IEEE 802.3bt PSEs present a single classification event (see Figure 1) to Class 0 through 3 PDs. A Class 0 through 3 PD presents its class signature to the PSE and is then powered on if sufficient power is available. Power limited IEEE 802.3bt PSEs may issue a single event to Class 4 and higher PDs in order to demote those PDs to Class 3 (13W). IEEE 802.3bt PSEs present up to three classification events, depending on PSE Type, to Class 4 PDs (see Figure 3). Class 4 PDs present a class signature 4 on all events. The third event differentiates a Class 4 PD from a higher Class PD. Power-limited IEEE 802.3bt PSEs may issue three events to Class 5 and higher PDs in order to demote those PDs to Class 4 (25.5W). IEEE 802.3bt PSEs present four classification events (see Figure 4) to Class 5 and 6 PDs. Class 5 and 6 PDs present a class signature 4 on the first two events, then present a class signature 0 or 1, respectively, on the remaining events. Power limited IEEE 802.3bt PSEs may issue four events to Class 7 and higher PDs in order to demote those PDs to Class 6 (51W). POWER ON VHSON VPORT VHSOFF 1ST CLASS 2ND CLASS 3RD CLASS 4TH CLASS VCLASSMIN VMARKMAX DETECT 1ST MARK VRESET 2ND MARK 3RD MARK 4TH MARK VSIGMIN 4294 F04 Figure 4. Type 3 or 4 PSE, 4-Event Class Sequence IEEE 802.3bt PSEs present five classification events (see Figure 5) to Class 7 and 8 PDs. Class 7 and 8 PDs present a class signature 4 on the first two events, then present a class signature 2 or 3, respectively, on the remaining events. The number of classification/mark events is communicated through the LT4294 T2P pin. See T2P Output section for more details. Classification Resistors (RCLS and RCLS++) The RCLS and RCLS++ resistors set the classification currents corresponding to the PD power classification. Select the value of RCLS and RCLS++ from Table 2 and connect each 1% resistor between the RCLASS, RCLASS++ pins and GND. Detection Signature Corrupt During Mark Event During the mark event, the LT4294 presents <11k to the port as required by the IEEE 802.3 specification. Inrush and Power On Once the PSE detects and classifies the PD, the PSE then powers on the PD. When the port voltage rises above the VHSON threshold, it begins to source IGPU out of the HSGATE pin. This current flows into an external capacitor, CGATE in Figure 6, that causes a voltage to ramp up the gate of the external MOSFET. The external MOSFET acts as a source follower and ramps the voltage up on the output bulk capacitor, CPORT, thereby determining the inrush current, IINRUSH. Design IINRUSH to be approximately ~100mA. See equation below: C IINRUSH = I GPU * PORT CGATE POWER ON VHSON VPORT VHSOFF VPORT IINRUSH 1ST CLASS 2ND CLASS 3RD CLASS 4TH CLASS 5TH CLASS CPORT CGATE VCLASSMIN HSGATE VPORT VMARKMAX HSSRC LT4294 DETECT VRESET + 3.3k 1ST MARK 2ND MARK 3RD MARK 4TH MARK 5TH MARK GND 4294 F06 VSIGMIN 4294 F05 Figure 5. Type 4 PSE, 5-Event Class Sequence Figure 6. Configuring IINRUSH Rev. A For more information www.analog.com 9 LT4294 APPLICATIONS INFORMATION The LT4294 internal charge pump provides an N-channel MOSFET solution, eliminating a larger and more costly P-channel MOSFET. The low RDS(ON) MOSFET also maximizes power delivery and efficiency, reduces power and heat dissipation, and eases thermal design. Power Good The PWRGD pin is held low by its open drain output until HSGATE charges up to approximately 7V above HSSRC. The PWRGD pin is used to hold off the downstream circuitry until inrush is complete and the external MOSFET is fully enhanced. The HSGATE pin remains high and the PWRGD pin remains open-drain until the port voltage falls below VHSOFF. A capacitor up to 1000pF may be placed between the AUX pin and GND to improve noise immunity. VAUXON must be lower than VHSOFF. T2P Output The LT4294 communicates the PSE allocated power to the PD application via the T2P pin. The T2P pin state is determined by the AUX pin, the RCLASS++ pin, and the number of classification events. The LT4294 uses a 4-state encoding for the T2P output. T2P state and the associated PSE allocated power are shown in Table 3. Table 3. T2P Response to Determine PSE Allocated Power AUX STATE Delay Start When the PSE powers up the port, the PD application should not draw more than 350mA for 80ms to comply with the IEEE 802.3 standard. PD REQUESTED NUMBER CLASS OF CLAST2P WITH (RCLASS/ SIFICATION RESPECT TO RCLASS++) EVENTS GND 0-4 Auxiliary 5-8 0-4 Auxiliary Supply Override If the AUX pin is held above VAUXT, the LT4294 enters auxiliary power supply override mode. In this mode the signature resistor disconnects, classification is disabled, HSGATE pulls down, the PWRGD pin is open drain and T2P pin indicates max available power. The AUX pin allows for setting the auxiliary supply turn on and turn off voltage thresholds, VAUXON, and VAUXOFF respectively. The auxiliary supply hysteresis voltage, VAUXHYS, is generated with sinking current, IAUXH, and is active only when the AUX pin voltage is less than VAUXT. Use the following equations to set VAUXON and VAUXOFF via R1 and R2 in Figure 7. Note that an internal 6.5V Zener limits the voltage on the AUX pin. R1= R2 = R1 VAUXON - VAUXOFF VAUXHYS + = IAUXH IAUXH R1 VAUXOFF - 1 V AUXT VAUX(MAX) - VAUXT 1.4mA VAUX LT4294 AUX Power N/A AUX Power 1 Hi-Z 13W 2 Low-Z 25.5W 1 Hi-Z 13W 2 or 3 Low-Z 25.5W 4 50% Low-Z, 50% Hi-Z Min (PD Requested Class, 51W) 5 25% Low-Z, 75% Hi-Z Min (PD Requested Class, 71.3W) The highest priority input is the AUX pin. AUX is asserted to enter the auxiliary power state and deasserted to enter the PoE state. In the auxiliary power state, the T2P pin indicates the highest available power, based on PD Requested Class. The auxiliary power supply must be sized to provide at least the PD Requested Class Power. LT4294 VCC T2P 25% Low-Z V(T2P) AUX GND R2 4294 F08 GND GND 75% Hi-Z TIME 4294 F07 Figure 7. AUX Threshold and Hysteresis Calculation 10 Low-Z 25% Low-Z, 75% Hi-Z VCC R1 - N/A PoE 5-8 PSE ALLOCATED POWER Figure 8. Response Example for 25% Low-Z, 75% Hi-Z Rev. A For more information www.analog.com LT4294 APPLICATIONS INFORMATION Second, the PD Requested Class is configured using the RCLASS and RCLASS++ pins. The RCLASS++ pin alone can be used to determine if the PD Class is 0-4 or 5-8, as shown in Table 2. Last, the number of classification events determines the amount of power allocated by the PSE as described in Table 1. Overtemperature Protection The IEEE 802.3 specification requires a PD to withstand any applied voltage from 0V to 57V indefinitely. During classification, however, the power dissipation in the LT4294 may be as high as 1.5W. The LT4294 can easily tolerate this power for the maximum IEEE classification timing but overheats if this condition persists abnormally. The LT4294 includes an overtemperature protection feature which is intended to protect the device during momentary overload conditions. If the junction temperature exceeds the overtemperature threshold, the LT4294 pulls down HSGATE pin, and disables classification. EXTERNAL INTERFACE AND COMPONENT SELECTION PoE Input Bridge A PD is required to polarity-correct its input voltage. There are several different options available for bridge rectifiers; silicon diodes, Schottky diodes, and ideal diodes. When silicon or Schottky diode bridges are used, the diode forward voltage drops affect the voltage at the VPORT pin. The LT4294 is designed to tolerate these voltage drops. Note, the voltage parameters shown in the Electrical Characteristics are specified at the LT4294 package pins. A silicon diode bridge consumes up to 4% of the available power. In addition, silicon diode bridges exhibit poor pairset-to-pairset unbalance performance. Each branch of a silicon diode bridge shares source/return current, and thermal runaway can cause large, non-compliant current unbalances between pairsets. While using Schottky diodes can help reduce the power loss with a lower forward voltage, the Schottky bridge may not be suitable for high temperature PD applications. Schottky diode bridges exhibit temperature induced leakage currents. The leakage current has a voltage dependency that can invalidate the measured detection signature. In addition, these leakage currents can back-feed through the unpowered branch and the unused bridge, violating IEEE 802.3 specifications. For high efficiency applications, the LT4294 supports an LT4321-based PoE ideal diode bridge that reduces the forward voltage drop from 0.7V to 20mV per diode while maintaining IEEE 802.3 compliance. The LT4321 simplifies thermal design, eliminates costly heatsinks, and can operate in space-constrained applications. Auxiliary Input Diode Bridge Some PDs are required to receive AC or DC power from an auxiliary power source. A diode bridge is typically required to handle the voltage rectification and polarity correction. In high efficiency applications, or in low auxiliary input voltage applications, the voltage drop across the rectifier cannot be tolerated. The LT4294 can be configured with an LT4320-based ideal diode bridge to recover the diode voltage drop and ease thermal design. For applications with auxiliary input voltages below 10V, the LT4294 must be configured with an LT4320-based ideal diode bridge to recover the voltage drop and guarantee the minimum VPORT voltage is within the VPORT AUX Mode Range as specified in the Electrical Characteristics table. An example of a high efficiency typical application circuit is show in the Typical Application section. Input Capacitor A 0.1F capacitor is needed from VPORT to GND to meet the input impedance requirement in IEEE 802.3 and to properly bypass the LT4294. When operating with the LT4321, locally bypass each with a 0.047F capacitor, thus keeping the total port capacitance within specification. Transient Voltage Suppressor The LT4294 specifies an absolute maximum voltage of 100V and is designed to tolerate brief overvoltage events Rev. A For more information www.analog.com 11 LT4294 APPLICATIONS INFORMATION LAYOUT CONSIDERATIONS due to Ethernet cable surges. To protect the LT4294 from an overvoltage event, install a unidirectional transient voltage suppressor (TVS) such as an SMAJ58A between the VPORT and GND pins. For PD applications that require an auxiliary power input, install a TVS between VIN and GND. See Layout Considerations for TVS placement. Avoid excessive parasitic capacitance on the RCLASS and RCLASS++ pins and place resistors RCLS and RCLS++ close to the LT4294. It is strictly required for maximum protection to place the 0.1F input capacitor, CPD, and transient voltage suppressor as close to the LT4294 as possible. When operating the LT4294 with the LT4321, place a 0.047F capacitor, CPD1, as close as possible to the LT4294 VPORT and GND pins (pin 10 and pin 5, respectively), and a 0.047F capacitor, CPD2, as close as possible to the LT4321 OUTP and OUTN pins. For extremely high cable discharge and surge protection, contact Analog Devices Applications. Exposed Pad The LT4294 DFN package has an exposed pad that is internally electrically connected to GND. The exposed pad may only be connected to GND on the printed circuit board. TYPICAL APPLICATIONS High Efficiency 25.5W PD Solution with 12VDC and 24VAC Auxiliary Input BSZ110N06NS3 x4 TG2 OUTP TG1 LT4320 VAUX 9V TO 57VDC OR 24VAC PSMN075-100MSE x4 IN1 IN2 1F BG2 BG1 MMSD4148 x3 OUTN PSMN075-100MSE 1 CPD1 0.047F DATA PAIRS 2 TG12 BG12 BG36 TG36 3 OUTP CPD2 0.047F 6 IN36 LT4321 IN45 EN IN78 OUTN 4 + HSGATE HSSRC AUX 0.1F 680F VIN 3.3k 158k SMAJ58A EN IN12 SPARE PAIRS VPORT LT4294 150nF RCLASS 34.8 931k PWRGD 100k ISOLATED POWER SUPPLY + VOUT - RUN GND GND 4294 TA03 5 BG78 TG78 7 TG45 BG45 8 WURTH 749022017 PSMN075-100MSE x4 12 Rev. A For more information www.analog.com LT4294 PACKAGE DESCRIPTION DD Package 10-Lead Plastic DFN (3mm x 3mm) (Reference LTC DWG # 05-08-1699 Rev C) 0.70 0.05 3.55 0.05 1.65 0.05 2.15 0.05 (2 SIDES) PACKAGE OUTLINE 0.25 0.05 0.50 BSC 2.38 0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 3.00 0.10 (4 SIDES) R = 0.125 TYP 6 0.40 0.10 10 1.65 0.10 (2 SIDES) PIN 1 NOTCH R = 0.20 OR 0.35 x 45 CHAMFER PIN 1 TOP MARK (SEE NOTE 6) 0.200 REF 5 0.75 0.05 0.00 - 0.05 1 (DD) DFN REV C 0310 0.25 0.05 0.50 BSC 2.38 0.10 (2 SIDES) BOTTOM VIEW--EXPOSED PAD NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2). CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE Rev. A For more information www.analog.com 13 LT4294 PACKAGE DESCRIPTION MS Package 10-Lead Plastic MSOP (Reference LTC DWG # 05-08-1661 Rev F) 0.889 0.127 (.035 .005) 5.10 (.201) MIN 3.20 - 3.45 (.126 - .136) 3.00 0.102 (.118 .004) (NOTE 3) 0.50 0.305 0.038 (.0197) (.0120 .0015) BSC TYP RECOMMENDED SOLDER PAD LAYOUT 0.254 (.010) 10 9 8 7 6 3.00 0.102 (.118 .004) (NOTE 4) 4.90 0.152 (.193 .006) DETAIL "A" 0.497 0.076 (.0196 .003) REF 0 - 6 TYP GAUGE PLANE 1 2 3 4 5 0.53 0.152 (.021 .006) DETAIL "A" 0.18 (.007) SEATING PLANE 0.86 (.034) REF 1.10 (.043) MAX 0.17 - 0.27 (.007 - .011) TYP 0.50 (.0197) BSC NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 14 0.1016 0.0508 (.004 .002) MSOP (MS) 0213 REV F Rev. A For more information www.analog.com LT4294 REVISION HISTORY REV DATE DESCRIPTION A 09/18 Updated to IEEE 802.3af/at/bt (Draft 3.5) Revised T2P Output Applications Information Revised External Interface and Component Selection Applications Information PAGE NUMBER 1-16 10, 11 11, 12 Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license For is granted implication or otherwise under any patent or patent rights of Analog Devices. more by information www.analog.com 15 LT4294 TYPICAL APPLICATION IEEE 802.3bt-Compliant > 99% Efficiency 71.3W Powered Device PSMN075-100MSE x4 PSE TYPE (TO P) OPTO PSMN040-100MSE 1 CPD1 0.047F DATA PAIRS 2 TG12 BG12 BG36 TG36 3 VPORT SMAJ58A OUTP 6 IN36 EN LT4321 CPD2 0.047F T2P LT4294 PWRGD IN45 IN78 VIN 100k 47nF RCLASS 4294 TA02 22F 3.3k RCLASS++ GND 4 SPARE PAIRS HSSRC AUX EN IN12 + HSGATE RCLS 49.9 RCLS++ 118 ISOLATED POWER SUPPLY + VOUT - RUN GND OUTN 5 BG78 TG78 7 TG45 BG45 8 WURTH 749022016 PSMN075-100MSE x4 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT4295 IEEE 802.3bt PD with Forward/Flyback Switching Regulator Controller External Switch, IEEE 802.3bt Support, Configurable Class, Forward or No-Opto Flyback Operation, Frequency, PG/SG Delays, Soft-Start, and Aux Support as Low as 9V, Including Housekeeping Buck, Slope Compensation LT4321 PoE Ideal Diode Bridge Controller Controls 8-NMOSFETs for IEEE-Required PD Voltage Rectification without Diode Drops LT4320/LT4320-1 Ideal Diode Bridge Controller 9V - 72V, DC to 600Hz Input. Controls 4-NMOSFETs, Voltage Rectification without Diode Drops LTC4279 Single PoE/PoE+/LTPoE++ PSE Controller Supports IEEE 802.3af, IEEE 802.3at, LTPoE++ and Proprietary PDs LT4276A/B/C LTPoE++/PoE+/PoE PD with Forward/ Flyback Switching Regulator Controller External Switch, LTPoE++ Support, User-Configurable Class, Forward or No-Opto Flyback Operation, Frequency, PG/SG Delays, Soft-Start, and Aux Support as Low as 9V, Including Housekeeping Buck, Slope Compensation LT4275A/B/C LTPoE++/PoE+/PoE PD Controller External Switch, LTPoE++ Support LTC4269-1 IEEE 802.3at PD Interface with Integrated 2-Event Classification, Programmable Class, Synchronous No-Opto Flyback Controller, Flyback Switching Regulator 50kHz to 250kHz, Aux Support LTC4269-2 IEEE 802.3at PD Interface with Integrated 2-Event Classification, Programmable Class, Synchronous Forward Controller, 100kHz Forward Switching Regulator to 500kHz, Aux Support LTC4278 IEEE 802.3at PD Interface with Integrated 2-Event Classification, Programmable Class, Synchronous No-Opto Flyback Controller, Flyback Switching Regulator 50kHz to 250kHz, 12V Aux Support LTC4267/LTC4267-1/ IEEE 802.3af PD Interface with Integrated Internal 100V, 400mA Switch, Programmable Class, 200/300kHz Constant LTC4267-3 Switching Regulator Frequency PWM LTC4290/LTC4271 16 8-Port PoE/PoE+/LTPoE++ PSE Controller Transformer Isolation, Supports IEEE 802.3af, IEEE 802.3at and LTPoE++ PDs Rev. A D17136-0-9/18(A) www.analog.com For more information www.analog.com ANALOG DEVICES, INC. 2017-2018