2010-2015 Microchip Technology Inc. DS40001303H-page 1
PIC18F2XK20/4XK20
High-Performance RISC CPU
• C Compiler Optimized Architecture:
- Optional extended instruct ion set designed to
optimize re-en t ran t code
• Up to 1024 bytes Data EEPROM
• Up to 64 Kbytes Linear Prog ram Memory
Addressing
• Up to 39 36 bytes Lin ear Data Mem ory Addressin g
• Up to 16 MIPS Operation
• 16-bit Wide Instructions, 8-bit Wide Data Path
• Priority Levels for Interrupts
• 31-Level, Software Accessible Hardware Stack
• 8 x 8 Single-Cycle Hardware Multiplier
Flexible Oscil lator Structure
• Precision 16 MHz Internal Oscillator Block:
- Factory calibrated to ± 1%
- Software selec table frequencies range of
31 kHz to 16 MHz
- 64 MHz performance available u s ing PLL –
no external components required
• Four Crystal Modes up to 64 MHz
• Two External Clock Modes up to 64 MHz
• 4X Phase Lock Loo p (PLL)
• Secondary Oscillator using Timer1 @ 32 kHz
• Fail-Safe Clock Monitor:
- Allows for safe shutdown, if peripheral clock
stops
- Two-Speed Oscillator Start-up
S pecial Microcontr oller Features
• Operating Voltage Range: 1.8V to 3.6V
• Self-Programmable under Software Control
• Programmable 16-Level High/Low-Voltage
Detection (HLVD) module:
- Interrupt on High/Low-Voltage Detection
• Programmable Brown-out Reset (BOR):
- With software enable option
• Extended Wa tchdog Timer (WDT):
- Programmable period from 4 ms to 131s
• Single-Supply 3V In-Circuit Serial
Programming™ (ICSP™) via Two Pins
• In-Circuit Debug (ICD) via Two Pins
Extreme Low-Power Management
with XLP
• Sleep Mode: < 100 nA @ 1.8V
• Watchdog Timer: < 800 nA @ 1.8V
• Timer1 Oscillator: < 800 nA @ 32 kHz and 1.8V
Analog Features
• Analog-to-Digital Converter (ADC) Module:
- 10-bit resolution, 13 External Channels
- Auto-acquisition capability
- Conversion available during Sleep
- 1.2V Fixed Voltage Reference (FVR) channel
- Independent input multiplexing
• Analog Comparator Module:
- Two rail-to-rail analog comparators
- Independent input multiplexing
• Voltage Re fere nc e (CVREF) Module
- Programmable (% VDD), 16 steps
- Two 16-level voltage ranges using VREF pins
Peripheral Highl ights
• Up to 35 I/O Pins plus 1 Input-only Pin:
- High-Current Sink /So urc e 25 mA/25 mA
- Three programmable external interrupts
- Four programmabl e interrupt-on-change
- Eight programmable weak pull-ups
- Programmable slew rate
• Capture/Compare/PWM (CCP) Module
• Enhanced CCP (ECCP) module:
- One, two or four PWM outputs
- Selectab le pol ari ty
- Programmable dead time
- Auto-shutdown and auto-restart
• Master Synchronous Serial Port (MSSP) Module
- 3-wire SPI (supports all four modes)
-I
2C™ Master and Slave modes with addres s
mask
• Enhanced Universal Synchronous Asynchronous
Receiver Transmitter (EUSART) Module:
- Supports RS-485, RS-232 and LIN
- RS-232 operation using internal oscillator
- Auto-Wake-up on Brea k
- Auto-Baud Detect
28/40/44-Pin Flash Microcontrollers
with XLP Technology
PIC18F2XK20/4XK20
DS40001303H-page 2 2010-2015 Microchip Technology Inc.
-
PIC18F2XK20/4XK20 Family Types
Device Program Memory Data Memory I/O(1) 10-bit
A/D
(ch)(2)
CCP/
ECCP
(PWM)
MSSP
EUSART
Comp. Timers
8/16-bit
Flash
(bytes) # Single-Word
Instructions SRAM
(bytes) EEPROM
(bytes) SPI Master
I2C™
PIC18F23K20 8K 4096 512 256 25 11 1/1 Y Y 1 2 1/3
PIC18F24K20 16K 8192 768 256 25 11 1/1 Y Y 1 2 1/3
PIC18F25K20 32K 16384 1536 256 25 11 1/1 Y Y 1 2 1/3
PIC18F26K20 64k 32768 3936 1024 25 11 1/1 Y Y 1 2 1/3
PIC18F43K20 8K 4096 512 256 36 14 1/1 Y Y 1 2 1/3
PIC18F44K20 16K 8192 768 256 36 14 1/1 Y Y 1 2 1/3
PIC18F45K20 32K 16384 1536 256 36 14 1/1 Y Y 1 2 1/3
PIC18F46K20 64k 32768 3936 1024 36 14 1/1 Y Y 1 2 1/3
Note 1: One pin is input-only.
2: Channel count includes internal Fixed Voltage Reference channel.
Note: For other small form-factor package availability and marking information, please visit
http://www.microchip.com/packaging or contact your local sales office.
2010-2015 Microchip Technology Inc. DS40001303H-page 3
PIC18F2XK20/4XK20
Pin Diagrams
FIGURE 1: 28-PIN SPDIP, SOIC, SSOP
FIGURE 2: 28-PIN QFN/UQFN
10
11
2
3
4
5
6
1
8
7
9
12
13
14 15
16
17
18
19
20
23
24
25
26
27
28
22
21
MCLR/VPP/RE3
AN0/C12IN0-/RA0
AN1/C12IN1-/RA1
AN2/VREF-/CVREF/C2IN+/RA2
AN3/VREF+/C1IN+/RA3
T0CKI/C1OUT/RA4
AN4/SS/HLVDIN/C2OUT/RA5
VSS
OSC1/CLKIN/RA7
OSC2/CLKOUT/RA6
T1OSO/T13CKI/RC0
T1OSI/CCP2(1)/RC1
CCP1/P1A/RC2
SCK/SCL/RC3
RB7/KBI3/PGD
RB6//KBI2/PGC
RB5/KBI1/PGM
RB4/KBI0/AN11/P1D
RB3/AN9/C12IN2-/CCP2(1)
RB2/INT2/AN8/P1B
RB1/INT1/AN10/C12IN3-/P1C
RB0/INT0/FLT0/AN12
VDD
VSS
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
PIC18F23K20
PIC18F24K20
PIC18F25K20
PIC18F26K20
Note: See Table 1 for pin allocation table.
1011
2
3
6
1
18
19
20
21
22
121314 15
8
716
17
232425262728
9
T1OSO/T13CKI/RC0
5
4
RB7/KBI3/PGD
RB6/KBI2/PGC
RB5/KBI1/PGM
RB4/KBI0/AN11/P1D
RB3/AN9/C12IN2-/CCP2(1)
RB2/INT2/AN8/P1B
RB1/INT1/AN10/C12IN3-/P1C
RB0/INT0/FLT0/AN12
VDD
VSS
RC7/RX/DT
TX/CK/RC6
SDO/RC5
SDI/SDA/RC4
RE3/MCLR/VPP
RA0/AN0/C12IN0-
RA1/AN1/C12IN1-
AN2/VREF-/CVREF/C2IN+/RA2
AN3/VREF+/C1IN+/RA3
T0CKI/C1OUT/RA4
AN4/SS/HLVDIN/C2OUT/RA5
VSS
OSC1/CLKIN/RA7
OSC2/CLKOUT/RA6
T1OSI/CCP2(1)/RC1
CCP1/P1A/RC2
SCK/SCL/RC3
PIC18F23K20
PIC18F24K20
PIC18F25K20
PIC18F26K20
Note 1: RB3 is the alternate pin for CCP2 multiplexing.
2: UQFN package availability applies only to PIC18F23K20.
3: See Table 1 for pin allocation table.
4: The exposed pad should be connected to VSS.
PIC18F2XK20/4XK20
DS40001303H-page 4 2010-2015 Microchip Technology Inc.
FIGURE 3: 40-PIN PDIP
FIGURE 4: 40-PIN UQFN
RB7/KBI3/PGD
RB6/KBI2/PGC
RB5/KBI1/PGM
RB4/KBI0/AN11
RB3/AN9/C12IN2-/CCP2(1)
RB2/INT2/AN8
RB1/INT1/AN10/C12IN3-
RB0/INT0/FLT0/AN12
VDD
VSS
RD7/PSP7/P1D
RD6/PSP6/P1C
RD5/PSP5/P1B
RD4/PSP4
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
MCLR/VPP/RE3
AN0/C12IN0-/RA0
AN1/C12IN1-/RA1
AN2/VREF-/CVREF/C2IN+/RA2
AN3/VREF+/C1IN+/RA3
T0CKI/C1OUT/RA4
AN4/SS/HLVDIN/C2OUT/RA5
RD/AN5/RE0
WR/AN6/RE1
CS/AN7/RE2
VDD
VSS
OSC1/CLKIN/RA7
OSC2/CLKOUT/RA6
T1OSO/T13CKI/RC0
T1OSI/CCP2(1)/RC1
CCP1/P1A/RC2
SCK/SCL/RC3
PSP0/RD0
PSP1/RD1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
PIC18F43K20
PIC18F44K20
PIC18F45K20
PIC18F46K20
Note: See Table 2 for pin allocation table.
10
11
2
3
4
5
6
1
18 19 20 21
22
12 13 14 15
38
8
7
40 39
16 17
29
30
31
32
33
23
24
25
26
27
28
36 34
35
9
37
AN1/C12/IN1-/RA1
AN0/C12IN0-/RA0
MCLR/VPP/RE3
AN9/C12IN2-/CCP/RB3
KBI3/PGD/RB7
KBI2/PGC/RB6
KBI1/PGM/RB5
KBI0/AN11/RB4 RC6/TX/Ck
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
RD1/PSP1
RD0/PSP0
RC3/SCK/SCL
RC2/CCP1/P1A
RC1/T1OSI/CCP2
RC0/T1OSO/T13CKI
RA6/OSC2/CLKOUT
RA7/OSC1/CLKIN
VSS
VDD
RE2/CS/AN7
RE1/WR/AN6
RE0/RD/AN5
RA5/AN4/SS/HLVDIN/C2OUT
RA4/T0CKI/C1OUT
RX/DT/RC7
RD4/PSP4/RD4
PSP5/P1B/RD5
RD6/PSP6/P1C/RD6
PSP7/P1D/RD7
VSS
VDD
INT0/FLT0/AN12/RB0
INT1/AN10/C12IN3-/RB1
INT2/AN8/RB2
AN3/VREF+/C1IN+/RA3
AN2/VREF-/CVREF/C2IN+/RA2
PIC18F4XK20
Note 1: See Table 2 for location of all peripheral functions.
2: It is recommended that the exposed bottom pad be connected to VSS.
2010-2015 Microchip Technology Inc. DS40001303H-page 5
PIC18F2XK20/4XK20
FIGURE 5: 44-PIN QFN
FIGURE 6: 44-PIN TQFP
10
11
2
3
4
5
6
1
18
19
20
21
22
12
13
14
15
38
8
7
44
43
42
41
40
39
16
17
29
30
31
32
33
23
24
25
26
27
28
36
34
35
9
37
AN3/VREF+/C1IN+/RA3
AN2/VREF-/CVREF/C2IN+/RA2
AN1/C12IN1-/RA1
AN0/C12IN0-/RA0
MCLR/VPP/RE3
AN9/C12IN2-/CCP2(1)/RB3
KBI3/PGD/RB7
KBI2/PGC/RB6
KBI1/PGM/RB5
KBI0/AN11/RB4
NC RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
RD1/PSP1
RD0/PSP0
RC3/SCK/SCL
RC2/CCP1/P1A
RC1/T1OSI/CCP2(1)
RC0/T1OSO/T13CKI
RA6/OSC2/CLKOUT
RA7/OSC1/CLKIN
VSS
VSS
VDD
VDD
RE2/CS/AN7
RE1/WR/AN6
RE0/RD/AN5
RA5/AN4/SS/HLVDIN/C2OUT
RA4/T0CKI/C1OUT
RX/DT/RC7
RD4/PSP4/RD4
PSP5/P1B/RD5
PSP6/P1C/RD6
PSP7/P1D/RD7
VSS
VDD
VDD
INT0/FLT0/AN12/RB0
INT1/AN10/C12IN3-/RB1
INT2/AN8/RB2
PIC18F43K20
PIC18F44K20
PIC18F45K20
PIC18F46K20
Note 1: RB3 is the alternate pin for CCP2 multiplexing.
2: The exposed pad should be connected to VSS.
3: See Table 2 for pin alloca ti on table.
10
11
2
3
4
5
6
1
18
19
20
21
22
12
13
14
15
38
8
7
44
43
42
41
40
39
16
17
29
30
31
32
33
23
24
25
26
27
28
36
34
35
9
37
AN3/VREF+/C1IN+/RA3
AN2/VREF-/CVREF/C2IN+/RA2
AN1/C12IN1-/RA1
AN0/C12IN0-/RA0
MCLR/VPP/RE3
NC
KBI3/PGD/RB7
KBI2/PGC/RB6
KBI1/PGM/RB5
KBI0/AN11/RB4
NC RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
RD1/PSP1
RD0/PSP0
RC3/SCK/SCL
RC2/CCP1/P1A
RC1/T1OSI/CCP2(1)
NC
NC
RC0/T1OSO/T13CKI
RA6/OSC2/CLKOUT
RA7/OSC1/CLKIN
VSS
VDD
RE2/CS/AN7
RE1/WR/AN6
RE0/RD/AN5
RA5/AN4/SS/HLVDIN/C2OUT
RA4/T0CKI/C1OUT
RX/DT/RC7
PSP4/RD4
PSP6/P1C/RD6
PSP7/P1D/RD7
VSS
VDD
INT0/FLT0/AN12/RB0
INT1/AN10/C12IN3-/RB1
INT2/AN8/RB2
AN9/C12IN2-/CCP2(1)/RB3
PIC18F43K20
PIC18F44K20
PIC18F45K20
PIC18F46K20
Note 1: RB3 is the alternate pin for CCP2 multiplexing.
2: See Table 2 for pin alloca tion table.
PSP5/P1B/RD5
PIC18F2XK20/4XK20
DS40001303H-page 6 2010-2015 Microchip Technology Inc.
Pin Allocation Tables
TABLE 1: 28-PIN ALLOCATION TABLE (PIC18F2XK20)
I/O
28-P in SPDIP, SOIC, SSO P
28-Pin QFN/UQFN
Analog
Comparator
Reference
ECCP
EUSART
MSSP
Timers
Slave
Interrupts
Pull-up
Basic
RA0 2 27 AN0 C12IN0- — — — — — — — — —
RA1 328 AN1 C12IN1- — — — — — — — — —
RA2 4 1 AN2 C2IN+ VREF-/
CVREF ——— ———— —
RA3 5 2 AN3 C1IN+ VREF+ — — — — — — — —
RA4 6 3 — C1OUT — — — — T0CKI — — — —
RA5 7 4 AN4 C2OUT HLVDIN — — SS — — — — —
RA6 10 7 — — — — — — — — — — OSC2/
CLKOUT
RA7 9 6 — — — — — — — — — — OSC1/
CLKIN
RB0 21 18 AN12 — — FLT0 — — — — INT0 Yes —
RB1 22 19 AN10 C12IN3- —P1C — — — — INT1 Yes —
RB2 23 20 AN8 — — P1B — — — — INT2 Yes —
RB3 24 21 AN9 C12IN2- CCP2(1) — — — — — Yes —
RB4 25 22 AN11 — — P1D — — — — KBI0 Yes —
RB5 26 23 — — — — — — — — KBI1 Yes PGM
RB6 27 24 — — — — — — — — KBI2 Yes PGC
RB7 28 25 — — — — — — — — KBI3 Yes PGD
RC0 11 8 — — — — — — T1OSO/
T13CKI ——— —
RC1 12 9 — — — CCP2(2) — — T1OSI — — — —
RC2 13 10 — — — CCP1/
P1A —— — ——— —
RC3 14 11 — — — — — SCK/
SCL — — — — —
RC4 15 12 — — — — — SDI/
SDA ———— —
RC5 16 13 — — — — — SDO — — — — —
RC6 17 14 — — — — TX/CK — — — — — —
RC7 18 15 — — — — RX/DT — — — — — —
RE3(3) 126 —— ————————
MCLR/
VPP
8 5 — — — — — — — — — — VSS
19 16 — — — — — — — — — — VSS
20 17 — — — — — — — — — — VDD
Note 1: CCP2 multiplexed with RB3 when CONFIG3H<0> = 0
2: CCP2 multiplexed with RC1 when CONFIG3H<0> = 1
3: Input-only
2010-2015 Microchip Technology Inc. DS40001303H-page 7
PIC18F2XK20/4XK20
TABLE 2: 40/44-PIN ALLOCATION TABLE (PIC18F4XK20)
I/O
40-Pin PDIP
40-Pin UQFN
44-Pin TQFP
44-Pin QFN
Analog
Comp.
Reference
ECCP
EUSART
MSSP
Timers
Slave
Interrupts
Pull-up
Basic
RA0 217 19 19 AN0 C12IN0
-— — — — — — — — —
RA1 3 18 20 20 AN1 C12IN1
-———————— —
RA2 419 21 21 AN2 C2IN+ VREF-/
CVREF — — — — — — — —
RA3 5 20 22 22 AN3 C1IN+ VREF+— — — — — — — —
RA4 621 23 23 —C1OUT — — — — T0CKI — — — —
RA5 7 22 24 24 AN4 C2OUT HLVDIN ——
SS ———— —
RA6 14 29 31 33 — — — — — — — — — — OSC2/
CLKOUT
RA7 13 28 30 32 — — — — — — — — — — OSC1/
CLKIN
RB0 33 8 8 9 AN12 — — FLT0 — — — — INT0 Yes —
RB1 34 9 9 10 AN10 C12IN3
-——————INT1Yes —
RB2 35 10 10 11 AN8 — — — — — — — INT2 Yes —
RB3 36 11 11 12 AN9 C12IN2
-— CCP2(1) —— — — —Yes —
RB4 37 12 14 14 AN11 — — — — — — — KBI0 Yes —
RB5 38 13 15 15 — — — — — — — — KBI1 Yes PGM
RB6 39 14 16 16 — — — — — — — — KBI2 Yes PGC
RB7 40 15 17 17 — — — — — — — — KBI3 Yes PGD
RC0 15 30 32 34 — — — — — — T1OSO/
T13CKI — — — —
RC1 16 31 35 35 — — — CCP2(2) ——T1OSI— —— —
RC2 17 32 36 36 — — — CCP1/
P1A — — — — — — —
RC3 18 33 37 37 — — — — — SCK/
SCL ———— —
RC4 23 38 42 42 — — — — — SDI/
SDA — — — — —
RC5 24 39 43 43 — — — — — SDO — — — — —
RC6 25 40 44 44 — — — — TX/
CK — — — — — —
RC7 26 1 1 1 — — — — RX/
DT ————— —
RD0 19 34 38 38 — — — — — — — PSP0 — — —
RD1 20 35 39 39 — — — — — — — PSP1 — — —
RD2 21 36 40 40 — — — — — — — PSP2 — — —
RD3 22 37 41 41 — — — — — — — PSP3 — — —
RD4 27 2 2 2 — — — — — — — PSP4 — — —
RD5 28 3 3 3 — — — P1B — — — PSP5 — — —
RD6 29 4 4 4 — — — P1C — — — PSP6 — — —
Note 1: CCP2 multiplexed with RB3 when CONFIG3H<0> = 0
2: CCP2 multiplexed with RC1 when CONFIG3H<0> = 1
3: Input-only.
PIC18F2XK20/4XK20
DS40001303H-page 8 2010-2015 Microchip Technology Inc.
RD7 30 5 5 5 — — — P1D — — — PSP7 — — —
RE0 823 25 25 AN5 — — — — — — RD — — —
RE1 9 24 26 26 AN6 ——————
WR —— —
RE2 10 25 27 27 AN7 — — — — — — CS — — —
RE3(3) 1161818 ——————————
MCLR/VPP
—11 7 7 7 — — — — — — — — — — VDD
—32262828 — — — — — — — — — — VDD
—12 6 6 6 — — — — — — — — — — VSS
—31272930 — — — — — — — — — — VSS
— – — NC 8 — — — — — — — — — — VDD
—–—NC29— — — — —— — — — — VDD
—–- —NC 31 — — — — — — — — — — VSS
TABLE 2: 40/44-PIN ALLOCATION TABLE (PIC18F4XK20) (CONTINUED)
I/O
40-Pin PDIP
40-Pin UQFN
44-Pin TQFP
44-Pin QFN
Analog
Comp.
Reference
ECCP
EUSART
MSSP
Timers
Slave
Interrupts
Pull-up
Basic
Note 1: CCP2 multiplexed with RB3 when CONFIG3H<0> = 0
2: CCP2 multiplexed with RC1 when CONFIG3H<0> = 1
3: Input-only.
2010-2015 Microchip Technology Inc. DS40001303H-page 9
PIC18F2XK20/4XK20
Table of Conte nts
1.0 Device Overview ....................................................................................................................... ...... ..... ...... ...... ..... ...... ...... .. ...... 11
2.0 Oscillator Module (With Fail-Safe Clock Monitor)...................................................................................................................... 26
3.0 Power-Managed Modes............................. ....... .. .... .. .... ....... .... .. .... .... .. ....... .... .... .. .... ....... .... ..................................................... 41
4.0 Reset......................................................................................................................................................................................... 48
5.0 Memory O rganization................................................................................................................................................................ 61
6.0 Flash Pro g ram Memory...................... ...... ....... ...... ...... ....... ...... ...... ...... ....... ...... ................. ....................................................... 84
7.0 Data EEP R OM Memo ry.... ........... ...... ...... ....... ...... ...... ....... ...... ................. .............................. ........ . ...... ...... ...... ..... .. ...... ...... .... 93
8.0 8 x 8 Hardware Multiplier............................................................................................................. ..... ...... ...... ...... ..... ...... .. ...... .... 98
9.0 Interrupts................................................................................................................................................................................. 100
10.0 I/O Ports.............. ...... ...... ...... ....... ...... ................................ ..................... ...... ...... .................................................................... 113
11.0 Capture/Compare/PWM (CCP) Modules ............................................................................... ........ ... ...................................... 134
12.0 Tim er0 Module ........................................................................................................................ ...... ..... ...... ...... ...... ..... ...... ...... .. 145
13.0 Tim er1 Module ........................................................................................................................ ...... ..... ...... ...... ...... ..... ...... ...... .. 148
14.0 Tim er2 Module ........................................................................................................................ ...... ..... ...... ...... ...... ..... ...... ...... .. 155
15.0 Tim er3 Module ........................................................................................................................ ...... ..... ...... ...... ...... ..... ...... ...... .. 157
16.0 Enhanc ed Capture/Com pare/P WM (ECCP) Module........................................................................................ .. ..... ...... ...... .. .. 161
17.0 Master Synchronous Serial Port (M SSP ) Module ................................................................................................................... 179
18.0 Enhanc ed Universal Sync hronous Asynchronous Receiver Transmitter (EUSART).......................................................... .. .. 22 2
19.0 Analog-t o-Digital Converter (AD C) Module ............................................................................................................................. 249
20.0 Comparator Module.......................... .... .... ......... .... .. .... .... ......... .... .. .... ......... .... .. .... .... .............................................................. 262
21.0 Voltage References..... .. .... .. ....... .... .. .. .... .. .. ....... .... .. .. .... .. ....... .... .. .. .... .. ....... .. .... .. .. .... ................ ...... ..... ...... ...... ..... ...... ...... ...... 2 7 2
22.0 High/Low-Voltage Detect (HLVD)............................ .... ............. .... ...... ........... ...... .... ............. ................................................... 276
23.0 Specia l Features of the CPU......................................... ....... ...... ................. ...... ...... ................................................................ 281
24.0 Instruction Set Summary......................................................................................................................................................... 296
25.0 Development Support............................................................................................................ .. ...... ..... ...... ...... ...... ..... ...... ...... .. 346
26.0 Electrical Characteristics........................................................................................................... ...... ..... ...... ...... ..... ...... ...... ...... 3 5 0
27.0 DC and AC Characteristics Graphs and Tables..................... .... ...... .... ......... .... .... .... ........... .... .... ..... ...................................... 387
28.0 Packagin g In fo rmation....................................... ...... ...... ................. ...... ....... ................. ........................................................... 410
Appendix A: Revision History . ........................................................................................................................................................... 435
Appendix B: Device Differences ....................................................................................................... ...... ..... ...... ...... ...... ..... ...... ...... .. 436
The Micro chip Web Si te...... ...... ...... ................................ ..................... ...... ....... ................................................................................ 437
Customer Change Notification Service................................................................................................... ..... ...... ...... ...... ..... ...... ...... .. 437
Customer Support................................................................. ................. ...... ................. .................................................................... 437
Product Identification System ........................................................................................................................................................... 438
PIC18F2XK20/4XK20
DS40001303H-page 10 2010-2015 Microchip Technology Inc.
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
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The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
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To determine if an errata sheet exists for a particular device, please check with one of the following:
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2010-2015 Microchip Technology Inc. DS40001303H-page 11
PIC18F2XK20/4XK20
1.0 DEVICE OVERVIEW
This do cu me nt co nta i ns dev ic e spec if i c in for m at ion fo r
the following devices:
This family offers the advantages of all PIC18
microcontrollers – namely, high computational
performance at an economical price – with the addition
of high-endurance, Flash program memory. On top of
these features, the PIC18F2XK20/4XK20 family
introduces design enhancements that make these
microcontrollers a logical choice for many
high-performance, power sensitive applications.
1.1 New Core Features
1.1.1 XLP TECHNOLOGY
All of the devices in the PIC18F2XK20/4XK20 family
incorporate a range of features that can significantly
reduce power consumption during operation. Key
items include:
•Alternate Run Modes: By clocking the controller
from the Timer1 source or the internal oscillator
block, power consumption during code execution
can be reduced by as much as 90%.
•Multiple Idle Modes: The controller can also run
with its CPU core disabled but the peripherals still
active . In these st ates, powe r consumptio n can be
reduced even further, to as little as 4% of normal
operation requirements.
•On-the-fly Mode Switch ing: The power-
manage d mode s a re invo ked b y user code d urin g
operation, allowing the user to incorporate
power-saving ideas into their application’s
software design.
•Low Consumption in Key Modules: The
power requirements for both Timer1 and the
Watchdog Timer are minimized. See
Section 26.0 “Electrical Specifications”
for values.
1.1.2 MULTIPLE OSCILLATOR OPTIONS
AND FEATURES
All of the devices in the PIC18F2XK20/4XK20 family
offer ten different oscillator options, allowing users a
wide range of choices in developing application
hardware. These include:
• Four Crystal modes, using crystals or ceramic
resonators
• Two External Clock modes, offering the option of
using two pins (oscillator input and a divide-by-4
clock output) or one pin (oscillator input, with the
second pin reassigned as general I/O)
• Two External RC Oscillator modes with the same
pin options as the External Clock modes
• An internal oscillator block which contains a
16 MHz HFINTOSC oscillator and a 31 kHz
LFINTOSC oscillator which together provide 8
user selec t able clock frequenci es , from 31 kHz to
16 MHz. This option frees the two oscillator pins
for use as additional general purpose I/O.
• A Phase Lo ck Loop (PLL) frequency multiplier,
ava ilable to both the high- speed crystal and inter-
nal o scillator mode s, which a llows clock speeds of
up to 64 MHz. Used wi th the internal oscillator, th e
PLL gives users a complete selection of clock
speeds , from 31 kHz to 64 MHz – all w ithout usin g
an external crystal or clock circuit.
Besides its availability as a clock source, the internal
oscill ato r blo ck pro vid es a s t ab le reference source th at
gives the family additional features for robust
operation:
•Fail-Safe Clock Monitor: This option constantly
monitors the main clock source against a
reference signal provided by the LFINTOSC. If a
clock failure occurs, the controller is switched to
the intern al oscill ator block , allowing f or continue d
operation or a safe application shutdown.
•Two-S pe ed S tart-up: This option allows the
internal oscillator to serve as the clock source
from Power-on Reset , or wake-up from Sleep
mode, until the prim ary clock source is available.
• PIC18F23K20 • PIC18F43K20
• PIC18F24K20 • PIC18F44K20
• PIC18F25K20 • PIC18F45K20
• PIC18F26K20 • PIC18F46K20
PIC18F2XK20/4XK20
DS40001303H-page 12 2010-2015 Microchip Technology Inc.
1.2 Other Speci al Features
•Memory Endurance: The Flash cells for both
program memory and data EEPROM are rated to
last for many thousands of erase/write cycles – up to
10K for program memory and 100K for EEPROM.
Data retention without refresh is conservatively
estimated to be greater than 40 years.
•Self-programmability: These devices can write
to their own progr am memory spaces under
internal software control. By using a bootloader
routine located in the protected Boot Block at the
top of program memory, it becomes possible to
create an application that can update itself in the
field.
•Extended Instruction Set: The PIC18F2XK20/
4XK20 family introduces an optional extension to
the PIC18 instruction set, which adds eight new
instructions and an Indexed Addressing mode.
This ext ensio n, enabl ed as a de vice c onf igurati on
option, has b een specifi cally des igned to opt imize
re-ent rant appli cation c ode origi nally d eveloped in
high-level languages, such as C.
•Enhanced CCP module: In PWM mode, this
module provides 1, 2 or 4 modulated outputs for
controlling half-bridge and full-bridge drivers.
Other features include:
- Auto-Shutdown, for disabling PWM outputs
on interrupt or other select conditions
- Auto-Restart, to reactivate outputs once the
conditi on has clea red
- Output steering to selectively enable one or
more of four outputs to provide the PWM
signal.
•Enhanced Addressable EUSART: This serial
communication module is capable of standard
RS-232 operation an d provides support for th e LIN
bus protocol. Other enhancements include
automatic baud rate detection and a 16-bit Baud
Rate Genera tor for improved res olution. Whe n the
microcontroller is using the internal oscillator
block, the EUSART provides stable operation for
applications that talk to the outside world without
using an external crystal (or its accompanying
power requirement).
•10-bit A/D Converter: This module incorporates
programmable acquisition time, allowing for a
channel to be selected and a conversion to be
initiated without wai ting for a sa mp ling period and
thus, reduce code overhead.
•Extended Watchdog Timer (WDT): This
enhanced version incorporates a 16-bit
postscaler, allowing an extended time-out range
that is sta ble acros s ope rati ng vol tage and
temperature. See Section 26.0 “Electrical
Specifications” for time-out periods.
1.3 Details on Individual Famil y
Members
Devices in the PIC18F2XK20/4XK20 family are
available in 28-pin and 40/44-pin packages. Block
diagrams for the two groups are shown in Figure 1-1
and Figure 1-2.
The devices are differentiated from each other in five
ways:
1. Flash program memory (8 Kbytes for
PIC18F23K20/43K20 devices, 16 Kbytes for
PIC18F24K20/44K20 devices, 32 Kbytes for
PIC18F25K20/45K20 AND 64 Kbytes for
PIC18F26K20/46K20).
2. A/D channels (11 for 28-pin devices, 14 for
40/44-pin devices).
3. I/O ports (three bidirectional ports on 28-pin
devices, five bidirectional ports on 40/44-pin
devices).
4. Parallel Slave Port (present only on 40/44-pin
devices).
All other feature s for devi ces in th is fami ly are ide ntical.
These are summarized in Table 1-1.
The pinou ts for all devices are listed in the pin summary
tables: Table and Table , and I/O description tables:
Table 1-2 and Table 1-3.
2010-2015 Microchip Technology Inc. DS40001303H-page 13
PIC18F2XK20/4XK20
TABLE 1-1: DEVICE FEATURES
Features PIC18F23K20 PIC18F24K20 PIC18F25K20 PIC18F26K20 PIC18F43K20 PIC18F44K20 PIC18F45K20 PIC18F46K20
Operating Frequency(2) DC – 64 MHz DC – 64 MHz DC – 64 MHz DC – 64 MHz DC – 64 MHz DC – 64 MHz DC – 64 MHz DC – 64 MHz
Program Memory (Bytes) 8192 16384 32768 65536 8192 16384 32768 65536
Program Memory
(Instructions) 4096 8192 16384 32768 4096 8192 16384 32768
Data Memory (Bytes) 512 768 1536 3936 512 768 1536 3936
Data EEPROM Memory
(Bytes) 256 256 256 1024 256 256 256 1024
Interrupt Sources 19 19 19 19 20 20 20 20
I/O Ports A, B, C, (E)(1) A, B, C, (E)(1) A, B, C, (E)(1) A, B, C, (E)(1) A, B, C, D, E A, B, C, D, E A, B, C, D, E A, B, C, D, E
Timers 4 4 44 44 44
Capture/Compare/PWM
Modules 11111111
Enhanced Capture/
Compare/PWM Modules 1 1 11 11 11
Serial Communications MSSP, Enhanced
EUSART MSSP, Enhanced
EUSART MSSP, Enhanced
EUSART MSSP, Enhanced
EUSART MSSP, Enhanced
EUSART MSSP, Enha nce d
EUSART MSSP, Enhanced
EUSART MSSP, Enhanced
EUSART
Parallel Communica-
tions (PSP) No No No No Yes Yes Yes Yes
10-bit An alo g-t o-D igital
Module 1 internal plus 10
Input Channels 1 inter nal pl us 10
Input Channels 1 internal plus 10
Input Channels 1 internal plus 10
Input Channels 1 internal plus 13
Input Channels 1 internal plus 13
Input Chan ne ls 1 internal plus 13
Input Channels 1 internal plus 13
Input Channels
Resets (and Delays) POR, BOR, RESET
Instruction, Stack
Full, Stack Underflow
(PWRT, OST),
MCLR (optional),
WDT
POR, BOR, RESET
Instruction, Stack
Full, S tack Underflow
(PWRT , OST), MCLR
(o ptional), WDT
POR, BOR, RESET
Instructio n, Stack
Full, Stack Underflow
(PWRT, OST),
MCLR (optional),
WDT
POR, BOR, RESET
Instruction, Stack
Full, S ta ck Underflow
(PWR T , OST), MCL R
(o ptional), WDT
POR, BOR, RESET
Instruction, Stack
Full, Stack Underflow
(PWRT, OST),
MCLR (optional),
WDT
POR, BOR, RESET
Instruction, Stack
Full, Stack Underflow
(PWRT, OST),
MCLR (optional),
WDT
POR, BOR, RESET
Instruction, Stack
Full, Stack Underflow
(PWRT, OST),
MCLR (optional ),
WDT
POR, BOR, RESET
Instruction, Stack
Full, Stack
Underflow (PWRT,
OST), MCLR
(optional), WDT
Programmable High/
Low-Voltage Detect Yes Yes Yes Yes Yes Yes Yes Yes
Programmable Brown-
out Reset Yes Yes Yes Yes Yes Yes Yes Yes
Instruction Set 75 Instructions; 83
wit h Extended
Instruction Set
enabled
75 Instructions; 83
with Extended
Instruction Set
enabled
75 Instructions; 83
wit h Extended
Instruction Set
enabled
75 Instructions; 83
with Extended
Instruction Set
enabled
75 Instructions; 83
with Extended
Instruction Set
enabled
75 Instructions; 83
with Exten ded
Instruction Set
enabled
75 Instructions; 83
with Extended
Instruction Set
enabled
75 Instructions; 83
with Extended
Instruc tion Set
enabled
Packages 28-pin PDIP
28-pin SOIC
28-pin QFN
28-pin SSOP
28-pin UQF N
28-pin PD IP
28-pin SOIC
28-pin QFN
28-pin SSO P
28-pin PDIP
28-pin SOIC
28-pin QFN
28-pin SSOP
28-pin PDIP
28-pin SOIC
28-pin QFN
28-pin SSO P
40-pin PDI P
44-pin QFN
44-pin TQFP
40-pin UQFN
40-pin PDIP
44-pin QFN
44-pin TQFP
40-pin UQFN
40-pin PD IP
44-pin QFN
44-pin TQFP
40-pin UQFN
40-pin PDIP
44-pin QFN
44-pin TQFP
40-pin UQFN
Note 1: PORTE contains the single RE3 read-only bit. The LATE and TRISE registers are not implemented.
2: Frequency range shown applies to industrial range devices only. Maximum frequency for extended range devices is 48 MHz.
PIC18F2XK20/4XK20
DS40001303H-page 14 2010-2015 Microchip Technology Inc.
FIGURE 1-1: PIC18F2XK20 (28-PIN) BLOCK DIAGRAM
Instruction
Decode and
Control
PORTA
PORTB
PORTC
RA4/T0CKI/C1OUT
RA5/AN4/SS/HLVDIN/C2OUT
RB0/INT0/FLT0/AN12
RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2(1)
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
RA3/AN3/VREF+
RA2/AN2/VREF-/CVREF
RA1/AN1
RA0/AN0
RB1/INT1/AN10/C12IN3-
Data Latch
Data Memory
Address Latch
Dat a Addr ess<12 >
12
Access
BSR FSR0
FSR1
FSR2
inc/dec
logic
Address
412 4
PCH PCL
PCLATH
8
31-Level Stack
Program Counter
PRODLPRODH
8 x 8 Multiply
8
BITOP 8
8
ALU<8>
20
8
8
Table Pointer<21>
inc/dec logic
21
8
Data Bus<8>
Table Latch
8
IR
12
3
ROM Latch
RB2/INT2/AN8
RB3/AN9/CCP2(1)/C12IN2-
PCLATU
PCU
OSC2/CLKOUT(3)/RA6
Note 1: CCP2 is multiplexed with RC1 when Configuration bit CCP2MX is set, or RB3 when CCP2MX is not set.
2: RE3 is only available when MCLR functionality is disabled.
3: OSC1/CLKIN and OSC2/CLKOUT are only available in select oscillator modes and when these pins are not being used as digital I/O.
Refer to S ect io n 2.0 “Osc illa to r Mo dule (Wi th Fail-Sa fe Clock Monit or)” for additional information.
RB4/KBI0/AN11
RB5/KBI1/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD
EUSARTComparator MSSP 10-bit
ADC
Timer2Timer1 Timer3Timer0
CCP2
HLVD
ECCP1
BOR Data
EEPROM
W
Instruction Bus <16>
STKPTR Bank
8
State machine
control signals
Decode
8
8
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
OSC1(3)
OSC2(3)
VDD,
Brown-out
Reset
Internal
Oscillator
Fail-Safe
Clock Monitor
Precision
Reference
Band Gap
VSS
MCLR(2)
Block
LFINTOSC
Oscillator
16 MHz
Oscillator
Single-Supply
Programming
In-Circuit
Debugger
T1OSO
OSC1/CLKIN(3)/RA7
T1OSI
PORTE
MCLR/VPP/RE3(2)
FVR
FVR
FVR
CVREF
Address Latch
Prog ram Memo ry
(8/16/32/64 Kbytes)
Data Latch
2010-2015 Microchip Technology Inc. DS40001303H-page 15
PIC18F2XK20/4XK20
FIGURE 1-2: PIC18F4X K20 (40/44-PIN) BLOCK DIAGRAM
Instruction
Decode and
Control
Data Latch
Dat a Memory
Addr ess La tch
Dat a Addr ess<12 >
12
Access
BSR FSR0
FSR1
FSR2
inc/dec
logic
Address
412 4
PCH PCL
31-Level Stack
Program Counter
PRODLPRODH
8 x 8 Multiply
8
BITOP 8
8
ALU<8>
Address Lat ch
Program Memory
(8/16/32/64Kbytes)
Data Latch
20
8
8
Table Pointer<21>
inc/dec logic
21
Data Bus<8>
Table Latch
8
IR
12
3
ROM Latch
PORTD RD0/PSP0
PCU
PORTE
MCLR/VPP/RE3(2)
RE2/CS/AN7
RE0/RD/AN5
RE1/WR/AN6
Note 1: CCP2 is multiplexed with RC1 when Configuration bit CCP2MX is set, or RB3 when CCP2MX is not set.
2: RE3 is only available when MCLR functionali ty is di sab led.
3: OSC1/CLKIN and OSC2/CLKOUT are only available in select oscillator modes and when these pins are not being used as digital I/O.
Refer to Section 2.0 “Oscillator Module (With Fail-Safe Clock Monitor)” for additional information.
EUSARTComparator MSSP 10-bit
ADC
Timer2Timer1 Timer3Timer0
CCP2
HLVD
ECCP1
BOR Data
EEPROM
W
Instruction Bus <16>
STKPTR Bank
8
State machine
control signals
Decode
8
8
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
OSC1(3)
OSC2(3)
VDD,
Brown-out
Reset
Internal
Oscillator
Fail-Safe
Clock Monitor
Precision
Reference
Band Gap
VSS
MCLR(2)
Block
LFINTOSC
Oscillator
16 MHz
Oscillator
Single-Supply
Programming
In-Circuit
Debugger
T1OSI
T1OSO
RD1/PSP1
RD2/PSP2
RD3/PSP3
PORTA
PORTB
PORTC
RA4/T0CKI/C1OUT
RA5/AN4/SS/HLVDIN/C2OUT
RB0/INT0/FLT0/AN12
RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2(1)
RC2/CCP1/P1A
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
RA3/AN3/VREF+
RA2/AN2/VREF-/CVREF
RA1/AN1
RA0/AN0
RB1/INT1/AN10/C12IN3-
RB2/INT2/AN8
RB3/AN9/CCP2(1)/C12IN2-
OSC2/CLKOUT(3)/RA6
RB4/KBI0/AN11
RB5/KBI1/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD
OSC1/CLKIN(3)/RA7
RD4/PSP4
RD5/PSP5/P1B
RD6/PSP6/P1C
RD7/PSP7/P1D
FVR
FVR PSP
FVR
CVREF
PCLATH
88
PCLATU
PIC18F2XK20/4XK20
DS40001303H-page 16 2010-2015 Microchip Technology Inc.
TABLE 1-2: PIC18F2XK20 PINOUT I/O DESCRIPTIONS
Pin Name Pin N um b e r Pin
Type Buffer
Type Description
PDIP,
SOIC QFN
MCLR/VPP/RE3
MCLR
VPP
RE3
126I
P
I
ST
ST
Master Clear (input) or programming voltage (input)
Active-low Master Clear (device Reset) input
Prog rammi ng voltage input
Digital input
OSC1/CLKIN/RA7
OSC1
CLKIN
RA7
96I
I
I/O
ST
CMOS
TTL
Oscillator crystal or external clock input
Oscillator crystal input or external clock source input
ST buffer when configured in RC mode; CMOS otherwise
External clock source input. Always associated with pin
function OSC1. (See related OSC1/CLKIN, OSC2/CLKOUT
pins)
General purpose I/O pin
OSC2/CLKOUT/RA6
OSC2
CLKOUT
RA6
10 7 O
O
I/O
—
—
TTL
Oscillator crystal or clock output
Oscillator crystal output. Connects to crystal or
resonator in Crystal Oscill ator mode
In RC mod e, OSC2 pi n outputs CLKOUT which h as 1/4 th e
frequency of OSC1 and denotes the instruction cycle rate
General purpose I/O pin
Legend: TTL= TTL co mpatible input CMOS = CMOS compatible input or outp ut
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Default assignment for CCP2 when Configu rati on bit CCP2MX i s set.
2: Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared.
2010-2015 Microchip Technology Inc. DS40001303H-page 17
PIC18F2XK20/4XK20
PORTA is a bidirectional I/O port.
RA0/AN0/C12IN0-
RA0
AN0
C12IN0-
227
I/O
I
I
TTL
Analog
Analog
Digital I/O
Analog input 0, ADC channel 0
Comparators C1 and C2 inverting input
RA1/AN1/C12IN1-
RA1
AN1
C12IN1-
328
I/O
I
I
TTL
Analog
Analog
Digital I/O
ADC input 1, ADC channel 1
Comparators C1 and C2 inverting input
RA2/AN2/VREF-/CVREF/
C2IN+
RA2
AN2
VREF-
CVREF
C2IN+
41
I/O
I
I
O
I
TTL
Analog
Analog
Analog
Analog
Digital I/O
Analog input 2, ADC channel 2
A/D reference voltage (low) input
Comparator reference voltage output
Comparator C2 non-inverting input
RA3/AN3/VREF+/C1IN+
RA3
AN3
VREF+
C1IN+
52
I/O
I
I
I
TTL
Analog
Analog
Analog
Digital I/O
Analog input 3, ADC channel 3
A/D reference voltage (high) input
Comparator C1 non-inverting input
RA4/T0CKI/C1OUT
RA4
T0CKI
C1OUT
63
I/O
I
O
ST
ST
CMOS
Digital I/O
Timer0 external clock input
Comparator C1 output
RA5/AN4/SS/HLVDIN/
C2OUT
RA5
AN4
SS
HLVDIN
C2OUT
74
I/O
I
I
I
O
TTL
Analog
TTL
Analog
CMOS
Digital I/O
Analog input 4, ADC channel 4
SPI slave select input
High/L ow- Volt age Detect inpu t
Comparator C2 output
RA6 See the OSC2/CLKOUT/RA6 pin
RA7 See the OSC1/CLKIN/RA7 pin
TABLE 1-2: PIC18F2XK20 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name Pin N um b e r Pin
Type Buffer
Type Description
PDIP,
SOIC QFN
Legend: TTL= TTL c ompatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Default assignment for CCP2 when Configuration bit CCP2MX is set.
2: Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared.
PIC18F2XK20/4XK20
DS40001303H-page 18 2010-2015 Microchip Technology Inc.
PORTB is a bidirectional I/O port. PORTB can be software
programmed for internal weak pull-up on each input.
RB0/INT0/FLT0/AN12
RB0
INT0
FLT0
AN12
21 18 I/O
I
I
I
TTL
ST
ST
Analog
Digital I/O
External interrupt 0
PWM Fault input for CCP1
Analog input 12, ADC channel 12
RB1/INT1/AN10/C12IN3-
/P1C
RB1
INT1
AN10
C12IN3-
P1C
22 19
I/O
I
I
I
O
TTL
ST
Analog
Analog
CMOS
Digital I/O
External interrupt 1
Analog input 10, ADC channel 10
Comparators C1 and C2 inverting input
Enhanced CCP1 PWM output
RB2/INT2/AN8/P1B
RB2
INT2
AN8
P1B
23 20 I/O
I
I
O
TTL
ST
Analog
CMOS
Digital I/O
External interrupt 2
Analog input 8, ADC channel 8
Enhanced CCP1 PWM output
RB3/AN9/C12IN2-/CCP2
RB3
AN9
C12IN2-
CCP2(2)
24 21 I/O
I
I
I/O
TTL
Analog
Analog
ST
Digital I/O
Analog input 9, ADC channel 9
Comparators C1 and C2 inverting input
Capture 2 input/Compare 2 output/PWM 2 output
RB4/KBI0/AN11/P1D
RB4
KBI0
AN11
P1D
25 22 I/O
I
I
O
TTL
TTL
Analog
CMOS
Digital I/O
Interrupt-on-change pin
Analog input 11, ADC channel 11
Enhanced CCP1 PWM output
RB5/KBI1/PGM
RB5
KBI1
PGM
26 23 I/O
I
I/O
TTL
TTL
ST
Digital I/O
Interrupt-on-change pin
Low-Voltage ICSP™ Programming enable pin
RB6/KBI2/PGC
RB6
KBI2
PGC
27 24 I/O
I
I/O
TTL
TTL
ST
Digital I/O
Interrupt-on-change pin
In-Circuit Debugger and ICSP™ programming clock pin
RB7/KBI3/PGD
RB7
KBI3
PGD
28 25 I/O
I
I/O
TTL
TTL
ST
Digital I/O
Interrupt-on-change pin
In-Circuit Debugger and ICSP™ programming data pin
TABLE 1-2: PIC18F2XK20 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name Pin N um b e r Pin
Type Buffer
Type Description
PDIP,
SOIC QFN
Legend: TTL= TTL c ompatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Default assignment for CCP2 when Configu rati on bit CCP2MX i s set.
2: Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared.
2010-2015 Microchip Technology Inc. DS40001303H-page 19
PIC18F2XK20/4XK20
PORTC is a bidirectional I/O port.
RC0/T1OSO/T13CKI
RC0
T1OSO
T13CKI
11 8 I/O
O
I
ST
—
ST
Digital I/O
Timer1 os cillator output
Timer1/Timer3 external clock input
RC1/T1OSI/CCP2
RC1
T1OSI
CCP2(1)
12 9 I/O
I
I/O
ST
Analog
ST
Digital I/O
Timer1 oscillator input
Capture 2 input/Compare 2 output/PWM 2 output
RC2/CCP1/P1A
RC2
CCP1
P1A
13 10 I/O
I/O
O
ST
ST
CMOS
Digital I/O
Capture 1 input/Co mpare 1 output
Enhanced CCP1 PWM output
RC3/SCK/SCL
RC3
SCK
SCL
14 11 I/O
I/O
I/O
ST
ST
ST
Digital I/O
Synchronous serial clock input/output for SPI mode
Synchronous serial clock input/output for I2C™ mode
RC4/SDI/SDA
RC4
SDI
SDA
15 12 I/O
I
I/O
ST
ST
ST
Digital I/O
SPI data in
I2C™ data I/O
RC5/SDO
RC5
SDO
16 13 I/O
OST
—Digital I/O
SPI data out
RC6/TX/CK
RC6
TX
CK
17 14 I/O
O
I/O
ST
—
ST
Digital I/O
EUSART asynchronous transmit
EUSART synchronous clock (see related RX/DT)
RC7/RX/DT
RC7
RX
DT
18 15 I/O
I
I/O
ST
ST
ST
Digital I/O
EUSART asynchronous receive
EUSART synchronous data (see related TX/CK)
RE3 — — — — See MCLR/VPP/RE3 pin
VSS 8, 19 5, 16 P — Ground reference for logic and I/O pins
VDD 20 17 P — Positive supply for logic and I/O pins
TABLE 1-2: PIC18F2XK20 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name Pin N um b e r Pin
Type Buffer
Type Description
PDIP,
SOIC QFN
Legend: TTL= TTL c ompatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Default assignment for CCP2 when Configuration bit CCP2MX is set.
2: Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared.
PIC18F2XK20/4XK20
DS40001303H-page 20 2010-2015 Microchip Technology Inc.
TABLE 1-3: PIC18F4XK20 PINOUT I/O DESCRIPTIONS
Pin Name Pin Number Pin
Type Buffer
Type Description
PDIP QFN TQFP UQFN
MCLR/VPP/RE3
MCLR
VPP
RE3
1181816I
P
I
ST
ST
Master Clear (input) or programming voltage
(input)
Active-low Master Clear (device Reset) input
Programming voltage input
Digit al inp ut
OSC1/CLKIN/RA7
OSC1
CLKIN
RA7
13 32 30 28 I
I
I/O
ST
CMOS
TTL
Oscillator crystal or external clock input
Oscillator crystal input or external clock source
input
ST buffer when configured in RC mode;
analog otherwise
External clock source input. Always associated
with
pin function OSC1 (See related OSC1/CLKIN,
OSC2/CLKOUT pins)
General pur pose I/O pin
OSC2/CLKOUT/
RA6
OSC2
CLKOUT
RA6
14 33 31 29 O
O
I/O
—
—
TTL
Oscillator crystal or clock output
Oscillator crystal output. Connects to crystal
or resonator in Crystal Oscillator mode
In RC mode, OSC2 pin outputs CLKOUT which
has 1/4 the frequency of OSC1 and denotes
the instruction cycle rate
General pur pose I/O pin
Legend: TTL= TTL c ompatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Default assignment for CCP2 when Configu rati on bit CCP2MX i s set.
2: Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared.
2010-2015 Microchip Technology Inc. DS40001303H-page 21
PIC18F2XK20/4XK20
PORTA is a bi directional I/O port.
RA0/AN0/C12IN0-
RA0
AN0
C12IN0-
21919 I/O
I
I
TTL
Analog
Analog
Digit al I/O
Analog inpu t 0, ADC channel 0
Comparator C1 and C2 inverting input
RA1/AN1/C12IN0-
RA1
AN1
C12IN0-
32020 I/O
I
I
TTL
Analog
Analog
Digit al I/O
Analog inpu t 1, ADC channel 1
Comparator C1 and C2 inverting input
RA2/AN2/VREF-/
CVREF/C2IN+
RA2
AN2
VREF-
CVREF
C2IN+
42121
I/O
I
I
O
I
TTL
Analog
Analog
Analog
Analog
Digit al I/O
Analog inpu t 2, ADC channel 2
A/D reference voltage (low) input
Comparator reference voltage output
Comparator C2 non-inverting input
RA3/AN3/VREF+/
C1IN+
RA3
AN3
VREF+
C1IN+
52222
I/O
I
I
I
TTL
Analog
Analog
Analog
Digit al I/O
Analog inpu t 3, ADC channel 3
A/D reference voltage (high) input
Comparator C1 non-inverting input
RA4/T0CKI/C1OUT
RA4
T0CKI
C1OUT
62323 I/O
I
O
ST
ST
CMOS
Digit al I/O
Timer0 exter nal clock input
Comparator C1 output
RA5/AN4/SS/HLV-
DIN/C2OUT
RA5
AN4
SS
HLVDIN
C2OUT
72424
I/O
I
I
I
O
TTL
Analog
TTL
Analog
CMOS
Digit al I/O
Analog inpu t 4, ADC channel 4
SPI slave select input
High/Low-Voltage Detect input
Comparator C2 output
RA6 See the OSC2/ C LKO UT/R A6 pin
RA7 See the OSC1/CLKIN/RA7 pin
TABLE 1-3: PIC18F4XK20 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name Pin Number Pin
Type Buffer
Type Description
PDIP QFN TQFP UQFN
Legend: TTL= TTL c ompatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Default assignment for CCP2 when Configuration bit CCP2MX is set.
2: Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared.
PIC18F2XK20/4XK20
DS40001303H-page 22 2010-2015 Microchip Technology Inc.
PORTB is a bidirectional I/O port. PORTB can
be software programmed for internal weak
pull-up on each input.
RB0/INT0/FLT0/
AN12
RB0
INT0
FLT0
AN12
33 9 8 I/O
I
I
I
TTL
ST
ST
Analog
Digit al I/O
External interrupt 0
PWM Fault input for Enhanced CCP1
Analog inpu t 12, ADC channel 12
RB1/INT1/AN10/
C12IN3-
RB1
INT1
AN10
C12IN3-
34 10 9
I/O
I
I
I
TTL
ST
Analog
Analog
Digit al I/O
External interrupt 1
Analog inpu t 10, ADC channel 10
Comparator C1 and C2 inverting input
RB2/INT2/AN8
RB2
INT2
AN8
35 11 10 I/O
I
I
TTL
ST
Analog
Digit al I/O
External interrupt 2
Analog inpu t 8, ADC channel 8
RB3/AN9/C12IN2-/
CCP2
RB3
AN9
C12IN23-
CCP2(2)
36 12 11
I/O
I
I
I/O
TTL
Analog
Analog
ST
Digit al I/O
Analog inpu t 9, ADC channel 9
Comparator C1 and C2 inverting input
Capture 2 input/Compare 2 output/PWM 2
output
RB4/KBI0/AN11
RB4
KBI0
AN11
37 14 14 I/O
I
I
TTL
TTL
Analog
Digit al I/O
Interrupt-on-change pin
Analog inpu t 11, ADC channel 11
RB5/KBI1/PGM
RB5
KBI1
PGM
38 15 15 I/O
I
I/O
TTL
TTL
ST
Digit al I/O
Interrupt-on-change pin
Low-Volta ge ICSP™ Programming enable p in
RB6/KBI2/PGC
RB6
KBI2
PGC
39 16 16 I/O
I
I/O
TTL
TTL
ST
Digit al I/O
Interrupt-on-change pin
In-Circuit Debugger and ICSP™
programming cl ock pin
RB7/KBI3/PGD
RB7
KBI3
PGD
40 17 17 I/O
I
I/O
TTL
TTL
ST
Digit al I/O
Interrupt-on-change pin
In-Circuit Debugger and ICSP™
programming data pin
TABLE 1-3: PIC18F4XK20 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name Pin Number Pin
Type Buffer
Type Description
PDIP QFN TQFP UQFN
Legend: TTL= TTL c ompatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Default assignment for CCP2 when Configu rati on bit CCP2MX i s set.
2: Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared.
2010-2015 Microchip Technology Inc. DS40001303H-page 23
PIC18F2XK20/4XK20
PORTC is a bidi rectional I/O port.
RC0/T1OSO/
T13CKI
RC0
T1OSO
T13CKI
15 34 32 I/O
O
I
ST
—
ST
Digit al I/O
Timer1 oscillator out put
Timer1/Timer3 external clock input
RC1/T1OSI/CCP2
RC1
T1OSI
CCP2(1)
16 35 35 I/O
I
I/O
ST
CMOS
ST
Digit al I/O
Timer1 oscillator input
Capture 2 input/Compare 2 output/PWM 2
output
RC2/CCP1/P1A
RC2
CCP1
P1A
17 36 36 I/O
I/O
O
ST
ST
—
Digit al I/O
Capture 1 input/Compare 1 output/PWM 1
output
Enhanced CCP1 output
RC3/SCK/SCL
RC3
SCK
SCL
18 37 37 I/O
I/O
I/O
ST
ST
ST
Digit al I/O
Synchronous serial clock input/output for
SPI mode
Synchronous serial clock input/output for I2C™
mode
RC4/SDI/SDA
RC4
SDI
SDA
23 42 42 I/O
I
I/O
ST
ST
ST
Digit al I/O
SPI data in
I2C™ data I/O
RC5/SDO
RC5
SDO
24 43 43 I/O
OST
—Digit al I/O
SPI data out
RC6/TX/CK
RC6
TX
CK
25 44 44 I/O
O
I/O
ST
—
ST
Digit al I/O
EUSA RT asynchronous transmit
EU SART synchronous cloc k (see related RX/
DT)
RC7/RX/DT
RC7
RX
DT
26 1 1 I/O
I
I/O
ST
ST
ST
Digit al I/O
EUSA RT asynchronous receive
EU SART synchronous data (see related TX/
CK)
TABLE 1-3: PIC18F4XK20 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name Pin Number Pin
Type Buffer
Type Description
PDIP QFN TQFP UQFN
Legend: TTL= TTL c ompatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Default assignment for CCP2 when Configuration bit CCP2MX is set.
2: Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared.
PIC18F2XK20/4XK20
DS40001303H-page 24 2010-2015 Microchip Technology Inc.
PORTD is a bidi rectional I/O port or a Parallel
Slave Port (PSP) for interfacing to a
microproc es so r po rt. These pins have TTL inp ut
buffers when PSP module is enabled.
RD0/PSP0
RD0
PSP0
19 38 38 I/O
I/O ST
TTL Digit al I/O
Parallel Slave Port data
RD1/PSP1
RD1
PSP1
20 39 39 I/O
I/O ST
TTL Digit al I/O
Parallel Slave Port data
RD2/PSP2
RD2
PSP2
21 40 40 I/O
I/O ST
TTL Digit al I/O
Parallel Slave Port data
RD3/PSP3
RD3
PSP3
22 41 41 I/O
I/O ST
TTL Digit al I/O
Parallel Slave Port data
RD4/PSP4
RD4
PSP4
27 2 2 I/O
I/O ST
TTL Digit al I/O
Parallel Slave Port data
RD5/PSP5/P1B
RD5
PSP5
P1B
28 3 3 I/O
I/O
O
ST
TTL
—
Digit al I/O
Parallel Slave Port data
Enhanced CCP1 output
RD6/PSP6/P1C
RD6
PSP6
P1C
29 4 4 I/O
I/O
O
ST
TTL
—
Digit al I/O
Parallel Slave Port data
Enhanced CCP1 output
RD7/PSP7/P1D
RD7
PSP7
P1D
30 5 5 I/O
I/O
O
ST
TTL
—
Digit al I/O
Parallel Slave Port data
Enhanced CCP1 output
TABLE 1-3: PIC18F4XK20 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name Pin Number Pin
Type Buffer
Type Description
PDIP QFN TQFP UQFN
Legend: TTL= TTL c ompatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Default assignment for CCP2 when Configu rati on bit CCP2MX i s set.
2: Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared.
2010-2015 Microchip Technology Inc. DS40001303H-page 25
PIC18F2XK20/4XK20
PORTE is a bidirectional I/O port
RE0/RD/AN5
RE0
RD
AN5
82525 I/O
I
I
ST
TTL
Analog
Digit al I/O
Read control for Parallel Slave Port
(see related WR and CS pins)
Analog inpu t 5, ADC channel 5
RE1/WR/AN6
RE1
WR
AN6
92626 I/O
I
I
ST
TTL
Analog
Digit al I/O
Write control for Parallel Slave Port
(see related CS and RD pins)
Analog inpu t 6, ADC channel 6
RE2/CS/AN7
RE2
CS
AN7
10 27 27 I/O
I
I
ST
TTL
Analog
Digit al I/O
Chip Select control for Parallel Slave Port
(see related RD and WR)
Analog inpu t 7, ADC channel 7
RE3 — — — — — See M C LR/VPP/RE3 pin
VSS 12, 31 6, 30,
31 6, 29 P — Ground reference for logic and I/O pins
VDD 11, 32 7, 8,
28, 29 7, 28 P — Positive supply for logic and I/O pins
NC — 13 12, 13,
33, 34 — — No connect
TABLE 1-3: PIC18F4XK20 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name Pin Number Pin
Type Buffer
Type Description
PDIP QFN TQFP UQFN
Legend: TTL= TTL c ompatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Default assignment for CCP2 when Configuration bit CCP2MX is set.
2: Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared.
PIC18F2XK20/4XK20
DS40001303H-page 26 2010-2015 Microchip Technology Inc.
2.0 OSCILLATOR MODULE (WITH
FAIL-SAFE CLOCK MONITOR)
2.1 Overview
The oscillator module has a wide variety of clock
sources and selection features that allow it to be used
in a wide range of applications while maximizing
performance and minimizing power consumption.
Figure 2-1 illustrates a block diagram of the oscillator
module.
Clock sources can be configured from external
oscilla tors, quartz crystal resonators , cerami c resonator s
and Resistor-Capacitor (RC) circuits. In addition, the
system clock source can be configured from one of two
internal oscillators, with a choice of speeds selectable via
softw are . Add itio nal clo ck feat ures inc lud e:
• Selectable system clock source between external
or inter nal via software.
• Two-Speed Start- up mo de, whic h min im iz es
latency between external oscillator start-up and
code execution.
• Fail-Safe Clock Monitor (FSCM) designed to
detect a failure of the e x ter nal clock source (LP,
XT, HS, EC or RC modes) and switch
automati cally to the internal oscillator.
The oscillator module can be configured in one of ten
primary clock modes.
1. LP Low-Power Crystal
2. XT Crystal/Resonator
3. HS High-Speed Crystal/Resonator
4. HSPLL High-Speed Crystal/Resonator
with PLL enabled
5. RC External Resistor/Capacitor with
FOSC/4 output on RA6
6. RCIO External Resistor/Cap acitor with I/O
on RA 6
7. INTOSC Internal Oscillator with FOSC/4
output on RA6 and I/O on RA7
8. INTOSCIO Internal Oscillator with I/O on RA6
and RA7
9. EC External Clock with FOSC/4 output
10. ECIO External Clock with I/O on RA6
Primary Clock modes are selected by the FOSC<3:0>
bits of the CONFIG1H Configuration Register. The
HFINTOSC and LFINTOSC are factory calibrated
high-frequency and low-frequency oscillators,
respectively, which are used as the internal clock
sources.
FIGURE 2-1: PIC® MCU CLOCK SOURCE BLOCK DIAGRAM
4 x PLL
FOSC<3:0>
Secondar y Osc illa to r
T1OSCEN
Enable
Oscillator
T1OSO
T1OSI
Clock Source Option
for other Modules
OSC1
OSC2
Sleep HSPLL, HFINTOSC/PLL
LP, XT, HS, RC, EC
T1OSC
CPU
Peripherals
IDLEN
Postscaler
MUX
MUX
16 MHz
8 MHz
4 MHz
2 MHz
1 MHz
250 kHz
500 kHz
OSCCON<6:4>
111
110
101
100
011
010
001
000
31 kHz
31 kHz
Source
Internal
Oscillator
Block
WDT, PWRT, FSCM
16 MHz
Internal Oscillator
(HFINTOSC)
Clock
Control
OSCCON<1:0>
Source
16 MHz
31 kHz (LFINTOSC)
OSCTUNE<6>(1)
0
1
OSCTUNE<7>
and Two-Speed Start-up
Primary Oscillator PIC18F2XK20/4XK20
Sleep
Sleep
Main
FOSC<3:0> OSCCON<1:0>
Note 1: Operates only when HFINTOSC is the primary oscillator.
2010-2015 Microchip Technology Inc. DS40001303H-page 27
PIC18F2XK20/4XK20
2.2 Oscillator Control
The OSCCON register (Register 2-1) controls several
aspects of the device clock’s operation, both in full
power ope ratio n and in pow e r-ma nag ed mo des .
• Main System Clock Selection (SCS)
• Intern al Freq uen cy sele cti on bits (IRCF)
• Clock Status bits (OSTS, IOFS)
• Power management selection (IDLEN)
2.2. 1 MAIN SYSTEM CLOCK SELECTION
The System Clock Select bits, SCS<1:0>, select the
main clock source. The available clock sources are
• Primary clock defined by the FOSC<3:0> bits of
CONFIG 1H. The primary clock can be the primary
oscillator, an external clock, or the internal
oscillator block.
• Secondary clock (Timer1 oscillator)
• Internal oscillator blo ck (HFINTOSC and
LFINTOSC).
The clock source changes immediately after one or
more of the bits is written to, following a brief clock
transition interval. The SCS bits are cleared to select
the prima ry clock on all forms of Reset.
2.2.2 INTERNAL FREQUENCY
SELECTION
The Internal Oscillator Frequency Select bits
(IRCF<2:0 >) selec t the fr equency output of th e interna l
oscill ator block. The choices are the LF INTOSC so urce
(31 kHz), the HFINTOSC source (16 MHz) or one of
the frequencies derived from the HFINTOSC
postscaler (31.25 kHz to 8 MHz). If the internal
oscillator block is supplying the main clock, changing
the states of these bits will have an immediate change
on the internal oscillator’s output. On device Resets,
the output frequency of the internal oscillator is set to
the default frequency of 1 MHz.
2.2.3 LOW FREQUENCY SELECTION
When a nominal ou tput frequenc y of 31 kHz is selecte d
(IRCF<2:0> = 000), users may choose which internal
oscillator acts as the source. This is done with the
INTSRC bit of the OSCTUNE register. Setting this bit
selects the HFINTOSC as a 31.25 kHz clock source by
enabling the divide-by-512 output of the HFINTOSC
postscaler. Clearing INTSRC selects LFINTOSC
(nominally 31 kHz) as the clock source.
This option allows users to select the tunable and more
precise HFINTOSC as a clock source, while
maint aining pow er savings wi th a very low clock speed.
Regardless of the setting of INTSRC, LFINTOSC
always remains the clock source for features such as
the Watchdog Timer and the Fail-Safe Clock Moni tor.
2.2.4 CLOCK STATUS
The OS TS and IOFS bits of the OSCCON reg ister, and
the T1RUN bit of the T1CON register, indicate which
clock s ou rce is c urr e ntl y pr ov id in g the ma i n clo ck. The
OSTS bit indicates that the Oscillator Start-up Timer
has timed out and the primary clock is providing the
dev ice c loc k. The IOF S b it in dica tes when th e in tern al
oscillator block has stabilized and is providing the
device clock in HFINTOSC Clock modes. The IOFS
and OSTS Status bits will both be set when
SCS<1:0> = 00 and HFINTOSC is the primary clock.
The T 1RUN bit indi cate s wh en th e Timer1 osc ill ato r is
providing the device clock in secondary clock modes.
When SCS<1:0> 00, only one of these three bits will
be set at any time. If none of these bits are set, the
LFINTOSC is providing th e clock or the HFINTOSC has
just started and is not yet stable.
2.2.5 POWER MANAGEMENT
The IDLEN bit of the OSCCON register determines if
the device goes into Sleep mode or one of the Idle
modes wh en the SLEEP instructi on is executed.
The use of the flag and control bits in the OSCCON
register is discussed in more detail in Section 3.0
“Power-M ana ged Modes”.
Note 1: The Timer1 os ci ll ator must be enabled to
select the secondary clock source. The
T imer1 os cillator is enabled by s etting the
T1OSCEN bit of the T1CON register. If
the Timer1 oscillator is not enabled, then
the main oscillator will continue to run
from th e pre vi o us ly sel e ct ed so ur c e. The
source will then switch to the secondary
oscillator after the T1OSCEN bit is set.
2: It is recommended that the Timer1
oscillator be operating and stable before
selecting the secondary clock source or a
very long delay may occur while the
Timer1 oscillator starts.
PIC18F2XK20/4XK20
DS40001303H-page 28 2010-2015 Microchip Technology Inc.
REGISTER 2-1: OSCCON: OSCILLATOR CONTROL REGISTER
R/W-0 R/W-0 R/W-1 R/W-1 R-q R-0 R/W-0 R/W-0
IDLEN IRCF2 IRCF1 IRCF0 OSTS(1) IOFS SCS1 SCS0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ q = depends on condition
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 IDLEN: Idle Enable bit
1 = Device enters Idle mode on SLEEP instruction
0 = Device enters Slee p mode on SLEEP instruction
bit 6-4 IRCF<2:0>: Internal Oscillator Frequency Select bits
111 = 16 MHz (HFINTOSC drives clock directl y )
110 = 8 MHz
101 = 4 MHz
100 = 2 MHz
011 = 1 MHz(3)
010 = 500 kHz
001 = 250 kHz
000 = 31 kHz (from either HFINTOSC/512 or LFINTOSC directly)(2)
bit 3 OSTS: Oscillator Start-up Time-out Status bit(1)
1 = Dev ice is running from the c lock defined b y FOSC <2:0> of the CONFIG1 r egister
0 = Dev ice is running from the inter nal oscillator (HFINTOSC or LFINTOSC)
bit 2 IOFS: HFINTOSC Frequency Stable bit
1 = HFINTOSC frequency is stable
0 = HFINTOSC frequency is not stable
bit 1-0 SCS<1:0>: System Clock Select bits
1x = Internal oscillator block
01 = Secondar y (Timer1 ) oscillator
00 = Primary clock (determined by CONFIG1H[FOSC<3:0>]).
Note 1: Reset state depends on state of the IESO Configuration bit.
2: Source selected by the INTSRC bit of the OSCTUNE register, see text.
3: Default output frequency of HFINTOSC on Reset.
2010-2015 Microchip Technology Inc. DS40001303H-page 29
PIC18F2XK20/4XK20
2.3 Clock Source Modes
Clock Source modes can be classified as external or
internal.
• External Clo ck mod es rely on e xternal circui try for
the clock source. Examples are: Clock modules
(EC mode), quartz crystal resonators or ceramic
resonators (LP, XT and HS modes) and Resistor-
Capacitor (RC mode) circuits.
• Internal clock sources are contained internally
within the Oscillator block. The Oscillator block
has two internal oscillators: the 16 MHz
High-Frequency Internal Oscillator (HFINTOSC)
and the 31 kHz Low -Frequency Internal Os cillator
(LFINTOSC).
The syste m cl oc k can be selected betwee n ex tern al or
internal clock sources via the System Clock Select
(SCS<1:0>) bits of the OSCCON register. See
Section 2.9 “Clock Switching” for additional
information.
2.4 External Clock Modes
2.4.1 OSCILLATOR START-UP TIMER (OST)
When t he os cil lator modu le is co nfi gure d for LP, XT or
HS mo des , the O sc illat or Start-up Time r (O ST) c oun ts
1024 oscillations from OSC1. This occurs following a
Power-on Reset (POR) and when the Power-up Ti mer
(PWRT) has expired (if configured), or a wake-up from
Sleep. During this time, the program counter does not
increment and program execution is suspended. The
OST ensures that the oscillator circuit, using a quartz
cryst al res onator o r ce ramic res onator, has st arte d and
is providing a stable system clock to the oscillator
module. When switching between clock sources, a
delay is required to allow the new clock to stabilize.
These oscillator delays are shown in Table 2-1.
In order to mi nimize laten cy between externa l oscillator
start-up and code execution, the Two-Speed Clock
Start-up mode can be selected (see Section 2.10
“Two-Speed Clock Start-up Mode”).
TABLE 2-1: OSCILLATOR DELAY EXAMPLES
2.4.2 EC MODE
The External Clock (EC) mode allows an externally
generated logic level as the system clock source. When
operating in this mode, an external clock source is
connected to the OSC1 input and the OSC2 is available
for general purpose I/O. Figure 2-2 shows the pin
connections for EC mode.
The Oscillator Start-up Timer (OST) is disabled when
EC mode is selected. Therefore, there is no delay in
operation after a Power-on Reset (POR) or wake-up
from Sleep. Because the PIC® MCU design is fully
static, stopping the external clock input will have the
effect of halting the device while leaving all data intact.
Upon restarting the external clock, the device will
resume operation as if no time had elapsed.
FIGURE 2-2: EXTERNAL CLOCK (EC)
MODE OPERATION
Switch From Switch To Frequency Oscillator Delay
Sleep/POR LFINTOSC
HFINTOSC 31 kHz
250 kHz to 16 MHz Oscillator Warm-Up Delay (TWARM)
Sleep/POR EC, RC DC – 64 MHz 2 instruction cycles
LFINTOSC (31 kHz) EC, RC DC – 64 MHz 1 cycle of each
Sleep/POR LP, XT, HS 32 kHz to 40 MHz 1024 Clock Cycles (OST)
Sleep/POR HSPLL 32 MHz to 64 MHz 1024 Clock Cycles (OST) + 2 ms
LFINTOSC (31 kHz) HFINTOSC 250 kHz to 16 MHz 1 s (approx.)
OSC1/CLKIN
OSC2/CLKOUT(1)
I/O
Clock from
Ext. System PIC® MCU
Note 1: Alternate pin functions are listed in
Section 1.0 “Device Overview”.
PIC18F2XK20/4XK20
DS40001303H-page 30 2010-2015 Microchip Technology Inc.
2.4.3 LP, XT, HS MODES
The LP, XT and HS modes support the use of quartz
crystal resonators or ceramic resonators connected to
OSC1 and OSC2 (Figure 2-3). The mod e select s a low ,
medium or high gain setting of the internal inverter-
amplifi er to support vari ous resonator typ es and spee d.
LP Oscillator mode selects the lowest gain setting of the
internal inverter-amplifier . LP mode current consumption
is the least of the three modes. This mode is bes t suited
to drive res onators with a low drive level spec ification, for
example, tuning fork type cry st als.
XT Oscillator mode selects the intermediate gain
setting of the internal inverter-amplifier. XT mode
current c onsumption is the medium of the three mo des.
This mode is best suited to drive resonators with a
medium drive level specification.
HS Oscillator mode selects the highest gain setting of the
internal inverter-amplifier . HS mode current consumption
is the highest of the three modes. This mode is best
suited fo r reso nato rs that require a high driv e s ettin g.
Figure 2-3 and Figure 2-4 show typical circuits for
quartz crystal and ceramic resonators, respectively.
FIGURE 2-3: QUARTZ CRYSTAL
OPERATION (LP, XT OR
HS MODE)
FIGURE 2-4: CERAMIC RESONATOR
OPERATION
(XT OR HS MODE)
Note 1: A series resistor (RS) may be required for
quartz crystals with low drive level.
2: The value of RF varies with the Oscillator mode
selected (typically between 2 M to 10 M.
C1
C2
Quartz
RS(1)
OSC1/CLKIN
RF(2) Sleep
To Internal
Logic
PIC® MCU
Crystal
OSC2/CLKOUT
Note 1: Quartz crystal characteristics vary
according to type, package and
manufacturer. The user should consult the
manuf actu rer da ta shee ts for spec ifi catio ns
and recom mended applicati on.
2: Always v erify osci llator pe rformance over
the VDD and temperature range that is
expected for the application.
3: For oscillator desig n assistance, reference
the following Microchip Applications Notes:
• AN826, “Crystal Oscillator Basics and
Crystal Selection for rfPIC® and PIC®
Devices” (DS00826)
• AN849, “Basic PIC® Oscillator Design”
(DS00849)
• AN943, “Practical PIC® Oscillator
Analysis and Design” (DS00943)
• AN949, “Making Your Oscillator Work”
(DS00949)
Note 1: A series resistor (RS) may be required for
ceramic resonators with low drive level.
2: The value of RF varies with the Oscillator mode
selected (typically between 2 M to 10 M .
3: An additional parallel feedback resistor (RP)
may be required for proper ceramic resonator
operation.
C1
C2 Ceramic RS(1)
OSC1/CLKIN
RF(2) Sleep
To Internal
Logic
PIC® MC U
RP(3)
Resonator OSC2/CLKOUT
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PIC18F2XK20/4XK20
2.4.4 EXTERNAL RC MODES
The external Resistor-Capacitor (RC) modes support
the use of an external RC circuit. This allows the
designer maximum flexibility in frequency choice while
keeping costs to a minimum when clock accuracy is not
required. There are two modes: RC and RCIO.
2.4.4.1 RC Mode
In RC mode, the RC circuit connects to OSC1. OSC2/
CLKOUT outputs the RC oscillator frequency divided
by 4. This signal may be used to provide a clock for
external circuitry, synchronization, calibration, test or
other application requirements. Figure 2-5 shows the
external RC mode connections.
FIGURE 2-5: EXTERNAL RC MODES
2.4.4.2 RCIO Mode
In RCIO mode, the RC circuit is connected to OSC1.
OSC2 becomes an additional general purpose I/O pin.
The RC oscillator frequency is a function of the supply
voltage, the resis tor (REXT) and cap aci tor (CEXT) values
and the operating temperature. Other factors affecting
the oscillator frequency are:
• input threshold voltage variation
• component tolerances
• pack aging variations i n capacitance
The user also needs to take into account variation due
to tolerance of external RC components used.
2.5 Internal Clock Modes
The oscillator module has two independent, internal
oscillators that can be configured or selected as the
system clock source.
1. The HFINTOSC (High-Frequency Internal
Oscillator) is factory calibrated and operates at
16 MHz. The frequency of the HFINTOSC can
be user-adjusted via software using the
OSCTUNE register (Register 2-2).
2. The LFINTOSC (Low-Frequency Internal
Oscillator) operates at 31 kHz.
The sy stem clock s peed can be selecte d via software
using the Internal Oscillator Frequency Select bits
IRCF<2:0> of the OSCCON register.
The syste m cl oc k can be selec ted be twee n external or
inte rnal cloc k sources via the S ystem Clo ck Select ion
(SCS<1:0>) bits of the OSCCON register. See
Section 2.9 “Clock Switching” for more information.
2.5.1 INTOSC AND INTOSCIO MODES
The INTOSC and INTOSCIO modes configure the
internal oscillators as the primary clock source. The
FOSC<3:0> bits in the CONFIG1H Configuration
register determine which mode is selected. See
Section 23.0 “Sp ecial Features of the CPU” for more
information.
In INTOSC mode, OSC1/ CLKIN is avail able for ge neral
purpose I/O. OSC2/CLKOUT outputs the selected
internal oscillator fre quency divide d by 4. The CLKO UT
signal may be used to provide a clock for external
circuitry, synchronization, calibration, test or other
application requirements.
In INTOSCIO mode, OSC1/CLKIN and OSC2/CLKOUT
are available for general purpose I/O.
2.5.2 HFINTOSC
The output of the HFINTOSC connects to a postscaler
and multiplexer (see Figure 2-1). One of eight
frequencies can be selected via software using the
IRCF<2:0> bits of the OSCCON register. See
Section 2.5.4 “Frequency Select Bits (IRCF)” for
more information.
The HFINTOSC is enabled when:
•SCS1 = 1 and IRCF<2:0> 000
•SCS1 = 1 and IRCF<2:0> = 000 and INTSRC = 1
• IESO bit of CONFIG1H = 1 enabling Tw o-Speed
Start-up.
• FCMEM bit of CONFIG1H = 1 enabling
Two-Speed Start-up and Fail-Safe mode.
• FOSC<3:0> of CONFIG1H selects the internal
oscillator as the p rimary clock
The HF Internal Oscillator (IOFS) bit of the OSCCON
register indicates whether the HFINTOSC is stable or not.
OSC2/CLKOUT(1)
CEXT
REXT
PIC® MCU
OSC1/CLKIN
FOSC/4 o r
Internal
Clock
VDD
VSS
Recommended values: 10 k REXT 100 k
CEXT > 20 pF
Note 1: Alternate pin functions are listed in
Section 1.0 “Device Overview”.
2: Output depend s upon RC or RCIO clock mod e.
I/O(2)
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DS40001303H-page 32 2010-2015 Microchip Technology Inc.
2.5.2.1 OSCTUNE Register
The HFINTOSC is factory calibrated but can be
adjusted in software by writing to the TUN<5:0> bits of
the OSCTUNE register (Register 2-2).
The default value of the TUN<5:0> is ‘000000’. The
value is a 6-bit two’s complement number.
When the OSCTUNE register is modified, the
HFINTOSC frequency will begin shifting to the new
frequency. Code execution continues during this shift.
There is no indication that the shif t has occurred.
OSCTUNE does not affect the LFINTOSC frequency.
Operation of features that depend on the LFINTOSC
clock source frequency, such as the Power-up Timer
(PWRT), Watchdog Timer (WDT), Fail-Safe Clock
Monitor (FSCM) and p eripherals, are not affected by the
change in frequency.
The OSCTUNE register also implements the INTSRC
and PLLEN bits, which control certain features of the
internal oscillator block.
The INTSRC bit allows users to select which internal
oscillator provides the clock source when the 31 kHz
frequenc y opt ion is se lected . This is cove red in greater
detail in Section 2.2.3 “Low Frequency Selection”.
The PLLEN bit controls the operation of the frequency
multiplier, PLL, in internal oscillator modes. For more
details about the function of the PLLEN bit see
Section 2.6.2 “PLL in HFINTOSC Modes”
REGISTER 2-2: OSCTUNE: OSCILLATOR TUNING REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
INTSRC PLLEN(1) TUN5 TUN4 TUN3 TUN2 TUN1 TUN0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 INTSRC: Internal Oscillator Low-Frequency Source Select bi t
1 = 31.25 kHz device clock derived from 16 MHz HFINTOSC source (divide-by-512 enabled)
0 = 31 kHz device clock derived directly from LFINTOSC internal oscillator
bit 6 PLLEN: Frequency Multiplier PLL for HFINTOSC Enable bit(1)
1 = PLL enabled for HFINTOSC (8 MHz and 16 MHz only)
0 = PLL disabl ed
bit 5-0 TUN<5:0>: Frequency Tuning bits
011111 = Maximu m frequency
011110 =
• • •
000001 =
000000 = Oscillator module is running at the factory calibrated frequency.
111111 =
• • •
100000 = Minimum frequency
Note 1: The PLLEN bit is acti ve only when the HFINTOSC is the primary clock source (FOSC<2:0> = 100X) and
the sele cted f requ ency is 8 MH z or 16 MHz . Othe rwise, th e PLLEN bit is un avail able a nd a lways reads ‘ 0’.
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PIC18F2XK20/4XK20
2.5.3 LFINTOSC
The Low-Frequency Internal Oscillator (LFINTOSC) is
a 31 k Hz internal clock source.
The output of the LFINTOSC connects to internal
oscillator block frequency selection multiplexer (see
Figure 2-1). Select 31 kHz, via software, using the
IRCF<2:0> bits of the OSCCON register and the
INTSRC bit of the OSCTUNE register. See
Section 2.5.4 “Frequency Select Bits (IRCF)” for
more information. The LFINTOSC is also the frequency
for the Power-up Timer (PWRT), Watchdog Timer
(WDT) and Fail -Safe Cloc k M onitor (FSCM ).
The LFINTOSC is enabled when any of the following
are enabled:
• IRCF<2:0> bits of the OSCCON register = 000 and
INTSRC bit of the OSCTUNE register = 0
• Power-up Timer (PWRT)
• Watchdog Timer (WDT)
• Fail-Safe Clock Monitor (FSCM)
2.5.4 FREQUENCY SELECT BITS (IRCF)
The output of the 16 MHz HFINTOSC and 31 kHz
LFINTOSC connects to a postscaler and multiplexer
(see Figure 2-1). The Internal Oscillator Frequency
Select bits IRCF<2:0> of the OSCCON register select
the output frequency of the internal oscillators. One of
eight frequencies can be selected via software:
•16 MHz
•8 MHz
•4 MHz
•2 MHz
• 1 MHz (Default after Reset)
• 500 kHz
• 250 kHz
• 31 kHz (LFINTOSC or HFINTOSC/512)
2.5.5 HFINTOSC FREQUENCY DRIFT
The factory calibr ates the internal oscillator bl ock output
(HFINTOSC) for 16 MHz. However, this frequency may
drift as VDD or temperature changes, which can affect the
controller opera tion in a variety of ways. It is possible to
adjust the H FINTOSC fr equency by modifying the va lue
of the TUN<5:0> bits in the OSCTUNE register. This has
no effect on the LFINTOSC clock source frequency.
T uning the HFINTOSC source requires knowing when to
make the adjustment, in which direction it should be
made and in some cases, how large a change is
needed. Three possible compensation techniques are
discussed in the following sections, however other
techniques may be used.
2.5.5.1 Compensating with the EUSART
An adjustment may be required when the EUSART
begins t o genera te frami ng errors or receive s dat a with
errors while in Asynchronous mode. Framing errors
indicate that the device clock frequency is too high; to
adjust for this, decrement the value in OSCTUNE to
reduce the clock frequency. On the other hand, errors
in data may suggest that the clock speed is too low; to
compensate, increment OSCTUNE to increase the
clock frequency.
2.5.5.2 Compensating with the Timers
This technique compares device clock speed to some
reference clock. Two timers may be used; one timer is
clocked by the peripheral clock, while the other is
clocked by a fixed reference source, such as the
Timer1 oscillator.
Both timers are cleared, but the timer clocked by the
reference generates interrupts. When an interrupt
occurs, the internally clocked timer is read and both
timers are cleared. If the internally clocked timer value
is greater than expected, then the internal oscillator
blo ck is r unni ng to o fas t. To adju st for thi s, dec remen t
the OSCTUNE register.
2.5.5.3 Compensating with the CCP Module
in Capture Mode
A CCP mod ule c a n u se free running Timer1 (o r Timer3),
clocked by the internal oscillator block and an external
event with a known period (i.e., AC power frequency).
The time of the first event is captured in the
CCPRxH:CCPRxL registers and is recorded for use later .
When the second event causes a capture, the time of the
first event is subtracted from the time of the second
event. Since the period of the external event is known,
the time difference between events can be calculated.
If the measured time is much greater than the calcu-
lated time, the internal oscillator block is running too
fast; to compensate, decrement the OSCTUNE register .
If the measured time is much less than the calculated
time, the int er nal osci llator block is runn ing t oo slow; to
compensate, increment the OSCTUNE register .
Note: Following any Reset, the IRCF<2:0> bits
of the OSCCON register are set to ‘011’
and the frequency selection is set to
1 MHz. The user can mo dify the IRCF bi ts
to select a different frequency.
PIC18F2XK20/4XK20
DS40001303H-page 34 2010-2015 Microchip Technology Inc.
2.6 PLL Frequency Multiplier
A Phase-Locked Loop (PLL) circuit is provided as an
option for users who wish to use a lower frequency
oscillator circuit or to clock the device up to its highest
rated f requenc y from the crys ta l osci llator. This may be
useful for customers who are concerned with EMI due
to high-frequency crystals or users who require higher
clock speeds from an internal oscillator. There are
three conditions when the PLL can be us ed:
• When the primary clock is HSPLL
• When the primary clock is HFINTOSC and the
selected frequency is 16 MHz
• When the primary clock is HFINTOSC and the
selected frequency is 8 MHz
2.6.1 HSPLL OSCILLATOR MODE
The HSPL L mode makes use of the HS mode oscil lator
for freque ncies u p to 16 MH z. A PLL t hen mult iplies th e
oscillator output frequency by 4 to produce an internal
clock frequency up to 64 MHz. The PLLEN bit of the
OSCTUNE regis ter is act ive on ly when the H FINT OSC
is the primary clock and is not available in HSPLL
oscillator mode.
The PLL is only available to the primary oscillator when
the FOSC<3:0> Con figurat ion bit s are p rogrammed for
HSPLL mode (= 0110).
FIGURE 2-6: PLL BLOCK DIAGRAM
(HS MODE)
2.6.2 PLL IN HFINTOSC MODES
The 4x frequency multiplier can be used with the
internal oscillator block to produce faster device clock
speeds than are normally possible with an internal
oscillator. When enabled, the PLL produces a clock
speed of up to 64 MHz.
Unlike HSPLL mode, the PLL is controlled through
software. The PLLEN control bit of the OSCTUNE
register is used to enable or disable the PLL operation
when the HFINTOSC is used.
The PLL is available when the device is configured to
use the internal oscillator block as its primary clock
source (FOSC<3:0> = 1001 or 1000). Additionally, the
PLL will only function when the selected output fre-
quency is either 8 MHz or 16 MHz (OSCCON<6:4> =
111 or 110). If both of these conditions are not met, the
PLL is disabled.
The PLLEN control bit is only functional in those
internal osc il lat or m ode s w h ere t he PLL is available. In
all other modes, it is forced to ‘0’ and is effectively
unavailable.
MUX
VCO
Loop
Filter
Crystal
Osc
OSC2
OSC1
PLL Enable
FIN
FOUT
SYSCLK
Phase
Comparator
HS Oscillator Enable
4
(from Configuration Register 1H)
HS Mode
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PIC18F2XK20/4XK20
2.7 Effects of Power-Managed M odes
on the Various Clock Sources
For more information about the modes discussed in this
section see Section 3.0 “Power-Managed Modes”. A
quick reference list is also available in Table 3-1.
When PRI_IDLE mode is selected, the designated
primary oscillator continues to run without interruption.
For all other power-managed modes, the oscillator
using the OSC1 pin is disabled. The OSC1 pin (and
OSC2 pin, if us ed by th e oscillat or) will stop oscil lating.
In secondary clock modes (SEC_RUN and
SEC_IDLE), the Timer1 oscillator is operating and
providing the device clock. The Timer1 oscillator may
also run in all power-managed modes if required to
clock Timer1 or Timer3.
In internal oscillator modes (INTOSC_RUN and
INTOSC_IDLE), the internal oscillator block provides
the device clock source. The 31 kHz LFINTOSC output
can be used directly to provide the clock and may be
enabled to support various spe cial features, reg ardless
of the power-managed mode (see Section 23.2
“Watchdog Timer (WDT)”, Section 2.10 “Two-
S peed Clock S t art-up Mode” an d Section 2.1 1 “Fail-
Safe Clock Monitor” for more information on WDT,
Fail-Safe Clock Monitor and Two-Speed Start-up). The
HFINTOSC output at 16 MHz may be used directly to
clock the device or may be divided down by the
postscaler. The HFINTOSC output is disabled if the
clock is provided directly from the LFINTOSC output.
If the Sleep mode is selected, all clock sources are
stopped. Since all the transistor switching currents
have been stopped, Sleep mode achieves the lowest
current consumption of the device (only leakage
currents).
Enabling any on-chip feature that will operate during
Sleep w ill increase th e current cons umed during S leep.
The LFINTOSC is required to support WDT operation.
The Timer1 oscillator may be operating to support a
real-time clock. Other features may be operating that
do not require a device clock source (i.e., SSP slave,
PSP, INTn pins and others). Peripherals that may add
significant current consumption are listed in
Section TABLE 26-8: “Peripheral Supply Current,
PIC18F2XK20/4XK20”.
2.8 Power-up Delays
Power-up delays are controlled by two timers, so that
no exte rna l R e se t c ircui try is required fo r m os t a ppl ic a-
tions. The delays ensure that the device is kept in
Reset until the device powe r supply i s stable under nor-
mal circumstances and the primary clock is operating
and stable. For additional information on power-up
delays, see Section 4.5 “Device Reset Timers”.
The first timer is the Power-up Timer (PWRT), which
provides a fixed delay on power-up (parameter 33,
Table ). It is enabled by clearing (= 0) the PWRTEN
Configuration bit.
The second timer is the Oscillator Start-up Timer
(OST), intended to keep the chip in Reset until the
crystal oscillator is stable (LP, XT and HS modes). The
OST does this by counting 1024 oscillator cycles
before allowing the oscillator to clock the device.
When the HSPLL Oscillator mode is selected, the
device is k ept in Res et for an add itiona l 2 ms, foll owin g
the HS mode OST delay, so the PLL can lock to the
inco mi ng cl ock frequency.
There is a delay of interval TCSD (parameter 38, Table ),
following POR, while the controller becomes ready to
execute instructions. This delay runs concurrently with
any other delays. This may be the only delay that
occurs when any of the EC, RC or INTIO modes are
used as the primary clock source.
When the HFINTOSC is selected as the prim ary clock,
the main system clock can be delayed until the
HFINTOSC is stable. This is user selectable by the
HFOFST bit of the CONFIG3H Configuration register.
When the HFOFST bit is cle ared the main system cl ock
is delayed until the HFINTOSC is stable. When the
HFOFST bit is set the main system clock starts
immediately. In either case the IOFS bit of the
OSCCON register can be read to determine whether
the HFINTOSC is operating and stable.
TABLE 2-2: OSC1 AND OSC2 PIN STATES IN SLEEP MODE
OSC Mode OSC1 Pin OSC2 Pin
RC, INTOSC Floating, external resistor should pull high At logic low (clock/4 output)
RCIO Floating, external resistor should pull high Configured as PORTA, bit 6
INTOSCIO Configured as PORTA, bit 7 Configured as PORTA, bit 6
ECIO Floating, pulled by external clock Configured as PORTA, bit 6
EC Floating, pulled by external clock At logic low (clock/4 output)
LP, XT, HS and HSPLL Feedback inverter disabled at quiescent
volt a ge lev el Feedback inverter disabled at quiescent
voltage level
Note: See Table 4-2 in Section 4.0 “Reset” for time-outs due to Sleep and MCLR Reset.
PIC18F2XK20/4XK20
DS40001303H-page 36 2010-2015 Microchip Technology Inc.
2.9 Clock Switching
The system clock source can be switched between
external and internal clock sources via software using
the System Clock Select (SCS<1:0>) bits of the
OSCCON register.
PIC18F2XK20/4XK20 devices contain circuitry to
prevent clock “glitches” when switching between clock
sources. A short pause in the device clock occurs
during the clock switch. The length of this pause is the
sum of two cycles of the old clock source and three to
four cycles of the new clock source. This formula
assumes that the new clock source is stable.
Clock transitions are discussed in greater detail in
Section 3.1.2 “Entering Power-Managed Modes”.
2.9.1 SYSTEM CLOCK SELECT
(SCS<1:0>) BITS
The System Clock Select (SCS<1:0>) bits of the
OSCCON register select the sy stem clock source t hat
is used for the CPU and periph erals.
• When SCS< 1:0> = 00, the system clock source is
determined by configuration of the FOSC<2:0>
bits in the CONFI G1H Configuration register.
• When SCS< 1:0> = 10, the system clock source is
chosen by the internal oscillator frequency
selected by the INTSRC bit of the OSCTUNE
register and the IRCF<2 :0> bi ts of the OS CCON
register.
• When SCS< 1:0> = 01, the system clock source is
the 32.768 kHz s econdary oscillat or sha red with
Timer1.
After a Reset, the SCS<1:0> bits of the OSCCON
register are always cleared.
2.9.2 OSCILLA TOR START-UP TIME-OU T
STATUS (OSTS) BIT
The Oscillator Start-up Time-out Status (OSTS) bit of
the OSCCON register indicates whether the system
clock is running from the external clock source, as
defined by the FOSC<3:0> bits in the CONFIG1H
Configuration register, or from the internal clock
source. In particular, when the primary oscillator is the
source of the primary clock, OSTS indicates that the
Oscillator Start-up Timer (OST) has timed out for LP,
XT or HS modes.
2.9.3 CLOCK SWITCH TIMING
When switching between one oscillator and another,
the new oscillator may not be operating which saves
power (see Figure 2-7). If this is the case, there is a
del ay afte r the SCS<1:0> bits of the OSCCON register
are modi fied before the frequ enc y cha ng e t ak es pl ac e.
The OSTS and IOFS bits of the OSCCON register will
reflect the current active status of the external and
HFINTOSC oscillators. The timing of a frequency
selection is as follows:
1. SCS<1:0> bits of the OSCCON register are mod-
ified.
2. The old c lo ck co ntinues to operate until the new
clock is ready.
3. Clock switch circuitry waits for two consecutive
rising edges of the old clock after the new clock
ready signal goes true.
4. The syste m c lo ck is h eld lo w starting at the nex t
falling edge of the old clock.
5. Clock switc h cir cui try waits for an additional two
rising edges of the new clock.
6. On the ne xt fallin g edge of the n ew clock the low
hold on the system clock is released and new
clock is swi tch ed in as the system cl ock .
7. Clock swi tch is complete.
See Figure 2-1 for more details.
If the H FI NTOSC is the so urc e of b oth the old and new
frequency, there is no start-up delay before the new
frequency is active. This is because the old and new
frequencies are derived from the HFINTOSC via the
postscaler and multiplexer.
Start-up delay specifications are located in
Section 26.0 “Electrical Specifications”, under AC
Specifications (Oscillator Module).
Note: Any automatic clock switch, which may
occur from Two-Speed Start-up or Fail-
Safe Clock Monitor, does not update the
SCS<1:0> bits of the OSCCON register.
The user can m onitor the T1R UN bi t of the
T1CON register and the IOFS and OSTS
bits of the OSCCON register to determine
the current system clock source.
2010-2015 Microchip Technology Inc. DS40001303H-page 37
PIC18F2XK20/4XK20
2.10 Two-Speed Clock Start-up Mode
Two-Speed Start-up mode provides additional power
savings by minimizing the latency between external
oscillator start-up and code execution. In applications
that make heavy use of the Sleep mode, Two-Speed
Start-up will remove the external oscillator start-up
time from the time spent awake and can reduce the
overall power consumption of the device.
This mode allows the application to wake-up from
Sleep, perform a few instructions using the HFINTOSC
as the clock source and go back to Sleep without
waiting for the primary oscillator to become stable.
When the oscill ator module is configured fo r LP, XT or
HS modes, the Oscillator Start-up Timer (OST) is
enabled (see Section 2.4.1 “Oscillator St art-up Timer
(OST)”). The OST will suspend program execution until
1024 oscillations are counted. Two-Speed Start-up
mode minimizes the delay in code execution by
operating from the internal oscillator as the OST is
counting. When the OST count reaches 1024 and the
OSTS bit of the OSCCON register is set, program
execution switches to the external oscillator.
2.10.1 TWO-SPEED START-UP MODE
CONFIGURATION
Two-Speed Start-up mode is enabled when all of the
following settings are configured as noted:
• Two-Speed Start-up mode is enabled by setting
the IESO of the CONFIG1H Configuration register
is set. Fail-Safe mode (FCMEM = 1) also enabl es
two-speed by default.
• SCS<1:0> (of the OSCCON register) = 00.
• FOSC<2:0> bits of the CONFIG1H Configuration
register are configured for LP, XT or HS mode.
Two-Speed Start-up mode becomes active after:
• Power-on Reset (POR) and, if enabled, after
Power-up Timer (PWRT) has expired, or
• Wake-up from Sleep.
If the external clock oscillator is configured to be
anything other than LP, XT or HS mode, then
Two-Speed Start-up is disabled. This is because the
external clock oscillator does not require any
stabilization time after POR or an exit from Sleep.
2.10 .2 TWO-SPEED START-UP
SEQUENCE
1. Wake-up from Power-on Reset or Sleep.
2. Instructions begin executing by the internal
oscillator at the frequency set in the IRCF<2:0>
bits of th e O SCCON re giste r.
3. OST enabled to count 1024 external clock
cycles.
4. OST timed out. External clock is ready.
5. OSTS is set.
6. Clock switch finishes according to FIGURE 2-7:
“Clock Switch Timing”
2.10.3 CHECKI NG TW O-SPEED CLOCK
STATUS
Checking the state of the OSTS bit of the OSCCON
register will confirm if the microcontroller is running
from the external clock source, as defined by the
FOSC<2:0> bits in CONFIG1H Configuration register,
or the internal oscillator. OSTS = 0 when the external
oscillator is not ready, which indicates that the system
is running from the internal oscillator.
Note: Executing a SLEEP instruction will abort
the oscillator start-up time and will cause
the OSTS bit of the OSCCON register to
remain clear.
PIC18F2XK20/4XK20
DS40001303H-page 38 2010-2015 Microchip Technology Inc.
FIGURE 2-7: CLOCK SWITCH TIMING
Old Clock
New Clock
IRCF <2:0>
System Clock
Start-up Time(1) Clock Sync Running
High Speed Low Speed
Select Old Select New
New Clk Ready
Low Speed High Speed
Old Clock
New Clock
IRCF <2:0>
System Clock
Start-up Time(1) Clock Sync Running
Select Old Select New
New Clk Ready
Note 1: Start-up time includes TOST (1024 TOSC) for external clocks, plus TPLL (approx. 2 ms) for HSPLL mode.
2010-2015 Microchip Technology Inc. DS40001303H-page 39
PIC18F2XK20/4XK20
2.11 Fail-Safe Clock Monitor
The Fail-Saf e Cl oc k Mo nit or (FSC M) al lows the dev ic e
to continue operating sh oul d th e e xte rna l os ci llator fail.
The FSCM can detect oscillator failure any time after
the Oscillator Start-up Timer (OST) has expired. The
FSCM is enabled by setting the FCMEN bit in the
CONFIG1H Configuration register. The FSCM is
applicable to all external oscillator modes (LP, XT, HS,
EC, RC and RCIO).
FIGURE 2-8: FSCM BLOCK DIAGRAM
2.11.1 FAIL-SAFE DETECTION
The FSCM module detects a failed oscillator by
compari ng the extern al osci llat or to the FSCM sa mple
clock. The sample clock is generated by dividing the
LFINTOSC by 64. See Figure 2-8. Inside the fail
detector block is a latch. The external clock sets the
latch on each falling edge of the external clock. The
sample clock cle ars the latch on each ris ing edge of th e
sample c loc k. A fail ure is d ete cte d w h en an entire half-
cycle of the sample clock elapses before the primary
clock goes low.
2.11.2 FAIL-SAFE OPERATION
When the external clock fails, the FSCM switches the
devi ce clock to an interna l clock s ource and s ets the b it
flag OSC FIF of the PIR2 registe r. The OSCFIF flag will
generate an interrupt if the OSCFIE bit of the PIE2
register is also set. The device firmware can then take
steps to mitigate the problems that may arise from a
failed clock. The system clock will continue to be
sourced from the internal clock source until the device
firmware successfully restarts the external oscillator
and switches back to external operation. An automatic
transition back to the failed clock source will not occur.
The internal clock source chosen by the FSCM is
determined by the IRCF<2:0> bits of the OSCCON
register. This allows the internal oscillator to be
configured before a failure occurs.
2.11.3 FAIL-SAFE CONDITION CLEARING
The Fail-Safe condition is cleared by either one of the
following:
•Any Reset
• By togg ling the SCS1 bit of the OSCCON register
Both of these conditions restart the OST. While the
OST is running, the device continues to operate from
the INTOSC selected in OSCCON. When the OST
times out, the Fail-Safe condition is cleared and the
device automatically switches over to the external cl ock
source. The Fail-Safe condition need not be cleared
before the OSCFIF flag is cleared.
2.11.4 RESET OR WAKE-UP FROM SLEEP
The FSCM is designed to detect an oscillator failure
after the Oscillator Start-up Timer (OST) has expired.
The OST is used after waking up from Sleep and after
any type of Reset. The OST is not used w ith the EC or
RC Clock modes so that the FSCM will be active as
soon as the Reset or wake-up has completed. When
the FSCM is enabled, the Two-Speed Start-up is also
enabled . Therefore, the device will always be executing
code while the OST is operating.
External
LFINTOSC ÷ 64
S
R
Q
31 kHz
(~32 s) 488 Hz
(~2 ms)
Clock Monitor
Latch
Clock
Failure
Detected
Oscillator
Clock
Q
Sample Clock
Note: Due to the wide range of oscillator start-up
times, the Fail-Safe circuit is not active
during oscillator start-up (i.e., after exiting
Reset or Sleep). After an appropriate
amount of time, the user should check the
OSTS bit of the OSCCON register to verify
the oscillator start-up and that the system
clock switchover has successfully
completed.
PIC18F2XK20/4XK20
DS40001303H-page 40 2010-2015 Microchip Technology Inc.
FIGURE 2-9: FSCM TIMING DIAGRAM
TABLE 2-3: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES
OSCFIF
System
Clock
Output
Sample Clock
Failure
Detected
Oscillator
Failure
Note: The syste m clock is normally at a m uch higher frequency than the sam ple clock. The relative frequencies in
this example have been chosen for clarity.
(Q)
Test Test Test
Clock Monitor Output
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 B it 0 Value on
POR, BOR
Value on
all other
Resets(1)
CONFIG1H IESO FCMEN —— FOSC3 FOSC2 FOSC1 FOSC0 — —
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000x
OSCCON IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0 0011 q000 0011 q000
OSCTUNE INTSRC PLLEN TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 0000 0000 000u uuuu
PIE2 OSCFIE C1IE C2IE EEIE BCLIE HLVDIE TMR3IE CCP2IE 0000 0000 0000 0000
PIR2 OSCFIF C1IF C2IF EEIF BCLIF HLVDIF TMR3IF CCP2IF 0000 0000 0000 0000
IPR2 OSCFIP ———————1111 1111 1111 1111
Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by oscillators.
Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
2010-2015 Microchip Technology Inc. DS40001303H-page 41
PIC18F2XK20/4XK20
3.0 POWER-MANAGE D MODE S
PIC18F2XK20/4XK20 devices offer a total of seven
operating modes for more efficient power
management. These modes provide a variety of
options for selecti ve power conservation i n applications
where resources may be limited (i.e., battery-powered
devices).
There are three categories of power-managed modes:
• Run modes
• Idle mo des
• Sleep mode
These categories define which portions of the device
are clo cked and some times , what sp eed. The R un and
Idle modes may use any of the three available clock
sources (primary, secondary or internal oscillator
block); the Sleep mode does not use a clock source.
The power-managed modes include several
power-saving features offered on previous PIC®
microcontroller devices. One is the clock switching
feature which allows the controller to use the Timer1
oscillator in place of the primary osc illator. Also included
is the Sleep mode, offered by all PIC® microcontroller
devices, where all d evice c locks are stopped.
3.1 Selecting Power-Managed Modes
Selecting a power-managed mode requires two
decisions:
• Whether or not the CPU is to be clocked
• The selectio n of a clock source
The IDLEN bit of the OSCCON register controls CPU
clocking, while the SCS<1:0> bits of the OSCCON
register select the clock source. The individual modes,
bit settings, clock sources and affected modules are
summa riz ed in Table 3-1.
3.1.1 CLOCK SOURCES
The SCS<1:0> bits allow the selection of one of three
clock sources for power-managed modes. They are:
• the primary clock, as defined by the FOSC<3:0>
Configuration bits
• the secondary clock (the Timer1 oscillator)
• the internal oscillator bl ock
3.1.2 ENTERING POWER-MANAGED
MODES
Switching from one power-managed mode to another
begins by loading the OSCCON register. The
SCS<1:0> bits select the clock source and determine
which Run or Idle mode is to be used. Changing these
bits causes an immediate switch to the new clock
source, assuming that it is running. The switch may
also be subject to clock transition delays. These are
discussed in Section 3.1.3 “Clock Transitions and
Status Indicators” and subsequent sections.
Entry to the power-managed Idle or Sleep modes is
triggered by the execution of a SLEEP instruction. The
actual mode that results depends on the status of the
IDLEN bit of the OSCCON register.
Depending on the current mode and the mode being
switched to, a change to a power-managed mode does
not always require setting all of these bits. Many
transitions may be done by changing the oscillator select
bits, or changing the IDL EN bit, prior to issuing a SLEEP
instruction. If the IDLEN bit is already configured
correctly, it may only be necessary to perform a SLEEP
instruction to switch to the de sired mod e.
TABLE 3-1: POWER-MANAGED MODES
Mode OSCCON Bits Module Clocking A va ilab le Clo ck and Os cill ator Sour ce
IDLEN(1) SCS<1:0> CPU Peripherals
Sleep 0N/A Off Off None – All clocks are disabled
PRI_RUN N/A 00 Clocked Clocked Primary – LP, XT, HS, HSPLL, RC, EC and
Internal Oscillator Block(2).
This is the normal full power execution mo de.
SEC_RUN N/A 01 Clocked Clocked Secondary – Timer1 Oscillator
RC_RUN N/A 1x Clocked Clocked Internal Oscillator Block(2)
PRI_IDLE 100Off Clocked Primary – LP, XT, HS, HSPLL, RC, EC
SEC_IDLE 101Off Clocked Secondary – Timer1 Oscillator
RC_IDLE 11xOff Clocked Internal Oscillator Block(2)
Note 1: IDLEN reflects its value when the SLEEP instruction is executed.
2: Includes HFINTOSC and HFINTOSC postscaler, as well as the LFINTOSC source.
PIC18F2XK20/4XK20
DS40001303H-page 42 2010-2015 Microchip Technology Inc.
3.1.3 CLOCK TRANSITIONS AND S TATUS
INDICATORS
The length of the transition between clock sources is
the sum of:
• Start-up time of the new clock
• Two and one half cycles of the old clock source
• Two and one half cycles of the new clock
Three flag bits indicate the current clock source and its
status. They are:
• OSTS (of the OSCCON register)
• IOFS (of the OSCCON register)
• T1RUN (of the T1CON register)
In general, only one of these bits will be set while in a
given power-managed mode. Table 3-2 shows the
relat ionship o f the f lags to th e acti ve main system clock
source.
TABLE 3-2: SYSTEM CLOCK INDICATORS
.
3.1.4 MULTIPLE FUNCTIONS OF THE
SLEEP COMMAND
The power-managed mode that is invoked with the
SLEEP instruction is determined by the setting of the
IDLEN bit of the OSCCON register at the time the
instruction is executed. All clocks stop and minimum
power is consumed when SLEEP is executed with the
IDLEN bit cleared. The system clock continues to
supply a clock to the peripherals but is disconnected
from the CPU when SLEEP is executed w ith the IDLEN
bit set.
3.2 Run Modes
In the Run modes, clocks to both the core and
peripherals are active. The difference between these
modes is the clock sou r ce .
3.2.1 PRI_RUN MODE
The PRI_RUN mode is the normal, full power execution
mode of the microcontroller. This is also the default
mode up on a device Reset, unle ss T wo-S p eed S tart-u p
is enabled (see Section 2.10 “Two-Speed Clock
St art-up Mode” for det ails). In this mo de, the OS TS bit
is set. The IOFS bit will be set if the HFINTOSC is the
primary clock source and the oscillator is stable (see
Section 2.2 “Oscillator Control”).
3.2.2 SEC_RUN MODE
The SEC_RUN mode is the mode compatible to the
“clock switching” feature offered in other PIC18
devices. In this mode, the CPU and peripherals are
clock ed from the T ime r1 oscill ator . This gives us ers the
option of lower power consumption while still using a
high accuracy clock source.
SEC_RUN mode is entered by setting the SCS<1:0>
bits to ‘01’. When SEC_RUN mode is active all of the
following are true:
• The main clock s ource is switched to the Timer1
oscillator
• Primary oscillator is shut down
• T1RUN bit of the T1CON register is set
• OSTS bit is cleared.
On transitions from SEC_RUN mode to PRI_RUN, the
peripherals and CPU continue to be clocked from the
Timer1 oscillator while the primary clock is started.
When t he prima ry clo ck becom es r eady, a clock switc h
back to the primary clock occurs (see Figure 2-7).
When the clock switch is complete, the T1RUN bit is
cleared, the OSTS bit is set and the primary clock is
providing the main system clock. The Timer1 oscillator
continues to run as long as the T1OSCEN bit is set.
OSTS IOFS T1RUN Main System Clock Source
10 0 Primary Oscillator
01 0 HFINTOSC
00 1 Secondary Oscillator
11 0 HFINTOSC as primary clock
00 0 LFINTOSC or
HFINTOSC is not yet stable
Note 1: Executing a SLEEP instruction does not
necessarily place the device into Sleep
mode. It acts as the trigger to place the
controller into either the Sleep mode or
one of the Idle modes, depending on the
setting of the IDLEN bit.
Note: The Timer1 oscillator should already be
running prior to entering SEC_RUN
mode. If th e T1OSCE N bit is not set when
the SCS<1:0> bits are set to ‘01’, entry to
SEC_RUN mode will not occur until
T1O SCE N bit is s et and Timer1 o sci ll ator
is ready.
2010-2015 Microchip Technology Inc. DS40001303H-page 43
PIC18F2XK20/4XK20
3.2.3 RC_RUN MODE
In RC_RUN mode, the CPU and peripherals are
clocked from the internal oscillator block using one of
the selections from the HFINTOSC multiplexer. In this
mode, the primary oscillator is shut down. RC_RUN
mode provides the best power conservation of all the
Run modes when the LFINTOSC is the main clock
source. It wo rks well for u ser appl ications which are not
highly timing sensitive or do not require high-speed
cloc ks at all ti mes.
If the primary clock source is the internal oscillator
block (either LFINTOSC or HFINTOSC), there are no
distinguishable differences between PRI_RUN and
RC_RUN modes during execution. However, a clock
switch delay will occur during entry to and exit from
RC_RUN mode. Therefore, if th e primary clock source
is the internal oscillator block, the use of RC_RUN
mode is not recommended. See 2.9.3 “Clock Switch
Timing” for details about clock switching.
RC_RUN mode is entered by setting the SCS1 bit to
‘1’. The SCS0 bit can be either ‘0’ or ‘ 1’ but should be
‘0’ to maintain software compatibility with future
devices. When the clock source is switched from the
primary oscillator to the HFINTOSC multiplexer, the
primary oscillator is shut down and the OSTS bit is
clear e d. Th e I RC F bi ts m ay be mo d ifi ed a t a ny tim e t o
immediately change the clock speed.
On transitions from RC_RUN mode to PRI_RUN mode,
the device continues to be clocked from the internal
oscillator block while the primary oscillator is started.
When the primary oscillator becomes ready, a clock
switch to the primary clock occurs. When the clock
switch is complete, the IOFS bit is cleared, the OSTS
bit is s et and the pri mary oscillato r is provi ding the mai n
system clock. The HFINT OSC will contin ue to run if any
of the conditions noted in Section 2.5.2 “HFINTOSC”
are met. The LFINTO SC source will continue to run if
any of the conditions noted in Section 2.5.3 “LFIN-
TOSC” are met.
3.3 Sleep Mode
The Power-Managed Sleep mode in the PIC18F2XK20/
4XK20 devices is identical to the legacy Sleep mode
offered in all other PIC® microcontroller devices. It is
entered by clearing the IDLEN bit (the default state on
device Reset) and executing the SLEEP instruction.
This shuts down t he selected oscillator (Figure 3-1). All
clock source Status bits are cleared.
Entering th e Sleep mode from any other mode doe s not
require a clock switch. This is because no clocks are
needed once the controller has entered Sleep. If the
WDT is selected, the LFINT OSC source will continue to
operate. If the Timer1 oscillator is enabled, it will also
continue to run.
When a wake ev ent occurs in Sleep mode (by interrupt,
Reset or WDT time-o ut), the devi ce wil l not be clocke d
until the clock source selected by the SCS<1:0> bits
becomes ready (see Figure 3-2), or it will be clocked
from the internal o scillator block if either th e T wo-S peed
Start-up or the Fail-Safe Clock Monitor are enabled
(see Section 23.0 “Spe cial Features of the CPU”). In
either case , the OS TS bit is set when th e p rimary cl ock
is providing the device clo cks. The IDLEN and SCS bits
are not affected by the wake-up.
3.4 Idle Modes
The Idle modes allow the controller’s CPU to be
selectively sh ut down while the periph eral s continue to
operate. Selecting a particular Idle mode allows users
to further manage power cons umption.
If the IDLEN bit i s set to a ‘1’ when a SLEEP inst ruction is
exec uted, the periph erals will be cl ocked fr om the cl ock
source selected by the SCS<1:0> bits; however , the CPU
will not be clocked. The clock source Status bits are not
affected. Setting IDLEN and executing a SLEEP instruc-
tion provides a quick method of switching from a given
Run mode to its c orre s pon di ng I dl e m o de.
If the WDT is selected, the LFINTOSC source will
continue to operate. If the Timer1 oscillator is enabled,
it will also continue to run.
Since the CPU is not executing instructions, the only
exits from any of the Idle modes are by interrupt, WDT
time-out, or a Reset. When a wake event occurs, CPU
execution is delayed by an interval of TCSD
(parameter 38, Table ) while it becomes ready to exe-
cute code. When the CPU begins executing code, it
resumes with the same clock source for the current Idle
mode. For example, when waking from RC_IDLE
mode, the internal oscillator block will clock the CPU
and peripherals (in other words, RC_ RUN mo de). The
IDLEN and SCS bits are not affected by the wake-up.
While in any Idle mode or the Sleep mode, a WDT
time-out will result in a WDT wake-up to the Run mode
currently specified by the SCS<1:0> bits.
PIC18F2XK20/4XK20
DS40001303H-page 44 2010-2015 Microchip Technology Inc.
FIGURE 3-1: TRANSITION TIMING FOR ENTRY TO SLEEP MODE
FIGURE 3-2: TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL)
Q4Q3Q2
OSC1
Peripheral
Sleep
Program
Q1Q1
Counter
Clock
CPU
Clock
PC + 2PC
Q3 Q4 Q1 Q2
OSC1
Peripheral
Program PC
PLL Clock
Q3 Q4
Output
CPU Clock
Q1 Q2 Q3 Q4 Q1 Q2
Clock
Counter PC + 6
PC + 4
Q1 Q2 Q3 Q4
Wake Event
Note1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
TOST(1) TPLL(1)
OSTS bit set
PC + 2
2010-2015 Microchip Technology Inc. DS40001303H-page 45
PIC18F2XK20/4XK20
3.4.1 PRI_IDLE MODE
This mode is unique among the three low-power Idle
modes, in that it does not disable the primary device
clock. For timing sensitive applications, this allows for
the faste st resump tion of device op eration with its more
accur ate prima ry clock s ource, si nce the cl ock source
does not have to “warm-up” or transition from another
oscillator.
PRI_IDLE mode is entered from PRI_RUN mode by
setting the IDLEN bit and executing a SLEEP instruc-
tion. If the device is in another Run mode, set IDLEN
first, then clear the SCS bits and execute SLEEP.
Although the C PU is disab led, th e peri pherals continu e
to be clocked from the primary clock source specified
by the FOSC<3:0> Configuration bits. The OSTS bit
remains set (see Figure 3.3).
When a wake event occurs, the CPU is clocked from the
primary clock source. A delay of interval TCSD is
required between the wake event and when code
execution starts. This is required to allow the CPU to
become rea dy to execute instructions. After the wake-
up, the OSTS bit remains set. The IDLEN and SCS bits
are not affected by the wake-up (see Figure 3-4).
3.4.2 SEC_IDLE MODE
In SEC_IDLE mode, the CPU is disabled but the
peripherals continue to be clocked from the Timer1
oscillator. This mode is entered from SEC_RUN by
setting the IDLEN bit and executing a SLEEP
instruc tion. If the device is in another Run mode, set th e
IDLEN bit first, then set the SCS<1:0> bits to ‘ 01’ and
execute SLEEP. When the clock source is switched to
the Timer1 oscillator, the primary oscillator is shut
down, the OSTS bit is cleared an d the T1RUN bit is set.
When a wake event occurs, the peripherals continue to
be clocked from the Ti mer1 oscillator. After an interval
of TCSD followi ng the w ake event, the CPU b egi ns exe-
cuting c ode being cl ocked by the T imer1 osc illator. The
IDLEN and SCS bits are not affected by the wake-up;
the Timer1 oscillator continues to run (see Figure 3-4).
FIGURE 3-3: TRANSITION TIMING FOR ENTRY TO IDLE MODE
FIGURE 3-4: TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE
Note: The Timer1 oscillator should already be
running prior to entering SEC_IDLE
mode. If th e T1OSCE N bit is not set when
the SLEEP instruction is executed, the
main system clock will continue to operate
in the previously selected mode and the
corresponding IDLE mode will be entered
(i.e., PRI_IDLE or RC_IDLE).
Q1
Peripheral
Program PC PC + 2
OSC1
Q3 Q4 Q1
CPU Clock
Clock
Counter
Q2
OSC1
Peripheral
Program PC
CPU Clock
Q1 Q3 Q4
Clock
Counter
Q2
Wake Event
TCSD
PIC18F2XK20/4XK20
DS40001303H-page 46 2010-2015 Microchip Technology Inc.
3.4.3 RC_IDLE MODE
In RC_IDLE mode, the CPU is disabled but the
peripherals continue to be clocked from the internal
oscillator block from the HFINTOSC multiplexer output.
This mode allows for controllable power conservation
during I dle periods.
From RC_RUN, this mode is entered by setting the
IDLEN bit and executing a SLEEP instruction. If the
device is in a nother Run m ode, first s et IDLEN, th en set
the SCS1 bit and execute SLEEP. It is recommended
that SCS0 also be cleared, although its value is
ignored, to maintain software compatibility with future
devices. The HFINTOSC multiplexer may be used to
select a higher clock frequency by modify ing the IRCF
bits be for e ex ecut in g the SLEEP instruction. When the
clock source is switched to the HFINTOSC multiplexer ,
the primary oscillator is shut down and the OSTS bit is
cleared.
If the IRCF bits are set to any non-zero value, or the
INTSRC bit is set, the HFINTOSC output is enabled.
The IOF S bi t beco mes s et, af ter t he HF INT OSC o utput
becomes stable, after an interval of TIOBST
(parameter 39, Table ). Clocks to the peripherals con-
tinue while the HFINTOSC source stabilizes. If the
IRCF bits were previously at a non-zero value, or
INTSRC was set before the SLEEP inst ruction was exe-
cuted and the HFINTOSC source was already stable,
the IOFS bit will remain set. If the IRCF bits and
INTSRC ar e all cle ar, the HFINT OSC out put will no t be
enabled , the I OFS bit wi ll remain clear and t here wil l be
no indication of the current clock source.
When a w ake event o ccurs, the pe ripherals continue to
be clocked from the HFINTOSC multiplexer output.
After a delay of TCSD following th e wake event, the CPU
begins executing code being clocked by the
HFINTOSC multiplexer. The IDLEN and SCS bits are
not affected by the wake-up. The LFINTOSC source
will continue to run if either the WDT or the Fail-Safe
Clock Monitor is enabled.
3.5 Exiting Idle and Sleep Modes
An exit from Sleep mode or any of the Idle modes is
triggered by any one of the following:
• an interrupt
•a Reset
• a watchdog time-out
This section discusses the triggers that cause exits
from power-managed modes. The clocking subsystem
actions are discussed in each of the power-managed
modes (see Section 3.2 “Run Modes”, Section 3.3
“Sleep Mode” and Section 3.4 “Idle Modes”).
3.5. 1 EXIT BY INTERRUPT
Any of the available interrupt sources can cause the
device to exit from an Idle mode or the Sleep mode to
a Run mode. To enable this functionality, an interrupt
source m us t be en abl ed by s etti ng its enable bit in on e
of the INTCON or PIE registers. The PEIE bit must als o
be set If the desired interrupt enable bit is in a PIE
register. The exit sequence is initiated when the
corresponding interrupt flag bit is set.
The instruction immediately following the SLEEP
instruc tion is exec uted on all exit s by interru pt from Idle
or Sleep modes. Code execution then branches to the
interrupt vector if the GIE/GIEH bit of the INTCON
register is set, otherwise code execution continues
without branching (see Section 9.0 “Interrupts”).
A fixed delay of interval TCSD foll ow i ng th e wak e ev en t
is required when leaving Sleep and Idle modes. This
del ay is requi red for the CPU to prepare for executi on.
Instruction execution resumes on the first clock cycle
following this delay.
3.5.2 EXIT BY WDT TIME-OUT
A WDT time-out will cause different actions depending
on which power-managed mode the device is in when
the time-out occurs.
If th e dev ice i s not ex ecut ing code (all Idle mo des a nd
Sleep mod e), th e time-o ut wi ll res ul t in an ex it fro m the
power-managed mode (see Section 3.2 “Run
Modes” a nd Section 3.3 “Sleep Mode ”). If the device
is executing code (all Run modes), the time-out will
result in a WDT Reset (see Section 23.2 “Watchdog
Timer (WDT)”).
The WDT timer and postscaler are cleared by any one
of the fo llow ing:
• executin g a SLEEP instruction
• executin g a CLRWDT instruction
• the loss of the currently selected clock source
when the Fail-Safe Clock Monitor is enabled
• modifying the IRCF bits in the OSCCON register
when the internal oscillator block is the device
clock source
3.5. 3 EXIT BY RESET
Exiting Sleep and Idle modes by Reset causes code
execution to restart at address 0. See Section 4.0
“Reset” for more details.
The exit delay time from Reset to the start of code
execution depends on both the clock sources before
and after the wake-up and the type of oscillator. Exit
delays are summarized in Table 3-3.
2010-2015 Microchip Technology Inc. DS40001303H-page 47
PIC18F2XK20/4XK20
3.5.4 EXIT WITHOUT AN OSCILLATOR
START-UP DELAY
Certain exits from power-managed modes do not
invoke the OST at all. There are two cases:
• PRI_IDLE mode, where the primary clock source
is not stopped and
• the primary clock source is not any of the LP, XT,
HS or HSPLL modes.
In these instances, the primary clock source either
does not require an oscillator start-up delay since it is
already running (PRI_IDLE), or normally does not
require an oscillator start-up delay (RC, EC, INTOSC,
and INTOSCIO modes). However, a fixed delay of
interval TCSD following the wake event is still required
when leaving Sleep and Idle modes to allow the CPU
to pr epare for execution. Instruction execution resumes
on the first clock cycle following this delay.
TABLE 3-3: EXIT DELAY ON WAKE-UP BY RESET FROM SLEEP MODE OR ANY IDLE MODE
(BY CLOCK SOURCES)
Clock Source
before Wake-up Clock Source
after Wake-up Exit Delay Clock Ready Status
Bit (OSCCON)
Primary Device Clock
(PRI_IDLE mode)
LP, XT, HS
TCSD(1) OSTSHSPLL
EC, RC
HFINTOSC(2) IOFS
T1OSC or LFINT O SC(1)
LP, XT, HS TOST(3)
OSTSHSPLL TOST + tPLL(3)
EC, RC TCSD(1)
HFINTOSC(1) TIOBST(4) IOFS
HFINTOSC(2)
LP, XT, HS TOST(4)
OSTSHSPLL TOST + tPLL(3)
EC, RC TCSD(1)
HFINTOSC(1) None IOFS
None
(Sleep mode)
LP, XT, HS TOST(3)
OSTSHSPLL TOST + tPLL(3)
EC, RC TCSD(1)
HFINTOSC(1) TIOBST(4) IOFS
Note 1: TCSD (p arameter 38) is a req uired delay when w akin g from Sl eep and a ll Idle mod es and runs c oncurr ently
with any other required delays (see Section 3.4 “Idle Modes”). On Reset, HFINTOSC defaults to 1 MHz.
2: Includes both the HFINTOSC 16 MHz source and postscaler derived frequencies.
3: TOST is the Oscillator Start-up Timer ( parameter 32). tPLL is the PLL Lock-out Timer (parameter F12).
4: Execution continues during the HFINTOSC stabilization period, TIOBST (param eter 39).
PIC18F2XK20/4XK20
DS40001303H-page 48 2010-2015 Microchip Technology Inc.
4.0 RESET
The PIC18F2XK20/4XK20 devices differentiate
between various kin ds of Reset:
a) Power-on Reset (POR)
b) MCLR Reset during normal operation
c) MCLR Reset during power-managed modes
d) Watchdog Timer (WDT) Reset (during
execution)
e) Programmable Brown-out Reset (BOR)
f) RESET Inst ruction
g) Stack Full Reset
h) Stack Un derflow Reset
This section discusses Resets generated by MCLR,
POR and BO R and cov ers the ope rati on of the various
start-up timers. Stack Reset events are covered in
Section 5.1.2.4 “Stack Full and Underflow Resets”.
WDT Re sets a r e co v ere d i n Section 23.2 “Watchdog
Timer (WDT)”.
A simplif ied block diagra m of the On-Chip Rese t Circu it
is shown i n Figure 4-1.
4.1 RCON Register
Device Reset events are tracked through the RCON
register (Register 4-1). The lower five bits of the regis-
ter indic ate that a spec ific Reset event has oc curred. In
most ca ses, these b its can o nly be clear ed by the e vent
and must be set by the ap pli ca tio n af ter the event. The
state of these flag bits, taken together, can be read to
indicate the type of Reset that just occurred. This is
described in more detail in Section 4.6 “Reset State
of Registers”.
The RCON register also has control bits for setting
interrupt priority (IPEN) and software control of the
BOR (SBOREN). Interrupt priority is discussed in
Section 9.0 “Interrupts”. BOR is covered in
Section 4.4 “Brown-out Reset (BOR)”.
FIGURE 4-1: SI MPLIFI ED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External Reset
MCLR
VDD
OSC1
WDT
Time-out
VDD
Detect
OST/PWRT
LFINTOSC
POR
OST(2)
10-bit Ripple Counter
PWRT(2)
11-bit Ripple Counter
Enable OST(1)
Enable PWRT
Note 1: See Table 4-2 for time-out situations.
2: PWRT and OST counters are reset by POR and BOR. See Sections 4.3 and 4.4.
Brown-out
Reset BOREN
RESET
Instruction
Stack
Pointer Stack Full/Underflow Reset
Sleep
( )_IDLE
1024 Cycles
65.5 ms
32 s
MCLRE
S
RQChip_Reset
2010-2015 Microchip Technology Inc. DS40001303H-page 49
PIC18F2XK20/4XK20
REGISTER 4-1: RCON: RESET CONTROL REGISTER
R/W-0 R/W-1 U-0 R/W-1 R-1 R-1 R/W-0 R/W-0
IPEN SBOREN(1) —RITO PD POR(2) BOR
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 IPEN: Interrupt Priority Enable bit
1 = Enable priority levels on interrupts
0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode)
bit 6 SBOREN: BOR Software Enable bit(1)
If BOREN<1:0> = 01:
1 = BOR is enabled
0 = BOR is disabled
If BOREN<1:0> = 00, 10 or 11:
Bit is disabled and read as ‘0’.
bit 5 Unimplemented: Read as ‘0’
bit 4 RI: RESET Instruction Flag bit
1 = The RESET instruction was not executed (set by firmware or Power-on Reset)
0 = The RESET instruction was executed causing a device Reset (must be set in firmware after a
code-executed Reset occurs)
bit 3 TO: Watchdog Ti me-out Flag bit
1 = Se t by power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out occurred
bit 2 PD: Power-down Detection Flag bit
1 = Set by power-up or by the CLRWDT ins tru cti on
0 = Se t by execution of the SLEEP instruction
bit 1 POR: Power-on Reset Status bit(2)
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0 BOR: Brown-out Reset Status bit(3)
1 = A Brown-out Reset has not occurred (set by firmware only)
0 = A Brown-out Reset occurred (must be set by firmware after a POR or Brown-out Reset occurs)
Note 1: When CONFIG2L[2:1] = 01, then the SBOREN Reset state is ‘1’; otherwise, it is ‘0’.
2: The actual Reset value of POR is determined by the type of device Reset. See the notes following this
register and Section 4.6 “Reset State of Registers” for additional information.
3: See Table 4-3.
Note 1: Bro wn-out Res et is indica ted when BO R is ‘0’ and POR is ‘1’ (assuming th at both POR and BOR were set
to ‘1’ by firmware immediately after POR).
2: It is recommended th at the POR bit be set af ter a Power-on Reset has bee n dete cted so that su bse quent
Power-on Resets may be detected.
PIC18F2XK20/4XK20
DS40001303H-page 50 2010-2015 Microchip Technology Inc.
4.2 Master Clear (MCLR)
The MCLR pin provides a method for triggering an
external Reset of the device. A Reset is generated by
hold ing the pin low . T hese devi ces have a noise fi lter in
the MCLR Reset path which detects and ignores small
pulses.
The MCLR pin i s not driven l ow b y any i nter nal Res ets ,
including the WDT.
In PIC18F2XK20/4XK20 devices, the MCLR inpu t can
be disabled with the MCLRE Configuration bit. When
MCLR is disabled, the pin be comes a digit al in put . See
Section 10.6 “PORTE, TRISE and LATE Registers”
for more information.
4.3 Power-on Reset (POR)
A Power-on Reset pulse is generated on-chip
whenever VDD rises above a certain threshold. This
allows the device to start in the initialized state when
VDD is adequate for operation.
To take advantage of the POR circuitry, tie the MCLR
pin th rou gh a res ist or to V DD. This will eliminate exter-
nal RC components usually needed to create a
Power-on Reset delay. A minimum rise rate for VDD is
specified (parameter D004). For a slow rise time, see
Figure 4-2.
When the device sta rt s norm al ope ration (i.e., exit s the
Reset condition), device operating parameters
(voltage, frequency, temperature, etc.) must be met to
ensure proper operation. If these conditions are not
met, the device must be held in Reset until the
operating conditions are met.
POR events are captured by the POR bit of the RCON
register. The state of the bit is set to ‘0’ whenever a
POR occurs; it does not change for any other Reset
event. POR is not reset to ‘1’ by any hardware event.
To captur e m ult ipl e ev en ts, the us er mus t ma nu all y s et
the bit to ‘1’ by software following any POR.
FIGURE 4-2: EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW VDD POWER-UP)
Note 1: External Power-on Reset circuit is required
only if the VDD power-up slope is too slow.
The diode D helps discharge the capacitor
quickly when VDD powers down.
2: 15 k < R < 40 k is recommended to make
sure that the voltage drop ac ross R does not
violate the device’s electrical specification.
3: R1 1 k will limit any current flowing into
MCLR from external capacitor C, i n the event
of MCLR/VPP pin breakdown, due to
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS).
C
R1
R
D
VDD
MCLR
VDD
PIC® MCU
2010-2015 Microchip Technology Inc. DS40001303H-page 51
PIC18F2XK20/4XK20
4.4 Brown-out Reset (BOR)
PIC18F2XK20/4XK20 devices implement a BOR circuit
that provides the user with a numb er of co nfigurati on and
power-saving options. The BOR is controlled by the
BORV<1:0> and BOREN<1:0> bits of the CONFIG2L
Configuration register. There are a total of four BOR
confi gurations wh ic h are s um m ari ze d in Table 4-1.
The BOR threshold is set by the BORV<1:0> bits. If
BOR is enabled (any values of BOREN<1:0>, except
‘00’), any drop of VDD below VBOR (parameter D005)
for greater than TBOR (parameter 35) will reset the
device. A Reset may or may not occur if VDD fa lls below
VBOR for less than TBOR. The chip will remain in
Brown-out Reset until VDD rises above VBOR.
If the Powe r-up Ti mer is enabled , it will be invoke d after
VDD rises above VBOR; it then will keep the chip in
Reset for an additional time delay, TPWRT
(parameter 33). If VDD drops below VBOR while the
Power-up Timer is running, the chip will go back into a
Brown-out Reset and the Power-up Timer will be
initialized. Once VDD rises above VBOR, the Power-up
Timer will execute the additional time delay.
BOR and the Power-on Timer (PWRT) are
independently configured. Enabling BOR Reset does
not automatically enab le the PWRT.
The BOR ci rcui t h as an output th at fee ds into the POR
circuit and r earms the POR within th e operating range
of the BOR. This early rearming of the POR ensures
that the device will remain in Reset in the event that VDD
falls below the operating range of the BOR circuitry.
4.4.1 DETECTING BOR
When BO R is enab led, the BO R bi t alway s re set s to ‘0’
on any BOR or POR event. This makes it difficult to
deter mi ne if a BOR ev ent ha s occ urred just by reading
the state of BOR alone. A more reliable method is to
simultaneously check the state of both POR and BOR.
This assumes that the POR and BOR bits are reset to
‘1’ by software immediately after any POR event. If
BOR is ‘0’ wh il e POR is ‘1’, it can be reliably assumed
that a BOR event has occurred.
4.4.2 SOFTWARE ENABLED BOR
When BOREN<1:0> = 01, the BOR can be enabled or
disabled by the user in software. This is done with the
SBOREN control bit of the RCON register. Setting
SBOREN enables the BOR to function as previously
described. Clearing SBOREN disables the BOR
entirely. The SBOREN bit operates only in this mode;
otherwise it is read as ‘0’.
Placing the BOR under software control gives the user
the additional flexibility of tailoring the application to its
environment without having to reprogram the device to
change BOR configuration. It also allows the user to
tailor device power consumption in software by
eliminating the incremental current that the BOR
consumes. While the BOR current is typically very small,
it may have some im p act in low -pow er applic ations.
4.4.3 DISABLING BOR IN SLEEP MODE
When BOREN<1:0> = 10, the BOR remains under
hardware control and operates as previously
described. Whenever the device enters Sleep mode,
however, the BOR is automatically di sabled. When the
device returns to any other operating mode, BOR is
automatically re-enabled.
This mode allows for applications to recover from
brown-out situations, while actively executing code,
when the device requires BOR protection the most. At
the same time, it save s additional po wer in Sleep mode
by eliminating the small incremental BOR current.
4.4.4 MINIMUM BOR ENABLE TIME
Enabling the BOR also enables the Fixed Voltage
Reference (FVR) when no other peripheral requiring the
FVR is acti ve. The BOR be comes active only afte r the
FVR stabilizes. Therefore, to ensure BOR protection,
the FVR settling time must be considered when
enabling the BOR in software or when the BOR is
automatically enabled after waking from Sleep. If the
BOR is disabled, in software or by reentering Sleep
before the FVR stabilizes, the BOR circuit will not sense
a BOR condition. The FVRST bit of the CVRCON2
register can be used to determine FVR stability.
TABLE 4-1: BOR CONFIGURATIONS
Note: Even when BOR is under software
control, the BOR Reset volt age level is still
set by the BORV<1:0> Configuration bits.
It cannot be changed by software.
BOR Configuration Stat us of
SBOREN
(RCON<6>) BOR Operation
BOREN1 BOREN0
00Unavailable BOR disabled; must be enabled by reprogramming the Configuration bits.
01Available B O R enabled by software; operation controlled by SBOREN.
10Unavailable BOR enabled by hardware in Run and Idle modes, disabled during
Sleep mode.
11Unavailable BOR enabled by hardware; must be disabled by reprogramming the Configuration bits.
PIC18F2XK20/4XK20
DS40001303H-page 52 2010-2015 Microchip Technology Inc.
4.5 Device Reset Timers
PIC18F2XK20/4XK20 devices incorporate three
separate on-chip timers that help regulate the
Power-on Reset process. Their main function is to
ensure that the device clock is stable before code is
executed. These timers are:
• Power-up Timer (PWRT)
• Oscillator Start-up Timer (OST)
• PLL Lock Time-out
4.5.1 POWER-UP TIMER (PWRT)
The Power-up Timer (PWRT) of
PIC18F2XK20/4XK20 devices is an 11-bit counter
which uses the LFINTOSC source as the clock input.
This yields an approximate time interval of
2048 x 32 s = 65.6 ms. While the PWRT is counting,
the device is held in Reset.
The power-up time delay depends on the LFINTOSC
clock and will vary from chip-to-chip due to temperature
and process variation. See DC parameter 33 for
details.
The PWRT is enabled by clearing the PWRTEN
Configuration bit.
4.5.2 OSCILLA TOR STAR T-UP TIMER
(OST)
The Oscillator Start-up Timer (OST) provides a 1024
oscillator cycle (from OSC1 input) delay after the
PWRT del ay is ov er ( para me t er 33). This ensures that
the crystal oscillator or resonator has started and
stabilized.
The OST time-out is invoked only for XT, LP, HS and
HSPLL modes and only on Power-on Reset, or on exit
from al l power-ma naged mo des that st op the ex ternal
oscillator.
4.5.3 PLL LOCK TIME-OUT
With the PLL enabled in its PLL mode, the time-out
sequence following a Power-on Reset is slightly
different from other oscillator modes. A separate timer
is used to provide a fixed time-out that is sufficient for
the PLL to lock to the main oscillator frequency. This
PLL lock time-out (TPLL) is typically 2 ms and follows
the oscillator start-up time-out.
4.5.4 TIME-OUT SEQUENCE
On power-up, the time-out sequence is as follows:
1. After the POR pu lse has cleared, PWR T time-out
is invoked (if en abled).
2. Then, the OST is activated.
The total time-out will vary based on oscillator
configuration and the status of the PWRT. Figure 4-3,
Figure 4-4, Figure 4-5, Figure 4-6 and Figure 4-7 all
depict time-out sequences on power-up, with the
Power-up Timer enabled and the device operating in
HS Oscillator mode. Figures 4-3 through 4-6 also
apply to devices operating in XT or LP modes. For
devices in RC mode and with the PWRT disabled, on
the other hand, there will be no time-out at all.
Since the time-outs occur from the PO R pulse, if MCLR
is kept low long enough, all time-outs will expire, after
which, bringing MCLR high will allow program
execution to begin immediately (Figure 4-5). This is
useful for testing purpo ses or to synchroniz e more than
one PIC18FXXK20 device operating in parallel.
TABLE 4-2: TIME-O UT IN VARIOUS SITUATIONS
Oscillator
Configuration
Power-up(2) and Brown-out Exit from
Power-Managed Mode
PWRTEN = 0PWRTEN = 1
HSPLL 66 ms(1) + 1024 TOSC + 2 ms(2) 1024 TOSC + 2 ms(2) 1024 TOSC + 2 ms(2)
HS, XT, LP 66 ms(1) + 1024 TOSC 1024 TOSC 1024 TOSC
EC, ECIO 66 ms(1) ——
RC, RCIO 66 ms(1) ——
INTIO1, INTIO2 66 ms(1) ——
Note 1: 66 ms (65.5 ms) is the nominal Power-up Timer (PWRT) delay.
2: 2 ms is the nominal time required for the PLL to lock.
2010-2015 Microchip Technology Inc. DS40001303H-page 53
PIC18F2XK20/4XK20
FIGURE 4-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT)
FIGURE 4-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
FIGURE 4-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
TPWRT
TOST
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
TPWRT
TOST
VDD
MCLR
INTER N AL PO R
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
TPWRT
TOST
PIC18F2XK20/4XK20
DS40001303H-page 54 2010-2015 Microchip Technology Inc.
FIGURE 4-6: SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT)
FIGURE 4-7: TIME-OUT SEQUENCE ON POR W/PLL ENABLED (MCLR TIED TO VDD)
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL R ESET
0V 5V
TPWRT
TOST
TPWRT
TOST
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-O UT
INTERNAL RESET
PLL TIME-OUT
TPLL
Note: TOST = 1024 clock cycles.
TPLL 2 ms max. First three stages of the PWRT timer.
2010-2015 Microchip Technology Inc. DS40001303H-page 55
PIC18F2XK20/4XK20
4.6 Reset State of Registers
Some registers are unaffected by a Reset. Their status
is unknown on POR and unchanged by all other
Resets. All other reg isters are forc ed to a “R es et s t a te”
depending on the type of Reset that occurred.
Most registers are not affected by a WDT wake-up,
since this is viewed as the resumption of normal
operation. Status bits from the RCON register, RI, TO,
PD, POR and BOR, are set or cleared differently in
different Reset situations, as indicated in Table 4-3.
These bits are used by software to determine the
nature of the Reset.
Table 4-4 describes the Reset states for all of the
Special Function Registers. These are categorized by
Power-on and Brown-out Resets, Master Clear and
WDT Resets and WDT wake-ups.
TABLE 4-3: STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION
FOR RCON REGISTER
Condition Program
Counter
RCON Register STKPTR Register
SBOREN RI TO PD POR BOR STKFUL STKUNF
Power-on Reset 0000h 1 11100 0 0
RESET Instruction 0000h u(2) 0uuuu u u
Brown-out Reset 0000h u(2) 111u0 u u
MCLR during Power-Managed
Run Modes 0000h u(2) u1uuu u u
MCLR during Power-Managed
Idle Modes and Sleep Mode 0000h u(2) u10uu u u
WDT T ime-out during Full Power
or Power-Managed Run Mode 0000h u(2) u0uuu u u
MCLR during Full Po wer
Execution 0000h u(2) uuuuu u u
Stack Full Reset (STVREN = 1) 0000h u(2) uuuuu 1 u
Stack Underflow Reset
(STVREN = 1)0000h u(2) uuuuu u 1
Stack Underflow Error (not an
actual Reset, STVREN = 0)0000h u(2) uuuuu u 1
WDT Time-out during
Power-Managed Idle or Sleep
Modes
PC + 2 u(2) u00uu u u
Interrupt Ex it from
Power-Managed Modes PC + 2(1) u(2) uu0uu u u
Legend: u = unchanged
Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the
inter rupt ve cto r (008h or 0018 h).
2: Reset state is ‘1’ for SBOREN and unchanged for all other Resets when software BOR is enabled
(BOREN<1:0> Configuration bits = 01). Otherwise, the Reset state is ‘0’.
PIC18F2XK20/4XK20
DS40001303H-page 56 2010-2015 Microchip Technology Inc.
TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS
Register App licable Devices Power-on Reset,
Brown- out Reset
MCLR Resets,
WDT Reset,
RESET Instruction,
Stack Resets
Wake-up via WDT
or Interrupt
TOSU PIC18F2XK20 PIC18F4XK20 ---0 0000 ---0 0000 ---0 uuuu (3)
TOSH PIC18F2XK20 PIC18F4XK20 0000 0000 0000 0000 uuuu uuuu(3)
TOSL PIC18F2XK20 PIC18F4XK20 0000 0000 0000 0000 uuuu uuuu(3)
STKPTR PIC18F2XK20 PIC18F4XK20 00-0 0000 uu-0 0000 uu-u uuuu(3)
PCLATU PIC18F2XK20 PIC18F4XK20 ---0 0000 ---0 0000 ---u uuuu
PCLATH PIC18F2XK20 PIC18F4XK20 0000 0000 0000 0000 uuuu uuuu
PCL PIC18F2XK20 PIC18F4XK20 0000 0000 0000 0000 PC + 2(2)
TBLPTRU PIC18F2XK20 PIC18F4XK20 --00 0000 --00 0000 --uu uuuu
TBLPTRH PIC18F2XK20 PIC18F4XK20 0000 0000 0000 0000 uuuu uuuu
TBLPTRL PIC18F2XK20 PIC18F4XK20 0000 0000 0000 0000 uuuu uuuu
TABLAT PIC18F2XK20 PIC18F4XK20 0000 0000 0000 0000 uuuu uuuu
PRODH PIC18F2XK20 PIC18F4XK20 xxxx xxxx uuuu uuuu uuuu uuuu
PRODL PIC18F2XK20 PIC18F4XK20 xxxx xxxx uuuu uuuu uuuu uuuu
INTCON PIC18F2XK20 PIC18F4XK20 0000 000x 0000 000u uuuu uuuu(1)
INTCON2 PIC18F2XK20 PIC18F4XK20 1111 -1-1 1111 -1-1 uuuu -u-u(1)
INTCON3 PIC18F2XK20 PIC18F4XK20 11-0 0-00 11-0 0-00 uu-u u-uu(1)
INDF0 PIC18F2XK20 PIC18F4XK20 N/A N/A N/A
POSTINC0 PIC18F2XK20 PIC18F4XK20 N/A N/A N/A
POSTDEC0 PIC18F2XK20 PIC18F4XK20 N/A N/A N/A
PREINC0 PIC18F2XK20 PIC18F4XK20 N/A N/A N/A
PLUSW0 PIC18F2XK20 PIC18F4XK20 N/A N/A N/A
FSR0H PIC18F2XK20 PIC18F4XK20 ---- 0000 ---- 0000 ---- uuuu
FSR0L PIC18F2XK20 PIC18F4XK20 xxxx xxxx uuuu uuuu uuuu uuuu
WREG PIC18F2XK20 PIC18F4XK20 xxxx xxxx uuuu uuuu uuuu uuuu
INDF1 PIC18F2XK20 PIC18F4XK20 N/A N/A N/A
POSTINC1 PIC18F2XK20 PIC18F4XK20 N/A N/A N/A
POSTDEC1 PIC18F2XK20 PIC18F4XK20 N/A N/A N/A
PREINC1 PIC18F2XK20 PIC18F4XK20 N/A N/A N/A
PLUSW1 PIC18F2XK20 PIC18F4XK20 N/A N/A N/A
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector
(0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with
the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack.
4: See Table 4-3 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as
PORTA pins, they are disabled and read ‘0’.
6: All bits of the ANSELH register initialize to ‘0’ if the PBADEN bit of CONFIG3H is ‘0’.
2010-2015 Microchip Technology Inc. DS40001303H-page 57
PIC18F2XK20/4XK20
FSR1H PIC18F2XK20 PIC18F4XK20 ---- 0000 ---- 0000 ---- uuuu
FSR1L PIC18F2XK20 PIC18F4XK20 xxxx xxxx uuuu uuuu uuuu uuuu
BSR PIC18F2XK20 PIC18F4XK20 ---- 0000 ---- 0000 ---- uuuu
INDF2 PIC18F2XK20 PIC18F4XK20 N/A N/A N/A
POSTINC2 PIC18F2XK20 PIC18F4XK20 N/A N/A N/A
POSTDEC2 PIC18F2XK20 PIC18F4XK20 N/A N/A N/A
PREINC2 PIC18F2XK20 PIC18F4XK20 N/A N/A N/A
PLUSW2 PIC18F2XK20 PIC18F4XK20 N/A N/A N/A
FSR2H PIC18F2XK20 PIC18F4XK20 ---- 0000 ---- 0000 ---- uuuu
FSR2L PIC18F2XK20 PIC18F4XK20 xxxx xxxx uuuu uuuu uuuu uuuu
STATUS PIC18F2XK20 PIC18F4XK20 ---x xxxx ---u uuuu ---u uuuu
TMR0H PIC18F2XK20 PIC18F4XK20 0000 0000 0000 0000 uuuu uuuu
TMR0L PIC18F2XK20 PIC18F4XK20 xxxx xxxx uuuu uuuu uuuu uuuu
T0CON PIC18F2XK20 PIC18F4XK20 1111 1111 1111 1111 uuuu uuuu
OSCCON PIC18F2XK20 PIC18F4XK20 0011 qq00 0011 qq00 uuuu uuuu
HLVDCON PIC18F2XK20 PIC18F4XK20 0-00 0101 0-00 0101 u-uu uuuu
WDTCON PIC18F2XK20 PIC18F4XK20 ---- ---0 ---- ---0 ---- ---u
RCON(4) PIC18F2XK20 PIC18F4XK20 0q-1 11q0 0u-q qquu uu-u qquu
TMR1H PIC18F2XK20 PIC18F4XK20 xxxx xxxx uuuu uuuu uuuu uuuu
TMR1L PIC18F2XK20 PIC18F4XK20 xxxx xxxx uuuu uuuu uuuu uuuu
T1CON PIC18F2XK20 PIC18F4XK20 0000 0000 u0uu uuuu uuuu uuuu
TMR2 PIC18F2XK20 PIC18F4XK20 0000 0000 0000 0000 uuuu uuuu
PR2 PIC18F2XK20 PIC18F4XK20 1111 1111 1111 1111 1111 1111
T2CON PIC18F2XK20 PIC18F4XK20 -000 0000 -000 0000 -uuu uuuu
SSPBUF PIC18F2XK20 PIC18F4XK20 xxxx xxxx uuuu uuuu uuuu uuuu
SSPADD PIC18F2XK20 PIC18F4XK20 0000 0000 0000 0000 uuuu uuuu
SSPSTAT PIC18F2XK20 PIC18F4XK20 0000 0000 0000 0000 uuuu uuuu
SSPCON1 PIC18F2XK20 PIC18F4XK20 0000 0000 0000 0000 uuuu uuuu
SSPCON2 PIC18F2XK20 PIC18F4XK20 0000 0000 0000 0000 uuuu uuuu
TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register App licable Devices Power-on Reset,
Brown- out Reset
MCLR Resets,
WDT Reset,
RESET Instruction,
Stack Resets
Wake-up via WDT
or Interrupt
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector
(0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with
the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack.
4: See Table 4-3 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as
PORTA pins, they are disabled and read ‘0’.
6: All bits of the ANSELH register initialize to ‘0’ if the PBADEN bit of CONFIG3H is ‘0’.
PIC18F2XK20/4XK20
DS40001303H-page 58 2010-2015 Microchip Technology Inc.
ADRESH PIC18F2XK20 PIC18F4XK20 xxxx xxxx uuuu uuuu uuuu uuuu
ADRESL PIC18F2XK20 PIC18F4XK20 xxxx xxxx uuuu uuuu uuuu uuuu
ADCON0 PIC18F2XK20 PIC18F4XK20 --00 0000 --00 0000 --uu uuuu
ADCON1 PIC18F2XK20 PIC18F4XK20 --00 0qqq --00 0qqq --uu uuuu
ADCON2 PIC18F2XK20 PIC18F4XK20 0-00 0000 0-00 0000 u-uu uuuu
CCPR1H PIC18F2XK20 PIC18F4XK20 xxxx xxxx uuuu uuuu uuuu uuuu
CCPR1L PIC18F2XK20 PIC18F4XK20 xxxx xxxx uuuu uuuu uuuu uuuu
CCP1CON PIC18F2XK20 PIC18F4XK20 0000 0000 0000 0000 uuuu uuuu
CCPR2H PIC18F2XK20 PIC18F4XK20 xxxx xxxx uuuu uuuu uuuu uuuu
CCPR2L PIC18F2XK20 PIC18F4XK20 xxxx xxxx uuuu uuuu uuuu uuuu
CCP2CON PIC18F2XK20 PIC18F4XK20 --00 0000 --00 0000 --uu uuuu
PSTRCON PIC18F2XK20 PIC18F4XK20 ---0 0001 ---0 0001 ---u uuuu
BAUDCON PIC18F2XK20 PIC18F4XK20 0100 0-00 0100 0-00 uuuu u-uu
PWM1CON PIC18F2XK20 PIC18F4XK20 0000 0000 0000 0000 uuuu uuuu
ECCP1AS PIC18F2XK20 PIC18F4XK20 0000 0000 0000 0000 uuuu uuuu
CVRCON PIC18F2XK20 PIC18F4XK20 0000 0000 0000 0000 uuuu uuuu
CVRCON2 PIC18F2XK20 PIC18F4XK20 00-- ---- 00-- ---- uu-- ----
TMR3H PIC18F2XK20 PIC18F4XK20 xxxx xxxx uuuu uuuu uuuu uuuu
TMR3L PIC18F2XK20 PIC18F4XK20 xxxx xxxx uuuu uuuu uuuu uuuu
T3CON PIC18F2XK20 PIC18F4XK20 0000 0000 uuuu uuuu uuuu uuuu
SPBRGH PIC18F2XK20 PIC18F4XK20 0000 0000 0000 0000 uuuu uuuu
SPBRG PIC18F2XK20 PIC18F4XK20 0000 0000 0000 0000 uuuu uuuu
RCREG PIC18F2XK20 PIC18F4XK20 0000 0000 0000 0000 uuuu uuuu
TXREG PIC18F2XK20 PIC18F4XK20 0000 0000 0000 0000 uuuu uuuu
TXSTA PIC18F2XK20 PIC18F4XK20 0000 0010 0000 0010 uuuu uuuu
RCSTA PIC18F2XK20 PIC18F4XK20 0000 000x 0000 000x uuuu uuuu
EEADR PIC18F2XK20 PIC18F4XK20 0000 0000 0000 0000 uuuu uuuu
EEADRH PIC18F26K20 PIC18F46K20 ---- --00 ---- --00 ---- --uu
EEDATA PIC18F2XK20 PIC18F4XK20 0000 0000 0000 0000 uuuu uuuu
EECON2 PIC18F2XK20 PIC18F4XK20 0000 0000 0000 0000 0000 0000
EECON1 PIC18F2XK20 PIC18F4XK20 xx-0 x000 uu-0 u000 uu-0 u000
TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register App licable Devices Power-on Reset,
Brown- out Reset
MCLR Resets,
WDT Reset,
RESET Instruction,
Stack Resets
Wake-up via WDT
or Interrupt
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector
(0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with
the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack.
4: See Table 4-3 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as
PORTA pins, they are disabled and read ‘0’.
6: All bits of the ANSELH register initialize to ‘0’ if the PBADEN bit of CONFIG3H is ‘0’.
2010-2015 Microchip Technology Inc. DS40001303H-page 59
PIC18F2XK20/4XK20
IPR2 PIC18F2XK20 PIC18F4XK20 1111 1111 1111 1111 uuuu uuuu
PIR2 PIC18F2XK20 PIC18F4XK20 0000 0000 0000 0000 uuuu uuuu(1)
PIE2 PIC18F2XK20 PIC18F4XK20 0000 0000 0000 0000 uuuu uuuu
IPR1 PIC18F2XK20 PIC18F4XK20 1111 1111 1111 1111 uuuu uuuu
PIC18F2XK20 PIC18F4XK20 -111 1111 -111 1111 -uuu uuuu
PIR1 PIC18F2XK20 PIC18F4XK20 0000 0000 0000 0000 uuuu uuuu(1)
PIC18F2XK20 PIC18F4XK20 -000 0000 -000 0000 -uuu uuuu(1)
PIE1 PIC18F2XK20 PIC18F4XK20 0000 0000 0000 0000 uuuu uuuu
PIC18F2XK20 PIC18F4XK20 -000 0000 -000 0000 -uuu uuuu
OSCTUNE PIC18F2XK20 PIC18F4XK20 0000 0000 0000 0000 uuuu uuuu
TRISE PIC18F2XK20 PIC18F4XK20 ---- -111 ---- -111 ---- -uuu
TRISD PIC18F2XK20 PIC18F4XK20 1111 1111 1111 1111 uuuu uuuu
TRISC PIC18F2XK20 PIC18F4XK20 1111 1111 1111 1111 uuuu uuuu
TRISB PIC18F2XK20 PIC18F4XK20 1111 1111 1111 1111 uuuu uuuu
TRISA(5) PIC18F2XK20 PIC18F4XK20 1111 1111(5) 1111 1111(5) uuuu uuuu(5)
LATE PIC18F2XK20 PIC18F4XK20 ---- -xxx ---- -uuu ---- -uuu
LATD PIC18F2XK20 PIC18F4XK20 xxxx xxxx uuuu uuuu uuuu uuuu
LATC PIC18F2XK20 PIC18F4XK20 xxxx xxxx uuuu uuuu uuuu uuuu
LATB PIC18F2XK20 PIC18F4XK20 xxxx xxxx uuuu uuuu uuuu uuuu
LATA(5) PIC18F2XK20 PIC18F4XK20 xxxx xxxx(5) uuuu uuuu(5) uuuu uuuu(5)
PORTE PIC18F2XK20 PIC18F4XK20 ---- x000 ---- u000 ---- uuuu
PIC18F2XK20 PIC18F4XK20 ---- x--- ---- u--- ---- u---
PORTD PIC18F2XK20 PIC18F4XK20 xxxx xxxx uuuu uuuu uuuu uuuu
PORTC PIC18F2XK20 PIC18F4XK20 xxxx xxxx uuuu uuuu uuuu uuuu
PORTB PIC18F2XK20 PIC18F4XK20 xxx0 0000 uuu0 0000 uuuu uuuu
PORTA(5) PIC18F2XK20 PIC18F4XK20 xx0x 0000(5) uu0u 0000(5) uuuu uuuu(5)
ANSELH(6) PIC18F2XK20 PIC18F4XK20 ---1 1111 ---1 1111 ---u uuuu
ANSEL PIC18F2XK20 PIC18F4XK20 1111 1111 1111 1111 uuuu uuuu
IOCB PIC18F2XK20 PIC18F4XK20 0000 ---- 0000 ---- uuuu ----
WPUB PIC18F2XK20 PIC18F4XK20 1111 1111 1111 1111 uuuu uuuu
CM1CON0 PIC18F2XK20 PIC18F4XK20 0000 0000 0000 0000 uuuu uuuu
CM2CON0 PIC18F2XK20 PIC18F4XK20 0000 0000 0000 0000 uuuu uuuu
TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register App licable Devices Power-on Reset,
Brown- out Reset
MCLR Resets,
WDT Reset,
RESET Instruction,
Stack Resets
Wake-up via WDT
or Interrupt
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector
(0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with
the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack.
4: See Table 4-3 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as
PORTA pins, they are disabled and read ‘0’.
6: All bits of the ANSELH register initialize to ‘0’ if the PBADEN bit of CONFIG3H is ‘0’.
PIC18F2XK20/4XK20
DS40001303H-page 60 2010-2015 Microchip Technology Inc.
CM2CON1 PIC18F2XK20 PIC18F4XK20 0000 ---- 0000 ---- uuuu ----
SLRCON PIC18F2XK20 PIC18F4XK20 ---1 1111 ---1 1111 ---u uuuu
SSPMSK PIC18F2XK20 PIC18F4XK20 1111 1111 1111 1111 uuuu uuuu
TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register App licable Devices Power-on Reset,
Brown- out Reset
MCLR Resets,
WDT Reset,
RESET Instruction,
Stack Resets
Wake-up via WDT
or Interrupt
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector
(0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with
the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack.
4: See Table 4-3 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as
PORTA pins, they are disabled and read ‘0’.
6: All bits of the ANSELH register initialize to ‘0’ if the PBADEN bit of CONFIG3H is ‘0’.
2010-2015 Microchip Technology Inc. DS40001303H-page 61
PIC18F2XK20/4XK20
5.0 MEMORY ORGANIZATION
There are three types of memory in PIC18 Enhanced
microcontroller devices:
• Program Memory
• Data RAM
• Data EEPROM
As Harvard arc hitecture devices, the da ta and progra m
memories use separate busses; this allows for
concurr ent access of the two memory spaces . The data
EEPROM, for practical purposes, can be regarded as
a peripheral device, since it is addressed and accessed
through a set of control registers.
Additional detailed information on the operation of the
Flash program memory is provided in Section 6.0
“Flash Program Memory”. Data EEPROM is
discussed separately in Section 7.0 “Data EEPROM
Memory”.
5.1 Program Memory Organization
PIC18 microcontrollers implement a 21-bit program
counter, which is capable of addressing a 2-Mbyte
progra m memory sp ace. Acces sing a lo cation b etween
the upper boundary of the physically implemented
memory and the 2-Mbyte address will return all ‘ 0’s (a
NOP instr ucti on).
This family of devices contain the following:
• PIC18F23K20, PIC18F43K20: 8 Kbytes of Flash
Memory, up to 4,096 single-word instructions
• PIC18F24K20, PIC18F44K20: 16 Kbytes of Flash
Memory, up to 8,192 single-word instructions
• PIC18F25K20, PIC18F45K20: 32 Kbytes of Flash
Memory, up to 16,384 single-word instructions
• PIC18F26K20, PIC18F46K20: 64 Kbytes of Flash
Memory, up to 37,768 single-word instructions
PIC18 devices have two interrupt vectors. The Reset
vector address is at 0000h and the interrupt vector
addresses are at 0008h and 0018h.
The program memory map for PIC18F2XK20/4XK20
devices is shown in Figure 5-1. Memory block details
are shown in Figure 23-2.
FIGURE 5-1: PROGRAM MEMORY MAP AND STACK FOR PIC18F2XK20/4XK20 DEVICES
PC<20:0>
Stack Level 1
Stack Level 31
Reset Vector
Low Priority Interrupt Vector
CALL,RCALL,RETURN
RETFIE,RETLW 21
0000h
0018h
On-Chip
Program Memory
High Pr iority In t e r ru p t Ve ctor 0008h
User Memor y Space
1FFFFFh
4000h
3FFFh
Read ‘0’
200000h
8000h
7FFFh
On-Chip
Program Memory
Read ‘0’
1FFFh
2000h
On-Chip
Program Memory
Read ‘0’
PIC18F25K20/
45K20
PIC18F24K20/
44K20
PIC18F23K20/
43K20
Read ‘0’
FFFFh
PIC18F26K20/
46K20
On-Chip
Program Memory
10000h
PIC18F2XK20/4XK20
DS40001303H-page 62 2010-2015 Microchip Technology Inc.
5.1.1 PROGRAM COUNTER
The Progra m Counter (PC) s pecifies the address of the
instruction to fetch for execution. The PC is 21 bits wide
and is contained in three separate 8-bit registers. The
low byte, known as the PCL register, is both readable
and wr itable. Th e high byt e, or PCH regi ster, contai ns
the PC<1 5:8> bits; it is not directly re adable or writ able.
Update s to the PCH register are performe d through the
PCLATH register. The upper byte is called PCU. This
register contains the PC<20:16> bits; it is also not
directly readable or writable. Updates to the PCU
register are performed through the PCLATU register.
The contents of PCLATH and PCLATU are transferred
to the program counter by any operation that writes
PCL. Similarly, the upper two bytes of the program
counter are tran sferred to PCL ATH and PCLATU by an
operation that reads PCL. This is useful for computed
offsets to the PC (see Section 5.1.4.1 “Computed
GOTO”).
The PC addresses bytes in the program memory. To
prevent the PC from becoming misaligned with word
instructions, the Least Significant bit of PCL is fixed to
a value of ‘0’. The PC increments by two to address
sequential instructions in the program memory.
The CALL, RCALL, GOTO and program branch
instructions write to the program counter directly. For
these instructions, the contents of PCLATH and
PCLATU are not transferred to the program counter.
5.1.2 RETURN ADDRESS STACK
The return address st ac k al low s any combinatio n of up
to 31 program calls and interrupts to occur. The PC is
pushed onto the stack when a CALL or RCALL
instruction is executed or an interrupt is Acknowledged.
The PC value is pulled off the stack on a RETURN,
RETLW or a RETFIE instruction . PCLATU and PCLATH
are not affected by any of the RETURN or CALL
instructions.
The stac k operates as a 31-word by 21-bit RAM and a
5-bit Stack Pointer, STKPTR. The stack space is not
part of either program or data sp ace. The St ack Pointer
is readable and writable and the address on the top of
the stack is readable and writable through the Top-of-
Stack (TOS) Special File Registers. Data can also be
pushed to, or popped from the stack, using these
registers.
A CALL ty pe inst ruct ion cause s a pus h onto t he stac k;
the Stack Pointer is first incremented and the location
pointed to by the Stack Pointer is written with the
contents of the PC (already pointing to the instruction
following the CALL). A RETURN type instruction causes
a pop from the stack; the contents of the location
pointed to by the STKPTR are transferred to the PC
and then the Stack Pointer is decremented.
The Stack Pointer is initialized to ‘00000’ after all
Resets. There is no RAM associated with the location
corresponding to a Stack Pointer value of ‘00000’; this
is only a R eset v alue. S t at us bits indicate if th e s t ac k is
full or has overflowed or has underflowed.
5.1.2.1 Top-of-Stack Access
Only the top of the return address stack (TOS) is readable
and writable. A set of three registers, TOSU:TOSH:TOSL,
hold the contents of the stack location pointed to by the
STKPTR register (Figure 5-2). This allows users to
implement a software stack if necessary. After a CALL,
RCALL or interrupt, the software can read the pushed
value by reading the TOSU:TOSH:TOSL registers. These
values can be placed on a user defined software stack. At
return time, the software can return these values to
TOSU:TOSH:TOSL and do a return.
The user must disable the global interrupt enable bits
while accessing the stack to prevent inadvertent stack
corruption.
FIGURE 5-2: RETURN ADDRESS STACK AND ASSOCIATED REGISTERS
00011
001A34h
11111
11110
11101
00010
00001
00000
00010
Return Address Stack <20:0>
Top-of-Stack 000D58h
TOSLTOSHTOSU 34h1Ah00h STKPTR<4:0>
Top -of-S tack Registers S tack Pointer
2010-2015 Microchip Technology Inc. DS40001303H-page 63
PIC18F2XK20/4XK20
5.1.2.2 Return St ack Pointer (STKPTR)
The STKPTR regis ter (Register 5-1) cont ains the S t ack
Pointer value, the STKFUL (stack full) Status bit and
the STKU NF (stack und erflow) S ta tus bits. Th e value of
the Stack Pointer can be 0 through 31. The Stack
Pointer increments before values are pushed onto the
stack and decrem ents after values are popped off the
stack. On Reset, the Stack Pointer value will be zero.
The user may read and write the Stack Pointer value.
This feature can be used by a Real-Time Operating
System (RTOS) for return stack maintenance.
Aft er the PC is pu shed ont o the st a ck 31 ti mes (w itho ut
popping any values off the stack), the STKFUL bit is
set. The STKFUL bit is cleared by software or by a
POR.
The action that takes place when the stack becomes
full depends on the state of the STVREN (Stack Over-
flow Reset Enable) Configuration bit. (Refer to
Section 23.1 “Configuration Bit s” for a desc ription of
the device Configuration bits.) If STVREN is set
(default), the 31st push will push the (PC + 2) value
onto the stack, set the STKFUL bit and reset the
device. The STKFUL bit will remain set and the Stack
Pointer will be set to zero.
If STVREN is clea red, the STKFUL bi t will be se t on the
31st push and the Stack Pointer will increment to 31.
Any additional pushes will not overwrite the 31st push
and STKPTR will remain at 31.
When the stack has been popped enough times to
unload th e stack, the ne xt pop will return a value of zero
to the PC and sets the STKUNF bit, while the Stack
Pointer remains at zero. The STKUNF bit will remain
set until cleared by software or until a POR occurs.
5.1.2.3 PUSH and POP Instructions
Since the Top-of-Stack is readable and writable, the
ability to pus h values onto the stac k and pull values off
the stack without disturbing normal program execution
is a desirable feature. The PIC18 instruction set
includes two instructions, PUSH and POP, that permit
the TOS to be manipulated under software control.
TOSU , T OSH and T OS L can be m odifie d to plac e dat a
or a return address on the stack.
The PUSH instruction places the current PC value onto
the stack. This increments the Stack Pointer and loads
the current PC value onto the stack.
The POP instruction discards the current TOS by
decrementing the Stack Pointer. The previous value
pushed onto the stack then becomes the TOS value.
Note: Ret urni ng a value of ze ro to the PC on an
underflow has the effect of vectoring the
program to the Reset vector, where the
stack conditions can be verified and
appropriate actions can be taken. This is
not t he same as a R ese t, as the conte nts
of the SFRs are not affected.
REGISTER 5-1: STKPTR: STACK POINTER REGISTER
R/C-0 R/C-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
STKFUL(1) STKUNF(1) — SP4 SP3 SP2 SP1 SP0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented C = Clearable only bit
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 STKFUL: Stack Full Flag bit(1)
1 = Stack became full or overflowed
0 = Stack has not become full or overflowed
bit 6 STKUNF: Stack Underflow Flag bit(1)
1 = Stack underflow occ urred
0 = Stack underflow did not occur
bit 5 Unimplemented: Read as ‘0’
bit 4-0 SP<4:0>: Stack Pointer Location bits
Note 1: Bit 7 and bit 6 are cleared by user software or by a POR.
PIC18F2XK20/4XK20
DS40001303H-page 64 2010-2015 Microchip Technology Inc.
5.1.2.4 Stack Full and Underflow Resets
Device Resets on stack overflow and stack underflow
conditions are enabled by setting the STVREN bit in
Config ura tion Regi ster 4L. When STVREN is set, a full
or underflow will set the appropriate STKFUL or
STKUNF bit and then cause a device Reset. When
STVREN is cleared, a full or underflow condi tion will set
the appropriate STKFUL or STKUNF bit but not cause
a device Reset. The STKFUL or STKUNF bits are
cleared by the user software or a Power-on Reset.
5.1.3 FAST REGISTER STACK
A fast register stack is provided for the Status, WREG
and BSR registers, to provide a “fast return” option for
interrupts. The stack for each register is only one level
deep and is neither readable nor writable. It is loaded
with the current value of the corresponding register
when the processor vectors for an interrupt. All inter-
rupt sources will push values into the stack registers.
The values in the registers are then loaded back into
their associated registers if the RETFIE, FAST
instruction is used to return from the interrupt.
If both low and high priority interrupts are enabled, the
stack registers cannot be used reliably to return from
low priority interrupts. If a high priority interrupt occurs
while servicing a low priority interrupt, the stack register
values stored by the low priority interrupt will be
overwritten. In these cases, users must save the key
registers by software during a low priority interrupt.
If interrupt pri ority is not used, all interrupts may use the
fast register stack for returns from interrupt. If no
inter rupts are used, the fast regis t e r st ac k c an be use d
to restore the Status, WREG and BSR registers at the
end of a subroutine call. To use the fast register stack
for a subroutine call, a CALL label,FAST instruct ion
must be executed to save the Status, WREG and BSR
registers to the fast register stack. A RETURN,FAST
instruction is then executed to restore these registers
from the fast register stack.
Example 5-1 show s a source cod e exampl e that us es
the fast register stack during a subroutine call and
return.
EXAMPLE 5-1: FAST REGISTER STACK
CODE EXAMPLE
5.1.4 LOOK-UP TABLES IN PROGRAM
MEMORY
There may be programming situations that require the
creation of data structures, or look-up tables, in
program memory. For PIC18 devices, look-up tables
can be implemented in two ways:
• Computed GOTO
• Table Reads
5.1.4.1 Computed GOTO
A comput ed GOTO i s a cco mplished by adding a n offset
to the program counter. An example is shown in
Example 5-2.
A look-up table can be formed with an ADDWF PCL
instruction and a group of RETLW nn instructions. The
W register is loa ded with an offset into the ta ble befo re
executi ng a c al l to tha t t a ble. The first instru cti on of the
called routine is the ADDWF PCL instruction. The next
instruction executed will be one of the RETLW nn
instructions that returns the value ‘nn’ to the calling
function.
The offset value (in WREG) specifies the number of
bytes that the program counter should advance and
should be mu ltiples of 2 (LSb = 0).
In this method, only one data byte may be stored in
each instruction location and room on the return
address stack is required.
EXAMPLE 5-2: COMPUTED GOTO USING
AN OFFSET VALUE
5.1.4.2 Table Reads and Table Writes
A better method of storing data in program memory
allow s two bytes of dat a to be stored in each instruc tion
location.
Look-up table data may be stored two bytes per
program word by using table reads and writes. The
Table Pointer (TBLPTR) register specifies the byte
address and the Table Latch (TABLAT) register
cont ains the da ta that is read from o r written to pro gram
memory. Data is transferred to or from program
memory one byte at a time.
Table read and table write operations are discussed
further in Section 6.1 “Table Reads and Table
Writes”.
CALL SUB1, FAST ;STATUS, WREG, BSR
;SAVED IN FAST REGISTER
;STACK
SUB1
RETURN, FAST ;RESTORE VALUES SAVED
;IN FAST REGISTER STACK
MOVF OFFSET, W
CALL TABLE
ORG nn00h
TABLE ADDWF PCL
RETLW nnh
RETLW nnh
RETLW nnh
.
.
.
2010-2015 Microchip Technology Inc. DS40001303H-page 65
PIC18F2XK20/4XK20
5.2 PIC18 Instruction Cycle
5.2.1 CLOCKING SCHEME
The microcontroller clock input, whether from an
internal or external source, is internally divided by four
to generate four non-overlapping quadrature clocks
(Q1, Q2, Q3 and Q4). Interna lly, t he program c ounter i s
incremented on every Q1; the instruction is fetched
from the program memory and latched into the
instruction register during Q4. The instruction is
decode d and exec uted during the follow ing Q1 th rough
Q4. The clocks and instruction execution flow are
shown in Figure 5-3.
5.2.2 INSTRUCTION FLOW/PIPELINING
An “Instruction Cycle” consists of four Q cycles: Q1
through Q4. The instruction fetch and execute are
pipelined in such a manner that a fetch takes one
instruction cycle, while the decode and execute take
another instruction cycle. However, due to the
pipelining, each instruction effectively executes in one
cycle. If an instruction causes the program c ounter to
change (e.g., GOTO), then two cycles are required to
complete the inst ruction (Example 5-3).
A fetch cycle begins with the Program Counter (PC)
incrementing in Q1.
In the ex ecution cycle , the fetched instruction i s latched
into the Instruction Register (IR) in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q 3 and Q4 c ycles. Dat a mem ory is read during Q2
(operand read) and written during Q4 (destination
write).
FIGURE 5-3: CLOCK/INSTRUCTION CYCLE
EXAMPLE 5-3: INSTRUCTION PIPELINE FLOW
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
Q1
Q2
Q3
Q4
PC
OSC2/CLKOUT
(RC mode)
PC PC + 2 PC + 4
Fetch INST (PC)
Execute INST (PC – 2)
Fetch INST (PC + 2)
Execute IN ST (P C)
Fetch INST (PC + 4)
Execute INST (PC + 2)
Internal
Phase
Clock
All instruc tions are single cycle, exc ept for any program bran ches. These tak e two cycles sin ce the fetch instruct ion
is “flushed” from the pipeline while the new instruction is being fetched and then executed.
TCY0TCY1TCY2TCY3TCY4TCY5
1. MOVLW 55h Fetch 1 Execute 1
2. MOVWF PORTB Fetch 2 Execute 2
3. BRA SUB_1 Fetch 3 Execute 3
4. BSF PORTA, BIT3 (Forced NOP) Fetch 4 Flush (NOP)
5. Instruction @ address SUB_1 Fetch SUB_1 Execute SUB_1
PIC18F2XK20/4XK20
DS40001303H-page 66 2010-2015 Microchip Technology Inc.
5.2.3 INSTRUCTIONS IN PROGRAM
MEMORY
The program memory is addressed in bytes.
Instr uctions are stored as ei ther two byt es or four byte s
in program memory. The Least Significant Byte of an
instruc tion wo rd is alway s stored in a program me mory
location with an even address (LSb = 0). To maintain
alignment with instruction boundaries, the PC
increments in steps of 2 and the LSb will always read
‘0’ (see Section 5.1.1 “Program Counter”).
Figure 5-4 shows an ex am ple of how instruction words
are stored in the program memory.
The CALL and GOTO instructions have the absolute
program memory address embedded into the
instruction. Since instructions are always stored on word
boundaries, the data contained in the instruction is a
word address. The word address is written to PC<20:1>,
which accesses the desired byte address in program
memory. Instruction #2 in Figure 5-4 shows how the
instruction GOTO 0006h is encoded in the program
memory. Program branch instructions, which encode a
relative address offset, operate in the same manner . The
of fset value stored in a branch instruction represent s the
number of single-word instructions that the PC will be
offset by. Section 24.0 “Instruction Set Summary”
provides further details of the instruction s et.
FIGURE 5-4: INS TRUCTIONS IN PROGRAM MEM ORY
5.2.4 TWO-WORD INSTRUCTIONS
The standard PIC18 instruction set has four two-word
instructions: CALL, MOVFF, GOTO and LSFR. In all
cases, the second word of the instruction always has
‘1111’ as its four M ost Si gnifican t bit s; the ot her 12 bit s
are literal data, usually a data memory address.
The use of ‘1111’ in the 4 MSbs of an instruction
specifies a special form of NOP. If the instruction is
executed in proper sequence – immediately after the
first word – the data in the second word is accessed
and used by the instruction sequence. If the first word
is skipped for some reason and the second word is
executed by itself, a NOP is executed instead. This is
necessary for cases when the two-word instruction is
prec ed ed by a co nd i tio na l in str u ct ion t h at c h an ge s the
PC. Example 5-4 shows how this works.
EXAMPLE 5-4: TWO-WORD INSTRUCTIONS
Word Address
LSB = 1LSB = 0
Program Memory
Byte Locations 000000h
000002h
000004h
000006h
Instruction 1: MOVLW 055h 0Fh 55h 000008h
Instruction 2: GOTO 0006h EFh 03h 00000Ah
F0h 00h 00000Ch
Instruction 3: MOVFF 123h, 456h C1h 23h 00000Eh
F4h 56h 000010h
000012h
000014h
Note: See Section 5.6 “PIC18 Instruction
Execution and the Extended Instruc-
tion Set” for information on two-word
instructions in the extended instruction set.
CASE 1:
Object Code Source Code
0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0?
1100 0001 0010 0011 MOVFF REG1, REG2 ; No, skip this word
1111 0100 0101 0110 ; Execute this word as a NOP
0010 0100 0000 0000 ADDWF REG3 ; continue code
CASE 2:
Object Code Source Code
0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0?
1100 0001 0010 0011 MOVFF REG1, REG2 ; Yes, execute this word
1111 0100 0101 0110 ; 2nd word of instruction
0010 0100 0000 0000 ADDWF REG3 ; continue code
2010-2015 Microchip Technology Inc. DS40001303H-page 67
PIC18F2XK20/4XK20
5.3 Data Memory Organization
The data memory in PIC18 dev ices is implemented as
static RAM. Each register in the data memory has a
12-bit address, allowing up to 4096 bytes of data
memory. The memory sp ace is div ided into as many as
16 banks that contain 256 bytes each. Figures 5-5
through 5 -7 show th e data m emory organi zation for th e
PIC18F2XK20/4XK20 devices.
The data memory contains Special Function Registers
(SFRs) and General Purpose Registers (GPRs). The
SFRs are used for control and status of the controller
and per ipheral functio ns, while GP Rs are used for dat a
storage and scratchpad operations in the user’s
applic ation. Any read of an unim plemente d locat ion will
read as ‘0’s.
The instruction set and architecture allow operations
across all banks. The entire data memory may be
accessed by Direct, Indirect or Indexed Addressing
modes. Addressing modes are discussed later in this
subsection.
To ensure that commonly used registers (SFRs and
select GP Rs) c an b e ac cess ed i n a singl e cycle, PI C18
devices implement an Ac ce ss Bank. This is a 256 -by te
memor y space that provid es fa st acc ess to SFRs and
the lower portion of GPR Bank 0 wit hout using the Bank
Select Register (BSR). Section 5.3.2 “Access Bank”
provides a detailed description of the Access RAM.
5.3. 1 BANK S ELECT REGISTER (BSR)
Large areas of data memory require an efficient
addressing scheme to make rapid access to any
address possible. Ideally, this means that an entire
address doe s no t need to be provided for e ach read or
write operation. For PIC18 devices, this is accom-
plished with a RAM banking scheme. This divides the
memory space into 16 contiguous banks of 256 bytes.
Depending on the instruction, each location can be
addressed directly by its full 12-bit address, or an 8-bit
low-order address and a 4-bit Bank Pointer.
Most in struct ions in th e PIC18 instru ction se t make us e
of the Ban k Pointer , known as the Ba nk Select Reg ister
(BSR). This SFR holds the four Most Signif ic ant bits of
a location’s address; the instruction itself includes the
eight Least Significant bits. Only the four lower bits of
the BSR a re i mplem en ted (BSR <3:0 >). T he upp er fo ur
bit s are unused; the y will always read ‘0’ an d cannot be
written to. T he BSR can be l oaded direct ly by using the
MOVLB instruction.
The value of the BSR indicates the bank in data
memory; the eight bits in the instruction show the
location in the bank and can be thought of as an offset
from the bank’s lower boundary. The relationship
betwee n the BSR’ s valu e an d the ba nk div is ion in data
memory is shown in Figures 5-5 through 5-7.
Since up to 16 regis ters m ay share the s ame l ow-order
address, the user must always be careful to ensure that
the proper bank is selected before performing a data
read or write. For example, writing what should be
progra m data to an 8-bit address of F9h while th e BSR
is 0Fh will end up resetting the program counter.
While any bank can be sel ec ted, only those ba nk s th at
are actually implemented can be read or written to.
Writes to unimplemented banks are ignored, while
reads from unimplemented banks will return ‘0’s. Even
so, the STATUS register will still be affected as if the
operation was successful. The data memory maps in
Figures 5-5 through 5-7 indicate which banks are
implemented.
In the core PIC18 instruction set, only the MOVFF
instruction fully specifies the 12-bit address of the
source a nd target reg isters. This i nstruction ig nores the
BSR comple tely when it ex ecutes. All othe r instruction s
include only the low-order address as an operand and
must use either the BSR or the Access Bank to locate
their targ et regis te rs.
Note: The operation of some aspects of data
memory are changed when the PIC18
extended instruction set is enabled. See
Section 5.5 “Data Memory and the
Extended Instruction Set” for more
information.
PIC18F2XK20/4XK20
DS40001303H-page 68 2010-2015 Microchip Technology Inc.
FIGURE 5-5: DATA MEMORY MAP FOR PIC18F23K20/43K20 DEVICES
Bank 0
Bank 1
Bank 14
Bank 15
Data Memory Map
BSR<3:0>
= 0000
= 0001
= 1111
060h
05Fh
F60h
FFFh
00h
5Fh
60h
FFh
Access B ank
When ‘a’ = 0:
The BSR is ignored and the
Access Bank is used.
The first 96 bytes are
general purpose RAM
(from Bank 0).
The second 160 bytes are
Special Function Registers
(from Bank 15).
When ‘a’ = 1:
The BSR spec ifies t he Ban k
used by the instruction.
F5Fh
F00h
EFFh
1FFh
100h
0FFh
000h
Access RAM
FFh
00h
FFh
00h
FFh
00h
GPR
GPR
SFR
Access RAM High
Access RAM Low
Bank 2
= 0110
= 0010
(SFRs)
2FFh
200h
3FFh
300h
4FFh
400h
5FFh
500h
6FFh
600h
7FFh
700h
8FFh
800h
9FFh
900h
AFFh
A00h
BFFh
B00h
CFFh
C00h
DFFh
D00h
E00h
Bank 3
Bank 4
Bank 5
Bank 6
Bank 7
Bank 8
Bank 9
Bank 10
Bank 11
Bank 12
Bank 13
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
= 0011
= 0100
= 0101
= 0111
= 1000
= 1001
= 1010
= 1011
= 1100
= 1101
= 1110
Unused
Read 00h
Unused
2010-2015 Microchip Technology Inc. DS40001303H-page 69
PIC18F2XK20/4XK20
FIGURE 5-6: DATA MEMORY MAP FOR PIC18F24K20/44K20 DEVICES
Bank 0
Bank 1
Bank 14
Bank 15
Data Memory Map
BSR<3:0>
= 0000
= 0001
= 1111
060h
05Fh
F60h
FFFh
00h
5Fh
60h
FFh
Access B ank
When ‘a’ = 0:
The BSR is ignored and the
Access Bank is used.
The first 96 bytes are
general purpose RAM
(from Bank 0).
The second 160 bytes are
Special Function Registers
(from Bank 15).
When ‘a’ = 1:
The BSR spec ifies t he Ban k
used by the instruction.
F5Fh
F00h
EFFh
1FFh
100h
0FFh
000h
Access RAM
FFh
00h
FFh
00h
FFh
00h
GPR
GPR
SFR
Access RAM High
Access RAM Low
Bank 2
= 0110
= 0010
(SFRs)
2FFh
200h
3FFh
300h
4FFh
400h
5FFh
500h
6FFh
600h
7FFh
700h
8FFh
800h
9FFh
900h
AFFh
A00h
BFFh
B00h
CFFh
C00h
DFFh
D00h
E00h
Bank 3
Bank 4
Bank 5
Bank 6
Bank 7
Bank 8
Bank 9
Bank 10
Bank 11
Bank 12
Bank 13
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
GPR
FFh
00h
= 0011
= 0100
= 0101
= 0111
= 1000
= 1001
= 1010
= 1011
= 1100
= 1101
= 1110
Unused
Read 00h
Unused
PIC18F2XK20/4XK20
DS40001303H-page 70 2010-2015 Microchip Technology Inc.
FIGURE 5-7: DATA MEMORY MAP FOR PIC18F25K20/45K20 DEVICES
Bank 0
Bank 1
Bank 14
Bank 15
Data Memory Map
BSR<3:0>
= 0000
= 0001
= 1111
060h
05Fh
F60h
FFFh
00h
5Fh
60h
FFh
Access B ank
When ‘a’ = 0:
The BSR is ignored and the
Access Bank is used.
The first 96 bytes are
general purpose RAM
(from Bank 0).
The second 160 bytes are
Special Function Registers
(from Bank 15).
When ‘a’ = 1:
The BSR spec ifies t he Ban k
used by the instruction.
F5Fh
F00h
EFFh
1FFh
100h
0FFh
000h
Access RAM
FFh
00h
FFh
00h
FFh
00h
GPR
GPR
SFR
Access RAM High
Access RAM Low
Bank 2
= 0110
= 0010
(SFRs)
2FFh
200h
3FFh
300h
4FFh
400h
5FFh
500h
6FFh
600h
7FFh
700h
8FFh
800h
9FFh
900h
AFFh
A00h
BFFh
B00h
CFFh
C00h
DFFh
D00h
E00h
Bank 3
Bank 4
Bank 5
Bank 6
Bank 7
Bank 8
Bank 9
Bank 10
Bank 11
Bank 12
Bank 13
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
GPR
FFh
00h
= 0011
= 0100
= 0101
= 0111
= 1000
= 1001
= 1010
= 1011
= 1100
= 1101
= 1110
Unused
Read 00h
Unused
GPR
GPR
GPR
2010-2015 Microchip Technology Inc. DS40001303H-page 71
PIC18F2XK20/4XK20
FIGURE 5-8: DATA MEMORY MAP FOR PIC18F26K20/46K20 DEVICES
Bank 0
Bank 1
Bank 14
Bank 15
Data Memory Map
BSR<3:0>
= 0000
= 0001
= 1111
060h
05Fh
F60h
FFFh
00h
5Fh
60h
FFh
Access B ank
When ‘a’ = 0:
The BSR is ignored and the
Access Bank is used.
The first 96 bytes are
general purpose RAM
(from Bank 0).
The second 160 bytes are
Special Function Registers
(from Bank 15).
When ‘a’ = 1:
The BSR spec ifies t he Ban k
used by the instruction.
F5Fh
F00h
EFFh
1FFh
100h
0FFh
000h
Access RA M
FFh
00h
FFh
00h
FFh
00h
GPR
GPR
SFR
Access RAM High
Access RAM Low
Bank 2
= 0110
= 0010
(SFRs)
2FFh
200h
3FFh
300h
4FFh
400h
5FFh
500h
6FFh
600h
7FFh
700h
8FFh
800h
9FFh
900h
AFFh
A00h
BFFh
B00h
CFFh
C00h
DFFh
D00h
E00h
Bank 3
Bank 4
Bank 5
Bank 6
Bank 7
Bank 8
Bank 9
Bank 10
Bank 11
Bank 12
Bank 13
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
GPR
FFh
00h
= 0011
= 0100
= 0101
= 0111
= 1000
= 1001
= 1010
= 1011
= 1100
= 1101
= 1110
GPR
GPR
GPR
GPR
GPR
GPR
GPR
GPR
GPR
GPR
GPR
GPR
GPR
PIC18F2XK20/4XK20
DS40001303H-page 72 2010-2015 Microchip Technology Inc.
FIGURE 5-9: USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING)
Note 1: The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to
the registers of the Access Bank.
2: The MOVFF instruction embeds the entire 12-bit address in the instruction.
Data Memory
Bank Select(2)
70
From Opcode(2)
0000
000h
100h
200h
300h
F00h
E00h
FFFh
Bank 0
Bank 1
Bank 2
Bank 14
Bank 15
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
Bank 3
through
Bank 13
0011 11111111
70
BSR(1)
2010-2015 Microchip Technology Inc. DS40001303H-page 73
PIC18F2XK20/4XK20
5.3.2 ACCESS BANK
While the use of the BSR with an embedded 8-bit
address allows users to address the entire range of
data mem ory, it also mean s th at the user must a lways
ensure that the correct bank is selected. Otherwise,
data may be read from or written to the wrong location.
This can be disastrous if a GPR is the intended ta rget
of an operation, but an SFR is written to instead.
Verifying and/or changing the BSR for each read or
write to data memory can become very inefficient.
To streamlin e access for the most com monly used da ta
memory locations, the data memory is configured with
an Access Bank, which allows users to access a
mapped block of memory without specifying a BSR.
The Acc ess Bank con sist s o f the f irst 96 byte s of mem-
ory (00h -5Fh) in Bank 0 and the last 160 byte s of mem-
ory (60h-FFh) in Block 15. The lower half is known as
the “Access RAM” and is composed of GPRs. This
upper half is also where the device’s SFRs are
mapped. These two areas are mapped contiguously in
the Access Bank and can be addressed in a linear
fashion by an 8-bit address (Figures 5-5 through 5-7).
The Access Bank is used by core PIC18 instructions
that include the Access RAM bit (the ‘a’ parameter in
the instruction). When ‘a’ is equal to ‘1’, the inst r uct i on
uses the BSR and the 8-bit address included in the
opcode for the data memory address. When ‘a’ is ‘0’,
however, the instruction is forced to use the Access
Bank address map; the current value of the BSR is
ignored entirely.
Using this “forced” addres sing allows the instruction to
operate on a data address in a single cycle, without
updating the BSR first. For 8-bit addresses of 60h and
above, t his mean s that users can evaluate and opera te
on SFRs more efficiently. The Access RAM below 60h
is a goo d place for da ta values that the user might need
to access rapidly, such as immediate computational
results or common program variables. Access RAM
also allows for faster and more code efficient context
saving and switching of variables.
The mapping of the Access Bank is slightly different
when the extended instruction set is enabled (XINST
Configuration bit = 1). Th is is disc us sed in more deta il
in Section 5.5.3 “Mapping the Access Bank in
Indexed Literal Offset Mode”.
5.3.3 GENERAL PURPOSE REGISTER
FILE
PIC18 devices may have banked memory in the GPR
area. This is data RAM, which is available for use by all
instructions. GPRs start at the bottom of Bank 0
(address 000h) and grow upwards towards the bottom of
the SFR area. GPRs are not initialized by a Power-on
Reset and are unchanged on all other R eset s.
5.3.4 SPECIAL FUNCTION REGISTERS
The Special Function Registers (SFRs) are registers
used by the CPU an d peripheral mod ules for controlling
the desire d operation of the device. These reg isters are
implemented as static RAM. SFRs start at the top of
data m emory (FFFh) and ext end do wnward to occu py
the top portion of Bank 15 (F60h to FFFh). A list of
these registers is given in Table 5-1 and Table 5-2.
The SFRs can be classified into two sets: those
associated with the “core” device functionality (ALU,
Resets and interrupts) and those related to the
peripheral functions. The Reset and interrupt registers
are described in their respective chapters, while the
ALU’s STATUS register is described later in this
section. Registers related to the operation of a
peripheral feature are described in the chapter for that
peripheral.
The SFRs are typically distributed among the
periphera ls w ho se functions th ey c ontr ol. U nus ed SFR
locations are unimplemented and read as ‘0’s.
PIC18F2XK20/4XK20
DS40001303H-page 74 2010-2015 Microchip Technology Inc.
TABLE 5-1: SPECIAL FUNCTION REGISTER M AP FOR PIC18F2 XK20/4 XK20 DEVICE S
Address Name Address Name Address Name Address Name
FFFh TOSU FD7h TMR0H FAFh SPBRG F87h —(2)
FFEh TOSH FD6h TMR0L FAEh RCREG F86h —(2)
FFDh TOSL FD5h T0CON FADh TXREG F85h —(2)
FFCh STKPTR FD4h —(2) FACh TXSTA F84h PORTE
FFBh PCLATU FD3h OSCCON FABh RCSTA F83h PORTD(3)
FFAh PCLATH FD2h HLVDCON FAAh EEADRH(4) F82h PORTC
FF9h PCL FD1h WDTCON FA9h EEADR F81h PORTB
FF8h TBLPTRU FD0h RCON FA8h EEDATA F80h PORTA
FF7h TBLPTRH FCFh TMR1H FA7h EECON2(1) F7Fh ANSELH
FF6h TBLPTRL FCEh TMR1L FA6h EECON1 F7Eh ANSEL
FF5h TABLAT FCDh T1CON FA5h —(2) F7Dh IOCB
FF4h PRODH FCCh TMR2 FA4h —(2) F7Ch WPUB
FF3h PRODL FCBh PR2 FA3h —(2) F7Bh CM1CON0
FF2h INTCON FCAh T2CON FA2h IPR2 F7Ah CM2CON0
FF1h INTCON2 FC9h SSPBUF FA1h PIR2 F79h CM2CON1
FF0h INTCON3 FC8h SSPADD FA0h PIE2 F78h SLRCON
FEFh INDF0(1) FC7h SSPSTAT F9Fh IPR1 F77h SSPMSK
FEEh POSTINC0(1) FC6h SSPCON1 F9Eh PIR1 F76h —(2)
FEDh POSTDEC0(1) FC5h SSPCON2 F9Dh PIE1 F75h —(2)
FECh PREINC0(1) FC4h ADRESH F9Ch —(2) F74h —(2)
FEBh PLUSW0(1) FC3h ADRESL F9Bh OSCTUNE F73h —(2)
FEAh FSR0H FC2h ADCON0 F9Ah —(2) F72h —(2)
FE9h FSR0L FC1h ADCON1 F99h —(2) F71h —(2)
FE8h WREG FC0h ADCON2 F98h —(2) F70h —(2)
FE7h INDF1(1) FBFh CCPR1H F97h —(2) F6Fh —(2)
FE6h POSTINC1(1) FBEh CCPR1L F96h TRISE(3) F6Eh —(2)
FE5h POSTDEC1(1) FBDh CCP1CON F95h TRISD(3) F6Dh —(2)
FE4h PREINC1(1) FBCh CCPR2H F94h TRISC F6Ch —(2)
FE3h PLUSW1(1) FBBh CCPR2L F93h TRISB F6Bh —(2)
FE2h FSR1H FBAh CCP2CON F92h TRISA F6Ah —(2)
FE1h FSR1L FB9h PSTRCON F91h —(2) F69h —(2)
FE0h BSR FB8h BAUDCON F90h —(2) F68h —(2)
FDFh INDF2(1) FB7h PWM1CON F8Fh —(2) F67h —(2)
FDEh POSTINC2(1) FB6h ECCP1AS F8Eh —(2) F66h —(2)
FDDh POSTDEC2(1) FB5h CVRCON F8Dh LATE(3) F65h —(2)
FDCh PREINC2(1) FB4h CVRCON2 F8Ch LATD(3) F64h —(2)
FDBh PLUSW2(1) FB3h TMR3H F8Bh LATC F63h —(2)
FDAh FSR2H FB2h TMR3L F8Ah LATB F62h —(2)
FD9h FSR2L FB1h T3CON F89h LATA F61h —(2)
FD8h STATUS FB0h SPBRGH F88h —(2) F60h —(2)
Note 1: This is not a physical register.
2: Unimplemented re gisters are read as ‘0’.
3: This register is not available on PIC18F2XK20 devices.
4: This regi ster is only implemented in th e PIC18F46K20 and PIC18F26K20 devices.
2010-2015 Microchip Technology Inc. DS40001303H-page 75
PIC18F2XK20/4XK20
TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2XK20/4XK20)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR Details
on page:
TOSU — — — Top-of-Stack Upper Byte (TOS<20:16>) ---0 0000 56, 62
TOSH Top-of-Stack, High Byte (TOS<15:8>) 0000 0000 56, 62
TOSL Top-of-Stack, Low Byte (TOS<7:0>) 0000 0000 56, 62
STKPTR STKFUL STKUNF — SP4 SP3 SP2 SP1 SP0 00-0 0000 56, 63
PCLATU — — — Hold i ng Regi st er for PC<20: 16> ---0 0000 56, 62
PCLATH Holding R egist er for PC< 15: 8> 0000 0000 56, 62
PCL PC, Low Byte (PC<7:0>) 0000 0000 56, 62
TBLPTRU —— bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) --00 0000 56, 87
TBLPTRH Program Memory Table Pointer, High Byte (TBLPTR<15:8>) 0000 0000 56, 87
TBLPTRL Program Memory Table Pointer, Low Byte (TBLPTR<7:0>) 0000 0000 56, 87
TABLAT Program Memory Table Latch 0000 0000 56, 87
PRODH Product Register, High Byte xxxx xxxx 56, 98
PRODL Product Register, Low Byte xxxx xxxx 56, 98
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 56, 102
INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 —TMR0IP—RBIP1111 -1-1 56, 103
INTCON3 INT2IP INT1IP —INT2IEINT1IE— INT2IF INT1IF 11-0 0-00 56, 104
INDF0 Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register) N/A 56, 80
POSTINC0 Uses co ntents of FSR0 to address data memory – val ue of FSR0 post-incremented (not a physical regis ter) N/A 56, 80
POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register) N/A 56, 80
PREINC0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) N/A 56, 80
PLUSW0 Uses contents of FSR0 to address data memory – value of FSR0 offset by W (not a physical register) – N/A 56, 80
FSR0H ———— Indirect Data Memory Address Pointer 0, High Byte ---- 0000 56, 80
FSR0L Indirect Data Memory Address Pointer 0, Low Byte xxxx xxxx 56, 80
WREG Working Regist er xxxx xxxx 56
INDF1 Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register) N/A 56, 80
POSTINC1 Uses co ntents of FSR1 to address data memory – val ue of FSR1 post-incremented (not a physical regis ter) N/A 56, 80
POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register) N/A 56, 80
PREINC1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) N/A 56, 80
PLUSW1 Uses contents of FSR1 to address data memory – value of FSR1 offset by W (not a physical register) – value of N/A 56, 80
FSR1H ———— Indirect Data Memory Address Pointer 1, High Byte ---- 0000 57, 80
FSR1L Indirect Data Memory Address Pointer 1, Low Byte xxxx xxxx 57, 80
BSR ———— Bank Select Register ---- 0000 57, 67
INDF2 Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register) N/A 57, 80
POSTINC2 Uses co ntents of FSR2 to address data memory – val ue of FSR2 post-incremented (not a physical regis ter) N/A 57, 80
POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register) N/A 57, 80
PREINC2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) N/A 57, 80
PLUSW2 Uses contents of FSR2 to address data memory – value of FSR2 offset by W (not a physical register) – value of N/A 57, 80
FSR2H ———— Indirect Data Memory Address Pointer 2, High Byte ---- 0000 57, 80
FSR2L Indirect Data Memory Address Pointer 2, Low Byte xxxx xxxx 57, 80
STATUS — — —NOVZDCC---x xxxx 57, 78
Legend: x = unknown , u = unchanged, — = unimplemented, q = value depends on condition
Note 1: The SBOREN bit is only available when the BOREN<1:0> Configuration bits = 01; otherwise it is disabled and reads as ‘0’. See
Section 4 .4 “Brown-out Reset (BOR)”.
2: These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices;
individual unimplemented bits should be interpreted as ‘-’.
3: The PLLEN bit is only available in specific oscillator configuration; otherwise it is disabled and reads as ‘0’. See Section 2.6.2 “PLL in
HFINTOSC Modes”.
4: The RE3 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit = 0). Otherwise, RE3 reads as ‘0’. This bit is
read-only.
5: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes.
When disabled, these bits read as ‘0’.
6: All bits of the ANSELH register initialize to ‘0’ if the PBADEN bit of CONFIG3H is ‘0’.
7: This register is only implemented in the PIC18F46K20 and PIC18F26K20 devices.
PIC18F2XK20/4XK20
DS40001303H-page 76 2010-2015 Microchip Technology Inc.
TMR0H Timer0 Register, High Byte 0000 0000 57, 147
TMR0L Timer0 Register, Low Byte xxxx xxxx 57, 147
T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 1111 1111 57, 145
OSCCON IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0 0011 qq00 28, 57
HLVDCON VDIRMAG — IRVST HLVDEN HLVDL3 HLVDL2 HLVDL1 HLVDL0 0-00 0101 57, 276
WDTCON — — — — — — —SWDTEN--- ---0 57, 291
RCON IPEN SBOREN(1) —RITO PD POR BOR 0q-1 11q0 48, 55,
111
TMR1H Timer1 Register, High Byte xxxx xxxx 57, 154
TMR1L Timer1 Register, Low Bytes xxxx xxxx 57, 154
T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 57, 148
TMR2 Timer2 Register 0000 0000 57, 156
PR2 Timer2 Period Register 1111 1111 57, 156
T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 57, 155
SSPBUF SSP Receive Buffer/Transmit Register xxxx xxxx 57, 188,
189
SSPADD SSP Address Register in I2C™ Slave Mode. SSP Baud Rate Reload Register in I2C Master Mode. 0000 0000 57, 189
SSPSTAT SMP CKE D/A PSR/WUA BF 0000 0000 57, 181,
191
SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 57, 182,
192
SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 57, 193
ADRESH A/D Result Register, High Byte xxxx xxxx 58, 261
ADRESL A/D Result Register, Low Byte xxxx xxxx 58, 261
ADCON0 —— CHS3 CHS2 CHS1 CHS0 GO/DONE ADON --00 0000 58, 255
ADCON1 ——VCFG1VCFG0— — — — --00 ---- 59, 256
ADCON2 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 0-00 0000 58, 257
CCPR1 H Cap tur e/C o mpar e/PW M Regi s ter 1, Hig h Byt e xxxx xxxx 58, 135
CCPR1 L Capture/Compare/P WM R egis ter 1, Low Byt e xxxx xxxx 58, 135
CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 58, 161
CCPR2 H Cap tur e/C o mpar e/PW M Regi s ter 2, Hig h Byt e xxxx xxxx 58, 135
CCPR2 L Capture/Compare/P WM R egis ter 2, Low Byt e xxxx xxxx 58, 135
CCP2CON —— DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 58, 134
PSTRCON — — — STRSYNC STRD STRC STRB STRA ---0 0001 58, 175
BAUDCON ABDOVF RCIDL DTRXP CKTXP BRG16 — WUE ABDEN 0100 0-00 58, 233
PWM1CON PRSEN PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 0000 0000 58, 174
ECCP1AS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 0000 0000 58, 171
CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 0000 0000 58, 274
CVRCON2 FVREN FVRST ——————00-- ---- 58, 275
TMR3H Timer3 Register, High Byte xxxx xxxx 58, 160
TMR3L Timer3 Register, Low Byte xxxx xxxx 58, 160
T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 58, 157
TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2XK20/4XK20) (CONTINUED)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR Details
on page:
Legend: x = unknown , u = unchanged, — = unimplemented, q = value depends on condition
Note 1: The SBOREN bit is only available when the BOREN<1:0> Configuration bits = 01; otherwise it is disabled and reads as ‘0’. See
Section 4 .4 “Brown-out Reset (BOR)”.
2: These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices;
individual unimplemented bits should be interpreted as ‘-’.
3: The PLLEN bit is only available in specific oscillator configuration; otherwise it is disabled and reads as ‘0’. See Section 2.6.2 “PLL in
HFINTOSC Modes”.
4: The RE3 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit = 0). Otherwise, RE3 reads as ‘0’. This bit is
read-only.
5: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes.
When disabled, these bits read as ‘0’.
6: All bits of the ANSELH register initialize to ‘0’ if the PBADEN bit of CONFIG3H is ‘0’.
7: This register is only implemented in the PIC18F46K20 and PIC18F26K20 devices.
2010-2015 Microchip Technology Inc. DS40001303H-page 77
PIC18F2XK20/4XK20
SPBRGH EUSART Baud Rate Generator Register, High Byte 0000 0000 58, 226
SPBRG EUSART Baud Rate Generator Register, Low Byte 0000 0000 58, 226
RCREG EUSART Receive Register 0000 0000 58, 223
TXREG EUSART Transmit Register 0000 0000 58, 222
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 58, 231
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 58, 232
EEADR EEADR7 EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 0000 0000 58, 85, 93
EEADRH(7) —————— EEADR9 EEADR8 ---- --00 58, 85, 93
EEDATA EEPROM Data Register 0000 0000 58, 85, 93
EECON2 EEPROM Control Register 2 (not a physical register) 0000 0000 58, 85, 93
EECON1 EEPGD CFGS — FREE WRERR WREN WR RD xx-0 x000 58, 86, 93
IPR2 OSCFIP C1IP C2IP EEIP BCLIP HLVDIP TMR3IP CCP2IP 1111 1111 59, 110
PIR2 OSCFIF C1IF C2IF EEIF BCLIF HLVDIF TMR3IF CCP2IF 0000 0000 59, 106
PIE2 OSCFIE C1IE C2IE EEIE BCLIE HLVDIE TMR3IE CCP2IE 0000 0000 59, 108
IPR1 PSPIP(2) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 59, 109
PIR1 PSPIF(2) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 59, 105
PIE1 PSPIE(2) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 59, 107
OSCTUNE INTSRC PLLEN(3) TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 0q00 0000 32, 59
TRISE(2) IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 0000 -111 59, 126
TRISD(2) PORTD Data Direction Control Register 1111 1111 59, 122
TRISC PORTC Data Direction Control Register 1111 1111 59, 119
TRISB PORTB Data Direction Control Register 1111 1111 59, 116
TRISA TRISA7(5) TRISA6(5) Data Direction Control Register for PORTA 1111 1111 59, 113
LATE(2) ————— PORTE Data Latch Register
(Read and Write to Data Latch) ---- -xxx 59, 125
LATD(2) PORTD Data Latch Register (Read and Write to Data Latch) xxxx xxxx 59, 122
LATC PORTC Data Latch R egister (Read and Write to Data Latch) xxxx xxxx 59, 119
LATB PORTB Data Latch Register (Read and Write to Data Latch) xxxx xxxx 59, 116
LATA LATA7(5) LATA6(5) PORTA Data Latch Register (Read and Write to Data Latch) xxxx xxxx 59, 113
PORTE ————RE3
(4) RE2(2) RE1(2) RE0(2) ---- x000 59, 125
PORTD(2) RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx 59, 122
PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx 59, 119
PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxx0 0000 59, 116
PORTA RA7(5) RA6(5) RA5 RA4 RA3 RA2 RA1 RA0 xx0x 0000 59, 113
ANSELH(6) — — — ANS12 ANS11 ANS10 ANS9 ANS8 ---1 1111 59, 129
ANSEL ANS7(2) ANS6(2) ANS5(2) ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 59, 128
IOCB IOCB7 IOCB6 IOCB5 IOCB4 — — — — 0000 ---- 59, 116
WPUB WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 1111 1111 59, 116
CM1CON0 C1ON C1OUT C1OE C1POL C1SP C1R C1CH1 C1CH0 0000 0000 59, 267
CM2CON0 C2ON C2OUT C2OE C2POL C2SP C2R C2CH1 C2CH0 0000 0000 59, 268
CM2CON1 MC1OUT MC2OUT C1RSEL C2RSEL — — — — 0000 ---- 60, 270
SLRCON — — —SLRE
(2) SLRD(2) SLRC SLRB SLRA ---1 1111 60, 130
SSPMSK MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0 1111 1111 60, 200
TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2XK20/4XK20) (CONTINUED)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR Details
on page:
Legend: x = unknown , u = unchanged, — = unimplemented, q = value depends on condition
Note 1: The SBOREN bit is only available when the BOREN<1:0> Configuration bits = 01; otherwise it is disabled and reads as ‘0’. See
Section 4 .4 “Brown-out Reset (BOR)”.
2: These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices;
individual unimplemented bits should be interpreted as ‘-’.
3: The PLLEN bit is only available in specific oscillator configuration; otherwise it is disabled and reads as ‘0’. See Section 2.6.2 “PLL in
HFINTOSC Modes”.
4: The RE3 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit = 0). Otherwise, RE3 reads as ‘0’. This bit is
read-only.
5: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes.
When disabled, these bits read as ‘0’.
6: All bits of the ANSELH register initialize to ‘0’ if the PBADEN bit of CONFIG3H is ‘0’.
7: This register is only implemented in the PIC18F46K20 and PIC18F26K20 devices.
PIC18F2XK20/4XK20
DS40001303H-page 78 2010-2015 Microchip Technology Inc.
5.3.5 STATUS REGISTER
The STATUS register, shown in Register 5-2, contains
the arithmetic status of the ALU. As with any other SFR,
it can be the operan d for any instruction.
If the STATUS register is the destination for an
instruction that affects the Z, DC, C, OV or N bits, the
results of the instruction are not written; instead, the
STATUS register is updated according to the
instruction performed. Therefore, the result of an
instruction with the STATUS register as its destination
may be different than intended. As an example, CLRF
STATUS will set the Z bit and leave the remaining
Status bits unchanged (‘000u u1uu’).
It is recommended that only BCF, BSF, SWAPF, MOVFF
and MOVWF instructions are used to alter the STATUS
register, because thes e ins tructi ons d o not af fect t he Z,
C, DC, OV or N bits in the STATUS register.
For other i ns truc tions that do not affect Status bi t s , se e
the instruction set summaries in Table 24-2 and
Table 24-3.
Note: The C and DC bits operate as the borrow
and digit borrow bits, respectively, in
subtraction.
REGISTER 5-2: STATUS: STAT US REGIS TER
U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x
— — — NOV ZDC
(1) C(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-5 Unimplemented: Read as ‘0’
bit 4 N: Negative bit
This bit is used for sign ed arith metic (two’ s co mplem ent). It i ndica tes w hether t he resu lt was negat ive
(ALU MSB = 1).
1 = Result was neg at ive
0 = Result was positive
bit 3 OV: Overflow bit
This bit is used for signed arithmetic (two’s complement). It indicates an overflow of the 7-bit magni-
tude which causes the sign bit (bit 7 of the result) to change state.
1 = Overflow occurred for signed arithmetic (in this arithmetic operation)
0 = No overflow occurred
bit 2 Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1 DC: Digit Carry/Bo rrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)(1)
1 = A carry-out from the 4th low-order bit of the result occurred
0 = No carry-out from the 4th low-order bit of the result
bit 0 C: Carry/Borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1)
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the
second operand. For rot ate (RRF, RLF) instru ctions, this bit is loaded with either the high-orde r or low-o rder
bit of the source register.
2010-2015 Microchip Technology Inc. DS40001303H-page 79
PIC18F2XK20/4XK20
5.4 Data Addressing Modes
While the program memory can be addressed in only
one way – through the program counter – information
in the da ta m emory sp ace can be addr ess ed in severa l
ways. For most instructions, the addressing mode is
fixed. Other instructions may use up to three modes,
dependi ng on whic h operands are us ed and whe ther or
not the extended instruction set is enabled.
The addres sing modes are:
• Inherent
• Literal
•Direct
•Indirect
An additional addressing mode, Indexed Literal Offset,
is available when the extended instruction set is
enabled (XINST Configuration bit = 1). Its operation is
discussed in greater detail in Section 5.5.1 “Indexed
Addressing with Literal Offset”.
5.4.1 INHERENT AND LITERAL
ADDRESSING
Many PIC18 c ontrol in stru ctions do no t need any arg u-
ment at all; they either perform an operation that glob-
ally affects the device or they operate implicitly on one
register. This addressing mode is known as Inherent
Addressi ng. Examples include SLEEP, RESET and DAW.
Other instructions work in a similar way but require an
additional explicit argument in the opcode. This is
known as Literal Addressing mode because they
require some literal value as an argument. Examples
include ADDLW and MOVLW, which respectively, add or
move a literal value to the W register. Other examples
include CALL and GOTO, which include a 20-bit
program memory address.
5.4.2 DIRECT ADDRESSING
Direct addressing specifies all or part of the source
and/or destination address of the operation within the
opcode itself. The options are specified by the
arguments accompanying the instruction.
In the co re PIC1 8 inst ruction se t, bit-ori ented and by te-
oriented instructions use some version of direct
addressing by default. All of these instructions include
some 8-bit literal address as their Least Significant
Byte. This address specifies either a register add ress in
one o f the banks of d ata RAM ( Section 5.3.3 “G eneral
Purpose Register File”) or a location in the Access
Bank (Section 5.3.2 “Access Bank”) as the data
source for the instruction.
The Acc ess RA M bit ‘a’ determin es ho w the address is
interpreted. When ‘a’ is ‘1’, the contents of the BSR
(Section 5.3.1 “Bank Select Register (BSR)”) are
used with the addres s to determ ine the com plete 12-b it
addr ess of t he regis ter. W hen ‘a’ is ‘0’, the address is
interpreted as being a register in the Access Bank.
Addressing that uses the Access RAM is sometimes
also known as Direct Forced Addressing mode.
A few instructions, such as MOVFF, include the entire
12-bit address (either source or destination) in their
opcodes. In these cases, the BSR is ignored entirely.
The destin ation of the ope ration’ s result s is determine d
by the destination bit ‘d’. Wh en ‘d ’ is ‘1’, the results are
stor ed ba ck in th e s o ur c e re g is ter, overw rit i n g i ts or i gi-
nal contents. When ‘d’ is ‘0’, the results are stored in
the W register. Instructions without the ‘d’ argument
have a dest ination that is implic it in the inst ruction; their
destination is either the target register being operated
on or the W register.
5.4.3 INDIRECT ADDRESSING
Indirect addressing a llows the use r to access a location
in data memory without giving a fixed address in the
instruction. This is done by using File Select Registers
(FSRs) as pointers to the loca tions which are to be read
or written. Since the FSRs are themselves located in
RAM as Special File Registers, they can also be
directly manipulated under program control. This
makes FSRs very useful in implementing data
structures, such as tables and arrays in data memory.
The registers for indirect addressing are also
implemented with Indirect File Operands (INDFs) that
permit aut omati c mani pulati on of the poi nter val ue wi th
auto-incrementing, auto-decrementing or offsetting
with a not her value. This allows for ef fi ci ent code, usin g
loops, such as the example of clearing an entire RAM
bank in Example 5-5.
EXAMPLE 5-5: HOW TO CLEAR RAM
(BANK 1) USING
INDIRECT ADDRESSING
Note: The execution of some instructions in the
core PIC18 instruction set are changed
when the PIC18 extended instruction set is
enabled. See Section 5.5 “Data Memory
and the Extended Instruction Set” for
more information.
LFSR FSR0, 100h ;
NEXT CLRF POSTINC0 ; Clear INDF
; register then
; inc pointer
BTFSS FSR0H, 1 ; All done with
; Bank1?
BRA NEXT ; NO, clear next
CONTINUE ; YES, continue
PIC18F2XK20/4XK20
DS40001303H-page 80 2010-2015 Microchip Technology Inc.
5.4.3.1 FSR Register s and the INDF
Operand
At the core of indirect addressing are three sets of
registers: FSR0, FSR1 and FSR2. Each represents a
pair of 8-bit registers, FSRnH and FSRnL. Each FSR
pair holds a 12-bit value, therefore the four upper bits
of the FSRnH register are not used. The 12-bit FSR
value c an ad dress the ent ire rang e o f the da ta memo ry
in a linear fashion. The FSR register pairs, then, serve
as pointers to data memory locations.
Indirect addressing is accomplished with a set of
Indirect File Operands, INDF0 through INDF2. These
can be thought of as “virtual” registers: they are
mapped in the SFR space but are not physically
implemented. Reading or writing to a particular INDF
register actually accesses its corresponding FSR
register pair. A read from INDF1, for example, reads
the data at the address indicated by FSR1H:FSR1L.
Instructions that use the INDF registers as operands
actually use the contents of their corresponding FSR a s
a pointer to the instruction’s target. The INDF operand
is ju st a convenient way of using th e pointer.
Because indi rect ad dre ssing us es a full 1 2-bit a ddress ,
data RAM banking is not necessary. Thus, the current
contents of the BSR and the Access RAM bit have no
effect on determining the target address.
5.4.3.2 FSR Regi s ters and PO ST I NC,
POSTDEC, PREINC and PLUSW
In additi on to the INDF o perand, each F SR register p air
also has four additional indirect operands. Like INDF,
these are “virtual” registers which cannot be directly
read or written. Accessing these registers actually
accesses the location to which the associated FSR
register pair point s, and al so pe rform s a s pe ci fic ac tio n
on the FSR value. They are:
• POSTDEC: accesses the location to which the
FSR point s , then auto ma tic al ly dec rem en t s the
FSR by 1 afterwa r ds
• POSTINC: acc es se s the loc ati on to which the
FSR point s , then auto ma tic al ly inc rem en ts the
FSR by 1 afterwa r ds
• PREINC: auto ma tic al ly inc r em en t s the FSR by 1,
then uses the location to which the FSR points in
the operation
• PLUSW: adds the signed value of the W register
(range o f -127 to 128) t o that of th e FSR and uses
the location to which the result points in the
operation.
In this context, accessing an INDF register uses the
value in the associated FSR register without changing
it. Similarly, accessing a PLUSW register gives the
FSR value an offset by tha t in the W re gis ter ; however,
neither W nor the FSR is actually changed in the
operation. Accessing the other virtual registers
changes the value of the FSR register.
FIGURE 5-10: INDIR ECT ADDRESSI NG
FSR1H:FSR1L
0
7
Data Memory
000h
100h
200h
300h
F00h
E00h
FFFh
Bank 0
Bank 1
Bank 2
Bank 14
Bank 15
Bank 3
through
Bank 13
ADDWF, INDF1, 1
07
Using an instruction with one of the
indirect addressing register s as the
operand....
...uses the 12-bit address stored in
the FSR pair associated with that
register....
...to determine the data memory
location to be used in that operation.
In this case, the FSR1 pair contains
ECCh. This means the contents of
location ECCh will be added t o that
of the W register and stored back in
ECCh.
xxxx1110 11001100
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PIC18F2XK20/4XK20
Operations on the FSRs with POSTDEC, POSTINC
and PREINC affect the entire register pair; that is, roll-
overs of the FSR nL registe r from FFh to 00h carry over
to the FSRnH register. On the other hand, results of
these operations do not change the value of any flags
in the STATUS register (e.g., Z, N, OV, etc.).
The PLUSW register can be used to implement a form
of indexed addressing in the data memory space. By
manipulating the value in the W register, users can
reach addresses that are fixed offsets from pointer
addresses. In some applications, this can be used to
implement some powerful program control structure,
such as software stacks, inside of data memory.
5.4.3.3 Operations by FSRs on FSRs
Indirect addressing operations that target other FSRs
or virtual registers represent special cases. For
example, using an FSR to point to one of the virtual
registers will not result in successful operations. As a
specific case, assume that FSR0H:FSR0L contains
FE7h, the address of INDF1. Attempts to read the
value of the INDF1 using INDF0 as an operand will
return 00h. Attempts to write to INDF1 using INDF0 as
the operand will result in a NOP.
On the other hand, u sing the virtu al reg isters to wr ite to
an F SR p air may n ot oc cur as plan ned. I n t hese cases ,
the val ue will be w ritten to the FSR p air bu t withou t any
incrementing or decrementing. Thus, writing to either
the INDF2 or POSTDEC2 register will write the same
value to the FSR2H:FSR2L.
Since the FSRs are physical registers mapped in the
SFR space, they can be manipulated through all direct
operations. Users should proceed cautiously when
working on these registers, particularly if their code
uses indirect addressing.
Similarly , operations by indirect addressing are generally
permit ted on al l other SFRs. Use rs should exercise the
appropriate cautio n that they do not inadvert ently change
settin gs that might affect t he op era ti on of the devic e.
5.5 Data Memory and the Extended
Instruction Set
Enabling the PIC18 extended instruction set (XINST
Configuration bit = 1) significantly changes certain
aspects of data memory and its addressing. Specifi-
cally, the use of the Access Bank for many of the core
PIC18 instructions is different; this is due to the intro-
duct ion of a new addressing mode fo r the data memory
space.
What doe s not chan ge is ju st as im po rtant. The size of
the data memory space is unchanged, as well as its
linear addressing. The SFR map remains the same.
Core PIC18 instructions can still operate in both Direct
and Indirect Addressing mode; inherent and literal
instructions do not change at all. Indirect addressing
with FSR0 and FSR1 also remain unchanged.
5.5.1 INDEXED ADDRESSING WITH
LITERAL OFFSET
Enabling the PIC18 extended instruction set changes
the behavior of indirect addressing using the FSR2
register pair within Access RAM. Under the proper
conditi ons, instruct ions that use th e Access Ban k – that
is, most bit-oriented and byte-oriented instructions –
can invoke a form of indexed addressing using an
offset specified in the instruction. This special
address ing mod e is kn own as I ndexed Ad dressing with
Literal Offset, or Indexed Literal Offset mode.
When using the extended instruction set, this
addressing mode requires the following:
• The use o f the Ac c ess Ban k i s fo rced (‘a ’ = 0) an d
• The f ile ad dres s arg um ent is less than o r e qua l to
5Fh.
Under these conditions, the file address of the
instruction is not interpreted as the lower byte of an
address (used with the BSR in direct addres sing), or as
an 8- bit address i n the Acc ess Bank. In stead, the value
is interpreted as an offset value to an Address Pointer,
specified by FSR2. The offset and the contents of
FSR2 are added to obtain the target address of the
operation.
5.5.2 INSTRUCTIONS AFFECTED BY
INDEXED LITERAL OFFSET MODE
Any of the core PIC18 instructions that can use direct
addressing are potentially affected by the Indexed
Literal Offset Addressing mode. This includes all
byte-oriented and bit-oriented instructions, or almost
one-half of the standard PIC18 instruction set.
Instruct ions that only use Inherent or Literal Addressin g
modes are una ffected.
Additionally, byte-oriented and bit-oriented instructions
are not affected if they do not use the Access Bank
(Access RAM bit is ‘1’), or inc lud e a fi le address of 60h
or above. Instructions meeting these criteria will
continue to execute as before. A comparison of the
different possible addressing modes when the
extended instruction set is enabled is shown in
Figure 5-11.
Those who desire to use byte-oriented or bit-oriented
instructions in the Indexed Literal Offset mode should
note the changes to assembler syntax for this mode.
This is described in more detail in Section 24.2.1
“Extended Instruction Syntax”.
PIC18F2XK20/4XK20
DS40001303H-page 82 2010-2015 Microchip Technology Inc.
FIGURE 5-11: COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND
BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED)
EXAMPLE INSTRUCTION: ADDWF, f, d, a (Opcode: 0010 01da ffff ffff)
When ‘a’ = 0 and f 60h:
The instruction executes in
Direct Forced mode. ‘f’ is inter-
preted as a location in the
Access RAM between 060h
and 0FFh. Th is is th e sam e as
locations F60h to FFFh
(Bank 15) of data memory.
Locations below 60h are not
available in this addressing
mode.
When ‘a’ = 0 and f5Fh:
The instruction executes in
Indexed Literal Offset mode. ‘f’
is interpre ted as an offset to the
address value in FSR2. The
two are added together to
obtain the address of the target
register for the instruction. The
address can be anywhere in
the data memory space.
Note that in this mode, the
correct syn tax is now:
ADDWF [k], d
where ‘k’ is the same as ‘f’.
When ‘a’ = 1 (all values of f):
The instruction executes in
Direct mode (also known as
Direct Long mode). ‘f’ is inter-
preted as a location in one of
the 16 banks of the data
memory space. The bank is
design ated by the Bank Sel ect
Register (BSR). The address
can be in any implemented
bank in the data memory
space.
000h
060h
100h
F00h
F60h
FFFh
Valid range
00h
60h
FFh
Data Memory
Access RAM
Bank 0
Bank 1
through
Bank 14
Bank 15
SFRs
000h
060h
100h
F00h
F60h
FFFh Data Memory
Bank 0
Bank 1
through
Bank 14
Bank 15
SFRs
FSR2H FSR2L
ffffffff001001da
ffffffff001001da
000h
060h
100h
F00h
F60h
FFFh Data Memory
Bank 0
Bank 1
through
Bank 14
Bank 15
SFRs
for ‘f’
BSR
00000000
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PIC18F2XK20/4XK20
5.5.3 MAPPING THE ACCESS BANK IN
INDEXED LITERAL OFFSET MODE
The use of Indexed Literal Offset Addressing mode
effe ctively chan ges how the first 96 location s of Access
RAM (0 0h to 5Fh ) are mapped. Rather than contai nin g
just the contents of the bottom section of Bank 0, this
mode ma p s the co nte nts from a user define d “window”
that can be located anywhere in the data memory
space. The value of FSR2 establishes the lower bound-
ary of the addresses mapped int o the window , while the
upper boundary is defined by FSR2 plus 95 (5Fh).
Addresse s in the Acces s RAM above 5Fh are mapped
as previously described (see Section 5.3.2 “Access
Bank”). An example of Acc ess Bank rem appin g in this
addressing mode is shown in Figure 5-12.
Remapping of the Access Bank applies only to
operations using the Indexed Literal Offset mode.
Operations that use the BSR (Access RAM bit is ‘1’) will
continue to use direct addressing as before.
5.6 PIC18 Instruction Executi on and
the Extended Instruction Set
Enabling the extended instruction set adds eight
additional commands to the existing PIC18 instruction
set. These instructions are executed as described in
Section 24.2 “Extended Instruction Set”.
FIGURE 5-12: REMAPPING THE ACCESS BANK WITH INDEXED LITERAL OFFSET
ADDRESSING
Data Memory
000h
100h
200h
F60h
F00h
FFFh
Bank 1
Bank 15
Bank 2
through
Bank 14
SFRs
ADDWF f, d, a
FSR2H:FSR2L = 120h
Locations in the region
from the FSR2 pointer
(120h) to the pointer plus
05Fh (17Fh) are mapped
to the bottom of the
Access RAM (000h-05Fh).
Special File Registers at
F60h through FFFh are
mapped to 60h through
FFh, as usual.
Bank 0 addresses below
5Fh can still be addressed
by using the BSR. Access Bank
00h
60h
FFh
SFRs
Bank 1 “Window”
Bank 0
Window
Example Situation:
120h
17Fh
5Fh
Bank 1
PIC18F2XK20/4XK20
DS40001303H-page 84 2010-2015 Microchip Technology Inc.
6.0 FLASH PROGRAM MEMORY
The Flash program memory is readable, writable and
erasable during normal operation over the entire VDD
range.
A read from program memory is executed one byte at
a time. A write to program memory is executed on
blocks of 64, 32 or 16 byt es at a time, depend ing on the
specific device (See Table 6-1). Program memory is
erased in blocks of 64 bytes at a time. The difference
between the write and erase block sizes requires from
1 to 4 block writes to restore the contents of a single
block erase. A bulk erase operation cannot be issued
from user code.
TABLE 6-1: WRITE/ERASE BLOCK SIZES
Writing or erasing program memory will cease
instruction fetches until the operation is complete. The
program memory cannot be accessed during the write
or erase, therefore, code cannot execute. An internal
programming timer terminates program memory writes
and erases.
A value written to program memory does not need to be
a valid instruction. Executing a program memory
location that forms an invalid instruction results in a
NOP.
6.1 Table Reads and Table Writes
In order to read and write program memory, there are
two operations that allow the processor to move bytes
between the program memory space and the data RAM:
• Table Read (TBLRD)
• Table Write (TBLWT)
The program memory space is 16 bits wide, while the
data RAM space is eight bits wide. Table reads and
table writes move data between these two memory
spaces through an 8-bit register (TABLAT).
The table read operation retrieves one byte of data
directly from program memory and places it into the
TABLAT register. Figure 6-1 shows the operation of a
tabl e read.
The table write operation stores one byte of data from the
TABLAT register into a write block holding register. The
procedure to write the contents of the holding registers
into program memory is detailed in Section 6.5 “W riting
to Flash Program Memory”. Figure 6-2 shows the
operation of a table write with program memory and data
RAM.
Table operations work with byte entities. Tables
containing data, rather than program instructions, are
not required to be word aligned. Therefore, a table can
start and end at any byte address. If a table write is being
used to write executable code into program memory,
program instructions will need to be word aligned.
FIGURE 6-1: TABLE R EAD OPER ATION
Device Write Block
Size (bytes) Erase Block
Size (b ytes)
PIC18F43K20,
PIC18F23K20 16 64
PIC18F24K20,
PIC18F25K20,
PIC18F44K20,
PIC18F45K20
32 64
PIC18F26K20,
PIC18F46K20 64 64
Ta ble Pointer(1) Table Latch (8-bit)
Program Memory
TBLPTRH TBLPTRL TABLAT
TBLPTRU
Instruction: TBLRD*
Note 1: Table Pointer register points to a byte in program memory.
Program Memory
(TBLPTR)
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PIC18F2XK20/4XK20
FIGURE 6-2: TABLE WRITE OPERATION
6.2 Control Registers
Several control registers are used in conjunction with
the TBLRD and TBLWT instructions. These include the:
• EECON1 register
• EECON2 register
• TABLAT register
• TBLPTR registers
6.2.1 EECON1 AND EECON2 REGISTERS
The EECON1 register (Register 6-1) is the control
register for memory acce sses. The EECON2 register is
not a physical register; it is used exclusively in the
memory write and erase sequences. Reading
EECON2 will read all ‘0’s.
The EEPGD control bit determi nes if th e access will be
a program or data EEPROM memory access. When
EEPGD is clear, any subsequent operations will
operate on the data EEPROM memory. When EEPGD
is set, any subsequent operations will operate on the
program memory .
The CFGS control bit determines if the access will be
to the Co nfigur ation/Ca librati on regis ter s or to pro gram
memory/data EEPROM memory. When CFGS is set,
subsequent operations will operate on Configuration
registers regardless of EEPGD (see Section 23.0
“Special Features of the CPU”). When CF GS is clear ,
memory selection access is determined by EEPGD.
The FREE bit allows the program memory erase
operation. When FREE is set, an erase operation is
initiated on the next WR command. When FREE is
clear, only writes are enabled.
The WREN bit, when set, will allow a write operation.
The WREN bit is clear on power-up.
The WRERR bit is set by hard ware w he n the WR bit i s
set and cleared when the internal programming timer
expires and the write operation is complete.
The WR control bit initiates write operations. The WR
bit cannot be cleared, only set, by firmware. Then WR
bit is cleared b y hardw are at the complet ion of the write
operation.
Table Pointer(1) Table Latch (8-bit)
TBLPTRH TBLPTRL TABLAT
Program Memory
(TBLPTR<MSBs>)
TBLPTRU
Instruction: TBLWT*
Note 1: During table writes the Table Pointer does not point directly to Program Memory. The LSBs of TBLPRTL
actually point to an address within the write block holding registers. The MSBs of the Table Pointer deter-
mine where the write block will eventually be written. The process for writing the holding registers to t he
program memory array is discussed in Section 6.5 “Writing to Flash Program Memory”.
Holding Registers
Program Memory
Note: During normal operation, the WRERR is
read as ‘1’. This can indicate that a write
operation was prematurely terminated by
a Reset, or a write operation was
attempted improperly.
Note: The EEIF interrupt flag bit of the PIR2
register is set when the write is complete.
The EEIF flag stays set until cleared by
firmware.
PIC18F2XK20/4XK20
DS40001303H-page 86 2010-2015 Microchip Technology Inc.
REGISTER 6-1: EECON1: DATA EEPROM CONTROL 1 REGISTER
R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0
EEPGD CFGS — FREE WRERR WREN WR RD
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit
S = Bit can be set by software, but not cleared U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit
1 = Access Flash program memory
0 = Access data EEPROM memory
bit 6 CFGS: Flash Program/D at a EEPROM or Configur ati on Sele ct bit
1 = Access Configuration registers
0 = Access Flash program or data EEPROM memory
bit 5 Unimplemented: Read as ‘0’
bit 4 FREE: Flash Row (Block) Erase Enable bit
1 = Erase the program memory block addressed by TBLPTR on the next WR command
(cleared by completion of erase operation)
0 = Perform write-only
bit 3 WRERR: Flash Program/Data EEPROM Error Flag bit(1)
1 = A write opera tio n is prema ture ly termi nat ed (an y Rese t duri ng self-timed programm ing in normal
operation, or an improper write attempt)
0 = The write ope rati on com pl ete d
bit 2 WREN: Flash Program/Data EEPROM Write Enable bit
1 = Allows write cycles to Flash program/data EEPROM
0 = Inhibits write cycles to Flash program/data EEPROM
bit 1 WR: Write Control bit
1 = Initiates a data EEPROM erase/write cycle or a program m emory eras e cycl e or write cycle.
(The operation is self-timed and the bit is cleared by hardware once write is complete.
The WR bit can only be set (not cleared) by software.)
0 = Write cycle to the EEPROM is complete
bit 0 RD: Read Control bit
1 = Initiates an EEPROM rea d (Read takes one cycle. RD is cleared by ha rdware. The RD bit can only
be set (not cleared) by sof tware. RD bit cannot be s et when EEPGD = 1 or CFGS = 1.)
0 = Does not initiate an EEPROM read
Note 1: When a WRER R occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the
error condition.
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6.2.2 TABLAT – TABLE LATCH REGISTER
The Table La tch (TABLAT) is an 8-bit register mapped
into the SFR sp ace. The Table Latch register is used to
hold 8-bit data during data transfers between program
memory and data RAM.
6.2.3 TBLPTR – TABLE POINTER
REGISTER
The Table Po in ter (TBLPTR) register add res ses a by te
within the progra m memo ry. The T BLPTR is comprise d
of three SFR regis ters: Table Po inter U pper Byte, Table
Pointer High Byte and Table Pointer Low Byte
(TBLPTRU:TBLPTRH:TBLPTRL). These three regis-
ters join to form a 22-bit wide pointer. The low-order
21 bits allow the device to address up to 2 Mbytes of
progra m memory sp ace. Th e 22nd b it allow s acce ss to
the device ID, the user ID and the Configuration bits.
The Table Pointer register, TBLPTR, is used by the
TBLRD and TBLWT ins t ru cti ons . T hes e i ns truc tio ns ca n
update the TBLPTR in one of four ways based on the
table operation. These operations are shown in
Table 6-2. Th ese operation s on the TBLPTR af fect only
the low-order 21 bits.
6.2.4 TABLE POINTER BOUNDARI ES
TBLPTR is used in reads, writes and erases of the
Flash program memory.
When a TBLRD i s ex ecut ed , all 22 b its of th e T BLPT R
determine which byte is read from program memory
directly into the TABL AT register.
When a TBLWT is executed the byte in the TABLAT
register is written, not to Flash memo ry but, to a holding
register in prepa ration for a program memory write. The
holding registers constitute a write block which varies
dependi ng on the devic e (See Table 6-1).The 3, 4, or 5
LSbs of the TBLPTRL register determine which specific
address within the holding register block is written to.
The MSBs of the Table Pointer have no effect during
TBLWT operations .
When a program memory write is executed the entire
holding register block i s wr i tte n to th e Flash memory at
the address determined by the MSbs of the TBLPTR.
The 3, 4, or 5 LSBs are ignored during Flash memory
writes. For more detail, see Section 6.5 “Writing to
Flash Program Memory”.
When an erase of program memory is executed, the
16 MSbs of the Table Po inter register (T BLPTR<21:6>)
point to the 64-byte block that wi ll be erased. The Leas t
Significant bits (TBLPTR<5:0>) are ignored.
Figure 6-3 describes the relevant boundaries of
TBLPTR based on Flash program memory operations.
TABLE 6-2: TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS
FIGURE 6-3: TABLE PO INTER BOUNDARI ES BASED ON OPERATION
Example Operation on Table Pointer
TBLRD*
TBLWT* TBLPTR is not modified
TBLRD*+
TBLWT*+ TBLPTR is incremented after the read/write
TBLRD*-
TBLWT*- TBLPTR is decremented after the read/write
TBLRD+*
TBLWT+* TBLPTR is incremented before the read/write
21 16 15 87 0
TABLE ERASE/WRITE TABLE WRITE
TABLE READ – TBLPTR<21:0>
TBLPTRLTBLPTRH
TBLPTRU
TBLPTR<n:0>(1)
TBLPTR<21:n+1>(1)
Note 1: n = 3, 4, 5, or 6 for block sizes of 8, 16, 32 or 64 bytes, respectively.
PIC18F2XK20/4XK20
DS40001303H-page 88 2010-2015 Microchip Technology Inc.
6.3 Reading the Flash Program
Memory
The TBLRD instruction retrieves data from program
memory and plac es it into data RAM. Table r ead s fro m
program memory are performed one byte at a time.
TBLPTR points to a byte address in program space.
Executing TBLRD places the byte pointed to into
TABLAT. In addition, TBLPTR can be modified
automatically for the next table read operation.
The interna l program memory is typically organize d by
words. The Least Significant b it of th e address selects
between the high and low bytes of the word. Figure 6-4
shows the interface between the internal program
memory and the TABLAT.
FIGURE 6-4: READS FROM FLASH PROGRAM MEMORY
EXAMPLE 6-1: READING A FLASH PROGRAM MEMORY WORD
(Even Byte Address)
Program Memory
(Odd Byte Address)
TBLRD TABLAT
TBLPTR = xxxxx1
FETCH
Instruction Register
(IR) Read Register
TBLPTR = xxxxx0
MOVLW CODE_ADDR_UPPER ; Load TBLPTR with the base
MOVWF TBLPTRU ; address of the word
MOVLW CODE_ADDR_HIGH
MOVWF TBLPTRH
MOVLW CODE_ADDR_LOW
MOVWF TBLPTRL
READ_WORD TBLRD*+ ; read into TABLAT and increment
MOVF TABLAT, W ; get data
MOVWF WORD_EVEN
TBLRD*+ ; read into TABLAT and increment
MOVFW TABLAT, W ; get data
MOVF WORD_ODD
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PIC18F2XK20/4XK20
6.4 Erasing Flash Program Memory
The mi nimum eras e block is 32 words or 64 byte s. Only
through the use of an external programmer, or through
ICSP™ control, can larger blocks of program memory
be bulk erased. Word erase in the Flash array is not
supported.
When initiating an erase sequence from the
Microcontroller itself, a block of 64 bytes of program
memory is erased. The Most Significant 16 bits of the
TBLPTR<21:6> point to the block being erased. The
TBLPTR<5:0> bits are ignored.
The EECON1 regis te r com ma nds the era se opera tio n.
The EEPGD bit must be set to point to the Flash pro-
gram memory. The WREN bit must be set to enable
write op erations. The FREE bit is s et to selec t an erase
operation.
The write initiate sequence for EECON2, shown as
steps 4 through 6 in Section 6.4.1 “Flash Program
Memory Erase Sequence”, is used to guard against
accidental writes. This is sometimes referred to as a
long write.
A long w rite i s nec essary for erasing th e i nternal Fl ash.
Instruction execution is halted during the long write
cycle. The long write is terminated by the internal
programming timer.
6.4.1 FLASH PROGRAM MEMORY
ERASE SEQUENCE
The sequence of events for erasing a block of internal
program memory is:
1. Load Table Pointer register with address of
block being erased.
2. Set the EECON1 register for the erase operation:
• set EEPGD bit to point to program memory;
• clear the CFGS bit to access program memory;
• set WREN bit to enable writes;
• set FREE bit to enable the erase.
3. Disable int errup ts.
4. Write 55h to EECON2.
5. Write 0AAh to EECON2.
6. Set the WR bit. This will begin the block erase
cycle.
7. The CPU will stall for duration of the erase
(about 2 ms using internal timer).
8. Re-enable interrupts.
EXAMPLE 6-2: ERASING A FLASH PROGRAM MEMORY BLOCK
MOVLW CODE_ADDR_UPPER ; load TBLPTR with the base
MOVWF TBLPTRU ; address of the memory block
MOVLW CODE_ADDR_HIGH
MOVWF TBLPTRH
MOVLW CODE_ADDR_LOW
MOVWF TBLPTRL
ERASE_BLOCK
BSF EECON1, EEPGD ; point to Flash program memory
BCF EECON1, CFGS ; access Flash program memory
BSF EECON1, WREN ; enable write to memory
BSF EECON1, FREE ; enable block Erase operation
BCF INTCON, GIE ; disable interrupts
Required MOVLW 55h
Sequence MOVWF EECON2 ; write 55h
MOVLW 0AAh
MOVWF EECON2 ; write 0AAh
BSF EECON1, WR ; start erase (CPU stall)
BSF INTCON, GIE ; re-enable interrupts
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DS40001303H-page 90 2010-2015 Microchip Technology Inc.
6.5 Writing to Flash Program Memory
The programming block size is 16, 32 or 64 bytes,
dependi ng on th e device (See Table 6-1). Word or byte
program ming is not supported.
Table writes are used internally to load the holding
registers needed to program the Flash memory. There
are only as many holding registers as there are bytes
in a write block (See Table 6-1).
Since the Table Latch (TABLAT) is only a single byte,
the TBLWT instruct ion may need to be executed 16, 32
or 64 times, depending on the device, for each pro-
gramming operation. All of the table write operations
will e ssentially be short writ es because on ly the holdin g
register s are written. Af ter all t he holding regist ers have
been written, the programming operation of that block
of mem ory is st arted by config uring the EECON1 re gis-
ter for a program memory write and perf orming the long
write sequence.
The long write is necessary for programming the
inte rnal Fl ash. I nstruc tion ex ecution is hal ted duri ng a
long write cycle. The long write will be terminated by
the internal programming timer.
The EEPROM on-chip timer controls the write time.
The write/erase voltages are generated by an on-chip
charge pump, rated to operate over the voltage range
of the device.
FIGURE 6-5: TABLE WRITES TO FLASH PROGRAM MEMORY
6.5.1 FLASH PROGRAM MEMORY WRITE
SEQUENCE
The sequence of events for programming an internal
program memory lo cation sh ould be:
1. Read 64 by tes into RAM.
2. Update data values in RAM as necessary.
3. Load Table Pointer register with address being
erased.
4. Execute the block erase procedure.
5. Load Table Pointer register with address of first
byte being written.
6. Write the 16, 3 2 or 64 by te block into the holding
registers with auto-increment.
7. Set the EECON 1 register for the wri te operation:
• set EEPGD bit to point to program memory;
• clear the CFGS bit to access program memory;
• set WREN to enable byte writes.
8. Disable int errup ts.
9. Write 55h to EECON2.
10. Write 0AAh to EECON2.
11. Set the WR bit. This will begin the wr ite cy cl e.
12. The CPU w ill st all fo r duration of the write (abo ut
2 ms using internal timer).
13. Re-enable interrupts.
14. Repeat steps 6 to 13 for each block until all 64
bytes are written.
15. Verify the memory (table read).
This procedure will require about 6 ms to update each
write block of memory . An example of the required code
is gi ven in Example 6-3.
Note: The default value of the holding registers on
device R es ets an d afte r wr ite op e rat io ns is
FFh. A write of FFh to a holding register
does not modify that byte. This means that
individual bytes of program memory may
be mo dified, provid ed t hat the change does
not atte mpt to cha nge any bi t from a ‘0’ to a
‘1’. When modifying individual bytes, it is
not necessary to load all holding registers
before execu ting a lon g writ e opera tion.
TABLAT
TBLPT R = xxxxYY(1)
TBLPTR = xxxx01TBLPTR = xxxx00
Write Register
TBLPT R = xxxx02
Program Memory
Holding Register Holding Register Holding Register Holding Register
88 8 8
Note 1: YY = x7, xF, or 1F for 8, 16 or 32 byte write blocks, respectively.
Note: Before setting the WR bit, the Table
Pointer address needs to be within the
intended address range of the byte s in the
holding registers.
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EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY
MOVLW D'64’ ; number of bytes in erase block
MOVWF COUNTER
MOVLW BUFFER_ADDR_HIGH ; point to buffer
MOVWF FSR0H
MOVLW BUFFER_ADDR_LOW
MOVWF FSR0L
MOVLW CODE_ADDR_UPPER ; Load TBLPTR with the base
MOVWF TBLPTRU ; address of the memory block
MOVLW CODE_ADDR_HIGH
MOVWF TBLPTRH
MOVLW CODE_ADDR_LOW
MOVWF TBLPTRL
READ_BLOCK TBLRD*+ ; read into TABLAT, and inc
MOVF TABLAT, W ; get data
MOVWF POSTINC0 ; store data
DECFSZ COUNTER ; done?
BRA READ_BLOCK ; repeat
MODIFY_WORD MOVLW BUFFER_ADDR_HIGH ; point to buffer
MOVWF FSR0H
MOVLW BUFFER_ADDR_LOW
MOVWF FSR0L
MOVLW NEW_DATA_LOW ; update buffer word
MOVWF POSTINC0
MOVLW NEW_DATA_HIGH
MOVWF INDF0
ERASE_BLOCK MOVLW CODE_ADDR_UPPER ; load TBLPTR with the base
MOVWF TBLPTRU ; address of the memory block
MOVLW CODE_ADDR_HIGH
MOVWF TBLPTRH
MOVLW CODE_ADDR_LOW
MOVWF TBLPTRL
BSF EECON1, EEPGD ; point to Flash program memory
BCF EECON1, CFGS ; access Flash program memory
BSF EECON1, WREN ; enable write to memory
BSF EECON1, FREE ; enable Erase operation
BCF INTCON, GIE ; disable interrupts
MOVLW 55h
Required MOVWF EECON2 ; write 55h
Sequence MOVLW 0AAh
MOVWF EECON2 ; write 0AAh
BSF EECON1, WR ; start erase (CPU stall)
BSF INTCON, GIE ; re-enable interrupts
TBLRD*- ; dummy read decrement
MOVLW BUFFER_ADDR_HIGH ; point to buffer
MOVWF FSR0H
MOVLW BUFFER_ADDR_LOW
MOVWF FSR0L
WRITE_BUFFER_BACK MOVLW BlockSize ; number of bytes in holding register
MOVWF COUNTER
MOVLW D’64’/BlockSize ; number of write blocks in 64 bytes
MOVWF COUNTER2
WRITE_BYTE_TO_HREGS MOVF POSTINC0, W ; get low byte of buffer data
MOVWF TABLAT ; present data to table latch
TBLWT+* ; write data, perform a short write
; to internal TBLWT holding register.
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DS40001303H-page 92 2010-2015 Microchip Technology Inc.
EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY (CONTINUED)
6.5.2 WRITE VERIFY
Depending on the application, good programming
practice may dictate that the value written to the
memory should be verified against the original value.
This should be used in applications where excessive
writes can stress bits near the specification limit.
6.5.3 UNEXPECTED TERMINATION OF
WRITE OPER ATION
If a wri te is term in ate d by an unplanned event, s uc h a s
loss of power or an unexpected Reset, the memory
location just programmed should be verified and
reprogrammed if needed. If the write operation is
interrupted by a MCLR Reset or a WDT Time-out Reset
during normal operation, the WRERR bit will be set
whic h the us er can ch eck to d ecide whe ther a r ewrite
of the location(s) is needed.
6.5.4 PROTECTION AGAINST
SPURIOUS WRITES
To protect against spurious writes to Flash program
memory, the write initiate sequence must also be
followed. See Section 23.0 “Special Features of the
CPU” for more detail.
6.6 Flash Program Operation During
Code Protection
See Section 23.3 “Program Verification and Code
Protection” for details on code protection of Flash
program memory.
TABLE 6-3: REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY
DECFSZ COUNTER ; loop until holding registers are full
BRA WRITE_WORD_TO_HREGS
PROGRAM_MEMORY BSF EECON1, EEPGD ; point to Flash program memory
BCF EECON1, CFGS ; access Flash program memory
BSF EECON1, WREN ; enable write to memory
BCF INTCON, GIE ; disable interrupts
MOVLW 55h
Required MOVWF EECON2 ; write 55h
Sequence MOVLW 0AAh
MOVWF EECON2 ; write 0AAh
BSF EECON1, WR ; start program (CPU stall)
DCFSZ COUNTER2 ; repeat for remaining write blocks
BRA WRITE_BYTE_TO_HREGS ;
BSF INTCON, GIE ; re-enable interrupts
BCF EECON1, WREN ; disable write to memory
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset
Values on
page
TBLPTRU —— bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) 56
TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 56
TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 56
TABLAT Program Me mory Table Latch 56
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 56
EECON2 EEPROM Control Register 2 (not a physical register) 58
EECON1 EEPGD CFGS — FREE WRERR WREN WR RD 58
IPR2 OSCFIP C1IP C2IP EEIP BCLIP HLVDIP TMR3IP CCP2IP 59
PIR2 OSCFIF C1IF C2IF EEIF BCLIF HLVDIF TMR3IF CCP2IF 59
PIE2 OSCFIE C1IE C2IE EEIE BCLIE HLVDIE TMR3IE CCP2IE 59
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access.
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7.0 DATA EEPROM MEMORY
The dat a EEPROM is a nonvola tile memory array, sep-
arate from the data RAM and program memory, which
is used for long-term storage of program data. It is not
directly mapped in either the register file or program
memory space but is indirectly addressed through the
Special Function Registers (SFRs). The EEPROM is
readable and writ able durin g normal ope ration over th e
entire VDD range.
Four SFRs are used to read and write to the data
EEPROM as well as the program memory. They are:
• EECON1
• EECON2
• EEDATA
• EEADR
• EEADRH
The data EEPROM allows byte read and write. When
interfacing to the data memory block, EEDATA holds
the 8-bit data for read/write and the EEADR:EEADRH
register pair hold the address of the EEPROM location
being accessed.
The EEPROM data memory is rated for high erase/write
cycle endurance. A byte write automatically erases the
location and writes the new data (erase-before-write).
The write time is controlled by an on-chip timer; it will
vary with voltage and temperature as well as from chip-
to-chip. Please refer to param eter D122 (Table 26-10 in
Section 26.0 “Electrical Specifications”) for exact
limits.
7.1 EEADR and EEADRH Registers
The EEADR register is used to address the data
EEPROM for read and write operations. The 8-bit
range of the register can address a memory range of
256 bytes (00h to FFh). The EEADRH register e xpand s
the range to 1024 bytes by adding an additional two
address bits.
7.2 EECON1 and EECON2 Registers
Access to the data EEPROM is controlled by two
register s: EECON1 an d EECON2. Thes e are the same
registers which control access to the program memory
and are used in a similar manner for the data
EEPROM.
The EECON 1 re gister (Register 7-1) is the co ntro l re g-
ister for data and program memory access. Control bit
EEPGD determines if the access will be to program or
data EEPROM memory. When the EEPGD bit is clear,
operations will access the data EEPROM memory.
When the EEPGD bit is set, program memory is
accessed.
Control bit, CFGS, determines if the access will be to
the Con fig urat ion reg ist ers or to pro gram m em ory /data
EEPROM memory. When the CFGS bit is set,
subseq uent ope rations acce ss Confi gur ation reg isters.
When the CFGS bit is clear, the EEPGD bit selects
either program Flash or data EEPROM memory.
The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is clear.
The WRERR bit is set by hard ware w he n the WR bit i s
set and cleared when the internal programming timer
expires and the write operation is complete.
The WR control bit initiates write operations. The bit
can be set but no t cleared b y software . It is cle ared only
by hardware at the co mpletion of th e write ope ration.
Control bits, RD and WR, start read and erase/write
operat ions, respec tively . These bi ts are set by fi rmware
and cleared by hardware at the completion of the
operation.
The RD bit cannot be set when accessing program
memory (EEPGD = 1). Program memory is read using
table read instructions. See Section 6.1 “T abl e Reads
and Table Writes” regarding table reads.
The EECON2 register is not a physical register. It is
used exclusively in the memory write and erase
sequences. Reading EECON2 will read all ‘0’s.
Note: During normal operation, the WRERR
may read as ‘1’. This can indicate that a
write operation was prematurely termi-
nated by a Reset, or a write operation was
attempted improperly.
Note: The EEIF interrupt flag bit of the PIR2
register is set when the write is complete.
It must be cleared by software.
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DS40001303H-page 94 2010-2015 Microchip Technology Inc.
REGISTER 7-1: EECON1: DATA EEPROM CONTROL 1 REGISTER
R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0
EEPGD CFGS — FREE WRERR WREN WR RD
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit
S = Bit can be set by software, but not cleared U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit
1 = Access Flash program memory
0 = Access data EEPROM memory
bit 6 CFGS: Flash Program/D at a EEPROM or Configur ati on Sele ct bit
1 = Access Configuration registers
0 = Access Flash program or data EEPROM memory
bit 5 Unimplemented: Read as ‘0’
bit 4 FREE: Flash Row (Block) Erase Enable bit
1 = Erase the program memory block addressed by TBLPTR on the next WR command
(cleared by completion of erase operation)
0 = Perform write-only
bit 3 WRERR: Flash Program/Data EEPROM Error Flag bit(1)
1 = A write opera tio n is prema ture ly termi nat ed (an y Rese t duri ng self-timed programm ing in normal
operation, or an improper write attempt)
0 = The write ope rati on com pl ete d
bit 2 WREN: Flash Program/Data EEPROM Write Enable bit
1 = Allows write cycles to Flash program/data EEPROM
0 = Inhibits write cycles to Flash program/data EEPROM
bit 1 WR: Write Control bit
1 = Initiates a data EEPROM erase/write cycle or a program m emory eras e cycl e or write cycle.
(The operation is self-timed and the bit is cleared by hardware once write is complete.
The WR bit can only be set (not cleared) by software.)
0 = Write cycle to the EEPROM is complete
bit 0 RD: Read Control bit
1 = Initiates an EEPROM read (Read takes one cycle. RD is cle ared by hardware. The RD bit ca n only
be set (not cleared) by sof tware. RD bit cannot be s et when EEPGD = 1 or CFGS = 1.)
0 = Does not initiate an EEPROM read
Note 1: When a WRER R occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the
error condition.
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PIC18F2XK20/4XK20
7.3 Reading the Dat a EEPROM
Memory
To read a dat a memory location, the user must write the
address to the EEADR register, clear the EEPGD con-
trol bit of the EECON1 register and then set control bit,
RD. The data is available on the very next instruction
cycle; therefore, the EEDATA register can be read by
the next instruction. EEDATA will hold this value until
another read operation, or until it is written to by the
user (during a write operation).
The basic process is shown in Example 7-1.
7.4 Writing to the Data EEPROM
Memory
To write an EEPROM data location, the address must
first be writ ten to the EEAD R r egiste r and the da ta writ-
ten to the EEDATA register. The sequence in
Example 7-2 must be followed to initiate the write cycle.
The write will not begin if this sequence is not exactly
followed (write 55h to EECON2, write 0AAh to
EECON2, then set WR bit) for each byte. It is strongly
recommended that interrupts be disabled during this
code segment.
Additionally, the WREN bit in EECON1 must be set to
enable writes. This mechanism prevents accidental
writes to data EEPROM due to unexpected code
execution (i.e., runaway programs). The WREN bit
should be ke pt clear at all times , excep t whe n upda tin g
the EEPROM. The WREN bit is not cleared by
hardware.
After a write sequence has been initiated, EECON1,
EEADR and EEDATA cannot be modified. The WR bit
will be inhibited from being set unless the WREN bit is
set. Both WR and WREN cannot be set with the same
instruction.
At the completion of the write cycle, the WR bit is
cleared by hardware and the EEPROM Interrupt Flag
bit, EEIF, is set. The user may either enable this
interrupt or poll this bit. EEIF must be cleared by
software.
7.5 Write Verify
Depending on the application, good programming
practice may dictate that the value written to the
memory should be verified against the original value.
This should be used in applications where excessive
writes can stress bits near the specification limit.
EXAMPLE 7-1: DATA EEPROM READ
EXAMPLE 7-2: DATA EEPROM WRITE
MOVLW DATA_EE_ADDR ;
MOVWF EEADR ; Data Memory Address to read
BCF EECON1, EEPGD ; Point to DATA memory
BCF EECON1, CFGS ; Access EEPROM
BSF EECON1, RD ; EEPROM Read
MOVF EEDATA, W ; W = EEDATA
MOVLW DATA_EE_ADDR_LOW ;
MOVWF EEADR ; Data Memory Address to write
MOVLW DATA_EE_ADDR_HI ;
MOVWF EEADRH ;
MOVLW DATA_EE_DATA ;
MOVWF EEDATA ; Data Memory Value to write
BCF EECON1, EEPGD ; Point to DATA memory
BCF EECON1, CFGS ; Access EEPROM
BSF EECON1, WREN ; Enable writes
BCF INTCON, GIE ; Disable Interrupts
MOVLW 55h ;
Required MOVWF EECON2 ; Write 55h
Sequence MOVLW 0AAh ;
MOVWF EECON2 ; Write 0AAh
BSF EECON1, WR ; Set WR bit to begin write
BSF INTCON, GIE ; Enable Interrupts
; User code execution
BCF EECON1, WREN ; Disable writes on write complete (EEIF set)
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DS40001303H-page 96 2010-2015 Microchip Technology Inc.
7.6 Operation During Code-Protect
Data EEPROM memory has its own code-p rotect bits in
Configuration Words. External read and write
operations are disabled if code protection is enabled.
The mic rocontroll er its elf can bo th read and write to the
internal data EEPROM, regardless of the state of the
code-protect Configuration bit. Refer to Section 23.0
“Special Features of the CPU” for additional
information.
7.7 Protection Against Spurious Write
There are conditions when the user may not want to
write to the data EEPROM memory. To protect against
spurious EEPROM writes, various mechanisms have
been implemented. On power-up, the WREN bit is
cleared. In addition, writes to the EEPROM are bloc ked
during the Power-up Timer period (TPWRT,
parameter 33).
The write initiate sequence an d the WREN bi t tog eth er
help prevent an accidental write during brown-out,
power glitch or software malfunction.
7.8 Using the Data EEPROM
The data EEPROM is a high-endurance, byte
addressable array that has been optimized for the
storage of frequently changing information (e.g.,
program variables or other dat a that are updated of ten).
When variables in one section change frequently, while
variables in another sec tion do not c hange, it is possible
to exceed the total number of write cycles to the
EEPROM (specification D124) without exceeding the
total number of write cycles to a single byte (specification
D120). If this is the case, then an array refresh must be
performed. For this reason, variables that change
infrequently (such as constants, IDs, calibration, etc.)
should be stored in Flash program m emory.
A simple data EEPROM refresh routine is shown in
Example 7-3.
EXAMPLE 7-3: DATA EEPROM REFRESH ROUTINE
Note: If data EEPROM is only used to store
const ants and/or dat a that chan ges rarely,
an array re fres h is l ike ly n ot requ ire d. See
specification.
CLRF EEADR ; Start at address 0
BCF EECON1, CFGS ; Set for memory
BCF EECON1, EEPGD ; Set for Data EEPROM
BCF INTCON, GIE ; Disable interrupts
BSF EECON1, WREN ; Enable writes
Loop ; Loop to refresh array
BSF EECON1, RD ; Read current address
MOVLW 55h ;
MOVWF EECON2 ; Write 55h
MOVLW 0AAh ;
MOVWF EECON2 ; Write 0AAh
BSF EECON1, WR ; Set WR bit to begin write
BTFSC EECON1, WR ; Wait for write to complete
BRA $-2
INCFSZ EEADR, F ; Increment address
BRA LOOP ; Not zero, do it again
BCF EECON1, WREN ; Disable writes
BSF INTCON, GIE ; Enable interrupts
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PIC18F2XK20/4XK20
TABLE 7-1: REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 56
EEADR EEADR7 EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 58
EEADRH(1) — — ———— EEADR9 EEADR8 58
EEDATA EEPROM Data Register 58
EECON2 EEPROM Control Register 2 (not a physical register) 58
EECON1 EEPGD CFGS — FREE WRERR WREN WR RD 58
IPR2 OSCFIP C1IP C2IP EEIP BCLIP HLVDIP TMR3IP CCP2IP 59
PIR2 OSCFIF C1IF C2IF EEIF BCLIF HLVDIF TMR3IF CCP2IF 59
PIE2 OSCFIE C1IE C2IE EEIE BCLIE HLVDIE TMR3IE CCP2IE 59
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access.
Note 1: PIC18F26K20/PIC18F46K20 only.
PIC18F2XK20/4XK20
DS40001303H-page 98 2010-2015 Microchip Technology Inc.
8.0 8 x 8 HARDWARE MULTIPLIER
8.1 Introduction
All PIC18 devices include an 8 x 8 hardware multiplier
as part of the ALU. The multipl ier performs an unsigned
operation and yields a 16-bit result that is stored in the
product register pair, PRODH:PRODL. The multiplier’s
operation does not affect any flags in the STATUS
register.
Making multiplication a hardware operation allows it to
be com pl eted i n a single instru cti on cycle. This has th e
advantages of higher computational throughput and
reduced code size for multiplication algorithms and
allows the PIC18 devices to be used in many applica-
tions previously reserved for digital signal processors.
A comparison of various hardware and software
multiply operations, along with the savings in memory
and execution tim e, is shown in Table 8-1.
8.2 Operation
Example 8-1 show s the instruc tion sequen ce for an 8 x 8
unsigned multiplication. Only one instruction is required
when one of the arguments is already loaded in the
WREG regis ter.
Example 8-2 shows the sequence t o do an 8 x 8 signed
multiplication. To account for the sign bits of the argu-
ments, each argument’s Most Significant bit (MSb) is
tested and the appropriate subtractions are done.
EXAMPLE 8-1: 8 x 8 UNSIGNED
MULTIPLY ROUTINE
EXAMPLE 8-2: 8 x 8 SIGNED MULTIPLY
ROUTINE
TABLE 8-1: PERFORMANCE COMPARISON FOR VARIOUS MULTIPLY OPERATIONS
MOVF ARG1, W ;
MULWF ARG2 ; ARG1 * ARG2 ->
; PRODH:PRODL
MOVF ARG1, W
MULWF ARG2 ; ARG1 * ARG2 ->
; PRODH:PRODL
BTFSC ARG2, SB ; Test Sign Bit
SUBWF PRODH, F ; PRODH = PRODH
; - ARG1
MOVF ARG2, W
BTFSC ARG1, SB ; Test Sign Bit
SUBWF PRODH, F ; PRODH = PRODH
; - ARG2
Routine Multiply Method Program
Memory
(Words)
Cycles
(Max)
Time
@ 40 MHz @ 10 MHz @ 4 MHz
8 x 8 unsigned Without hardware multiply 13 69 6.9 s27.6 s69 s
Hardware multiply 1 1 100 ns 400 ns 1 s
8 x 8 signed Without hardware multiply 33 91 9.1 s36.4 s91 s
Hardware multiply 6 6 600 ns 2.4 s6 s
16 x 16 unsigned Without hardware multiply 21 242 24.2 s96.8 s 242 s
Hardware multiply 28 28 2.8 s 11.2 s28 s
16 x 16 signed Without hardware multiply 52 254 25.4 s 102.6 s 254 s
Hardware multiply 35 40 4.0 s16.0 s40 s
2010-2015 Microchip Technology Inc. DS40001303H-page 99
PIC18F2XK20/4XK20
Example 8-3 shows the sequence to do a 16 x 16
unsigned multiplication. Equation 8-1 shows the
algorith m that is us ed. The 32-b it result is stored in fo ur
registers (RES<3:0>).
EQUATION 8-1: 16 x 16 UNSIGNED
MULTIPLICATION
ALGORITHM
EXAMPLE 8- 3: 16 x 16 UNSIGNED
MULTIPLY ROUTINE
Example 8-4 shows the sequence to do a 16 x 16
signed multiply. Equation 8-2 shows the algorithm
used. The 32-bit result is stored in four registers
(RES<3:0>). To account for the sign bits of the argu-
ments, the MSb for each argument pair is tested and
the approp riate subtractions are done.
EQUATION 8-2: 16 x 16 SIGNED
MULTIPLICATION
ALGORITHM
EXAMPLE 8-4: 16 x 16 SIGNED
MULTIP LY ROUTINE
RES3:RES0 = ARG1 H:ARG1L ARG2H:ARG2L
= (ARG1H ARG2H 216) +
(ARG1H ARG2L 28) +
(ARG1L ARG2H 28) +
(ARG1L ARG2L)
MOVF ARG1L, W
MULWF ARG2L ; ARG1L * ARG2L->
; PRODH:PRODL
MOVFF PRODH, RES1 ;
MOVFF PRODL, RES0 ;
; MOVF ARG1H, W
MULWF ARG2H ; ARG1H * ARG2H->
; PRODH:PRODL
MOVFF PRODH, RES3 ;
MOVFF PRODL, RES2 ;
; MOVF ARG1L, W
MULWF ARG2H ; ARG1L * ARG2H->
; PRODH:PRODL
MOVF PRODL, W ;
ADDWF RES1, F ; Add cross
MOVF PRODH, W ; products
ADDWFC RES2, F ;
CLRF WREG ;
ADDWFC RES3, F ;
; MOVF ARG1H, W ;
MULWF ARG2L ; ARG1H * ARG2L->
; PRODH:PRODL
MOVF PRODL, W ;
ADDWF RES1, F ; Add cross
MOVF PRODH, W ; products
ADDWFC RES2, F ;
CLRF WREG ;
ADDWFC RES3, F ;
RES3:RES0 = ARG1H:ARG1L ARG2H:ARG2L
= (ARG1H ARG2H 216) +
(ARG1H ARG2L 28) +
(ARG1L ARG2H 28) +
(ARG1L ARG2L) +
(-1 ARG2H<7> ARG1H:ARG1L 216) +
(-1 ARG1H<7> ARG2H:ARG2L 216)
MOVF ARG1L, W
MULWF ARG2L ; ARG1L * ARG2L ->
; PRODH:PRODL
MOVFF PRODH, RES1 ;
MOVFF PRODL, RES0 ;
; MOVF ARG1H, W
MULWF ARG2H ; ARG1H * ARG2H ->
; PRODH:PRODL
MOVFF PRODH, RES3 ;
MOVFF PRODL, RES2 ;
; MOVF ARG1L, W
MULWF ARG2H ; ARG1L * ARG2H ->
; PRODH:PRODL
MOVF PRODL, W ;
ADDWF RES1, F ; Add cross
MOVF PRODH, W ; products
ADDWFC RES2, F ;
CLRF WREG ;
ADDWFC RES3, F ;
; MOVF ARG1H, W ;
MULWF ARG2L ; ARG1H * ARG2L ->
; PRODH:PRODL
MOVF PRODL, W ;
ADDWF RES1, F ; Add cross
MOVF PRODH, W ; products
ADDWFC RES2, F ;
CLRF WREG ;
ADDWFC RES3, F ;
; BTFSS ARG2H, 7 ; ARG2H:ARG2L neg?
BRA SIGN_ARG1 ; no, check ARG1
MOVF ARG1L, W ;
SUBWF RES2 ;
MOVF ARG1H, W ;
SUBWFB RES3
;
SIGN_ARG1
BTFSS ARG1H, 7 ; ARG1H:ARG1L neg?
BRA CONT_CODE ; no, done
MOVF ARG2L, W ;
SUBWF RES2 ;
MOVF ARG2H, W ;
SUBWFB RES3
;
CONT_CODE
:
PIC18F2XK20/4XK20
DS40001303H-page 100 2010-2015 Microchip Technology Inc.
9.0 INTERRUPTS
The PIC18F2XK20/4XK20 devices have multiple
interrupt sources and an interrupt priority feature that
allows most interrupt sources to be assigned a high
priority level or a low priority level. The high priority
interr upt vector is at 0008h and the low priority interru pt
vector is at 0018h. A high priority interrupt event will
inter rupt a low priorit y interrupt tha t may be in p rogress.
There are ten registers which are used to control
interrupt operation. These registers are:
• RCON
•INTCON
• INTCON2
• INTCON3
• PIR1, PIR2
• PIE1, PIE2
• IPR1, IPR2
It is recommended that the Microchip header files sup-
plied with MPLAB® IDE be used for the symbolic bit
names in these registers. This allows the assembler/
compil er to automa tical ly ta ke care of the pla ceme nt of
these bits within the specified register.
In ge nera l, in terru pt so urces have thre e bits t o con trol
their operation. They are:
•Flag bit to indicate that an interrupt event
occurred
•Enable bit that allows program execution to
branch to the interrupt vector address when the
flag bit is set
•Priority bit to select high priority or low priority
9.1 Mid-Range Compatibili ty
When the IPEN b it is cleared (default st ate), the interrupt
priority feature is disabled and interrupts are com p atible
with PIC® microcontroller mid-range devices. In
Comp atibility mode, the interrupt priority bit s of the IPRx
registers have no effect. The PEIE bit of the INTCON
register is the glo bal interrupt enable for the p eripherals.
The PEIE bit disables only the peripheral interrupt
sources and enables the peripheral interrupt sources
when the GIE bit is also set. The GIE bit of the INTCON
register is the global interrupt enable which enables all
non-peripheral interrupt sources and disables all
interrupt sources, including the peripherals. All interrupt s
branch to address 0008h in C omp atib ility mo de.
9.2 Interrupt Priority
The interrupt priority feature is enabled by setting the
IPEN bit of the RCON register. When interrupt priority
is enabled the GIE and PEIE global interrupt enable
bits of Compatibility mode are replaced by the GIEH
high priority, and GIEL low priority, global interrupt
enables. When set, the GIEH bit of the INTCON regis-
ter enables all interrupts that have their associated
IPRx register or INTCONx register priority bit set (high
priority). When clear, the GIEH bit disables all interrupt
sources including those selected as low priority. When
clear , the GIEL bit of t he INTCON register disa bles only
the interrupts that have their associated priority bit
cleared (low priority). When set, the GIEL bit enables
the low priority sources when the GIEH bit is also set.
When the interrupt flag, enable bit and appropriate
global interrupt enable bit are all set, the interrupt will
vector immediately to address 0008h for high priority,
or 0018h for low priority, depending on level of the
interrupting source’s priority bit. Individual interrupts
can be disabled through their corresponding interrupt
enable bits.
9.3 Interrupt Response
When an interrupt is responded to, the global interrupt
enable bit is cleared to disable further interrupts. The
GIE bit is the gl oba l i nterrupt enable wh en the IPEN b it
is cleared. When the IPEN bit is set, enabling interrupt
priority levels, the GIEH bit is the high priority global
interrupt enable and the GIEL bit is the low priority
global interrupt enable. High priority interrupt sources
can interrupt a low priority interrupt. Low priority
interrupts are not processed while high priority
interrupts are in progress.
The return address is pushed onto the stack and the
PC is loaded with the interrupt vector address (0008h
or 0018h). Once in the Interrupt Service Routine, the
source(s) of the interrupt can be determined by polling
the interrupt flag bits in the INTCONx and PIRx
registers. The interrupt flag bits must be cleared by
software before re-enabling interrupts to avoid
repeating the same interrupt.
The “return from interrupt” instruction, RETFIE, exits
the interrup t routine and set s the GIE bit (GIEH or GI EL
if priority levels are used), which re-enables interrupts.
For external interrupt events, such as the INT pins or
the PORTB interrupt-on-change, the interrupt latency
will be three to four instruction cycles. The exact
late ncy is th e same fo r one-c ycle or tw o-cycl e inst ruc-
tions. In divid ual int errupt fla g bit s are set, re gardle ss of
the status of their corresponding enable bits or the
global interrupt enable bit.
2010-2015 Microchip Technology Inc. DS40001303H-page 101
PIC18F2XK20/4XK20
FIGURE 9-1: PIC18 INTERRUPT LOGIC
Note:
Do not use the
MOVFF
instruction to modify
any of the interrupt control registers while
any
interrupt is enabled. Doing so may
cause erratic microcontroller behavior.
TMR0IE
GIEH/GIE
Wake-up if in
Interrupt to CPU
Vector to Location
0008h
INT2IF
INT2IE
INT2IP
INT1IF
INT1IE
INT1IP
TMR0IF
TMR0IE
TMR0IP
RBIF
RBIE
RBIP
TMR0IF
TMR0IP
INT1IF
INT1IE
INT1IP
INT2IF
INT2IE
INT2IP
RBIF
RBIE
RBIP
INT0IF
INT0IE
GIEL/PEIE
Interrupt to CPU
Vector to Location
IPEN
IPEN
0018h
SSPIF
SSPIE
SSPIP
SSPIF
SSPIE
SSPIP
ADIF
ADIE
ADIP
RCIF
RCIE
RCIP
Additio na l Perip her al Inter ru pts
ADIF
ADIE
ADIP
High Priority Interrupt Generation
Low Priority Interrupt Generation
RCIF
RCIE
RCIP
Additional Peripheral Interrupts
Idle or Sleep modes
GIEH/GIE
Note 1: The RBIF interrupt also requires the individual pin IOCB enables.
(1)
(1)
IPEN
GIEL/PEIE
PIC18F2XK20/4XK20
DS40001303H-page 102 2010-2015 Microchip Technology Inc.
9.4 INTCON Registers
The INTCON registers are readable and writable
registers, which contain various enable, priority and
flag bits.
Note: Interru pt flag bits are set w hen an interrupt
conditi on occurs, regard less of the s tate of
its corresponding enable bit or the global
enable bit. User software should ensure
the appropriate interrupt flag bi ts are clear
prior to enabling an interrupt. This feature
allows for software polling.
REGISTER 9-1: INTCON: INTERRUPT CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x
GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 GIE/GIEH: Global Interrupt Enable bit
When IPEN = 0:
1 = Enables all unmasked interrupts
0 = Disables all interrupts including peripherals
When IPEN = 1:
1 = Enables all high priority interrupts
0 = Disables all int errupts including low priority.
bit 6 PEIE/GIEL: Peripheral Interrupt Enable bit
When IPEN = 0:
1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral interrupts
When IPEN = 1:
1 = Enables all low priority interrupts
0 = Disables all low priority interrupts
bit 5 TMR0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 overflow interrupt
0 = Disables the TMR0 overflow interrupt
bit 4 INT0IE: INT0 External Interrupt Enable bit
1 = Enables the INT0 external interrupt
0 = Disables the INT0 external interrupt
bit 3 RBIE: RB Port Change Interrupt Enable bit(2)
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
bit 2 TMR0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared by software)
0 = TMR0 register did not overflow
bit 1 INT0IF: INT0 External Interrupt Flag bit
1 = The INT0 external interrupt occurred (must be cleared by software)
0 = The INT0 external interrupt did not occur
bit 0 RBIF: RB Port Change Interrupt Flag bit(1)
1 = At least one of the RB<7:4> pins changed state (must be cleared by software)
0 = None of the RB<7:4> pins have changed state
Note 1: A mismatch condition will continue to set the RBIF bit. Reading PORTB will end the
mismatch condition and allow the bit to be cleared.
2: RB port change interrupts also require the individual pin IOCB enables.
2010-2015 Microchip Technology Inc. DS40001303H-page 103
PIC18F2XK20/4XK20
REGISTER 9-2: INTCON2: INTERRUPT CONTROL 2 REGISTER
R/W-1 R/W-1 R/W-1 R/W-1 U-0 R/W-1 U-0 R/W-1
RBPU INTEDG0 INTEDG1 INTEDG2 —TMR0IP—RBIP
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 RBPU: PORTB Pull-up Enable bit
1 = All PORTB pull-ups are disabled
0 = PORTB pul l-up s are ena bled pro vided that the pin is an inp ut and the c orrespo nding WPUB bit is
set.
bit 6 INTEDG0: External Interrupt 0 Edge Select bit
1 = Interrupt on rising edge
0 = Interrupt on fallin g edge
bit 5 INTEDG1: External Interrupt 1 Edge Select bit
1 = Interrupt on rising edge
0 = Interrupt on fallin g edge
bit 4 INTEDG2: External Interrupt 2 Edge Select bit
1 = Interrupt on rising edge
0 = Interrupt on fallin g edge
bit 3 Unimplemented: Read as ‘0’
bit 2 TMR0IP: TMR0 Overflow Interrupt Priority bit
1 =High priority
0 = Low priority
bit 1 Unimplemented: Read as ‘0’
bit 0 RBIP: RB Port Change Interrupt Priority bit
1 =High priority
0 = Low priority
Note: Interru pt flag bit s are set when an inter rupt
condition occurs, regardless of the st ate of
its corresponding enable bit or the global
enable bit. User software should ensure
the appr opri ate in terrupt f lag bi ts are cl ear
prior to enabling an interrupt. This feature
allows for software polling.
PIC18F2XK20/4XK20
DS40001303H-page 104 2010-2015 Microchip Technology Inc.
REGISTER 9-3: INTCON3: INTERRUPT CONTROL 3 REGISTER
R/W-1 R/W-1 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0
INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 INT2IP: INT2 External Interrupt Priority bit
1 = High pr iority
0 = Low priority
bit 6 INT1IP: INT1 External Interrupt Priority bit
1 = High pr iority
0 = Low priority
bit 5 Unimplemented: Read as ‘0’
bit 4 INT2IE: INT2 External Interrupt Enable bit
1 = Enables the INT2 external interrupt
0 = Disables the INT2 external interrupt
bit 3 INT1IE: INT1 External Interrupt Enable bit
1 = Enables the INT1 external interrupt
0 = Disables the INT1 external interrupt
bit 2 Unimplemented: Read as ‘0’
bit 1 INT2IF: INT2 External Interrupt Flag bit
1 = The INT2 external interrupt occurred (mus t be cleared by software)
0 = The INT2 external interrupt did not occur
bit 0 INT1IF: INT1 External Interrupt Flag bit
1 = The INT1 external interrupt occurred (must be cleared by software)
0 = The INT1 external interrupt did not occur
Note: Interru pt flag bit s are set when an inter rupt
condition occurs, regardless of the st ate of
its corresponding enable bit or the global
enable bit. User software should ensure
the appr opri ate in terrupt f lag bi ts are cl ear
prior to enabling an interrupt. This feature
allows for software polling.
2010-2015 Microchip Technology Inc. DS40001303H-page 105
PIC18F2XK20/4XK20
9.5 PIR Registers
The PIR regi sters c onta in the ind ividu al flag bit s for the
peripheral interrupts. Due to the number of peripheral
interrupt sources, there are two Peripheral Interrupt
Request Flag registers (PIR1 and PIR2).
Note 1: Interrupt flag bits are set when an inter-
rupt condition occurs, regardless of the
state of its corresponding enable bit or the
Global Interrupt Enable bit, GIE of the
INTCON register.
2: User software should ensure the appro-
priate interrupt flag bits are cleared prior
to enabl ing an interrupt and af ter servicing
that interrupt.
REGISTER 9-4: PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1
R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0
PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 PSPIF: Parallel Slave Port Read/Write Interrupt Flag bit(1)
1 = A read or a write operation has taken place (must be cleared by software)
0 = No read or write has occurred
bit 6 ADIF: A/D Converter Interrupt Flag bit
1 = An A/D conversion completed (must be cleared by software)
0 = The A/D conversion is not complete or has not been started
bit 5 RCIF: EUSART Receive Interrupt Flag bit
1 = The EUSART receive buffer, RCREG, is full (cleared when RCREG is read)
0 = The EUS ART receive buffer is empty
bit 4 TXIF: EUSART Transmit Interrupt Flag bit
1 = The EUS ART transmit buffer, TXREG, is empty (cleared when TXR EG is written)
0 = The EUS ART transmit bu ffer is full
bit 3 SSPIF: Master Synchronous Serial Port Interrupt Flag bit
1 = The transmission/reception is complete (must be cleared by software)
0 = Waiting to transmit/receive
bit 2 CCP1IF: CCP1 Interrupt Flag bit
Capture mode:
1 = A TMR1 r egister c apture occurred (must be cleared by software)
0 = No TMR1 regi ster capture oc curred
Compare mode:
1 = A TMR1 register compare match occurred (must be cleared by software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused in this mode
bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred (must be cleared by software)
0 = No TMR2 to PR2 match occurred
bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be clear ed by software)
0 = TMR1 regi ster did not overflow
Note 1: The PSPIF bit is unimplemented on 28-pin devices and will read as ‘0’.
PIC18F2XK20/4XK20
DS40001303H-page 106 2010-2015 Microchip Technology Inc.
REGISTER 9-5: PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
OSCFIF C1IF C2IF EEIF BCLIF HLVDIF TMR3IF CCP2IF
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 OSCFIF: Oscillator Fail Interrupt Flag bit
1 = Device oscillator failed, clock input has changed to HFINTOSC (must be cleared by software)
0 = Device clock operating
bit 6 C1IF: Comparator C1 Interrupt Flag bit
1 = Comparator C1 output has changed (must be cleared by software)
0 = Comparator C1 output has not changed
bit 5 C2IF: Comparator C2 Interrupt Flag bit
1 = Comparator C2 output has changed (must be cleared by software)
0 = Comparator C2 output has not changed
bit 4 EEIF: Data EEPROM/Flash Write Operation Interrupt Flag bit
1 = The write operation is complete (must be cleared by software)
0 = The write operation is not complete or has not been started
bit 3 BCLIF: Bus Collision Interrupt Flag bit
1 = A bus collision occurred (must be cleared by software)
0 = No bus collision occurred
bit 2 HLVDIF: Low-Voltage Detect Interrupt Flag bit
1 = A low-voltage condition occurred (direction determined by the VDIRMAG bit of the
HLVDCON register)
0 = A low-voltage condition has not occurred
bit 1 TMR3IF: TMR3 Overflow Interrupt Flag bit
1 = TMR3 register overflowed (must be clear ed by software)
0 = TMR3 regi ster did not overflow
bit 0 CCP2IF: CCP2 Interrupt Flag bit
Capture mode:
1 = A TMR1 r egister capture occurred (must be cleared by software)
0 = No TMR1 regi ster capture occurred
Compare mode:
1 = A TMR1 register compare match occurred (must be cleared by software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused in this mode .
2010-2015 Microchip Technology Inc. DS40001303H-page 107
PIC18F2XK20/4XK20
9.6 PIE Registers
The PIE registers contain the individual enable bits for
the peripheral interrupts. Due to the number of periph-
eral interrupt sources, there are two Peripheral Interrupt
Enable registers (PIE1 and PIE2). When IPEN = 0, the
PEIE bit must be set to enable any of these peripheral
interrupts.
REGISTER 9-6: PIE1: PERIPHERAL INTERRUPT ENABLE (FLAG) REGISTER 1
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 PSPIE: Parallel Slave Port Read/Write Interrupt Enable bit(1)
1 = Enables the PSP read/write interrupt
0 = Disables the PSP read/write interrupt
bit 6 ADIE: A/D Converter Interrupt Enable bit
1 = Enables the A/D interrupt
0 = Disables the A/D inte rrupt
bit 5 RCIE: EUSART Receive Interrupt Enable bit
1 = Enables the EUSART receive interrupt
0 = Disables the EUSART receive interrupt
bit 4 TXIE: EUSART Transmit Interrupt Enable bit
1 = Enables the EUSART transmit interrupt
0 = Disables the EUSART transmit interrupt
bit 3 SSPIE: Master Synchronous Serial Port Interrupt Enable bit
1 = Enables the MSSP interrupt
0 = Disables the MSSP interrupt
bit 2 CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 inter rupt
bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
Note 1: The PSPIE bit is unimplemented on 28-pin devices and will read as ‘0’.
PIC18F2XK20/4XK20
DS40001303H-page 108 2010-2015 Microchip Technology Inc.
REGISTER 9-7: PIE2: PERIPHERAL INTERRUPT ENABLE (FLAG) REGISTER 2
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
OSCFIE C1IE C2IE EEIE BCLIE HLVDIE TMR3IE CCP2IE
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 OSCFIE: Oscillator Fail Interrupt Enable bit
1 = Enabled
0 =Disabled
bit 6 C1IE: Comparator C1 Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 5 C2IE: Comparator C2 Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 4 EEIE: Data EEPROM/Flash Write Operation Interrupt Enable bit
1 = Enabled
0 =Disabled
bit 3 BCLIE: Bus Collision Interrupt Enable bit
1 = Enabled
0 =Disabled
bit 2 HLVDIE: Low-Voltage Detect Interrupt Enable bit
1 = Enabled
0 =Disabled
bit 1 TMR3IE: TMR3 Overflow Interrupt Enable bit
1 = Enabled
0 =Disabled
bit 0 CCP2IE: CCP2 Interrupt Enable bit
1 = Enabled
0 =Disabled
2010-2015 Microchip Technology Inc. DS40001303H-page 109
PIC18F2XK20/4XK20
9.7 IPR Registers
The IPR registers contain the individual priority bits for the
peripheral interrupts. Due to the number of peripheral
interrupt sources, there are two Peripheral Interrupt
Priority reg isters (IPR1 and IP R2). Using the prio rity bits
requires that the Interrupt Priority Enable (IPEN) bit be
set.
REGISTER 9-8: IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 PSPIP: Parallel Slave Port Read/Write Interrupt Priority bit(1)
1 = High priority
0 = Low priority
bit 6 ADIP: A/D Converter Interrupt Priority bit
1 = High priority
0 = Low priority
bit 5 RCIP: EUSART Receive Interrupt Priority bit
1 = High priority
0 = Low priority
bit 4 TXIP: EUSART Transmit Interrupt Priority bit
1 = High priority
0 = Low priority
bit 3 SSPIP: Master Synchronous Serial Port Interrupt Priority bit
1 = High priority
0 = Low priority
bit 2 CCP1IP: CCP1 Interrupt Priority bit
1 = High priority
0 = Low priority
bit 1 TMR2IP: TMR2 to PR2 Match Interrupt Priority bit
1 = High priority
0 = Low priority
bit 0 TMR1IP: TMR1 Overflow Interrupt Priority bit
1 = High priority
0 = Low priority
Note 1: The PSPIF bit is unimplemented on 28-pin devices and will read as ‘0’.
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DS40001303H-page 110 2010-2015 Microchip Technology Inc.
REGISTER 9-9: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
OSCFIP C1IP C2IP EEIP BCLIP HLVDIP TMR3IP CCP2IP
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 OSCFIP: Oscillat or Fail Interrupt Priority bit
1 = High pr iority
0 = Low priority
bit 6 C1IP: Comparator C1 Interrupt Priority bit
1 = High pr iority
0 = Low priority
bit 5 C2IP: Comparator C2 Interrupt Priority bit
1 = High pr iority
0 = Low priority
bit 4 EEIP: Data EEPROM/Flash Write Operation Interrupt Priority bit
1 = High pr iority
0 = Low priority
bit 3 BCLIP: Bus Collision Interrupt Priority bit
1 = High pr iority
0 = Low priority
bit 2 HLVDIP: Low-Voltage Detect Interrupt Priority bit
1 = High pr iority
0 = Low priority
bit 1 TMR3IP: TMR3 Overflow Interrupt Priority bit
1 = High pr iority
0 = Low priority
bit 0 CCP2IP: CCP2 Interrupt Priority bit
1 = High pr iority
0 = Low priority
2010-2015 Microchip Technology Inc. DS40001303H-page 111
PIC18F2XK20/4XK20
9.8 RCON Register
The RCO N regist er conta ins flag b its whic h are used to
deter mine the cause of the last R es et or wake -up fro m
Idle or Slee p mo des . R CO N a lso contains the IPE N bit
which enables interrupt priorities.
The operation of the SBOREN bit and the Reset flag
bits is discussed in more detail in Section 4.1 “RCON
Register”.
REGISTER 9-10: RCON: RESET CONTROL REGISTER
R/W-0 R/W-1 U-0 R/W-1 R-1 R-1 R/W-0 R/W-0
IPEN SBOREN(1) —RITO PD POR(1) BOR
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 IPEN: Interrupt Priority Enable bit
1 = Enable priority levels on interrupts
0 = Disable priority levels on interrupts (Mid-Range Compatibility mode)
bit 6 SBOREN: Software BOR Enable bit(1)
For details of bit operation, see Register 4-1.
bit 5 Unimplemented: Read as ‘0’
bit 4 RI: RESET Instruction Flag bit
For details of bit operation, see Register 4-1.
bit 3 TO: Watchdog Ti me-out Flag bit
For details of bit operation, see Register 4-1.
bit 2 PD: Power-down Detection Flag bit
For details of bit operation, see Register 4-1
bit 1 POR: Power-on Reset Status bit
For details of bit operation, see Register 4-1.
bit 0 BOR: Brown-out Reset Status bit
For details of bit operation, see Register 4-1.
Note 1: Actual Reset values are determined by device configuration and the nature of the device Reset.
See Register 4-1 for additional information.
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DS40001303H-page 112 2010-2015 Microchip Technology Inc.
9.9 INTn Pin Interrupts
External interrupts on the RB0/INT0, RB1/INT1 and
RB2/INT2 p ins are edge-triggered. If the corresponding
INTEDGx bit in the INTCON2 register is set (= 1), the
interrupt is triggered by a rising edge; if the bit is clear,
the trigger is on the falling edge. When a valid edge
appears on the RBx/INTx pin, the corresponding flag
bit, INTxF, is set. This interrupt can be disabled by
clearing the corresponding enable bit, INTxE. Flag bit,
INTxF, must be cleared by software in the Interrupt
Service Routine before re-enabling the interrupt.
All extern al interrupt s (INT0, INT1 an d INT2) can wake-
up the processor from Idle or Sleep modes if bit INTxE
was set prior to going into those modes. If the Global
Interrupt Enable bit, GIE, is set, the processor will
branch to the interrupt vector following wake-up.
Interrupt priority for INT1 and INT2 is determined by the
value con tained in the inte rrupt priority bit s, INT1IP and
INT2IP o f the I NTCON3 regis ter. The re is no prio rity b it
associated with INT0. It is always a high priority inter-
rupt source.
9.10 TMR0 Interrupt
In 8-b it mod e (whic h is the de faul t), a n overfl ow in t he
TMR0 register (FFh 00h) will set flag bit, TMR0IF. In
16-bit mode, an overflow in the TMR0H:TMR0L regis-
ter pair (FFFFh 0000h) will set TMR0IF. The interrupt
can be enabled/disabled by setting/clearing enable bit,
TMR0IE of the INTCON register. Interrupt priority for
Timer0 is determined by the value contained in the
interrupt priority bit, TM R0IP of the INTCON2 register.
See Section 12.0 “Timer0 Module” for further details
on the Timer0 module.
9.11 PORTB Interrupt-on-Change
An input c ha nge on PO RTB<7:4> sets f lag bi t, R BIF of
the INTCON register. The interrupt can be enabled/
disabled by setting/clearing enable bit, RBIE of the
INTCON register. Pins must also be individually
enabled with the IOCB register. Interrupt priority for
PORTB in terrupt-on-change is determined by the value
contained in the interrupt priority bit, RBIP of the
INTCON2 regi ste r.
9.12 Context Saving During Interrupts
During interrupts, the return PC address is saved on
the stack. Additionally, the WREG, STATUS and BSR
registers are saved on the fast return stack. If a fast
return from interrupt is not used (see Section 5.1.3
“Fast R egister S tac k”), the user may need to save the
WREG, STATUS and BSR registers on entry to the
Interrupt Service Routine. Depending on the user’s
applic ation, o the r regist ers ma y also ne ed to be save d.
Example 9-1 saves and restores the WREG, STATUS
and BSR regi sters d uring an In terrupt Serv ice Rou tine.
EXAMPLE 9-1: SAVING STATUS, WREG AND BSR REGISTERS IN RAM
MOVWF W_TEMP ; W_TEMP is in virtual bank
MOVFF STATUS, STATUS_TEMP ; STATUS_TEMP located anywhere
MOVFF BSR, BSR_TEMP ; BSR_TMEP located anywhere
;
; USER ISR CODE
;
MOVFF BSR_TEMP, BSR ; Restore BSR
MOVF W_TEMP, W ; Restore WREG
MOVFF STATUS_TEMP, STATUS ; Restore STATUS
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PIC18F2XK20/4XK20
10.0 I/O PORTS
Depending on the device selected and features
enabled, there are up to five ports available. Some pins
of the I/O ports are multiplexed with an alternate
function from the peripheral features on the device. In
general, when a perip heral is ena bled, that pi n may not
be used as a general purpose I/O pin.
Each port has three registers for its operation. These
registers are:
• TRIS register (data direction regi ster)
• PORT register (rea ds the lev els on the pin s of the
device)
• LAT register (output latch)
The Dat a Latch (LAT re gister) is usef ul for read-modif y-
write operations on the value that the I/O pins are
driving.
A simplified model of a generic I/O port, without the
inter faces to other peripherals, is s hown in Figure 10-1.
FIGURE 10-1: GENERIC I/O PORT
OPERATION
10.1 PORTA, TRISA and LATA Registers
PORTA is an 8-bit wide, bidirectional port. The
corresp ond ing data direction re gis ter is TRISA. Se ttin g
a TRISA bit (= 1) will make the corresponding PORTA
pin an input (i.e., disable the output driver). Clearing a
TRISA bit (= 0) will make th e corresponding PORT A pin
an output (i.e., enable the output driver and put the
contents of the output latch on the selected pin).
Reading the PORTA register reads the status of the
pins, whe reas wri ting to it, will write to the P OR T la tch.
The Data La tch (LA TA) register is al so memory mapped.
Read-modify-write operations on the LATA register read
and write the latched output valu e for PORTA.
The RA4 pin is multiplexed with the Timer0 module
clock input and one of the comparator outputs to
become the RA4/T0CKI/C1OUT pin. Pins RA6 and
RA7 are multiplexed with the main oscillator pins; they
are enabled as oscillator or I/O pins by the selection of
the main oscillator in the Configuration register (see
Section 23.1 “Configuration Bits” for details). When
they are not used as port pins, RA6 and RA7 and their
associated TRIS and LAT bits are read as ‘0’.
The other PORTA pins are multiplexed with analog
inputs, the analog VREF+ and VREF- inputs, and the
comparator voltage reference output . The operati on of
pins RA<3:0> and RA5 as analog is selected by setting
the ANS<4:0> bits in the ANSEL register which is the
default setting after a Power-on Reset.
Pins RA0 through RA5 may also be used as comparator
inputs or outputs by setting the appropriate bits in the
CM1CON0 and CM2CON0 registers.
The R A4 / T0 CK I /C 1O UT pi n is a S c hm itt Trigg e r in p ut .
All other PORTA pins have TTL input levels and full
CMOS out put driv ers.
The TRISA register controls the drivers of the PORTA
pins, ev en w he n th ey a re being used as analog inputs.
The user should ensure the bits in the TRISA register
are maintained se t whe n using them as a nal og inputs.
EXAMPLE 10-1: INITIA LI ZING PORTA
Data
Bus
WR LAT
WR TRIS
RD Port
Data Latch
TRIS Latc h
RD TRIS
Input
Buffer
I/O pin(1)
QD
CK
QD
CK
EN
QD
EN
RD LAT
or Port
Note 1: I/O pins have diode protection to VDD and VSS.
Note: On a Power-on Reset, RA5 and RA<3:0>
are configured as analog inputs and read
as ‘0’. RA4 is co nfigur ed as a digital input.
CLRF PORTA ; Initialize PORTA by
; clearing output
; data latches
CLRF LATA ; Alternate method
; to clear output
; data latches
MOVLW E0h ; Configure I/O
MOVWF ANSEL ; for digital inputs
MOVLW 0CFh ; Value used to
; initialize data
; direction
MOVWF TRISA ; Set RA<3:0> as inputs
; RA<5:4> as outputs
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DS40001303H-page 114 2010-2015 Microchip Technology Inc.
TABLE 10-1: PORTA I/O SUMMARY
Pin Function TRIS
Setting I/O I/O
Type Description
RA0/AN0/C12IN0- RA0 0O DIG LATA<0> data output; not affect ed by analog input.
1I TTL POR TA<0> data input; disabled when analog input enabled.
AN0 1I ANA ADC input channel 0. Default input configuration on POR; does not
affect digital output.
C12IN0- 1I ANA Comparators C1 and C2 inverting input, channel 0. Analog select is
shared with ADC.
RA1/AN1/C12IN1- RA1 0O DIG LATA<1> data output; not affect ed by analog input.
1I TTL POR TA<1> data input; disabled when analog input enabled.
AN1 1I ANA ADC input channel 1. Default input configuration on POR; does not
affect digital output.
C12IN1- 1I ANA Comparators C1 and C2 inverting input, channel 1. Analog select is
shared with ADC.
RA2/AN2/C2IN+
VREF-/CVREF RA2 0O DIG LATA<2> data output; not affected by analog input. Disabled when
CVREF output enabled.
1I TTL POR TA<2> data input. Disabled when analog functions enabled;
disabled when CVREF output enabled.
AN2 1I ANA ADC input channel 2. Default input configuration on POR; not affected
by analog output.
C2IN+ 1I ANA Comparator C2 non-inverting input. Analog selection is shared with
ADC.
VREF-1I ANA ADC and comparator voltage reference low input.
CVREF xO ANA Comparator voltage reference output. Enabling this feature disables
digital I/O.
RA3/AN3/C1IN+/
VREF+RA3 0O DIG LATA<3> data output; not affected by analog input.
1I TTL POR TA<3> data input; disabled when analog input enabled.
AN3 1I A NA A/D input channel 3. Default input configuration on POR.
C1IN+ 1I ANA Comparator C1 non-inverting input. Analog selection is shared with
ADC.
VREF+1I ANA ADC and comparator voltage reference high input.
RA4/T0CKI/C1OUT RA4 0O DIG LATA<4> data output.
1I ST PORTA<4> data input; default configuration on POR.
T0CKI 1I ST Timer0 clock input.
C1OUT 0O DIG Comparator 1 output; takes priority over port data.
RA5/AN4/SS/
HLVDIN/C2OUT RA5 0O DIG LATA<5> data output; not affected by analog input.
1I TTL POR TA<5> data input; disabled when analog input enabled.
AN4 1I ANA A /D input channel 4. Default configuration on POR.
SS 1I TTL Slave select input for SSP (MSSP module).
HLVDIN 1I ANA Low-Voltage Detect external trip point input.
C2OUT 0O DIG Comparator 2 output; takes priority over port data.
OSC2/CLKOUT/
RA6 RA6 0O DIG LATA<6> data output. Enabled in RCIO, INTIO2 and ECIO modes only.
1I TTL PORTA<6> data input. Enabled in RCIO, INTIO2 and ECIO modes
only.
OSC2 xO ANA Main oscillator feedback output connection (XT, HS and LP modes).
CLKOUT xO DIG System cycle clock output (FOSC/4) in RC, INTIO1 and EC Oscillator
modes.
Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt T rigger input buffer; ANA = Analog level input/output;
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
2010-2015 Microchip Technology Inc. DS40001303H-page 115
PIC18F2XK20/4XK20
TABLE 10-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
OSC1/CLKIN/RA7 RA7 0O DIG LATA<7> data output. Disabled in external oscillator modes.
1I TTL P ORTA<7> data input. Disabled in external oscillator modes.
OSC1 xI ANA Main oscillator input connection.
CLKIN xI ANA Main clock input connection.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset
Values
on page
PORTA RA7(1) RA6(1) RA5 RA4 RA3 RA2 RA1 RA0 59
LATA LATA7(1) LATA6(1) PORTA Data Latch Register (Read and Write to Data Latch) 59
TRISA TRISA7(1) TRISA6(1) PORTA Data Direction Control Register 59
ANSEL ANS7(2) ANS6(2) ANS5(2) ANS4 ANS3 ANS2 ANS1 ANS0 59
SLRCON ———SLRE(2) SLRD(2) SLRC SLRB SLRA 60
CM1CON0 C1ON C1OUT C1OE C1POL C1SP C1R C1CH1 C1CH0 59
CM2CON0 C2ON C2OUT C2OE C2POL C2SP C2R C2CH1 C2CH0 59
CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 58
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA.
Note 1: RA<7:6> and their associated latch and data direction bits are enabled as I/O pins based on oscillator
configuration; otherwise, they are read as ‘0’.
2: Not implemen ted on PIC 18F 2XK20 devices.
TABLE 10-1: PORTA I/O SUMMARY (CONTINUED)
Pin Function TRIS
Setting I/O I/O
Type Description
Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
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DS40001303H-page 116 2010-2015 Microchip Technology Inc.
10.2 PORTB, TRISB and LATB
Registers
PORTB is an 8-bit wide, bidirectional port. The corre-
sponding data direction register is TRISB. Setting a
TRISB bit (= 1) will make the corresponding PORTB
pin an input (i.e., disable the output driver). Clearing a
TRISB bit (= 0) will make the corresponding PORTB
pin an outpu t (i.e., enabl e the output driver and put the
contents of the output latch on the selected pin).
The Data Latch register (LATB) is also memory
mapped. Read-modify-write operations on the LATB
register read and write the latched output value for
PORTB.
EXAMPLE 10-2: INITIA LIZI NG PORTB
10.3 Additional PORTB Pin Functions
PORTB pins RB<7:4> have an interrupt-on-change
option. All PORTB pins ha ve a we ak pu ll-up option. An
alternate CCP2 peripheral option is available on RB3.
10.3.1 WEAK PULL-UPS
Each of the PORTB pins has an individually controlled
weak in tern al pul l-u p. Whe n set, each bit of the WPUB
register enables the corresponding pin pull-up. When
cleared, the RBPU bit of the INTC ON2 register ena bles
pull-up s on all pins which also have their corresponding
WPUB bit set. When set, the RBPU bit disables all
weak pull-up s. The weak pull-up is automatically turned
off when the port pin is configured as an output. The
pull -ups are disabled on a Power-on Reset.
10.3.2 INTERRUPT-ON-CHANGE
Four of the PORTB pins (RB<7:4>) are individually
configurable as interrupt-on-change pins. Control bits
in the IOCB register e nable (when set) or disable (when
clear) the interrupt function for each pin.
When se t, the RBIE bit of the INTCON reg ister enab les
interr upt s o n a ll pi ns w hi ch al so ha ve the ir correspond-
ing IOCB bit set. When clear, the RBIE bit disables all
interrupt-on-changes.
Only pins configured as inputs can caus e this interrupt
to occur (i .e., any RB<7:4 > pin co nfigure d as an outp ut
is exclud ed from th e interrupt-o n-change comp arison).
For enabled interrupt-on-change pins, the values are
comp ared with the old val ue latch ed on the la st read of
PORTB. The ‘mismatch’ outputs of the last read are
OR’d together to set the PORTB Change Inte rrupt flag
bit (RBIF) in the INTCON register.
This interrupt can wake the device from the Sleep
mode, or any of the Idle modes. The user, in the
Interrupt Service Routine, can clear the interrupt in the
following manner:
a) Any read or write of PORTB to clear the mis-
match condition (except when PORTB is the
source or destination of a MOVFF instruction).
b) Clear the flag bit, RBIF.
A mismatch condition will continue to set the RBIF flag bit.
Reading or writing PORTB will end the mismatch
condition and allow the RBIF bit to be cleared. The latch
holding the last read value is not affected by a MCLR nor
Brown-out Reset. After either one of these Resets, the
RBIF flag will continue to be set if a mismatch is present.
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
10.3.3 ALT ERNATE CCP2 OPTION
RB3 can be co nfig ured as the a lter nate periph eral pin
for the CCP2 module by clearing the CCP2MX Config-
uration bit of CONFIG3H. The default state of the
CCP2MX Configuration bit is ‘1’ which selects RC1 as
the CCP2 peripheral pin.
Note: On a Power-on Reset, RB<4:0> are
configu red as analog inputs by defau lt and
read as ‘0’; RB<7:5> are configured as
digital inputs.
When the PBADEN Configuration bit is
set to ‘1’, RB<4:0> will alternatively be
configured as digital inputs on POR.
CLRF PORTB ; Initialize PORTB by
; clearing output
; data latches
CLRF LATB ; Alternate method
; to clear output
; data latches
CLRF ANSELH ; Set RB<4:0> as
; digital I/O pins
;(required if config bit
; PBADEN is set)
MOVLW 0CFh ; Value used to
; initialize data
; direction
MOVWF TRISB ; Set RB<3:0> as inputs
; RB<5:4> as outputs
; RB<7:6> as inputs
Note: If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the RBIF
interrupt flag may not get set. Furthermore,
since a read or write on a port affects all
bits of that port, care must be taken when
using multiple pins in Interrupt-on-change
mode. Changes on one pin may not be
seen while servicing changes on another
pin.
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PIC18F2XK20/4XK20
TABLE 10-3: PORTB I/O SUMMARY
Pin Function TRIS
Setting I/O I/O
Type Description
RB0/INT0/FLT0/
AN12 RB0 0O DIG LATB<0> data output; not affected by analog input.
1I TTL PORTB<0> data input; Programmable weak pull-up. Disabled when
analog input enabled.(1)
INT0 1I ST External interrupt 0 input.
FLT0 1I ST Enhanced PWM Fault input (ECCP1 module); enabled by software.
AN12 1I ANA A/D input channel 12.(1)
RB1/INT1/AN10/
C12IN3-/P1C RB1 0O DIG LATB<1> data output; not affected by analog input.
1I TTL PORTB<1> data input; Programmable weak pull-up. Disabled when
analog input enabled.(1)
INT1 1I ST External Interrupt 1 input.
AN10 1I ANA ADC input channel 10.(1)
C12IN3- 1I ANA Comparators C1 and C2 inverting input, channel 3. Analog select is
shared with ADC.
P1C 0O DIG ECCP PW M output (28-pin devices only).
RB2/INT2/AN8/
P1B RB2 0O DIG LATB<2> data output; not affected by analog input.
1I TTL PORTB<2> data input; Programmable weak pull-up. Disabled when
analog input enabled.(1)
INT2 1I ST External interrupt 2 input.
AN8 1I ANA ADC input channel 8.(1)
P1B 0O DIG ECCP PW M output (28-pin devices only).
RB3/AN9/C12IN2-/
CCP2 RB3 0O DIG LATB<3> data output; not affected by analog input.
1I TTL PORTB<3> data input; Programmable weak pull-up. Disabled when
analog input enabled.(1)
AN9 1I ANA ADC input channel 9.(1)
C12IN2- 1I ANA Comparators C1 and C2 inverting input, channel 2. Analog select is
shared with ADC.
CCP2(2) 0O DIG CCP2 compare and PWM output.
1I ST CCP2 capture input
RB4/KBI0/AN11/
P1D RB4 0O DIG LATB<4> data output; not affected by analog input.
1I TTL PORTB<4> data input; Programmable weak pull-up. Disabled when
analog input enabled.(1)
KBI0 1I TTL Interrupt-on-pin change.
AN11 1I ANA ADC input channel 11.(1)
P1D 0O DIG ECCP PW M output (28-pin devices only).
RB5/KBI1/PGM RB5 0O DIG LATB<5> data output.
1I TTL PORTB<5> data input; Programmable weak pull-up.
KBI1 1I TTL Interrupt-on-pin change.
PGM xI ST Single-Supply Programming mode entry (ICSP™). Enabled by LVP
Configuration bit; all other pin functions disabled.
Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Note 1: Configuration on POR is determined by the PBADEN Configuration bit. Pins are configured as analog inputs by default
when PBADEN is set and digital inputs when PBADEN is cleared.
2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is ‘0’. Default assignment is RC1.
3: All other pin functions are disabled when ICSP or ICD are enabled.
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DS40001303H-page 118 2010-2015 Microchip Technology Inc.
TABLE 10-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
RB6/KBI2/PGC RB6 0O DIG LATB<6> data output.
1I TTL PORTB<6> data input; Programmable weak pull-up.
KBI2 1I TTL Interrupt-on-pin change.
PGC xI ST Serial execution (ICSP) clock input for ICSP and ICD operation.(3)
RB7/KBI3/PGD RB7 0O DIG LATB<7> data output.
1I TTL PORTB<7> data input; Programmable weak pull-up.
KBI3 1I TTL Interrupt-on-pin change.
PGD xO DIG Serial execution data output for ICSP and ICD operation.(3)
xI ST Serial execution data input for ICSP and ICD operation.(3)
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset
Values
on page
PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 59
LATB PORTB Data Latch Register (Read and Write to Data Latch) 59
TRISB PORTB Data Direction Control Register 59
WPUB WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 59
IOCB IOCB7 IOCB6 IOCB5 IOCB4 — — — —59
SLRCON — — — SLRE(1) SLRD(1) SLRC SLRB SLRA 60
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 56
INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 —TMR0IP —RBIP56
INTCON3 INT2IP INT1IP —INT2IEINT1IE— INT2IF INT1IF 56
ANSELH — — — ANS12 ANS11 ANS10 ANS9 ANS8 59
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTB.
Note 1: Not implemented on PIC 18F 2XK20 devices.
TABLE 10-3: PORTB I/O SUMMARY (CONTINUED)
Pin Function TRIS
Setting I/O I/O
Type Description
Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt T rigger input buffer; ANA = Analog level input/output;
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Note 1: Configuration on POR is determined by the PBADEN Configuration bit. Pins are configured as analog inputs by default
when PBADEN is set and digital inputs when PBADEN is cleared.
2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is ‘0’. Default assignment is RC1.
3: All other pin functions are disabled when ICSP or ICD are enabled.
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PIC18F2XK20/4XK20
10.4 PORTC, TRISC and LATC
Registers
PORTC is an 8-bit wide, bidirectional port. The corre-
sponding data direction register is TRISC. Setting a
TRISC bit (= 1) will make the corresponding PORTC
pin an input (i.e., disable the output driver). Clearing a
TRISC bit (= 0) will make the corresponding PORTC
pin an outpu t (i.e., enabl e the output driver and put the
contents of the output latch on the selected pin).
The Data Latch register (LATC) is also memory
mapped. Read-modify-write operations on the LATC
register read and write the latched output value for
PORTC.
PORT C is multip lexed with s everal periphe ral function s
(Table 10-5) . The p ins have Schmitt Trig ger in put buf-
fers. RC1 is the default configuration for the CCP2
peripheral pin. The CCP2 function can be relocated to
the RB3 pin by clearing the CCP2MX bit of Configura-
tion Word CONFIG3H. The default state of the
CCP2MX Configuration bit is ‘1’.
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTC pin. The
EUSART and MSSP peripherals override the TRIS bit
to make a pin an output or an input, depending on the
peripheral configuration. Refer to the corresponding
peripheral section for additional information.
The contents of the TRISC register are affected by
peripheral overrides. Reading TRISC always returns
the current contents, even though a peripheral device
may be overriding one or more of the pins.
EXAMPLE 10-3: INITIALIZING PORTC
Note: On a Power-on Res et, these pins are con-
figured as digital inputs.
CLRF PORTC ; Initialize PORTC by
; clearing output
; data latches
CLRF LATC ; Alternate method
; to clear output
; data latches
MOVLW 0CFh ; Value used to
; initialize data
; direction
MOVWF TRISC ; Set RC<3:0> as inputs
; RC<5:4> as outputs
; RC<7:6> as inputs
PIC18F2XK20/4XK20
DS40001303H-page 120 2010-2015 Microchip Technology Inc.
TABLE 10-5: PORTC I/O SUMMARY
Pin Function TRIS
Setting I/O I/O
Type Description
RC0/T1OSO/
T13CKI RC0 0O DIG LATC<0> data output.
1I ST PORTC<0> data input.
T1OSO xO ANA Timer1 oscillator output; enabled when T imer1 oscillator enabled.
Disables digital I/O.
T13CKI 1I ST Timer1/T imer3 counter input.
RC1/T1OSI/CCP2 RC1 0O DIG LATC<1> data output.
1I ST PORTC<1> data input.
T1OSI xI ANA Timer1 oscillator input; enabled when Timer1 oscillator enabled.
Disables digital I/O.
CCP2(1) 0O DIG CCP2 compare and PWM output; takes priority over port data.
1I ST C CP2 capt ure input.
RC2/CCP1/P1A RC2 0O DIG LATC<2> data output.
1I ST PORTC<2> data input.
CCP1 0O DIG ECCP1 compare or PWM output; takes priority over port data.
1I ST ECCP1 capture input.
P1A 0O DIG ECCP1 Enhanced PWM output, channel A. May be configured for
tri-state during Enhanced PWM shutdown events. Takes priority over
port data.
RC3/SCK/SCL RC3 0O DIG LATC<3> data output.
1I ST PORTC<3> data input.
SCK 0O D IG S PI clock output (MSSP module); takes priority over port data.
1I ST S PI clock in put (MSSP module).
SCL 0ODIGI
2C™ clock output (MSSP module); takes priority over port data.
1II
2C/SMB I2C clock input (MSSP module); input type depends on module setting.
RC4/SDI/SDA RC4 0O DIG LATC<4> data output.
1I ST PORTC<4> data input.
SDI 1I ST SPI data input (MSSP module).
SDA 1ODIGI
2C data output (MSSP module); takes priority over port data.
1II
2C/SMB I2C data input (MSSP module); input type depends on module setting.
RC5/SDO RC5 0O DIG LATC<5> data output.
1I ST PORTC<5> data input.
SDO 0O D IG S PI data output (MSSP module); takes priority over port data.
RC6/TX/CK RC6 0O DIG LATC<6> data output.
1I ST PORTC<6> data input.
TX 1O DIG Asynchronous serial transmit data output (EUSART module); takes
priority over port data. User must configure as output.
CK 1O DIG Sync hronous serial clock outpu t (EUSART module); takes priority over
port data.
1I ST S ync hronous serial clock input (EUSART module).
RC7/RX/DT RC7 0O DIG LATC<7> data output.
1I ST PORTC<7> data input.
RX 1I ST Asynchronous serial receive data input (EUSART module).
DT 1O DIG Synchronous serial data output (EUSART module); takes priority over
port data.
1I ST S ync hronous serial data input (EUSART module). User must configure
as an input.
Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt T rigger input buffer; ANA = Analog level input/output;
I2C/SMB = I2C/SMBus input b uffer; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set. Alternate assignment is RB3.
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PIC18F2XK20/4XK20
TABLE 10-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset
Values
on page
PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 59
LATC PORTC Data Latch Register (Read and Write to Data Latch) 59
TRISC PORTC Data Direction Control Register 59
T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 57
T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 58
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 58
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 58
SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 57
CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 58
CCP2CON — — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 58
ECCP1AS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 58
SLRCON ———SLRE(1) SLRD(1) SLRC SLRB SLRA 60
Legend: — = unimplemented, read as ‘0’. Shaded cells are no t used by PORTC.
Note 1: Not implemented on PIC18F2XK20 devices.
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DS40001303H-page 122 2010-2015 Microchip Technology Inc.
10.5 PORTD, TRISD and LATD
Registers
PORTD is an 8-bit wide, bidirectional port. The corre-
sponding data direction register is TRISD. Setting a
TRISD bit (= 1) will make the corresponding PORTD
pin an input (i.e., disable the output driver). Clearing a
TRISD bit (= 0) will make the corresponding PORTD
pin an outpu t (i.e., enabl e the output driver and put the
contents of the output latch on the selected pin).
The Data Latch register (LATD) is also memory
mapped. Read-modify-write operations on the LATD
register read and write the latched output value for
PORTD.
All pins on PORTD are implemented with Schmitt Trig-
ger input buffers. Each pin is individually configurable
as an input or output.
Three of the PORTD pins are multiplexed with outputs
P1B, P1C an d P1D of t he enha nced CCP modul e. The
operation of these additional PWM output pins is
covered in greater detail in Section 16.0 “Enhanced
Capture/Compare/PWM (ECCP) Module”.
POR TD can also be configured as an 8- bit w id e m icr o-
processor port (Parallel Slave Port) by setting control
bit, PSPMODE (TRISE<4>). In this mode, the input
buffers are TTL. See Section 10.9 “Parallel Slave
Port” for additional information on the Parallel Slave
Port (PSP).
EXAMPLE 10-4: INITIALIZING PORTD
Note: PORTD is only available on 40/44-pin
devices.
Note: On a Power-on Reset, these pins are
configured as digital inputs.
Note: When the enhanced PWM mode is used
with either dual or quad outputs, the PSP
functions of PORTD are automatically
disabled.
CLRF PORTD ; Initialize PORTD by
; clearing output
; data latches
CLRF LATD ; Alternate method
; to clear output
; data latches
MOVLW 0CFh ; Value used to
; initialize data
; direction
MOVWF TRISD ; Set RD<3:0> as inputs
; RD<5:4> as outputs
; RD<7:6> as inputs
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PIC18F2XK20/4XK20
TABLE 10-7: PORTD I/O SUMMARY
Pin Function TRIS
Setting I/O I/O
Type Description
RD0/PSP0 RD0 0O DIG LATD<0> data output.
1I ST PORTD<0> data input.
PSP0 xO DIG P SP read data output (LATD<0>); takes priority over port data.
xI TTL PSP write data input.
RD1/PSP1 RD1 0O DIG LATD<1> data output.
1I ST PORTD<1> data input.
PSP1 xO DIG P SP read data output (LATD<1>); takes priority over port data.
xI TTL PSP write data input.
RD2/PSP2 RD2 0O DIG LATD<2> data output.
1I ST PORTD<2> data input.
PSP2 xO DIG P SP read data output (LATD<2>); takes priority over port data.
xI TTL PSP write data input.
RD3/PSP3 RD3 0O DIG LATD<3> data output.
1I ST PORTD<3> data input.
PSP3 xO DIG P SP read data output (LATD<3>); takes priority over port data.
xI TTL PSP write data input.
RD4/PSP4 RD4 0O DIG LATD<4> data output.
1I ST PORTD<4> data input.
PSP4 xO DIG P SP read data output (LATD<4>); takes priority over port data.
xI TTL PSP write data input.
RD5/PSP5/P1B RD5 0O DIG LATD<5> data output.
1I ST PORTD<5> data input.
PSP5 xO DIG P SP read data output (LATD<5>); takes priority over port data.
xI TTL PSP write data input.
P1B 0O DIG ECCP1 Enhanced PWM output, channel B; t akes priority over port and
PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
RD6/PSP6/P1C RD6 0O DIG LATD<6> data output.
1I ST PORTD<6> data input.
PSP6 xO DIG P SP read data output (LATD<6>); takes priority over port data.
xI TTL PSP write data input.
P1C 0O DIG ECCP1 Enhanced PWM output, channel C; takes priority over port and
PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
RD7/PSP7/P1D RD7 0O DIG LATD<7> data output.
1I ST PORTD<7> data input.
PSP7 xO DIG P SP read data output (LATD<7>); takes priority over port data.
xI TTL PSP write data input.
P1D 0O DIG ECCP1 Enhanced PWM output, channel D; takes priority over port and
PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; x = Don’t care
(TRIS bit does not affect port direction or is overridden for this option).
PIC18F2XK20/4XK20
DS40001303H-page 124 2010-2015 Microchip Technology Inc.
TABLE 10-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset
Values
on page
PORTD(1) RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 59
LATD(1) PORTD Data Latch Register (Read and Write to Data La tch) 59
TRISD(1) PORT D Data Direction Control Register 59
TRISE(1) IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 59
CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 58
SLRCON — — — SLRE(1) SLRD(1) SLRC SLRB SLRA 60
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTD.
Note 1: Not implemented on PIC 18F 2XK20 devices.
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PIC18F2XK20/4XK20
10.6 PORTE, TRISE and LATE
Registers
Depending on the particular PIC18F2XK20/4XK20
device selected, PORTE is implemented in two
different ways.
10.6.1 PORTE IN PIC18F4XK20 DEVICES
For PIC18F4XK20 devices, POR TE is a 4-bit wide port.
Thre e pi n s (RE 0 /R D/AN5, RE1/WR/AN6 and RE2/CS/
AN7) are i ndi vi dually configurab le as i nputs or outputs.
These pins have Schmitt Trigger input buffers. When
select ed as an analog input, these pins will read as ‘0’s.
The corresponding data direction register is TRISE.
Setting a TRISE bit (= 1) will make the corresponding
PORTE pin an input (i.e., disable the output driver).
Clearing a TR ISE bit (= 0) will make the corresponding
PORT E pin an output (i .e., e nable th e output dri ver and
put the contents of the ou tput latch on the selected pin).
TRISE controls the direction of the RE pins, even when
they are being used as analog inputs. The user must
make sure to keep the pins configured as inputs when
using them as analog inputs.
The upper four bits of the TRISE register also control
the operati on of the Parallel Slav e Port. Their operatio n
is explained in Register 10-1.
The Data Latch register (LATE) is also memory
mapped. Read-modify-write operations on the LATE
register, read and write the latched output value for
PORTE.
The fourth pin of PORTE (MCLR/VPP/RE3) is an input
only pin. Its operation is controlled by the MCLRE
Configuration bit. When selected as a port pin
(MCLRE = 0), it functions as a digital input only pin; as
such, it does not have TRIS or LA T bits associated with its
operation. Otherwise, it function s as the device’s Master
Clear input. In either configuration, RE3 also functions as
the programming voltage input during programming.
EXAMPLE 10-5: INITIALIZING PORTE
10.6.2 PORTE IN PIC18F2XK20 DEVICES
For PIC18F2XK20 devices, PORTE is only available
when Master Clear functionality is disabled
(MCLR = 0). In these cases, PORTE is a single bit,
input only port comprised of RE3 only . The pin operates
as previously described.
Note: On a Power-on Reset, RE<2:0> are
configured as analog inputs.
Note: On a Power-on Reset, RE3 is enabled as
a digital input only if Master Clear
functionality is disabled.
CLRF PORTE ; Initialize PORTE by
; clearing output
; data latches
CLRF LATE ; Alternate method
; to clear output
; data latches
MOVLW 1Fh ; Configure analog pins
ANDWF ANSEL,w ; for digital only
MOVLW 05h ; Value used to
; initialize data
; direction
MOVWF TRISE ; Set RE<0> as input
; RE<1> as output
; RE<2> as input
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DS40001303H-page 126 2010-2015 Microchip Technology Inc.
REGISTER 10-1 : TRISE: PORT E/PSP CONTROL REGISTER (PIC18F4XK20 DEVICES ONLY)
R-0 R-0 R/W-0 R/W-0 U-0 R/W-1 R/W-1 R/W-1
IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 IBF: Input Buffer Full Status bit
1 = A word has been received and waiting to be read by the CPU
0 = No word has been received
bit 6 OBF: Output Buffer Full Status bit
1 = The output buffer still holds a previously written word
0 = The output buffer has been read
bit 5 IBOV: Input Buffer Overflow Detect bit (in Microprocessor mode)
1 = A write occurred when a previously input word has not been read (must be cleared by software)
0 = No overflow occurred
bit 4 PSPMODE: Parallel Slave Port Mode Select bit
1 = Parallel Slave Port mode
0 = General purpose I/O mode
bit 3 Unimplemented: Read as ‘0’
bit 2 TRISE2: RE2 Direction Control bit
1 = Input
0 = Output
bit 1 TRISE1: RE1 Direction Control bit
1 = Input
0 = Output
bit 0 TRISE0: RE0 Direction Control bit
1 = Input
0 = Output
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PIC18F2XK20/4XK20
TABLE 10-9: PORTE I/O SUMMARY
TABLE 10-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Pin Function TRIS
Setting I/O I/O
Type Description
RE0/RD/AN5 RE0 0O DIG LATE<0> data output; not affected by analog input.
1I ST PORTE<0> data input; disabled when analog input enabled.
RD 1I TTL PSP read enable input (PSP enabled).
AN5 1I ANA A/D input channel 5; default input configuration on POR.
RE1/WR/AN6 RE1 0O DIG LATE<1> data output; not affected by analog input.
1I ST PORTE<1> data input; disabled when analog input enabled.
WR 1I T TL PSP write enable input (PSP enabled).
AN6 1I ANA A/D input channel 6; default input configuration on POR.
RE2/CS/AN7 RE2 0O DIG LATE<2> data output; not affected by analog input.
1I ST PORTE<2> data input; disabled when analog input enabled.
CS 1I T TL PSP write enable input (PSP enabled).
AN7 1I ANA A/D input channel 7; default input configuration on POR.
MCLR/VPP/
RE3(1,2) MCLR — I ST External Master Clear input; enabled when MCLRE Configuration bit is
set.
VPP — I ANA High-voltage detection; used for ICSP™ mode entry detection. Always
available, regardless of pin mode.
RE3 —(2) I ST PORTE<3> data input; enabled when MCLRE Configuration bit is
clear.
Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Note 1: RE3 is available on both PIC18F2XK20 and PIC18F4XK20 devices. All other PORTE pins are only implemented on
PIC18F4XK20 devices.
2: RE3 does not have a corresponding TRIS bit to control data direction.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset
Values
on page
PORTE — — — —RE3
(1,2) RE2 RE1 RE0 59
LATE(2) — — — — — LATE Data O u tput Register 59
TRISE(3) IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 59
SLRCON — — —SLRE
(3) SLRD(3) SLRC SLRB SLRA 60
ANSEL ANS7(3) ANS6(3) ANS5(3) ANS4 ANS3 ANS2 ANS1 ANS0 59
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTE.
Note 1: Implemented only when Master Clear functionality is disabled (MCLRE Configuration bit = 0).
2: RE3 is the only PORTE bit implemented on both PIC18F2XK20 and PIC18F4XK20 de vices. All other bits
are implemented only when PORTE is implemented (i.e., PIC18F4XK20 devices).
3: Unimplemented on PIC18F2XK20 devic es .
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DS40001303H-page 128 2010-2015 Microchip Technology Inc.
10.7 Port Analog Control
Some port pins are multiplexed with analog functions
such as the Analog-to-Digital Converter and compara-
tors. When these I/O pins are to be used as analog
inputs it is necessary to disable the digital input buffer
to avoid excessive current caused by improper biasing
of the digital input. Individual control of the digital i nput
buffers on pins which share analog functions is pro-
vided b y the ANSEL an d ANSELH registe rs. Setting a n
ANSx bit high will disable the associated digital input
buffer and cause all reads of that pin to return ‘0’ while
allowing analog functions of that pin to operate
correctly.
The state of the ANSx bits has no affect on digital
output functions. A pin with the associated TRISx bit
clear and ANSx bit set will still operate as a digital
output but the input mode will be analog. This can
cause unexpected behavior when performing read-
modify-write operations on the affected port.
REGISTER 10-2: ANSEL: ANALOG SELECT REGISTER 1
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
ANS7(1) ANS6(1) ANS5(1) ANS4 ANS3 ANS2 ANS1 ANS0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 ANS7: RE2 Analog Select Control bit(1)
1 = Digital input buffer of RE2 is disabled
0 = Digital input buffer of RE2 is enabled
bit 6 ANS6: RE1 Analog Select Control bit(1)
1 = Digital input buffer of RE1 is disabled
0 = Digital input buffer of RE1 is enabled
bit 5 ANS5: RE0 Analog Select Control bit(1)
1 = Digital input buffer of RE0 is disabled
0 = Digital input buffer of RE0 is enabled
bit 4 ANS4: RA5 Analog Select Control bit
1 = Digital input buffer of RA5 is disabled
0 = Digital input buffer of RA5 is enabled
bit 3 ANS3: RA3 Analog Select Control bit
1 = Digital input buffer of RA3 is disabled
0 = Digital input buffer of RA3 is enabled
bit 2 ANS2: RA2 Analog Select Control bit
1 = Digital input buffer of RA2 is disabled
0 = Digital input buffer of RA2 is enabled
bit 1 ANS1: RA1 Analog Select Control bit
1 = Digital input buffer of RA1 is disabled
0 = Digital input buffer of RA1 is enabled
bit 0 ANS0: RA0 Analog Select Control bit
1 = Digital input buffer of RA0 is disabled
0 = Digital input buffer of RA0 is enabled
Note 1: These bits are not implemented on PIC18F2XK20 devices.
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PIC18F2XK20/4XK20
REGISTER 10-3: ANSELH: ANALOG SELECT REGISTER 2
U-0 U-0 U-0 R/W-1(1)R/W-1(1)R/W-1(1)R/W-1(1)R/W-1(1)
— — — ANS12 ANS11 ANS10 ANS9 ANS8
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-5 Unimplemented: Read as ‘0’
bit 4 ANS12: RB0 Analog Select Control bit
1 = Digital input buffer of RB0 is disabled
0 = Digital input buffer of RB0 is enabled
bit 3 ANS11: RB4 Anal og Select Control bit
1 = Digital input buffer of RB4 is disabled
0 = Digital input buffer of RB4 is enabled
bit 2 ANS10: RB1 Analog Select Control bit
1 = Digital input buffer of RB1 is disabled
0 = Digital input buffer of RB1 is enabled
bit 1 ANS9: RB3 Analog Select Control bit
1 = Digital input buffer of RB3 is disabled
0 = Digital input buffer of RB3 is enabled
bit 0 ANS8: RB2 Analog Select Control bit
1 = Digital input buffer of RB2 is disabled
0 = Digital input buffer of RB2 is enabled
Note 1: Default state is determined by the PBADEN bit of CONFIG3H. The default state is ‘0’ When
PBADEN = ‘0’.
PIC18F2XK20/4XK20
DS40001303H-page 130 2010-2015 Microchip Technology Inc.
10.8 Port Slew Rate Control
The output slew rate of each port is programmable to
select either the standard transition rate or a reduced
transition rate of 0.1 times the standard to minimize
EMI. The reduced transition time is the default slew
rate for all ports.
REGISTER 10-4: SLRCON: SLEW RATE CONTROL REGISTER
U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
— — —SLRE
(1)SLRD(1)SLRC SLRB SLRA
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-5 Unimplemented: Read as ‘0’
bit 4 SLRE: PORTE Slew Rate Control bit(1)
1 = All outputs on PORTE slew at a limited rate
0 = All outputs on PORTE slew at the standard rate
bit 3 SLRD: PORTD Slew Rate Control bit(1)
1 = All outputs on PORTD slew at a limited rate
0 = All outputs on PORTD slew at the standard rate
bit 2 SLRC: PORTC Slew Rate Control bit
1 = All outputs on PORTC slew at a limited rate
0 = All outputs on PORTC slew at the standard rate
bit 1 SLRB: PORTB Slew Rate Control bit
1 = All outputs on PORTB slew at a limited rate
0 = All outputs on PORTB slew at the standard rate
bit 0 SLRA: PORTA Slew Rate Control bit
1 = All outputs on PORTA slew at a limited rate(2)
0 = All outputs on PORTA slew at the standard rate
Note 1: These bits are not implemented on PIC18F2XK20 devices.
2: The slew rate of RA6 defaults to standard rate when the pin is used as CLKOUT.
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PIC18F2XK20/4XK20
10.9 Parallel Slave Port
In addition to its function as a general I/O port, PORTD
can also operate as an 8-bit wide Parallel Slave Port
(PSP) or microprocessor port. PSP operation is
controlled by the four upper bits of the TRISE register
(Register 10-1). Setting control bit, PSPMODE
(TRISE<4>), enables PSP operation as long as the
enhanced CCP module is not operating in dual output
or quad output PWM mode. In Slave mode, the port is
asynchronously readable and writable by the external
world.
The PSP can directly interface to an 8-bit
microprocess or data b us. Th e e xter na l microp ro cessor
can read or write the PORTD latch as an 8-bit latch.
Setting the control bit, PSPMODE, enables the PORTE
I/O pins to become control inputs for the microprocessor
port. When set, port pin RE0 is the RD input, RE1 is the
WR input and RE2 is the CS (Chip Select) input. For this
functionality , the corresponding data direction bits of the
TRISE register (TRISE<2:0>) must be configured as
inputs (set) and the ANSEL<7:5> bits must be cleared.
A write to the PSP occurs when both the CS and WR
lines are first detected low and ends when either are
detecte d high. The PSPIF and IBF flag bits are both s et
when the write ends.
A read from t he PSP occurs when both the CS and RD
lines are first detected low. The data in PORTD is read
out and the O BF bit is c lear. If the use r writes new dat a
to POR TD to set OBF, the dat a is imme diately read ou t;
however, the OBF bit is not set.
When either the CS or RD lines are detected high, the
PORT D pins retu rn to the inpu t sta te and th e PSPIF bit
is set. Use r applications should wait for PSPIF t o be set
before servicing the PSP; when this happens, the IBF
and OBF bits can be polled and the appropriate action
taken.
The timing for the control signals in Write and Read
modes is shown in Figure 10-3 and Figure 10-4,
respectively.
FIGURE 10-2: PORTD AND PORTE
BLOCK DIAGRAM
(PARALLEL SLAVE PORT)
Note: The Parallel Slave Port is only available
on PIC18F4XK20 devices.
Data Bus
WR LATD RDx pin
QD
CK
EN
QD
EN
RD PORTD
One bit of PORTD
Set Inte rrupt Flag
PSPIF (PIR1< 7>)
Read
Chip Select
Write
RD
CS
WR
TTL
TTL
TTL
TTL
or
WR PORTD
RD LATD
Data Latch
Note: I/O pins have diode protection to VDD and VSS.
PORTE Pins
PIC18F2XK20/4XK20
DS40001303H-page 132 2010-2015 Microchip Technology Inc.
FIGURE 10-3: PARALLEL SLAVE PORT WRITE WAVEFORMS
FIGURE 10-4: PARALLEL SLAVE PORT READ WAVEFORMS
Q1 Q2 Q3 Q4
CS
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
WR
RD
IBF
OBF
PSPIF
PORTD<7:0>
Q1 Q2 Q3 Q4
CS
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
WR
IBF
PSPIF
RD
OBF
PORTD<7:0>
2010-2015 Microchip Technology Inc. DS40001303H-page 133
PIC18F2XK20/4XK20
TABLE 10-11: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset
Values
on page
PORTD(1) RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 59
LATD(1) PORTD Data Latch Register (Read and Write to Data Latch) 59
TRISD(1) PORTD Data Direction Control Register 59
PORTE — — — — RE3 RE2(1) RE1(1) RE0(1) 59
LATE(1) — — — — — LATE Data Output bits 59
TRISE(1) IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 59
SLRCON — — —SLRE
(1) SLRD(1) SLRC SLRB SLRA 60
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 56
PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 59
PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 59
IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 59
ANSEL ANS7(1) ANS6(1) ANS5(1) ANS4 ANS3 ANS2 ANS1 ANS0 59
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Parallel Slave Port.
Note 1: Unimpleme nte d on PIC1 8F2 XK20 dev ic es .
PIC18F2XK20/4XK20
DS40001303H-page 134 2010-2015 Microchip Technology Inc.
11.0 CAPTURE/COMP ARE/ PWM
(CCP) MODULES
PIC18F2XK20/4XK20 devices have two CCP
Capture/Compare/PWM) modules. Each module
cont ains a 16-bi t regis ter wh ich can operate as a 1 6-bit
Capture register, a 16-bit Compare register or a PWM
Master/Sl ave Dut y Cycle register.
CCP1 is implemented as an enhanced CCP module with
standard Capture and Compare modes and enhanced
PWM modes. The ECCP implementation is discussed in
Section 16.0 “Enhanced Capture/Compare/PWM
(ECCP) Module”. CCP2 is implemented as a standard
CCP m odu le without th e en ha nc ed fe atures.
The Ca pture and Comp are opera tions de scribed in this
chapter apply to both standard and enhanced CCP
modules.
Note: Throughout this section and Section 16.0
“Enhanced Capture/Compare/PWM
(ECCP) Module”, references to the register
and bit names for CCP modules are referred
to generi call y by the use of ‘x’ or ‘y ’ in plac e of
the specific module number. Thus,
“CCPxCON” mi ght ref er t o th e c ontro l re gi st er
for CCP1, CCP2 or ECCP1. “CCPxCON” is
used thro ughout these sections to refer to t he
module control register , regardless of whether
the CCP module is a standard or enhanced
implementation.
REGISTER 11-1: CCP2CON: STANDARD CAPTURE/COMPARE/PWM CONTROL REGISTER
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—— DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 Unimplemented: Read as ‘0’
bit 5-4 DC2B<1:0>: PWM Duty Cycle bit 1 and bit 0 for CCP2 Module
Capture mode:
Unused.
Compare mode:
Unused.
PWM mode:
These bits are the two LSbs (bit 1 and bit 0) of the 10-bit PWM duty cycle. The eight MSbs
(DC2B<9:2>) of the duty cycle are found in CCPR2L.
bit 3-0 CCP2M<3:0>: CCP2 Mode Select bits
0000 = Capture/Compare/PWM disabled (resets CCP2 module)
0001 = Reserved
0010 = Compare mode, toggle output on match (CCP2IF bit is set)
0011 = Reserved
0100 = Capture mode, every falling edge
0101 = Capture mode, every rising edge
0110 = Capture mode, ev ery 4th ri sing edge
0111 = Capture mode, ever y 16th rising edge
1000 = C ompare mode: initialize CCP2 pin low; on compare match, force CCP2 pin high
(CCP2IF bit is set)
1001 = C ompare mode: initialize CCP2 pin high; on compare match, force CCP2 pin low
(CCP2IF bit is set)
1010 = Compare mode: generate software interrupt on comp are match (CCP2IF bit is set,
CCP2 pin reflect s I/O st ate)
1011 = C ompare mode: trigger special event, reset timer, start A/D conversion on
CCP2 match (CCP2IF bit is set)
11xx =PWM mode
2010-2015 Microchip Technology Inc. DS40001303H-page 135
PIC18F2XK20/4XK20
11.1 CCP Module Configuration
Each Capture/Compare/PWM module is associated
with a control register (generically, CCPxCON) and a
data register (CCPRx). The data register, in turn, is
comprised of two 8-bit registers: CCPRxL (low byte)
and CCPRxH (high byte). All registers are both
readable and writable.
11.1.1 CCP MODULES AND TIMER
RESOURCES
The CCP modules utilize Timers 1, 2 or 3, depending
on the mo de selected. T imer1 and T imer3 are available
to modules in Capture or Compare modes, while
Timer2 is available for modules in PWM mode.
TABLE 11-1: CCP MODE – TIMER
RESOURCE
The assignment of a particular timer to a module is
determined by the Timer-to-CCP enable bits in the
T3CON register (Register 15-1). Both modules can be
active at the same time and can share the same timer
resource if they are configured to operate in the same
mode (Capture/Compare or PWM). The interactions
between the two modules are summarized in Figure 11-1
and Figure 11-2. In Asynchronous Counter mode, the
capture operation will not work reliably .
11.1.2 CCP2 PIN ASSIGNMENT
The pin as signment fo r CCP2 (Capture inpu t, Compare
and PW M output) c an chang e, based o n device config-
uratio n. The CCP2MX Configurat ion bit determ ines the
pin with which CCP2 is multiplexed. By default, it is
assign ed to RC1 (C CP2MX = 1). If the Configuration bit
is cleared, CCP2 is multiplexed with RB3.
Changing the pin assignment of CCP2 does not
automatically change any requirements for configuring
the port pin. Users must always verify that the
appropriate TRIS register is configured correctly for
CCP2 operation, regardless of where it is located.
TABLE 11-2: INTERACTIONS BETWEEN CCP1 AND CCP2 FOR TIMER RESOURCES
CCP/ECCP Mode Timer Resource
Capt ure Timer1 or Timer3
Compare Timer1 or Timer3
PWM Timer2
CCP1 Mode CCP2 Mode Interaction
Capture Capture Each module can use TMR1 or TMR3 as the time base. The time base can be different
for each CCP.
Capture Compare CCP2 can be configured for the Special Event Trigger to reset TMR1 or TMR3
(depending upon which time base is used). Automatic A/D conversions on trigger event
can also be done. Operation of CCP1 could be affected if it is using the same timer as a
time base.
Compare Capture CCP1 can be configured for the Special Event Trigger to reset TMR1 or TMR3
(depending upon which time base is used). Operation of CCP2 could be affected if it is
using the same timer as a time base.
Compare Compare Either module can be configured for the Special Event Trigger to reset the time base.
Automatic A/D conversions on CCP2 trigger event can be done. Conflicts may occur if
both modules are using the same time base.
Capture PWM None
Compare PWM None
PWM(1) Capture None
PWM(1) Compare None
PWM(1) PWM Both PWMs will have the same frequency and update rate (TMR2 interrupt).
Note 1: Includes standard and enhanced PWM operation.
PIC18F2XK20/4XK20
DS40001303H-page 136 2010-2015 Microchip Technology Inc.
11.2 Capture Mode
In Capture mode, the CCPRxH:CCPRxL register pair
captures the 16-bit value of the TMR1 or TMR3
registers when an event occurs on the corresponding
CCPx pin. An event is defined as one of the following:
• every falling edge
• every rising edge
• every 4th rising edge
• every 16th rising edge
The event is selected by the mode select bits,
CCPxM<3:0> of the CCPxCON register. When a cap-
ture is made, the interrupt request flag bit, CCPxIF, is
set; it must be cleared by software. If another capture
occurs before the value in register CCPRx is read, the
old captured value is overwritten by the new captured
value.
11.2.1 CCP PIN CONFIGURATION
In Capture mode, the appropriate CCPx pin should be
configured as an input by setting the corresponding
TRIS direction bit.
11.2.2 TIMER1/TIMER3 MODE SELECTION
The tim ers that are to be used with the capture feature
(Timer1 and/or Timer3) must be running in Timer mode or
Synchr oni zed Count er mode . I n As ynchr ono us Co unt er
mode, the capture operation may not work. The timer to
be used with each CCP module is selected in the T3CON
register (see Section 11.1.1 “CCP Modules and Timer
Resources”).
11.2.3 SOFTWARE INTERRUPT
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep the
CCPxIE interrupt enable bit clear to avoid false inter-
rupts. The interrupt flag bit, CCPxIF, should also be
cleared following any such change in operating mode.
11.2.4 CCP PRESCALER
There are four prescaler settings in Capture mode; they
are sp ecified as part of the ope rating mode selected by
the mode select bits (CCPxM<3:0>). Whenever the
CCP mo dule is turned of f or C apture m ode is di sable d,
the prescaler counter is cleared. This means that any
Reset will clear the prescaler counter.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleare d; therefore , the first cap ture may be from
a non-zero prescaler. Example 11-1 shows the
recommended method for switching between capture
prescalers. This example also clears the prescaler
counter and will not generate the “false” interrupt.
EXAMPLE 11 -1: CHANGING BETWEEN
CAPTURE PRESCALERS
(CCP2 SHOWN)
Note: If th e CCPx p in is c onfigured as an output,
a write to the port can cause a capture
condition.
CLRF CCP2CON ; Turn CCP module off
MOVLW NEW_CAPT_PS ; Load WREG with the
; new prescaler mode
; value and CCP ON
MOVWF CCP2CON ; Load CCP2CON with
; this value
2010-2015 Microchip Technology Inc. DS40001303H-page 137
PIC18F2XK20/4XK20
FIGURE 11-1: CAPTURE MODE OPERATION BLOCK DIAGRAM
CCPR1H CCPR1L
TMR1H TMR1L
Set CCP1IF TMR3
Enable
Q1:Q4
CCP1CON<3:0>
CCP1 pin Prescaler
1, 4, 16 and
Edge Detect TMR1
Enable
T3CCP2
T3CCP2
CCPR2H CCPR2L
TMR1H TMR1L
Set CCP2IF
TMR3
Enable
CCP2CON<3:0>
CCP2 pin Prescaler
1, 4, 16
TMR3H TMR3L
TMR1
Enable
T3CCP2
T3CCP1
T3CCP2
T3CCP1
TMR3H TMR3L
and
Edge Detect
4
44
PIC18F2XK20/4XK20
DS40001303H-page 138 2010-2015 Microchip Technology Inc.
11.3 Compare Mode
In Compare mode, the 16 -bit CCPRx register value is
constantly compared against either the TMR1 or TMR3
register pair value. Whe n a match occurs, the CCPx pin
can be:
• driven high
• driven low
• toggled (high-to-low or low-to-high)
• remain u nchanged (tha t is, reflects t he state of th e
I/O latch)
The acti on on the pin is b ased on the val ue of the mode
select bits (CCPxM<3:0>). At the same time, the inter-
rupt flag bit, CCPxIF, is set.
11.3.1 CCP PIN CONFIGURATION
The user must configure the CCPx pin as an output by
clearing the appropriate TRIS bit.
11.3.2 TIMER1/TIMER3 MODE SELECTION
Timer1 and/or Timer3 must be running in Timer mode
or Synchronized Counter mode if the CCP module is
using the compare feature. In Asynchronous Counter
mode, the compare operation will not work reliably.
11.3.3 SOFTWARE INTERRUPT MODE
When the Ge nerate Softwa re I nterrupt mode i s cho sen
(CCPxM<3:0> = 1010), the correspo nding CCPx pin is
not affected. On ly the CCPxIF interrup t flag is affected.
11.3.4 SPECIAL EVENT TRIGGER
Both CCP modules are equipped with a Special Event
Trigger. This is an internal hardware signal generated
in Co mpare mo de to trig ger actio ns by oth er mod ule s.
The Special Event Trigger is enabled by selecting
the Compare Special Event Trigger mode
(CCPxM<3:0> = 1011).
For either CCP module, the S pecial Event T rigger reset s
the timer register pair for whichever timer resource is
currently assigned as the module’s time base. This
allows the CCPRx registers to serve as a programm able
period register for either timer.
The Special Event Trigger for CCP2 can also start an
A/D conversion. In order to do this, the A/D converter
must already be enabled.
FIGURE 11-2: COMPARE MODE OPERATION BLOCK DIAGRAM
Note: Clearing the CCPxCON register will force
the CCPx compare output latch (depend-
ing on device configuration) to the default
low level. This is not the PORTB or
PORTC I/O data latch.
CCPR1H CCPR1L
TMR1H TMR1L
Comparator Q
S
R
Output
Logic
Special Event Trigger
Set CCP1IF
CCP1 pin
TRIS
CCP1CON<3:0>
Output Enable
TMR3H TMR3L
CCPR2H CCPR2L
Comparator
1
0
T3CCP2
T3CCP1
Set CCP2IF
1
0
Compare
4
(Timer1/Timer3 Reset)
Q
S
R
Output
Logic
Special Event Trigger
CCP2 pin
TRIS
CCP2CON<3:0>
Output Enable
4
(Timer1/Timer3 Reset, A/D Trigger)
Match
Compare
Match
2010-2015 Microchip Technology Inc. DS40001303H-page 139
PIC18F2XK20/4XK20
TABLE 11-3: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 56
RCON IPEN SBOREN —RI TO PD POR BOR 55
PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 59
PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 59
IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 59
PIR2 OSCFIF C1IF C2IF EEIF BCLIF HLVDIF TMR3IF CCP2IF 59
PIE2 OSCFIE C1IE C2IE EEIE BCLIE HLVDIE TMR3IE CCP2IE 59
IPR2 OSCFIP C1IP C2IP EEIP BCLIP HLVDIP TMR3IP CCP2IP 59
TRISB PORTB Data Direction Control Register 59
TRI SC PORTC Data Direction C ontrol Register 59
TMR1L Timer1 Register, Low Byte 57
TMR1H Timer1 Register, High Byte 57
T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 57
TMR3H Timer3 Register, High Byte 58
TMR3L Timer3 Register, Low Byte 58
T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 58
CCPR1L Capture/Compare/PWM Register 1, Low Byte 58
CCPR1H Capture/Compare/PWM Register 1, High Byt e 58
CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 58
CCPR2L Capture/Compare/PWM Register 2, Low Byte 58
CCPR2H Capture/Compare/PWM Register 2, High Byt e 58
CCP2CON — — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 58
Legend: — = unimplemented, read as ‘0’. Shade d cell s are not use d by Captu r e/Co mpare, Tim er1 or Timer3.
Note 1: Not implemented on PIC18F2XK20 devices.
PIC18F2XK20/4XK20
DS40001303H-page 140 2010-2015 Microchip Technology Inc.
11.4 PWM Mode
The PWM mode generates a Pulse-Width Modulated
signal on the CCP2 pin for the CCP module and the
P1A through P1D pins for the ECCP module. Hereafter
the modulated output pin will be referred to as the CCPx
pin. The duty cycle, period and resolution are
determined by the following reg isters:
•PR2
•T2CON
• CCPRxL
• CCPxCON
In Pulse-Width Modulation (PWM) mode, the CCP
module produce s up to a 10 -bit resol ution PWM outp ut
on the CCPx pin. Since the CCPx pin is multiplexed
with the POR T dat a latch, the TRIS for that pi n must be
cleared to enable the CCPx pin output driver.
Figure 11.1.1 shows a simplified block diagram of
PWM operation.
Figure 11-4 shows a typical waveform of the PWM
signal.
For a ste p-by-step proc edure on how t o set up the CC P
module for PWM operation, see Section 11.4.7
“Setup for PWM Operation”.
FIGURE 11-3: SIMPLIFIED PWM BLOCK
DIAGRAM
The PWM output (Figure 11-4) has a time base
(period) and a time that the output stays high (duty
cycle).
FIGURE 11-4: CCP PWM OUTPUT
Note: Clearing the CCPxCON register will
relinquish CCPx control of the CCPx pin.
CCPRxL
CCPRxH(2) (Slave)
Comparator
TMR2
PR2
(1)
RQ
S
Duty Cycle Registers DCxB<1:0>
Clear Timer2 ,
toggle CCPx pin and
latch duty cycle
Note 1: The 8-bit timer TMR2 register is concatenated
with the 2-bit internal system clock (FOSC), or
2 bits of the prescaler , to create the 10-bit time
base.
2: In PWM mode, CCPRxH is a read-only register.
TRIS
CCPx
Comparator
Period
Pulse Width
TMR2 = 0
TMR2 = CCPRxL:DCxB<1:0>
TMR2 = PR2
2010-2015 Microchip Technology Inc. DS40001303H-page 141
PIC18F2XK20/4XK20
11.4.1 PWM PERIO D
The PWM period is specified by the PR2 register of
Timer2. The PWM period can be calculated using the
formula of Equation 11-1.
EQUATION 11-1: PWM PERIOD
When TM R2 is equa l to PR2, t he followi ng three ev ents
occur on t he next increment cycle:
• TMR2 is cl eare d
• The CCPx pin is set. (Exception: If the PWM duty
cycle = 0%, the pin will not be set.)
• The PWM dut y cyc le is la tched from CCPRxL into
CCPRxH.
11.4.2 PW M DUTY CYCL E
The PWM duty cycle is specified by writing a 10-bit
value to multiple registers: CCPRxL register and
DCxB<1:0> bits of the CCPxCON register. The
CCPRxL contains the eight MSbs and the DCxB<1:0>
bits of the CCPxCON register contain the two LSbs.
CCPRxL and DCxB<1:0> bits of the CCPxCON
register can be written to at any time. The duty cycle
value is not latched into CCPRxH unt il aft er the per iod
completes (i.e., a match between PR2 and TMR2
registers occurs). While using the PWM, the CCPRxH
register is read-on ly.
Equation 11-2 is used to calculate the PWM pulse
width.
Equation 11-3 is used to calculate the PWM duty cycle
ratio.
EQUATION 11-2: PULSE WIDTH
EQUATION 11-3: DUTY CYCLE RATIO
The CCPRxH register and a 2-bit internal latch are
used to dou ble buf fer th e PWM duty cycle. Thi s doubl e
buffering is essential for glitchless PWM operation.
The 8-bit timer TMR2 register is concatenated with
either the 2-bit internal system clock (FOSC), or two bits
of the prescaler, to create the 10-bit time base. The
system clock is used if the T imer2 prescaler is set to 1:1.
When the 10-bit time base matches the CCPRxH and
2-bit latch, then the CCPx pin is cleared (see
Figure 11-3).
Note: The Timer2 postscaler (see Section 14.1
“Timer2 Operation”) is not used in the
determination of the PWM frequency.
PWM Period PR21+4TOSC =
(TM R2 Prescale Value)
Note: TOSC = 1/FOSC.
Pulse Width CCPRxL:DCxB<1:0>
=
TOSC
(TM R2 Prescale Value)
Duty Cycle Ratio CCPRxL:DCxB<1:0>
4PR2 1+
-----------------------------------------------------------=
PIC18F2XK20/4XK20
DS40001303H-page 142 2010-2015 Microchip Technology Inc.
11.4.3 PW M RES O LUTION
The res olution de termine s the nu mber of avai lable dut y
cycles for a given period. For example, a 10-bit resolution
will r e sult in 10 24 di sc ret e d ut y c ycl es , wh er eas an 8- b it
resol uti on wi ll re su lt in 2 56 di s cre te du ty c ycl es .
The maximum PWM resolution is ten bits when PR2 is
255. The resolution is a function of the PR2 register
value as shown by Equation 11-4.
EQUATION 11-4: PWM RESOLUTION
TABLE 11-4: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz
TABLE 11-5: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz)
TABLE 11-6: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz)
Note: If the pulse width value is greater than the
period the assigned PWM pin(s) will
remain unchanged.
Resolution 4PR2 1+log 2log
------------------------------------------ bits=
PWM Frequency 2.44 kHz 9.77 kHz 39.06 kHz 156.25 kHz 312.50 kHz 416.67 kHz
Timer Prescaler (1, 4, 16)1641111
PR2 Value FFh FFh FFh 3Fh 1Fh 17h
Maximum Resolution (bits) 10 10 10 8 7 6.5 8
PWM Frequency 1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz
Timer Prescale (1, 4, 16) 16 4 1 1 1 1
PR2 Value 0xFF 0xFF 0xFF 0x3F 0x1F 0x17
Maximum Resolution (bits) 10 10 10 8 7 6.6
PWM Frequency 1.22 kHz 4.90 kHz 19.61 kHz 76.92 kHz 153.85 kHz 200.0 kHz
Timer Prescale (1, 4, 16) 16 4 1 1 1 1
PR2 Value 0x65 0x65 0x65 0x19 0x0C 0x09
Maximum Resolution (bits) 8 8 8 6 5 5
2010-2015 Microchip Technology Inc. DS40001303H-page 143
PIC18F2XK20/4XK20
11.4.4 OPE RATION IN POWE R-MANAG ED
MODES
In Sleep mode, the TMR2 register will not increment
and the state o f the mo dule will no t change. I f the CC Px
pin is dri ving a value , it wil l cont inue to d rive th at valu e.
When the device wakes up, TMR2 wil l continue from it s
previous state.
In PRI_IDLE mode, the primary clock will continue to
clock the CCP module without change. In all other
power-managed modes, the selected power-managed
mode clock will clock Timer2. Other power-managed
mode clocks will most likely be different than the
primary clock frequency.
11.4.5 CHANGES IN SYSTEM CLOCK
FREQUENCY
The PWM frequency is derived from the system clock
frequency. Any changes in the system clock frequency
will result in changes to the PWM frequency. See
Section 2.0 “Oscillator Module (With Fail-Safe
Clock Monitor)” for additi onal details.
11.4.6 EFFECTS OF RESET
Any Reset will force all ports to Input mode and the
CCP registers to their Reset states.
11.4.7 SETUP FOR PWM OPERATION
The following steps should be taken when configuring
the CCP module for PWM operation:
1. Disable the PWM pin (CCPx) output drivers by
setting the associated TRIS bit.
2. For the ECCP module only: Select the desired
PWM outputs (P1A through P1D) by setting the
appropriate steering bits of the PSTRCON
register.
3. Set the PWM period by loading the PR2 register .
4. Configure the CCP module for the PWM mode
by loading the CCPxCON register with the
appropriate values.
5. Set the PWM duty cycle by loading the CCPRxL
register and CCPx bits of the CCPxCON register .
6. Configure and start Timer2:
• Clear the TMR2IF interrupt flag bit of the
PIR1 register.
• Set the T im er2 pres cale value by loa din g the
T2CKPS bits of the T2CON register.
• Enabl e Timer2 by se ttin g the TMR2ON bit of
the T2CON register.
7. Enable PW M ou tput af ter a new PWM c ycle has
started:
• Wait until Timer2 overflows (TMR2IF bit of
the PIR1 register is set).
• Enable the CCPx pin output driver by
clearing the associated TRIS bit.
PIC18F2XK20/4XK20
DS40001303H-page 144 2010-2015 Microchip Technology Inc.
TABLE 11-7: REGISTERS ASSOCIATED WITH PWM AND TIMER2
Name B it 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset
Values
on p ag e
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 56
RCON IPEN SBOREN —RI TO PD POR BOR 55
PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 59
PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 59
IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 59
TRISB PORTB Data Direction Control Register 59
TRISC PORTC Data Direc tion Control Register 59
TMR2 Timer2 Register 57
PR2 Timer2 Period Register 57
T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 57
CCPR1L Capture/Compare/PWM Register 1, Low Byte 58
CCPR1H Capture/Compare/PWM Register 1, High Byte 58
CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 58
CCPR2L Capture/Compare/PWM Register 2, Low Byte 58
CCPR2H Capture/Compare/PWM Register 2, High Byte 58
CCP2CON —— DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 58
ECCP1AS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 58
PWM1CON PRSEN PDC6 PDC5 PDC4 PDC3 PDC2 PDC PDC0 58
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PWM or Timer2.
Note 1: Not implemented on PIC 18F 2XK20 devices.
2010-2015 Microchip Technology Inc. DS40001303H-page 145
PIC18F2XK20/4XK20
12.0 TIMER0 MODULE
The T imer0 module incorporates the following features:
• Software selectable operation as a timer or
counter in both 8-bi t or 16-bit modes
• Readable and writable registers
• Dedicated 8-bit, software programmable
prescaler
• Selectable clock source (internal or exter nal)
• Edge select for external clock
• Interrupt-on-overflow
The T0CON register (Register 12-1) controls all
aspects of the module’s operation, including the
prescale selection. It is both readable and writable.
A simplified block diagram of the Timer0 module in 8-bit
mode is shown in Figure 12-1. Figure 12-2 shows a
simplified block diagram of the Timer0 module in 16-bit
mode.
REGISTER 12-1: T0CON: TIMER0 CONTROL REGISTER
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 TMR0ON: Timer0 On/Off Control bit
1 = Enables Timer0
0 = Stops Timer0
bit 6 T08BIT: Timer0 8-bit/16-bit Control bit
1 = Timer0 is configured as an 8-bit timer/counter
0 = Timer0 is configured as a 16-bit timer/counter
bit 5 T0CS: Timer0 Clock Source Select bit
1 = Transit ion on T0CK I pin
0 = Internal instruction cycle cl ock (CLKOUT )
bit 4 T0SE: Timer0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
bit 3 PSA: Timer0 Prescaler Assignment bit
1 = TImer0 prescaler is NO T assigned. Timer0 clock input bypasses pre s caler.
0 = Timer0 prescaler is assi gned. Timer0 clock inpu t comes from prescale r output.
bit 2-0 T0PS<2:0>: Timer0 Prescaler Select bits
111 = 1:256 prescale value
110 = 1:128 prescale value
101 = 1:64 prescale value
100 = 1:32 prescale value
011 = 1:16 prescale value
010 = 1:8 prescale value
001 = 1:4 prescale value
000 = 1:2 prescale value
PIC18F2XK20/4XK20
DS40001303H-page 146 2010-2015 Microchip Technology Inc.
12.1 Timer0 Operation
Timer0 can operate as either a timer or a counter; the
mode is selected with the T0CS bit of the T0CON
register. In Timer mode (T0CS = 0), the module
increments on every clock by default un less a different
prescaler value is selected (see Section 12.3
“Prescaler”). Timer0 incrementing is inhibited for two
instruction cycles following a TMR0 register write. The
user can work around this by adjusting the value written
to the T MR0 reg is ter to co mpensate for the a nti ci p ate d
missi ng inc rem en t s.
The Counter mode is selected by setting the T0CS bit
(= 1). In this mode, Timer0 increments either on every
rising or fal ling edge of pi n RA4/T0CKI . The increme nt-
ing edge is determined by the Timer0 Source Edge
Select bit , T0SE of the T0CON registe r; clearing this bit
selects the rising edge. Restrictions on the external
clock input are dis cuss ed below.
An external clock source can be used to drive Timer0;
however, it must meet certain requirements (see
Table ) to ensure that the external clock can be syn-
chronized with the internal phase clock (T OSC). There is
a delay between synchronization and the onset of
incremen ting t he timer/counter.
12.2 Timer0 Reads and Writes in
16-Bit Mode
TMR0H is not the actual high byte of Timer0 in 16-bit
mode; it is actually a buffered version of the real high
byte of Timer0 which is neither directly readable nor
writable (refer to Figure 12-2). TMR0H is updated with
the conte nts of the h igh by te of Timer0 durin g a read of
TMR0L. This provides the ability to read all 16 bits of
Timer0 without the need to verify that the read of the
high and low byte were valid. Invalid reads could
otherwise occur due to a rollover between successive
reads of the high and low byte.
Similarly, a write to the high byte of Timer0 must also
take place through the TMR0H Buffer register. Writing
to TMR0H does not directly affect Timer0. Instea d, the
high byte of Timer0 is updated with the contents of
TMR0H when a write occurs to TMR0L. This allow s all
16 bits of Timer0 to be updated at once.
FIGURE 12-1: TIMER0 BLOCK DIAGRAM (8-BIT MODE)
Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
T0CKI pin
T0SE
0
1
0
1
T0CS
FOSC/4
Programmable
Prescaler
Sync with
Internal
Clocks TMR0L
(2 TCY Delay)
Internal Data Bus
PSA
T0PS<2:0>
Set
TMR0IF
on Overflow
38
8
2010-2015 Microchip Technology Inc. DS40001303H-page 147
PIC18F2XK20/4XK20
FIGURE 12-2: TIMER0 BLOCK DIAGRAM (16-BIT MODE)
12.3 Prescaler
An 8-bi t counter i s availabl e as a presc aler for the T imer0
module. The prescaler is not directly readable or writable;
its value is set by the PSA and T0PS<2:0> bits of the
T0CON register which determine the prescaler
assi gn me nt and presca le ratio.
Clearing the PSA bit assigns the prescaler to the
Timer0 module. When the prescaler is assigned,
prescale values from 1:2 through 1:256 in integer
power-of-2 increments are selectable.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g., CLRF TMR0, MOVWF
TMR0, BSF TMR0, etc.) clear the prescaler count.
12.3.1 SW ITCHI NG PRE SC ALER
ASSIGNMENT
The prescaler assignment is fully under software
control and can be changed “on-the-fly” during program
execution.
12.4 Timer0 Interrupt
The TMR0 interrupt is generated when the TMR0 reg-
ister overflows from FFh to 00h in 8-bit mode, or from
FFFFh to 0000h in 16-bit mode. This overflow sets the
TMR0IF flag bit. The inte rrupt can be masked by cle ar-
ing the TMR0IE bit of the INTCON register. Before
re-enabling the interrupt, the TMR0IF bit must be
cleared by software in the Interrupt Service Routine.
Since Timer0 is shut down in Sleep mode, the TMR0
interrupt cannot awaken the processor from Sleep.
TABLE 12-1: REGISTERS ASSOCIATED WITH TIMER0
Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
T0CKI pin
T0SE
0
1
0
1
T0CS
FOSC/4
Programmable
Prescaler
Sync with
Internal
Clocks TMR0L
(2 TCY Delay)
Internal Data Bus
8
PSA
T0PS<2:0>
Set
TMR0IF
on Overflow
3
TMR0
TMR0H
High Byte
88
8
Read TMR0L
Write TMR0L
8
Note: Writing to TMR0 when the prescaler is
assign ed to Tim er0 will clear the presca ler
count but will not change the prescaler
assignment.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset
Values
on pag e
TMR0L Timer0 Register, Low Byte 57
TMR0H Timer0 Register, High Byte 57
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 56
T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 57
TRISA RA7(1) RA6(1) RA5 RA4 RA3 RA2 RA1 RA0 59
Legend: Shaded cells are not used by Timer0.
Note 1: PORTA<7:6> and their direction bits are individually configured as port pins based on various primary
oscillator modes. When disabled, these bits read as ‘0’.
PIC18F2XK20/4XK20
DS40001303H-page 148 2010-2015 Microchip Technology Inc.
13.0 TIMER1 MODULE
The Timer1 timer/counter module incorporates the
following features:
• Software selectable operation as a 16-bit timer or
counter
• Readable and writable 8-bit registers (TMR1H
and TMR1L)
• Selectable inte rnal or external clock source and
Timer1 oscillator options
• Interrupt-on-overflow
• Reset on CCP Special Event Trigger
• Device clock stat us flag (T1RUN)
A simplified block diagram of the Timer1 module is
shown in Figure 13-1. A block diagram of the mod ule ’s
operat ion in Read /Wr ite mode is show n in Figure 13-2.
The module incorporates its own low-power oscillator
to provide an additional clocking option. The Timer1
oscillator can also be used as a low-power clock source
for the microcontroller in power-managed operation.
Timer1 can also be used to provide Real-Time Clock
(RTC) functionality to applications with only a minimal
addition of external components and code overhead.
Timer1 is controlled through the T1CON Control
register (Register 13-1). It also contains the Timer1
Oscillator Enable bit (T1OSCEN). Timer1 can be
enabled or disabled by setting or clearing control bit,
TMR1ON of the T1CON register.
REGISTER 13-1: T1CON: TIMER1 CONTROL REGISTER
R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 RD16: 16-bit Read/Write Mode E nable bit
1 = Enables regist er read /write of TImer1 in one 16-bit ope rati on
0 = Enables register read/write of Timer1 in tw o 8-bit ope rati ons
bit 6 T1RUN: Timer1 System Clock Status bit
1 = Main system clock is derived from Timer1 oscillator
0 = Main system clock is derived from another source
bit 5-4 T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits
11 = 1:8 P resca le value
10 = 1:4 P resca le value
01 = 1:2 P resca le value
00 = 1:1 P resca le value
bit 3 T1OSCEN: Timer1 Oscilla tor Enable bit
1 = Timer1 oscillator is enabled
0 = Timer1 oscillator is shut off
The oscillator inverter and feedback resistor are turned off to eliminate power drain.
bit 2 T1SYNC: Timer1 External Clock Input Synchronization Select bit
When TMR1CS = 1:
1 = Do not synchronize external clock input
0 = Synchronize external clock input
When TMR1CS = 0:
This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.
bit 1 TMR1CS: Timer1 Clock Source Select bit
1 = External clock from pin RC0/T1OSO/T13CKI (on the rising edge)
0 = Internal clock (FOSC/4)
bit 0 TMR1ON: Timer1 On bit
1 = Enables Timer1
0 = Stops Timer1
2010-2015 Microchip Technology Inc. DS40001303H-page 149
PIC18F2XK20/4XK20
13.1 Timer1 Operation
Timer1 can operate in one of the following modes:
•Timer
• Synchronous Coun ter
• Asynchronous Counter
The operating mode is determined by the clock select
bit, TMR1CS of the T1CON register . When TMR1CS is
cleared (= 0), Timer1 increments on every internal
instr uction cyc le (FOSC/4). When the bi t is set, Timer 1
increments on every rising edge of either the Timer1
external clock input or the Timer1 oscillator, if enabled.
When the Timer1 oscillator is enabled, the digital
circuitry associated with the RC1/T1OSI and
RC0/T1OSO/T13CKI pins is disabl ed. This means the
values of TRISC<1:0> are ignored and the pins are
read as ‘0’.
FIGURE 13-1: TIMER1 BLOCK DIAGRAM
FIGURE 13-2: TIMER1 BLOCK DIAGRAM (16-BIT READ/WRITE MODE)
T1SYNC
TMR1CS
T1CKPS<1:0>
Sleep Input
T1OSCEN(1)
FOSC/4
Internal
Clock
On/Off
Prescaler
1, 2, 4, 8 Synchronize
Detect
1
02
T1OSO/T13CKI
T1OSI
1
0
TMR1ON
TMR1L Set
TMR1IF
on Overflow
TMR1
High Byte
Clear TMR1
(CCP Special Event Trigger)
Timer1 Oscillator
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
On/Off
Timer1
Timer1 Clock Input
T1SYNC
TMR1CS
T1CKPS<1:0>
Sleep Input
T1OSCEN(1)
FOSC/4
Internal
Clock
Prescaler
1, 2, 4, 8 Synchronize
Detect
1
02
T1OSO/T13CKI
T1OSI
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
1
0
TMR1L
Internal Data Bus
8
Set
TMR1IF
on Overflow
TMR1
TMR1H
High Byte
88
8
Read TMR1L
Write TMR1L
8
TMR1ON
Clear TMR1
(CCP S pecial Event Trigger)
Time r1 Oscillator
On/Off
Timer1
Timer1 Clock Inpu t
PIC18F2XK20/4XK20
DS40001303H-page 150 2010-2015 Microchip Technology Inc.
13.2 Clock Source Selection
The TMR1CS bit of the T1CON register is used to
select the clock source. When TMR1CS = 0, the clo c k
source is FOSC/4. When TMR1CS = 1, the clock source
is supplied externally.
13.2.1 INTERNAL CLOCK SOURCE
When the internal clock source is selected, the
TMR1H:TMR1L register pair w i ll increment on multiples
of TCY as determined by the Timer1 prescaler.
13.2.2 EXT ERN AL CLOCK SOURCE
When the external clock sour ce is selected, the Timer1
module may wo rk as a timer or a cou nter.
When counting, Timer1 is incremented on the rising
edge of the external clock input T1CKI. In addition, the
Counter mode clock can be synchronized to the
microcontroller system clock or run async hronously.
If an external clock oscillator is needed (and the
microc ontroller is using the INT OSC withou t CLKOUT),
Timer1 can use the LP oscillator as a clock source.
13.2.3 READING AND WRITING T IMER1 IN
ASYNCHRONOUS COUNTER
MODE
Reading TMR1H or TMR1L while the timer is running
from an e xternal asyn chronous cl ock will ens ure a valid
read (taken care of in hardware). However, the user
should keep i n mind that rea ding t he 16-bi t ti mer in two
8-bit values itself, poses certain problems, since the
timer may overflow between the reads.
For writes , it is re commend ed that th e user s imply sto p
the timer and write the desired values. A write
conte ntion may occ ur by writin g to th e time r regi sters,
while the register is incrementing. This may pro duce an
unpredictable value in the TMR1H:TTMR1L register
pair.
13.3 Timer1 Prescaler
Timer1 has four prescaler options allowing 1, 2, 4 or 8
divisions of the clock input. The T1CKPS bits of the
T1CON register control the prescale counter. The
prescale counter is not directly readable or writable;
however , the prescaler counter is cleared upon a write to
TMR1H or TMR1L.
13.4 Timer1 Operation in
Asynchronous Counter Mode
If control bit T1SYNC of the T1CON register is set, the
external clock input is not synchronized. The timer
continues to increment asynchronous to the internal
phase clocks. The timer will continue to run during
Sleep and can generate an interrupt on overflow,
which will wake-up the processor. However, special
precautions in software are needed to read/write the
timer (see Section 13.2.3 “Reading and Writing
Timer1 in Asynchronous C ounter Mode”).
FIGURE 13-3: TIMER1 INCREMENTING EDGE
Note: In Counter mode, a falling edge must be
registered by the counter prior to the first
incrementing rising edge after o ne or more
of the following conditions (see
Figure 13-3):
• Timer1 is enabled after POR or BOR
Reset
• A write to TMR1H or TMR1L
• Timer1 is disabled (TMR1ON = 0)
when T1CKI is high then Timer1 is
enabled (TMR1ON = 1) when T1CKI
is lo w.
Note 1: When switching from synchronous to
asynchronous operation, it is possible to
skip an increment. When switching from
asynchronous to synchronous operation,
it is possible to produce an additional
increment.
T1CKI = 1
when TMR1
Enabled
T1CKI = 0
when TMR1
Enabled
Note 1: Arrows indicate counter increm ents.
2: In Counter mode, a falling edge must be re gistered by the counter prior to t he first incrementing rising edge of
the clock.
2010-2015 Microchip Technology Inc. DS40001303H-page 151
PIC18F2XK20/4XK20
13.5 Timer1 16-Bit Read/Write Mode
Timer1 can be configured for 16-bit reads and writes
(see Figure 13-2). When the RD16 control bit of the
T1CON register is set, the address for TMR1H is
mapped to a b uffer register fo r the hi gh by te o f Timer1.
A read from TMR1L will load the contents of the high
byte of Timer1 into the Timer1 high byte buffer. This
provi des th e us er with the abil it y to acc urat ely rea d all
16 bits of Timer1 without the need to determine
whether a read of the high byte, followed by a read of
the low byte, has become invalid due to a rollover or
carry between reads.
Writing to TMR1H does not directly affect Timer1.
Instead, the high byte of Timer1 is updated with the
contents of TMR1H when a write occurs to TMR1L.
This all ow s a ll 1 6 bits of Ti me r1 to be updated at once.
The high byte of Timer1 is not directly readable or
writable in this mode. All reads and writes must take
place through the Timer1 High Byte Buffer register.
Writes to TMR1H do not clear the Timer1 prescaler.
The prescaler is only cleared on writes to TMR1L.
13.6 Timer1 Oscillator
An on-chip crystal oscillator circuit is incorporated
between pins T1OSI (input) and T1OSO (amplifier
output). It is enabled by setting the Timer1 Oscillator
Enable bit, T1OSCEN of the T1CON register. The
oscillator is a low-power ci rcuit rated for 32 kHz crystals.
It will continue to run during all power-managed modes.
The circuit for a typical LP oscillator is shown in
Figure 13-4. Table 13-1 shows the capacitor selection
for the Timer1 oscillator.
The user m us t prov id e a so ftware time delay to en su re
proper start-up of the Timer1 oscillator.
FIGURE 13-4: EXTER NAL
COMPONENTS FOR THE
TI MER1 LP OSCILLATOR
T ABLE 13-1: CAPACITOR SELECTION FOR
THE TIMER OSCILLATOR
13.6.1 USING TIMER1 AS A
CLOCK SOURCE
The T imer1 oscillator is also available as a clock source
in po wer-man aged mode s. By s etting t he cloc k select
bits, SCS<1:0> of the OSCCON register, to ‘01’, the
device switches to SEC_RUN mode; both the CPU and
periphera ls are clocked from the T imer1 oscillator . If the
IDLEN bit of the OSCCON register is cleared and a
SLEEP instruction is executed, the device enters
SEC_IDLE mode. Additional details are available in
Section 3.0 “Power-Managed Modes”.
Whenever the Timer1 oscillator is providing the clock
source, the T imer1 system clock status flag, T1RUN of
the T1CON register, is set . Thi s ca n be u sed t o dete r-
mine th e c ontroller’s cu rrent clocking mode. I t c an also
indicate which clock source is currently being used by
the Fail-Safe Clock Monitor. If the Clock Monitor is
enabled and the Timer1 oscillator fails while providing
the clock, polling the T1RUN bit will indicate whether
the clock is being provided by the Timer1 oscillator or
another source.
Note: See the Notes with Table 13-1 for additional
information about capacitor selection.
C1
C2
XTAL
T1OSI
T1OSO
32.768 kHz
27 pF
27 pF
PIC® MCU
Osc Type Freq C1 C2
LP 32 kHz 27 pF(1) 27 pF(1)
Note 1: Microchip suggests these values only as
a starting poin t in validati ng the oscillat or
circuit.
2: Higher capacitance increases the stabil-
ity of the oscillator but also increases the
start-up time.
3: Sinc e each res onato r/cry stal has i ts own
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate values of external
components.
4: Capacitor values are for design guidance
only.
PIC18F2XK20/4XK20
DS40001303H-page 152 2010-2015 Microchip Technology Inc.
13.6.2 LOW-POWER TIMER1 OPTION
The Timer1 oscillator can operate at two distinct levels
of power consumption based on device configuration.
When the LPT1OSC Configuration bit of the
CONFIG3H register is set, the Timer1 oscillator
operates in a low- po wer mo de. Wh en LPT1OSC is not
set, Timer1 operates at a higher power level. Power
consumption for a particular mode is relatively
constant, regardless of the device’s operating mode.
The default Timer1 configuration is the higher power
mode.
As the low-power Timer1 mode tends to be more
sensitive to interference, high noise environments may
cause some oscillator instability . The low-power option is,
therefore, best suited for low noise applications where
power conservation is an important design consideration.
13.6.3 TIMER1 OSCILLATOR LAYOUT
CONSIDERATIONS
The Timer1 oscillator circuit draws very little power
during operation. Due to the low-power nature of the
oscillator, it may also be sensitive to rapidly changing
signals in close proximity.
The oscillator circuit, shown in Figure 13-4, should be
located as close as possible to the microcontroller.
There should be no circuits passing within the oscillator
circuit boundaries other than VSS or VDD.
If a hig h-s pee d cir cui t m us t b e loc ate d near the oscill a-
tor (such as the CCP1 pin in Output Compare or PWM
mode, or the primary oscillator using the OSC2 pin), a
grounded guard ring around the oscillator circuit, as
shown in Figure 13-5, may be helpful when used on a
single-sided PCB or in addition to a ground plane.
FIGURE 13-5: OSCILLATOR CIRCUIT
WITH GROUNDED
GUARD RING
13.7 Timer1 Interrupt
The TMR1 register pair (TMR1H:TMR1L) increments
from 0000h to FFFFh and rolls over to 0000h. The
Timer1 interrupt, if enabled, is generated on overflow,
which is latched in the TMR1IF interrupt flag bit of the
PIR1 reg ister . This i nterrupt can be enabled o r disabled
by setting or clearing the TMR1IE Interrupt Enable bit
of the PIE1 register.
13.8 Resetting Timer1 Using the CCP
S pecial Event Trigger
If either of the CCP modules is configured to use Timer1
and generate a Special Event Trigger in Comp are mode
(CCP1M<3:0> or CCP2M<3:0> = 1011), this signal will
reset Timer1. The trigger from CCP2 will also start an
A/D conversion if the A/D module is enabled (see
Section 11.3.4 “Special Event Trigger” for more
information).
The module must be configured as either a timer or a
synch rono us cou nte r to t ak e a dva nt age of this feature.
When used this way, the CCPRH:CCPRL register pair
effectively becomes a period regi ste r for Timer1.
If Timer1 is running in Asynchronous Counter mode,
this Reset operation may not work.
In the event that a write to Timer1 coincides with a
special Event Trigger, the write operation will take
precedence.
VDD
OSC1
VSS
OSC2
RC0
RC1
RC2
Note: Not drawn to scale.
Note: The Special Event Triggers from the
CCP2 module will not set the TMR1IF
interrupt flag bit of the PIR1 register.
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PIC18F2XK20/4XK20
13.9 Using Timer1 as a Real-T ime Clock
Adding an extern al LP os cilla tor to Timer1 (such a s the
one described in Section 13.6 “Timer1 Oscillator”
above) giv es users the opti on to inc lu de RTC function-
ality to their applications. This is accomplished with an
inexpensive watch crystal to provide an accurate time
base and several lines of application code to calculate
the time. When operating in Sleep mode and using a
battery or supercapacitor as a power source, it can
completely eliminate the need for a separate RTC
dev ice and battery backup.
The application code routine, RTCisr, shown in
Example 13-1, demonstrates a simple method to
increment a counter at one-second intervals using an
Interrupt Service Routine. Incrementing the TMR1
register pair to overflow triggers the interrupt and calls
the routine, which increments the seconds counter by
one; additional counters for minutes and hours are
incremented on overflows of the less significant
counters.
Since the register pair is 16 bits wide, a 32.768 kHz
clock source will take two seconds to count up to over-
flow. To force the overflow at the required one-second
intervals, it is necessary to preload it; the simplest
method i s to set the MSb of TMR1H with a BSF instruc-
tion. Note that the TMR1L register is never preloaded
or altered; doing so may introduce cumulative error
over many cycl es .
For this m ethod to be a ccurate, T i mer1 must o perate in
Asynchronous mode and t he Timer1 overflow interrupt
must be enabled (PIE1<0> = 1), as shown in the
routine, RTCinit. The Timer1 oscillator must also be
enabled and running at all times.
EXAMPLE 13-1: IMPLEMENTING A REAL-TIME CLOCK USING A TIMER1 INTERRUPT SERVICE
RTCinit MOVLW 80h ; Preload TMR1 register pair
MOVWF TMR1H ; for 1 second overflow
CLRF TMR1L
MOVLW b’00001111’ ; Configure for external clock,
MOVWF T1CON ; Asynchronous operation, external oscillator
CLRF secs ; Initialize timekeeping registers
CLRF mins ;
MOVLW .12
MOVWF hours
BSF PIE1, TMR1IE ; Enable Timer1 interrupt
RETURN
RTCisr BSF TMR1H, 7 ; Preload for 1 sec overflow
BCF PIR1, TMR1IF ; Clear interrupt flag
INCF secs, F ; Increment seconds
MOVLW .59 ; 60 seconds elapsed?
CPFSGT secs
RETURN ; No, done
CLRF secs ; Clear seconds
INCF mins, F ; Increment minutes
MOVLW .59 ; 60 minutes elapsed?
CPFSGT mins
RETURN ; No, done
CLRF mins ; clear minutes
INCF hours, F ; Increment hours
MOVLW .23 ; 24 hours elapsed?
CPFSGT hours
RETURN ; No, done
CLRF hours ; Reset hours
RETURN ; Done
PIC18F2XK20/4XK20
DS40001303H-page 154 2010-2015 Microchip Technology Inc.
TABLE 13-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 56
PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 59
PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 59
IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 59
TMR1L Timer1 Register, Low Byte 57
TMR1H Timer1 Register, High Byte 57
T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 57
Legend: Shaded cells are not used by the Timer1 module.
Note 1: These bits are unimplemented on 28-pin devices; always maintain these bi ts clear.
2010-2015 Microchip Technology Inc. DS40001303H-page 155
PIC18F2XK20/4XK20
14.0 TIMER2 MODULE
The Timer2 module timer incorporates the following
features:
• 8-bit timer and period registers (TMR2 and PR2,
respectively)
• Readable and writable (both registers)
• Software programmable prescaler (1:1, 1:4 and
1:16)
• Software programmable postscaler (1:1 through
1:16)
• Interrupt on TMR2-to-PR2 match
• Optional use as the shift clock for the MSSP
module
The module is controlled through the T2CON register
(Register 14-1), which enables or disables the timer
and configures the prescaler and postscaler. Timer2
can be shut off by clearing control bit, TMR2ON of the
T2CON register, to minimize power consumption.
A simplified block diagram of the module is shown in
Figure 14-1.
14.1 Timer2 Operation
In normal op eration, TMR2 is incremen ted from 00h on
each clock (FOSC/4). A 4-bit counter/prescaler on the
clock input gives direct input, divide-by-4 and
divide-by-16 prescale options; these are selected by
the pres caler contro l bits, T 2CKPS<1:0> of the T2CON
register. The value of TMR2 is compared to that of the
period register, PR2, on each clock cycle. When the
two values match, the comparator generates a match
signal as the timer output. This signal also resets the
value of TMR2 to 00h on the next cycle and drives the
output counter/postscaler (see Section 14.2 “Timer2
Interrupt”).
The TMR2 and PR2 registers are both directly r eadable
and writable. The TMR2 register is cleared on any
device Reset, whereas the PR2 register initializes to
FFh. Both the prescaler and postscaler counters are
cleared on the following events:
• a write to the TMR2 register
• a write to the T2CON register
• any device Reset (Power-on Reset, MCLR Reset,
Watchdog Timer Reset or Brown-out Reset)
TMR2 is not cleared when T2CON is written.
REGISTER 14-1: T2CON: TIMER2 CONTROL REGISTER
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 Unimplemented: Read as ‘0’
bit 6-3 T2OUTPS<3:0>: Timer2 Output Postscale Select bits
0000 = 1:1 Postscale
0001 = 1:2 Postscale
•
•
•
1111 = 1:16 P ostscale
bit 2 TMR2ON: T im er2 On bit
1 = Timer2 is on
0 = Timer2 is off
bit 1-0 T2CKPS<1:0>: Timer2 Clock Prescale Select bits
00 = Prescaler is 1
01 = Prescaler is 4
1x = Prescaler is 16
PIC18F2XK20/4XK20
DS40001303H-page 156 2010-2015 Microchip Technology Inc.
14.2 Timer2 Interrupt
Timer2 can also generate an optional device interrupt.
The Timer2 output signal (TMR2-to-PR2 match) pro-
vides the input for the 4-bit output counter/postscaler.
This coun ter gen erat es th e TMR2 m atc h inter rupt flag
which is latched in TMR2IF of the PIR1 register. The
interrupt is enabled by setting the TMR2 Match Inter-
rupt Enable bit, TMR2IE of the PIE1 register.
A range of 16 post scale options (from 1 :1 through 1:16
inclusive) can be selected with the postscaler control
bits, T2OUTPS<3:0> of t he T2C ON r egister.
14.3 Timer2 Output
The unscaled output of TMR2 is available primarily to
the CCP modules, where it is used as a time base for
operat io ns in PWM mo de.
T i mer2 ca n be op tiona lly us ed as th e shif t cl ock so urce
for the MSSP module operating in SPI mode. Addi-
tional information is provided in Section 17.0 “Master
Synchronous Serial Port (MSSP) Module”.
FIGURE 14-1: TIMER2 BLOCK DIAGRAM
TABLE 14-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 56
PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 59
PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 59
IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 59
TMR2 Timer2 Register 57
T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 57
PR2 Timer2 Period Register 57
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module.
Note 1: These bits are unimplemented on 28-pin devices; always maintain these bi ts clear.
Comparator
TMR2 Outpu t
TMR2
Postscaler
Prescaler PR2
2
FOSC/4
1:1 to 1:16
1:1, 1:4, 1:16
4
T2OUTPS<3:0>
T2CKPS<1:0>
Set TMR2IF
Inte rn a l D a ta B u s 8
Reset TMR2/PR2
8
8
(to PWM or MSSP)
Match
2010-2015 Microchip Technology Inc. DS40001303H-page 157
PIC18F2XK20/4XK20
15.0 TIMER3 MODULE
The Timer3 module timer/counter incorporates these
features:
• Software selectable operation as a 16-bit timer or
counter
• Readable and writable 8-bit registers (TMR3H
and TMR3L)
• Selectable clock source (internal or external) with
device clock or Timer1 oscillator internal options
• Interrupt-on-overflow
• Module Reset on CCP Special Event Trigger
A simplified block diagram of the Timer3 module is
shown in Figure 15-1. A block diagram of the mod ule ’s
operat ion in Read /Wr ite mode is show n in Figure 15-2.
The Timer3 module is controlled through the T3CON
register (Register 15-1). It also selects the clock source
options for the CCP modules (see Section 11.1.1
“CCP Modules and Timer Resources” for more
information).
REGISTER 15-1: T3CON: TIMER3 CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 RD16: 16-bit Read/Write Mode Enable bit
1 = Enables register read/write of Timer3 in one 16-bit operation
0 = Enables register read/write of Timer3 in two 8-bit operations
bit 6,3 T3CCP<2:1>: Timer3 and Timer1 to CCPx Enable bits
1x = Timer3 is the capture/compare clock source for CCP1 and CP2
01 = Timer3 is the capture/compare clock source for CCP2 and
Timer1 is the capture/compare clock source for CCP1
00 = Timer1 is the capture/compare clock source for CCP1 and CP2
bit 5-4 T3CKPS<1:0>: Timer3 Input Clock Prescale Select bits
11 = 1:8 P resca le value
10 = 1:4 P resca le value
01 = 1:2 P resca le value
00 = 1:1 P resca le value
bit 2 T3SYNC: Timer3 External Clock Input Synchronization Control bit
(Not usable if the device clock comes from Timer1/Timer3.)
When TMR3CS = 1:
1 = Do not synchronize external clock input
0 = Synchronize external clock input
When TMR3CS = 0:
This bit is ignored. Timer3 uses the internal clock when TMR3CS = 0.
bit 1 TMR3CS: Timer3 Clock Source Select bit
1 = External clock input from Timer1 oscillator or T13CKI (on the rising edge after the first
falling edge)
0 = Internal clock (FOSC/4)
bit 0 TMR3ON: Timer3 On bit
1 = Enables Timer3
0 = Stops Timer3
PIC18F2XK20/4XK20
DS40001303H-page 158 2010-2015 Microchip Technology Inc.
15.1 Timer3 Operation
Timer3 can operate in one of three modes:
•Timer
• Synchronous Coun ter
• Asynchronous Counter
The operating mode is determined by the clock select
bit, TMR3CS of the T3CON register . When TMR3CS is
cleared (= 0), Timer3 increments on every internal
instr uction cyc le (FOSC/4). When the bi t is set, Timer 3
increme nt s on ev ery ris ing edg e o f the Timer1 ext erna l
clock input or the Timer1 oscillator, if enabled.
As with Timer1, the digital circuitry associated with the
RC1/T1OSI and RC0/T1OSO/T13CKI pins is disabled
when the Timer1 oscillator is enabled. This means the
values of TRISC<1:0> are ignored and the pins are
read as ‘0’.
FIGURE 15-1: TIMER3 BLOCK DIAGRAM
T3SYNC
TMR3CS
T3CKPS<1:0>
Sleep Input
T1OSCEN(1)
FOSC/4
Internal
Clock
Prescaler
1, 2, 4, 8 Synchronize
Detect
1
02
T1OSO/T13CKI
T1OSI
1
0
TMR3ON
TMR3L Set
TMR3IF
on Overflow
TMR3
High Byte
Timer1 Oscillato r
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
On/Off
Timer3
CCP1/CCP2 Special Event Trigger
CCP1/CCP2 Select from T3CON<6,3> Clear TMR3
Timer1 Clock Inp ut
2010-2015 Microchip Technology Inc. DS40001303H-page 159
PIC18F2XK20/4XK20
FIGURE 15-2: TIMER3 BLOCK DIAGRAM (16-BIT READ/WRITE MODE)
15.2 Timer3 16-Bit Read/Write Mode
Timer3 can be configured for 16-bit reads and writes
(see Figure 15-2). When the RD16 control bit of the
T3CON register is set, the address for TMR3H is
mapped to a b uffer register fo r the hi gh by te o f Timer3.
A read from TMR3L will load the contents of the high
byte of T imer3 into the T imer3 High Byte Buffer register .
This provides the user with the ability to accurately read
all 16 bits of Timer1 without having to determine
whether a read of the high byte, followed by a read of
the low byte, has become invalid due to a rollover
between reads.
A write to the high byte of Timer3 must also take place
through the TMR3H Buffer register. The Timer3 high
byte is updated with the contents of TMR3H when a
write occurs to TMR3L. This allows a user to write all
16 bit s to both the high and low bytes of T imer3 at once.
The high byte of Timer3 is not directly readable or
writable in this mode. All reads and writes must take
place through the Timer3 High Byte Buffer register.
Writes to TMR3H do not clear the Timer3 prescaler.
The prescaler is only cleared on writes to TMR3L.
15.3 Using the Timer1 Oscillator as t he
Timer3 Clock Source
The T i mer1 inte rnal oscil lator may be used as the clock
source for Timer3. The Timer1 oscillator is enabled by
setting th e T1OSCEN bit of the T1 CON register . To use
it as the Timer3 clock source, the TMR3CS bit must
also be set. As previously noted, this also configures
Timer3 to increment on every rising edge of the
oscillator source.
The Timer1 oscillator is described in Section 13.0
“Tim er 1 Mod ule” .
15.4 Timer3 Interrupt
The TMR3 register pair (TMR3H:TMR3L) increments
from 0000h to FFFFh and overflows to 0000h. The
Timer3 interrupt, if enabled, is generated on overflow
and is latched in interrupt flag bit, TMR3IF of the PIR2
register. This interrupt can be enabled or disabled by
setting or clearing the Timer3 Interrupt Enable bit,
TMR3IE of the PIE2 register.
T3SYNC
TMR3CS
T3CKPS<1:0>
Sleep Input
T1OSCEN(1)
FOSC/4
Internal
Clock
Prescaler
1, 2, 4, 8 Synchronize
Detect
1
02
T13CKI/T1OSO
T1OSI
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
1
0
TMR3L
Internal Data Bus
8
Set
TMR3IF
on Overflow
TMR3
TMR3H
High Byte
88
8
Read TMR1L
Write TMR1L
8
TMR3ON
CCP1/CCP2 Special Event Trigger
Timer1 Oscillato r
On/Off
Timer3
Timer1 Clock Inpu t
CCP1/CCP2 Select from T3CON<6,3> Clear TMR3
PIC18F2XK20/4XK20
DS40001303H-page 160 2010-2015 Microchip Technology Inc.
15.5 Resetting Timer3 Using the CCP
S pecial Event Trigger
If either of the CCP modules is configured to use
Timer3 and to generate a Special Event Trigger
in Compare mode (CCP1M<3:0> or CCP2M<3:0> =
1011), this signal will reset Timer3. It will also start an
A/D conversion if the A/D module is enabled (see
Section 11.3.4 “Special Event Trigger” for more
information).
The module must be configured as either a timer or
synch rono us cou nte r to t a ke a dv antage of this featu re.
When used this way, the CCPR2H:CCPR2L register
pair effectively becomes a period register for Timer3.
If Timer3 is running in Asynchronous Counter mode,
the Reset operation may not work.
In the event that a write to Timer3 coincides with a
S pecial Event Trigger from a CCP module, the write will
take precedence.
TABLE 15-1: REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER
Note: The Special Event Triggers from the
CCP2 module will not set the TMR3IF
interrupt flag bit of the PIR2 register.
Name Bit 7 Bit 6 B it 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 56
PIR2 OSCFIF C1IF C2IF EEIF BCLIF HLVDIF TMR3IF CCP2IF 59
PIE2 OSCFIE C1IE C2IE EEIE BCLIE HLVDIE TMR3IE CCP2IE 59
IPR2 OSCFIP C1IP C2IP EEIP BCLIP HLVDIP TMR3IP CCP2IP 59
TMR3L Timer3 Register, Low Byte 58
TMR3H Timer3 Register, High Byte 58
T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 57
T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 58
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module.
2010-2015 Microchip Technology Inc. DS40001303H-page 161
PIC18F2XK20/4XK20
16.0 ENHANCED
CAPTURE/COMPARE/PWM
(ECCP) MODULE
CCP1 is implemented as a standard CCP module with
enhanc ed PWM capabilities. Thes e inc lu de:
• Provision for two or four output channels
• Output steering
• Programmable polarity
• Programmable dead-band control
• Automatic shutdown and restart.
The enhanced features are discussed in detail in
Section 16.4 “PWM (Enhanced Mode)”. Capture,
Compare and single-output PWM functions of the
ECCP module are the same as described for the
standard CCP module.
The control register for the enhanced CCP module is
shown in Register 16-1. It differs from the CCP2CON
register in that the two Most Significant bits are
implemented to control PWM functionality.
REGISTER 16-1: CCP1CON: ENHANCED CAPTURE/COMPARE/PWM CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unim plem ented bit, rea d as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is clear ed x = Bi t is unk nown
bit 7-6 P1M<1:0>: Enhanced PW M O ut pu t Co nf igur at i on bits
If CCP1M<3:2> = 00, 01, 10:
xx = P1A assig ned as Capt ur e/ Com par e in put/output ; P1B, P1C , P1D assigned as po rt pi ns
If CCP1M<3:2> = 11:
00 = S ingle o utput: P1 A, P1B, P1 C an d P1D contro lled by steering (See Se ctio n 16.4.7 “Pu lse Steer ing
Mode”).
01 = Full-bridge output forward: P1D modulated; P1A active; P1B, P1C inactive
10 = Half-b ridg e out p ut : P1 A, P1B m odulated wit h de ad- band contr ol ; P1C , P1D assigned as por t pin s
11 = Full-bridg e output reverse : P1 B m odulated; P1C ac t ive; P1A, P1D inactive
bit 5-4 DC1B<1:0>: PWM Dut y Cycle bit 1 and bit 0
Captur e m ode:
Unused.
Compare mode:
Unused.
PWM mode:
The se bits are the two LSbs of the 10- bit PWM duty cycle. The eigh t MSbs of th e duty cycle a re found in
CCPR1L.
bit 3-0 CCP1M<3:0>: Enhanced C CP M ode Select bits
0000 = Capture/Compare/PWM off (resets ECCP module)
0001 = Reserved
0010 = Compare m ode, toggle output on mat ch
0011 = Reserved
0100 = Capture mode, ev er y fa lling edge
0101 = Capture mode, ev er y risi ng edge
0110 = Capture mode, ever y 4t h rising edge
0111 = Capture mode, ev er y 16t h rising edge
1000 = Compare m ode, initialize C C P1 pin low, set outpu t on com par e m at ch ( se t CC P1IF)
1001 = Compare m ode, initializ e CC P1 pin high, cl ear output on compare ma tc h (s et CCP1IF)
1010 = Compare m ode, genera te softw ar e int err upt only, CC P1 pin reverts to I/O s tate
1011 = Compare m ode, trigger special event (ECCP resets TMR1 or TMR 3, sets CC1IF bit)
1100 = PW M mode; P1A, P1C active-high; P1B, P1D active-high
1101 = PWM mode; P1A, P1C active -high; P1B, P1D active-low
1110 = P W M mo de ; P1A, P1C active-low; P1B, P1D active-h igh
1111 = PW M mode; P1A, P1C active-low; P1B, P1D active-low
PIC18F2XK20/4XK20
DS40001303H-page 162 2010-2015 Microchip Technology Inc.
In addition to the expanded range of modes available
through the CCP1CON register and ECCP1AS
register, the ECCP mo dule h as two additi onal re giste rs
associated with Enhanced PWM operation and
auto-shutdown features. They are:
• PWM1CON (Dead-band delay)
• PSTRCON (output steering)
16.1 ECCP Outputs and Configuration
The enhanced CCP mod ule m ay ha ve up to four PWM
outputs, depending on the selected operating mode.
These outputs, designated P1A through P1D, are
multiplexed with I/O pins on PORTC and PORTD (for
PIC18F4XK20 devices) or PORTB (for PIC18F2XK20
devices). The outputs that are active depend on the
CCP operating mode selected. The pin assignments
are summarized in Table 16-1.
To configure the I/O pins as PWM outputs, the proper
PWM mode must b e selected by set ting the P1M<1: 0>
and CCP1M<3:0> bits. The appropriate TRISC and
TRISD direction bits for the port pins must also be set
as outputs.
16.1.1 ECCP MODULES AND TIMER
RESOURCES
Like the standard CCP module s, the ECCP mod ule can
utilize Timers 1, 2 or 3, depending on the mode
select ed. Timer1 and Timer3 are a va ilable for modules
in Capture or Compare modes, while Timer2 is
available for modules in PWM mode. Interactions
betwee n the stand ard and enhanc ed CCP modul es are
identic al to those d escribed fo r standard CCP modules .
Additional details on timer resources are provided in
Section 11.1.1 “CCP Modules and Timer
Resources”.
16.2 Capture and Compare Modes
Except for the operation of the Special Event Trigger
discussed below, the Capture and Compare modes of
the ECCP module are identical in operation to that of
CCP2. These are discussed in detail in Section 11.2
“Capture Mode” and Section 11.3 “Compare
Mode”. No changes are required when moving
between 28-pin and 40/44-pin devices.
16.2.1 SPECIAL EVENT TRIGGER
The Special Event Trigger output of ECCP1 resets the
TMR1 o r TMR3 regist er pa ir , depe nding on w hich timer
resource is currently selected. This allows the CCPR1
register to effectively be a 16-bit programmable period
register for Timer1 or Timer3.
16.3 Standard PWM Mode
When configured in Single Output mode, the ECCP
module functions identically to the standard CCP
module in PWM mode, as described in Section 11.4
“PWM Mode”. This is also sometimes referred to as
“Single CCP” mode, as in Table 16-1.
2010-2015 Microchip Technology Inc. DS40001303H-page 163
PIC18F2XK20/4XK20
16.4 PWM (Enhanced Mode)
The Enhanced PWM Mode can generate a PWM signal
on up to four different output pins with up to ten bits of
resolution. It can do this through four different PWM
output modes:
• Single PWM
• Half-Bridge PWM
• Full-Bridge PWM, Forward mod e
• Full-Bridge PWM, Reverse mode
To select an Enhanced PWM mode, the P1M bits of the
CCP1CON register must be set appropriately.
The PWM outputs are multiplexed with I/O pins and are
designated P1A, P1B, P1C and P1D. The polarity of the
PWM pins is configurable and is selected by setting the
CCP1M bits in the CC P1CON register appropriately.
Table 16-1 shows the pin assignments for each
Enhanced PWM mode.
Figure 16-1 shows an example of a simplified block
diagram of the Enhanced PWM module.
FIGURE 16- 1: EXAMPLE SIMPLIFI ED B LOCK DIA GRAM OF T HE ENH ANC ED PW M MODE
TABLE 16-1: EXAMPLE PIN ASSIGNMENTS FOR VARIOUS PWM ENHANCED MODES
Note: The PW M Enhance d mode is availa ble on
the Enhanced Capture/Compare/PWM
module (CCP1) only.
Note: To prevent the generation of an
incomplete waveform when the PWM is
first enab led, the ECCP mo dule wait s until
the start of a new PWM period before
generating a PWM signal.
CCPR1L
CCPR1H (Slave)
Comparator
TMR2
Comparator
PR2
(1)
RQ
S
Duty Cycle Registers DC1B<1:0>
Clear Timer2,
toggle PWM pin and
latch duty cycle
Note 1: The 8-b i t tim er T MR2 re gister is con c ate na ted wi th the 2- bit i nte rna l Q clock, or 2 bits of the p res cal er to cr eat e t he 10- bit
time base.
TRIS
CCP1/P1A
TRIS
P1B
TRIS
P1C
TRIS
P1D
Output
Controller
P1M<1:0> 2CCP1M<3:0>
4
PWM1CON
CCP1/P1A
P1B
P1C
P1D
Note 1: The TRIS register value for each PWM output must be configured appropriately.
2: Clearing the CCPxCON register will relinquish ECCP control of all PWM output pins.
3: Any pin not used by an Enhanced PWM mode is available for alternate pin functions.
ECCP Mode P1M<1:0> CCP1/P1A P1B P1C P1D
Single 00 Yes(1) Yes(1) Yes(1) Yes(1)
Half-Bridge 10 Yes Yes No No
Full-Bridg e, Forward 01 Yes Yes Yes Yes
Full-Bridg e, Reve rse 11 Yes Yes Yes Yes
Note 1: Outputs are enabled by pulse steering in Single mode. See Register 16-4.
PIC18F2XK20/4XK20
DS40001303H-page 164 2010-2015 Microchip Technology Inc.
FIGURE 16-2: EXAMPL E PWM (ENHANCE D MODE) OUTPUT RELATIONSHIPS (ACTIVE-HIGH
STATE)
0
Period
00
10
01
11
Signal PR2+1
P1M<1:0>
P1A Modulated
P1A Modulated
P1B Modulated
P1A Active
P1B Inactive
P1C Inactive
P1D Modulated
P1A Inactive
P1B Modulated
P1C Active
P1D Inactive
Pulse
Width
(Single Output)
(Half-Bridge)
(Full-Bridge,
Forward)
(Full-Bridge,
Reverse)
Delay(1) Delay(1)
Relationships:
• Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Valu e)
• Pulse Width = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value)
• Delay = 4 * TOSC * (PWM1CON<6:0>)
Note 1: Dead-band delay is programmed using the PWM1CON register (Section 16.4.6 “Programmable Dead-Band Delay
mode”).
2010-2015 Microchip Technology Inc. DS40001303H-page 165
PIC18F2XK20/4XK20
FIGURE 16-3: EXAMPL E ENHA NCED PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE)
0
Period
00
10
01
11
Signal PR2+1
P1M<1:0>
P1A Modulated
P1A Modulated
P1B Modulated
P1A Active
P1B Inactive
P1C Inact ive
P1D Modulated
P1A Inactive
P1B Modulated
P1C Active
P1D Inact ive
Pulse
Width
(Single Output)
(Half-Bridge)
(Full-Bridge,
Forward)
(Full-Bridge,
Reverse)
Delay(1) Delay(1)
Relationships:
• Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value)
• Pulse Width = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value)
• Delay = 4 * TOSC * (PWM1CON<6:0>)
Note 1: Dead-band delay is programmed using the PWM1CON register (Section 16.4.6 “Programmable Dead-Band Delay
mode”).
PIC18F2XK20/4XK20
DS40001303H-page 166 2010-2015 Microchip Technology Inc.
16.4.1 HALF-BRIDGE MODE
In Half-Bridge mode, two pins are used as outputs to
drive push-pull load s. The PWM output s ign al is o utp ut
on the CCPx/P1A pin, while the complementary PWM
output signal is output on the P1B pin (see
Figure 16-5). This mode can be used for Half-Bridge
applications, as shown i n Figure 16-5, or for Full-Bridge
applications, where four power switches are being
modulated with two PWM signals.
In Half-Bridge mode, the programmable dead-band delay
can be used to prevent shoot-through current in
Half-Bridge power devices. The value of the PDC<6:0>
bits of the PWM1CON register sets the number of
instruction cycles before the output is driven active. If the
value is greater than the duty cycle, the corresponding
output remains inactive during the entire cycle. See
Section 16.4.6 “Programmable Dead-Band Delay
mode” for more details of the dead-band delay
operations.
Since the P1A and P1B outputs are multiplexed with
the PORT data latches, the associated TRIS bits must
be cleared to configure P1A and P1B as outputs.
FIGURE 16-4: EXAMPLE OF
HALF-BRIDGE PWM
OUTPUT
FIGURE 16-5: EXAMPLE OF HALF-BRIDGE APPLICATIONS
Period
Pulse Width
td
td
(1)
P1A(2)
P1B(2)
td = Dead-Band Delay
Period
(1) (1)
Note 1: At this t ime, the T MR2 reg ister is equal to the
PR2 register.
2: Output signals are shown as active-high.
P1A
P1B
FET
Driver
FET
Driver
Load
+
-
+
-
FET
Driver
FET
Driver
V+
Load
FET
Driver
FET
Driver
P1A
P1B
Standard Half-Bridge Circuit (“Push-Pull ”)
Half-Bridge Output Driving a Full-Bridge Circuit
2010-2015 Microchip Technology Inc. DS40001303H-page 167
PIC18F2XK20/4XK20
16.4.2 FULL-BRIDGE MODE
In Full-Bridge mode, all four pins are used as outputs.
An example of Full-Bridge application is shown in
Figure 16-6.
In the Forward mode, pin CCP1/P1A is driven to its
active state, pin P1D is modulated, while P1B and P1C
will be driven to their inactive state as shown in
Figure 16-7.
In the Reverse mode, P1C is driven to its active state,
pin P1B is modulated, while P1A and P1D wi l l be driven
to their inactive state as shown Figure 16-7.
P1A, P1B, P1C and P1D outputs are multiplexed with
the POR T dat a latc hes. The a ssoc iated T RIS bit s mus t
be cleared to configure the P1A, P1B, P1C and P1D
pins as outputs.
FIGURE 16-6: EXAMPL E OF FULL-BRIDGE APPLICAT ION
P1A
P1C
FET
Driver
FET
Driver
V+
V-
Load
FET
Driver
FET
Driver
P1B
P1D
QA
QB QD
QC
PIC18F2XK20/4XK20
DS40001303H-page 168 2010-2015 Microchip Technology Inc.
FIGURE 16-7: EXAMPLE OF FULL-BRIDGE PWM OUTPUT
Period
Pulse Width
P1A(2)
P1B(2)
P1C(2)
P1D(2)
Forw a r d M o de
(1)
Period
Pulse Width
P1A(2)
P1C(2)
P1D(2)
P1B(2)
Reverse Mode
(1)
(1)
(1)
Note 1: At this time, the TMR2 register is equal to the PR2 register .
2: Output signal is shown as active-high.
2010-2015 Microchip Technology Inc. DS40001303H-page 169
PIC18F2XK20/4XK20
16.4.2.1 Direction Change in Full-Bridge
Mode
In the Full-Bridge mode, the P1M1 bit in the CCP1CON
register allows users to control the forward/reverse
direction. When the application firmware changes this
direction co ntrol bit, the modu le will change to the new
direction on the next PWM cycle.
A direction change is initiated in software by changing
the P1M1 bit of the CCP1CON register. The following
sequence occurs prior to the end of the current PWM
period:
• The modu lated output s (P1B and P1D) are placed
in their inactive state.
• The associated unmodulated outputs (P1A and
P1C) are switched to drive in the opposite
direction.
• PWM mo dulati on resumes at the be ginnin g of the
next period.
See Figure 16-8 for an illustration of this sequence.
The Full-Bridge mode does not provide dead-band
delay. As one outpu t is modulated at a tim e, dead-band
delay is generally not required. There is a situation
where dead-band delay is required. This situation
occurs when both of the following conditions are true:
1. The direction of the PWM output changes when
the duty cycle of the output is at or near 100%.
2. The turn off time of the power switch, including
the power device and driver circuit, is greater
than the turn on time.
Figure 16-9 shows an example of the PWM direction
chan gi ng from for w ar d to rev ers e , at a ne ar 100% duty
cycle. In this example, at time t1, the output P1A and
P1D become inactive, while output P1C becomes
active. Since the turn off time of the power devices is
longer than the turn on time, a shoot-through current
will flow through power devices QC and QD (see
Figure 16-6) for the duration of ‘t’. The same
phenomenon will occur to power devices QA and QB
for PWM di rec t io n ch an ge from reve rs e to forw a rd.
If changing PWM direction at high duty cycle is required
for an app lication, two possible solutions f or eliminatin g
the shoot-through current are:
1. Reduce PWM duty cycle for one PWM period
before changing directions.
2. Use switch drivers that can drive the switches of f
faster than they can drive them on.
Other options to prevent shoot-through current may
exist.
FIGURE 16-8: EXAMP LE OF PWM DIRECTION CHANGE
Pulse Width
Period(1)
Signal
Note 1: The direction bit P1M1 of the CCP1CON register is written any time during the PWM cycle.
2: When changing directions, the P1A and P1C signals switch before the end of the current PWM c ycle. The
modulated P1B and P1D signals are inactive at this time. The length of this time is (1/FOSC) TMR2 prescale
value.
Period
(2)
P1A (Active-High)
P1B (Active-High)
P1C (Active-High)
P1D (Active-High)
Pulse Width
PIC18F2XK20/4XK20
DS40001303H-page 170 2010-2015 Microchip Technology Inc.
FIGURE 16-9: EXAMP LE OF PWM DIRECT ION CHANGE AT NEAR 100% DUTY CYCLE
16.4.3 START-UP CONSIDERATIONS
When any PWM mode is used, the application
hardware must use the proper external pull-up and/or
pull-down resistors on the PWM output pins.
The CCP1M<1:0> bits of the CCP1CON register allow
the us er t o ch oose whe the r th e P WM output si gna ls are
active-high or active-low for each pair of PWM output pins
(P1A/P1C and P1B/P1D). The PWM output polarities
must be selecte d bef ore the PWM pi n output driv ers ar e
enabled. Changing the polarity configuration while the
PWM pin outpu t dr ivers ar e enab le is no t recomme nde d
since it may result in damage to the application circuits.
The P1A, P1 B, P1C and P 1D output latches may not be
in the proper states when the PWM module is
initialized. Enabling the PWM pi n output drivers at the
same time as the Enhanced PWM modes may cause
damage to the application circuit. T he En han ce d PW M
modes must be enabled in the proper Output mode an d
complete a full PWM cycle before enabling the PWM
pin output drivers. The completion of a full PWM cycle
is indicated by the TMR2IF bit of the PIR1 register
being set as th e second P WM period begins.
Forward Period Reverse Period
P1A
TON
TOFF
T = TOFF – TON
P1B
P1C
P1D
External Switch D
Potential
Shoot-Through Current
Note 1: All signals are shown as active-high.
2: TON is the turn on delay of power switch QC and its driver.
3: TOFF is the turn off delay of power switch QD and its driver.
External Switch C
t1
PW
PW
Note: When the mi crocon troller is r eleas ed fr om
Reset, all of the I/O pins are in the
high-impedance state. The external cir-
cuits must keep the power switch devices
in the Off state until the microcontroller
drives the I/O pins with the proper signal
levels or activates the PWM output(s).
2010-2015 Microchip Technology Inc. DS40001303H-page 171
PIC18F2XK20/4XK20
16.4.4 ENHANCED PWM
AUTO-SHUTDOWN MODE
The PWM mode supports an Auto-Shut dow n m ode that
will disable the PWM outputs when an external
shutdown event occurs. Auto-Shutdown mode places
the PWM output pins into a predetermined state. This
mode is used to help prevent the PWM from damaging
the application.
The auto-shutdown sources are selected using the
ECCPAS<2:0> bits of the ECCP1AS register. A
shutdow n event ma y be generated by :
•A logic ‘0’ on the FLT0 pin
• Comparator C1
• Comparator C2
• Setting the ECCPASE bit in firmware
A shutdown condition is indicated by the ECCPASE
(Auto-Shutdown Event Status) bit of the ECCP1AS
register. If the bit is a ‘0’, the PWM p ins a re op erati ng
normally. If the bit is a ‘1’, the PWM outputs are in the
shutdown state.
When a shutdow n event oc curs, two things ha ppen:
The ECCPASE bit is set to ‘1’. The ECCPASE will
remain set until cleared in firmware or an auto-restart
occurs (see Section 16.4.5 “Auto-Restart Mode”).
The enabled PWM pins are asynchronously placed in
their shutdown states. The PWM output pins are
grouped into pairs [P1A/P1C] and [P1B/P1D]. The state
of each pin pair is determined by the PSSAC and
PSSBD bits of the ECCP1AS register . Each pin pair may
be placed into one of three st ates:
• Drive logic ‘1’
• Drive logic ‘0’
• Tri-state (high-impedance)
REGISTER 16-2: ECCP1AS: ENHANCED CAPTURE/COMPARE/PWM AUTO-SHUTDOWN
CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 ECCPASE: ECCP Auto-Shutdown Event Status bit
1 = A shutdown event has occurred; ECCP outputs are in shutdown state
0 = ECCP ou tputs are operating
bit 6-4 ECCPAS<2:0>: ECCP Auto-shutdown Source Select bits
000 = Auto-Shutdown is disabled
001 = Comparator C1OUT output is high
010 = Comparator C2OUT output is high
011 = Either C omparator C1 OUT or C2OUT is high
100 =V
IL on FLT0 pin
101 =V
IL on FLT0 pin or Comparator C1OUT output i s high
110 =V
IL on FLT0 pin or Comparator C2OUT output i s high
111 =V
IL on FLT0 pin or Comparator C1OUT or Comparator C2OUT is high
bit 3-2 PSSACn: Pins P1A and P1C Shutdown State Control bits
00 = Drive pins P1A and P1C to ‘0’
01 = Drive pins P1A and P1C to ‘1’
1x = Pins P1A and P1C tri-state
bit 1-0 PSSBDn: Pins P1B and P1D Shutdown State Control bits
00 = Drive pins P1B and P1D to ‘0’
01 = Drive pins P1B and P1D to ‘1’
1x = Pins P1B and P1D tri-state
PIC18F2XK20/4XK20
DS40001303H-page 172 2010-2015 Microchip Technology Inc.
FIGURE 16-10: PWM AUTO-SHUTDOWN WITH FIRMWARE RESTART (PRSEN = 0)
16.4.5 AUTO-RESTAR T MODE
The Enhanced PWM can be configured to automati-
cally restart the PWM signal once the auto-shutdown
condition has been removed. Auto-restart is enabled by
setting the PRSEN bit in the PWM1CON register.
If auto-restart is enabled, the ECCPASE bit will remain
set as long as the auto-shutdown condition is active.
When the auto-shutdown condition is removed, the
ECCPASE bit will be cleared via hardware and normal
operation will resume.
FIGURE 16-11: PWM AUTO-SHUTDOWN WITH AUTO-RESTART ENABLED (PRSEN = 1)
Note 1: The auto-shutdown condition is a
level-based signal, not an edge-based
signal . As long as the level i s present, the
auto-shutdown will persist.
2: Writing to the ECCPASE bit is disabled
while an auto-shutdown condition
persists.
3: Once the auto-shutdown condition has
been removed and the PWM restarted
(either through firmware or auto-restart)
the PWM signal will always restart at the
beginning of the next PWM period.
Shutdown
PWM
ECCPASE bit
Activity
Event
Shutdown
Event Occurs Shutdown
Event Clears PWM
Resumes
Normal PWM
Start of
PWM Period
ECCPASE
Cleared by
Firmware
PWM Period
Shutdown
PWM
ECCPAS E bit
Activity
Event
Shutdown
Event Occurs Shutdown
Event Cle ars PWM
Resumes
Normal PWM
Start of
PWM Period
PWM Period
2010-2015 Microchip Technology Inc. DS40001303H-page 173
PIC18F2XK20/4XK20
16.4.6 PROGRAMMABLE DEAD-B AND
DELAY MODE
In Half-Bridge applications where all power switches
are modulated at the PWM frequency, the power
switches normally require more time to turn off than to
turn on. If b oth the u pper and lowe r power swit ches ar e
switched at the same time (one turned on, and the
other turned off), both switches may be on for a short
period of time until one switch completely turns off.
During this brief interval, a very high current
(shoot-through current) will flow through both power
switches, shorting the bridge supply. To avoid this
potentially destructive shoot-through current from
flowin g d urin g s witc hin g, tu rning on either of the power
switches is normally delayed to allow the other switch
to completely turn off.
In Half-Bridge mode, a digitally programmable
dead-band delay is available to avoid shoot-through
current fro m destroying the bri dge power switc hes. The
delay occurs at the signal transition from the non-active
state to the active state. See Figure 16-12 for
illustration. The lower seven bits of the associated
PWM1CON register (Register 16-3) sets the delay
period in terms of microcontroller instruction cycles
(TCY or 4 TOSC).
FIGURE 16-12: EXAMPLE OF
HALF-BRIDGE PWM
OUTPUT
FIGURE 16-13 : EXAMPL E OF HALF-BRIDGE APPLICATIONS
Period
Pulse Width
td
td
(1)
P1A(2)
P1B(2)
td = Dead-Band Delay
Period
(1) (1)
Note 1: At this time, the TMR2 register is equal to the
PR2 register.
2: Output signals are shown as active-high.
P1A
P1B
FET
Driver
FET
Driver
V+
V-
Load
+
V
-
+
V
-
Standard Half-Bridge Circuit (“Push-Pull ”)
PIC18F2XK20/4XK20
DS40001303H-page 174 2010-2015 Microchip Technology Inc.
REGISTER 16-3: PWM1CON: ENHANCED PWM CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PRSEN PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 PRSEN: PWM Restart Enab le bit
1 = Upon auto-shutdown, the ECCPASE bit clears automatically once the shutdown event goes
away; the PWM restarts automatically
0 = Upon auto-shutdown, ECCPASE must be cleared by software to restart the PWM
bit 6-0 PDC<6:0>: PWM Delay Count bits
PDCn = Number of FOSC/4 (4 * TOSC) cycles between the scheduled time when a PWM signal
should transition active and the actual time it transitions active
2010-2015 Microchip Technology Inc. DS40001303H-page 175
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16.4.7 PULSE STEERING MODE
In Sing le Output mode, pul se steering all ows any of the
PWM pins to be t he modulated signal. Addi tio nal ly, the
same PWM signal can be simultaneously available on
multiple pins.
Once the Single Output mode is selected
(CCP1M<3:2> = 11 and P1M<1:0> = 00 of the
CCP1CON register), the user firmware can bring out
the same PWM signal to one, two, three or four output
pins by setting the appropriate STR<D:A> bits of the
PSTRCON register, as shown in Table 16-1.
While th e PWM Stee rin g m ode is ac ti ve, C CP1M <1:0 >
bits of the CCP1CON register select the PWM output
polarity for the P1<D:A> pins.
The PWM auto-shutdown operation also applies to
PWM Steering mode as described in Section 16.4.4
“Enhanced PWM Auto-shutdown mode”. An
auto-shutdown event will only affect pins that have
PWM outputs enabled.
Note: The associated TRIS bits must be set to
output (‘0’) to enable the pin output driver
in order t o see t he PWM signa l on th e pin.
REGISTER 16-4: PSTRCON: PULSE STEERING CONTROL REGISTER(1)
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1
— — — STRSYNC STRD STRC STRB STRA
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-5 Unimplemented: Read as ‘0’
bit 4 STRSYNC: Steering Sync bit
1 = Output steering update occurs on next PWM period
0 = Output steering update oc curs at the beginning of the instruction cycle boundary
bit 3 STRD: Steering Enable bit D
1 = P1D pin has the PWM waveform with polarity control from CCPxM<1:0>
0 = P1D pin is assigned to port pin
bit 2 STRC: Steering Enable bit C
1 = P1C pin has the PWM waveform with polarity control from CCPxM<1:0>
0 = P1C pin is assigned to port pin
bit 1 STRB: Steering Enable bit B
1 = P1B pin has the PWM waveform with polarity control from CCPxM<1:0>
0 = P1B pin is assigned to port pin
bit 0 STRA: Steering Enable bit A
1 = P1A pin has the PWM waveform with polarity control from CCPxM<1:0>
0 = P1A pin is assigned to port pin
Note 1: The PWM Steering mode is available only when the CCP1CON re gister bits C CP1M<3:2> = 11 an d
P1M<1:0> = 00.
PIC18F2XK20/4XK20
DS40001303H-page 176 2010-2015 Microchip Technology Inc.
FIGURE 16-14 : SI MPL IFI ED STEERING
BLOCK DIAGRAM
1
0TRIS
P1A pin
PORT Data
P1A Signal
STRA
1
0TRIS
P1B pin
PORT Data
STRB
1
0TRIS
P1C pin
PORT Data
STRC
1
0TRIS
P1D pin
PORT Data
STRD
Note 1: Port outputs are configured as shown when
the CCP1CON register bits P1M<1:0> = 00
and CCP1M<3:2> = 11.
2: Single PWM output requires setting at least
one of the STRx bits.
CCP1M1
CCP1M0
CCP1M1
CCP1M0
2010-2015 Microchip Technology Inc. DS40001303H-page 177
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16.4.7.1 Steering Synchronization
The STRSYNC bit of the PSTRCON register gives the
user two selections of when the steering event will
happen. When the STRSYNC bit is ‘0’, the steering
event will happen at the end of the instruction that
writes to the PSTRCON register. In this case, the
output signal at the P1<D:A> pins may be an
incomplete PWM waveform. This operation is useful
when the user firmware needs to immediately remove
a PWM signal from the pin.
When the STRSYNC bit is ‘1’, the effective steering
update will happen at the beginning of the next PWM
period. In this case, steering on/off the PWM output will
always produce a complete PWM waveform.
Figures 16-15 and 16-16 illustrate the timing diagrams
of the PWM steering depending on the STRSYNC
setting.
FIGURE 16-15: EXAMPLE OF STEERING EVENT AT END OF INSTRUCTION (STRSYNC = 0)
FIGURE 16-16: EXAMPLE OF STEERING EVENT AT BEGINNING OF INSTRUCTION
(STRSYNC = 1)
PWM
P1n = PWM
STRn
P1<D:A> PORT Data
PWM Period
PORT Data
PWM
PORT Data
P1n = PW M
STRn
P1<D:A> PORT Data
PIC18F2XK20/4XK20
DS40001303H-page 178 2010-2015 Microchip Technology Inc.
16.4.8 OPE RATION IN POWE R-MANAGED
MODES
In Sleep mode, all clock sources are disabled. Timer2
will not increment and the state of the module will not
change. If the ECCP pin is driving a value, it will con-
tinue to drive that value. When the device wakes up, it
will continue from this stat e. If Two-Spee d S t art-ups are
enabled, the initial start-up frequency from HFINTOSC
and the postscaler may not be stable immediately.
In PRI_IDLE mode, the primary clock will continue to
clock the ECCP module without change. In all other
power-managed modes, the selected power-managed
mode clock will clock Timer2. Other power-managed
mode clocks will most likely be different than the
primary clock frequency.
16.4.8.1 Operation with Fail-Safe
Clock Monitor
If the Fai l-Safe Cl ock Monito r is enabl ed, a clo ck failu re
will force the device into the RC_RUN Power-Managed
mode and the OSCFIF bit of the PIR2 register will be
set. The ECCP will then be clocked from the internal
oscillator clock source, which may have a different
clock frequency than the primary clock.
See the previous section for additional details.
16.4.9 EFFECTS OF A RESET
Both Power-on Reset and subsequent Reset s will force
all ports to Input mode and the CCP registers to their
Reset states.
This forces the enhanced CCP module to reset to a
state compatible with the standard CCP module.
2010-2015 Microchip Technology Inc. DS40001303H-page 179
PIC18F2XK20/4XK20
TABLE 16-2: REGISTERS ASSOCIATED WITH ECCP1 MODULE AND TIMER1 TO TIMER3
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 56
RCON IPEN SBOREN —RI TO PD POR BOR 55
PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 59
PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 59
IPR1 PSPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 59
PIR2 OSCFIF C1IF C2IF EEIF BCLIF HLVDIF TMR3IF CCP2IF 59
PIE2 OSCFIE C1IE C2IE EEIE BCLIE HLVDIE TMR3IE CCP2IE 59
IPR2 OSCFIP C1IP C2IP EEIP BCLIP HLVDIP TMR3IP CCP2IP 59
TRISB PORTB Data Direction Control Register 59
TRISC PORTC Data Direction Control Register 59
TRISD PORTD Data Direction Control Register 59
TMR1L Timer1 Register, Low Byte 57
TMR 1H Timer1 Regi st er, Hig h Byte 57
T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 57
TMR2 Timer2 Register 57
T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 57
PR2 Timer2 Pe riod Regis ter 57
TMR3L Timer3 Register, Low Byte 58
TMR 3H Timer3 Regi st er, Hig h Byte 58
T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 58
CCPR1L Capture/Compare/ PWM Register 1, Low Byte 58
CCPR1H Capture/Compare/PWM Register 1, High Byte 58
CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 58
ECCP1AS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 58
PWM1CON PRSEN PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 58
Legend: — = unimplem ented, re ad as ‘0’. Shaded cells are not used during ECCP operation.
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DS40001303H-page 180 2010-2015 Microchip Technology Inc.
17.0 MASTER SY NCHRONOUS
SERIAL PORT (MS SP)
MODULE
17.1 Master SSP (MSSP) Module
Overview
The Master Synchronous Serial Port (MSSP) module is
a serial interface, useful for communicating with other
peripher al or microc ontroll er dev ices . Thes e perip heral
devices may be serial EEPROMs, shift registers,
displa y drivers, A/D converte rs, etc. The MSSP modul e
can operate in one of two modes:
• Serial Peripheral Interface (SPI)
• Inter-Integrated Circuit (I2C)
- Full Master mode
- Slave mode (with general address call)
The I2C interface supports the following modes in
hardware:
•Master mode
• Multi-Master mode
• Slave mode
17.2 Control Registers
The MSSP module has seven associated registers.
These include:
• SSPSTA – STATUS register
• SSPCON1 – First Control register
• SSPCON2 – Second Control register
• SSPBUF – Transmit/Receive buffer
• SSPSR – Shift register (not directly accessible)
• SSPADD – Address register
• SSPMSK – Address Mask register
The use of thes e regis ters an d their i ndivi dual Con figu-
ration bits differ si gni fic ant ly depe nd ing on w he ther th e
MSSP module is operated in SPI or I2C mode.
Additional details are provided under the individual
sections.
17.3 SPI Mode
The SPI mode allows eight bits of data to be
synchronously transmitted and received
simult aneously . All four modes of SPI are supp orted. To
accomplish communication, typically three pins are
used:
• Serial Data Out – SDO
• Serial Data In – SDI/SDA
• Serial Clock – SCK/SCL
Additionally, a fourth pin may be used when in a Slave
mode of operation:
• Slave Select – SS
Figure 17-1 shows the block diagram of the MSSP
module when operating in SPI mode.
FIGURE 17-1: MSSP BLOCK DIAGRAM
(SPI MODE)
( )
Read Write
Internal
Data Bus
SSPSR Reg
SSPM<3:0>
bit 0 Shift
Clock
SS Control
Enable
Edge
Select
Clock Select
TMR2 Output
TOSC
Prescaler
4, 16, 64
2
Edge
Select
2
4
Data to TX/RX in SSPSR
TRIS bit
2
SMP:CKE
SDO
SSPBUF Reg
SDI/SDA
SS
SCK/SCL
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17.3.1 REGISTERS
The MSSP module has four registers for SPI mode
operation. These are:
• SSPCON1 – Control Register
• SSPSTAT – STATUS register
• SSPBUF – Serial Receive/Transmit Buffer
• SSPSR – Shift Register (Not directly accessible)
SSPCON1 and SSPSTAT are the control and STATUS
register s i n SPI mod e o pera tio n. Th e SSPCON1 re gi s-
ter is readable and writable. The lower six bits of the
SSPSTAT are read-only. The upper two bits of the
SSPSTAT are read/write.
SSPSR is the shift regi ster used for shifti ng data in and
out. SSPBUF provides indirect access to the SSPSR
register. SSPBUF is the buffer register to which data
bytes are written, and from which data bytes are read.
In receive operations, SSPSR and SSPBUF together
create a double-buffered receiver. When SSPSR
receives a complete byte, it is transferred to SSPBUF
and the SSPIF interrupt is set.
During transmission, the SSPBUF is not
double-buffered. A write to SSPBUF will write to both
SSPBUF and SSPSR.
REGISTER 17-1: SSPSTAT: MSSP STATUS REGISTER (SPI MODE)
R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0
SMP CKE D/A PSR/WUA BF
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 SMP: Sample bit
SPI Master mode:
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
SPI Slave mode:
SMP must be cleared when SPI is used in Slave mode.
bit 6 CKE: SPI Clock Select bit(1)
1 = Output data changes on clock transition from active to idle
0 = Output data changes on clock transition from idle to active
bit 5 D/A: Data/Address bit
Used in I2C mode onl y.
bit 4 P: Stop bit
Used in I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.
bit 3 S: Start bit
Used in I2C mode onl y.
bit 2 R/W: Read/Write Information bit
Used in I2C mode onl y.
bit 1 UA: Update Address bit
Used in I2C mode onl y.
bit 0 BF: Buffer Full Status bit (Receive mode only)
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
Note 1: Polarity of clock state is set by the CKP bit of the SSPCON1 register.
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REGISTER 17-2: SSPCON1: MSSP CONTROL 1 REGISTER (SPI MODE)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 WCOL: Write Collision Detect bit (Transmit mode only)
1 = The SSPBUF register is written while it is still transmitting the previous word
(must be cleared by software)
0 = No collis io n
bit 6 SSPOV: Receive Overflow Indicator bit(1)
SPI Slave mode:
1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of over-
flow, the data in SSPSR is lost. Overflow can only occur in Slave mode. The user must read the
SSPBUF, even if only transmitting data, to avoid setting overflow (must be cleared by software).
0 = No overflow
bit 5 SSPEN: Synchronous Serial Port Enable bit(2)
1 = Enab les serial port and config ures SCK, SD O, SDI and SS as serial p ort pins . When en abled , the
SDA and SCL pins must be configured as inputs.
0 = Disables serial port and configures these pins as I/O port pins
bit 4 CKP: Clock Polarity Select bit
1 = Idle state for clock is a high level
0 = Idle state for clock is a low level
bit 3-0 SSPM<3:0>: Synchronous Serial Port Mode Select bits(3)
0101 = SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin
0100 = SPI Slave mode, clock = SCK pin, SS pin control enabled
0011 = SPI Master mode, clock = TMR2 output/2
0010 = SPI Master mode, clock = FOSC/64
0001 = SPI Master mode, clock = FOSC/16
0000 = SPI Master mode, clock = FOSC/4
Note 1: In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by
writing to the SSPBUF register.
2: When enabled, these pins must be properly configured as input or output.
3: Bit combinations not specific ally listed here are either reserved or implemented in I2C mode only.
2010-2015 Microchip Technology Inc. DS40001303H-page 183
PIC18F2XK20/4XK20
17.3.2 OPERATION
When initializing the SPI, several options need to be
specif ied. This is done by progra mming the ap propriate
control bits (SSPCON1<5:0> and SSPSTAT<7:6>).
These control bits allow the following to be specified:
• Master mode (SCK is the clock output)
• Slave mode (SCK is the clock input)
• Clock Polarity (Idle state of SCK)
• Data Input Sample Phase (middle or end of data
output time)
• Clock Edge (output data on rising/falling edge of
SCK)
• Clock Rate (Master mode only)
• Slave Select mode (Slave mode only)
The MS SP consists of a transmi t/recei ve shift regi ster
(SSPSR) and a buf fer register (SSPBUF). The SSPSR
shifts the data in and out of the device, MSb first. The
SSPBUF holds the data that was written to the SSPSR
unti l the rece ived da ta is ready. Once th e eight bi ts of
data have been received, that byte is moved to the
SSPBUF register. Then , the Buf fer Full detect bit, BF of
the SSPSTA T registe r , and the i nterrupt flag bit, SSPIF,
are set. This double-buffering of the received data
(SSPBUF) allows the next byte to start reception b efore
reading the data that was just r eceived. Any write to the
SSPBUF registe r during tra nsmission/recep tion of data
will be ignored and the write collision detect bit WCOL
of the SSPCON1 register, will be set. User software
must cl ear t he WCOL bit so th at it can be dete rmined if
the following write(s) to the SSPBUF register
completed successfully.
When the application software is expecting to receive
valid da ta, the SSPBUF shoul d be read before th e next
byte of data to transfer is written to the SSPBUF. The
Buffer Full bit, BF of the SSPSTAT register, indicates
when SSPBUF has been loade d with the recei ved dat a
(transmiss ion is complete ). When the SSPBUF is read,
the BF bit is cleared. This data may be irrelevant if the
SPI is only a transmit ter . Generall y, the MSSP interru pt
is used to determine when the transmission/reception
has completed. The SSPBUF must be read and/or
written. If the interrupt method is not going to be used,
then sof tware pol ling can be d one to ensure that a write
collision does not occur. Example 17-1 shows the
loading of the SSPBUF (SSPSR) for data transmission.
The SSPSR is n ot directly reada ble or wri table and can
only be accessed by addressing th e SSPBUF register.
Additionally, the MSSP STATUS register (SSPSTAT)
indicates the various status conditions.
EXAMPLE 17-1: LOADING THE SSPBUF (SSPSR) REGISTER
LOOP BTFSS SSPSTAT, BF ;Has data been received (transmit complete)?
BRA LOOP ;No
MOVF SSPBUF, W ;WREG reg = contents of SSPBUF
MOVWF RXDATA ;Save in user RAM, if data is meaningful
MOVF TXDATA, W ;W reg = contents of TXDATA
MOVWF SSPBUF ;New data to xmit
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DS40001303H-page 184 2010-2015 Microchip Technology Inc.
17.3.3 ENABLING SPI I/O
To enable the serial port, SSP Enable bit, SSPEN of the
SSPCON1 register, must be set. To reset or reconfig-
ure SPI mode, clear the SSPEN bit, reinitialize the
SSPCON registers and then set the SSPEN bit. This
configures the SDI, SDO, SCK and SS pins as serial
port pin s. For the pins t o beha ve as t he serial port fun c-
tion, some must have their data direction bits (in the
TRIS register) appropriately programmed as follows:
• SDI is a utomatically con trolled by the SPI mo dul e
• SDO must have corresponding TRIS bit cleared
• SCK (Master mode) must have corresponding
TRIS bit cleared
• SCK (Slave mode) must have corresponding
TRIS bit set
•SS
must have corresponding TRIS bit set
Any serial port function that is not desired may be
overridden by programming the corresponding data
direction (TRIS) register to the opposite value.
17.3.4 TY PIC AL CO NNEC TION
Figure 17-2 shows a typical connection between two
microcontrollers. The master controller (Processor 1)
initiates the data transfer by sending the SCK signal.
Data is shifted out of both shift registers on their pro-
grammed clock e dge and l atched on the oppos ite edge
of the clock. Both processors should be prog rammed to
the same Clock Polarity (CKP), then both controllers
would send and receive data at the same time.
Whether the data is meaningful (or dummy data)
depends on the application software. This leads to
three scenarios for data transmission:
• Master send s data–Slave send s dummy data
• Master send s data–Slave sends data
• Master sends dummy data–Slave sends data
FIGURE 17-2: SPI MASTER/SLAVE CONNECTION
Serial Input Buffer
(SSPBUF)
Shift Register
(SSPSR)
MSb LSb
SDO
SDI
Processor 1
SCK
SPI Master SS PM<3:0> = 00xxb
Serial Input Buffer
(SSPBUF)
Shift Register
(SSPSR)
LSb
MSb
SDI
SDO
Processor 2
SCK
SPI Slav e SSPM < 3:0> = 010xb
Serial Clock
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PIC18F2XK20/4XK20
17.3.5 MASTER MODE
The master can initiate the data transfer at any time
because it controls the SCK. The master determines
when the slave (Processor 2, Figure 17-2) is to
broadcast data by the software protoc ol.
In Master mode, the data is transmitted/received as
soon as the SSPBUF registe r is written to. If the SPI is
only going to receive, the SDO output could be dis-
abled (programmed as an input). The SSPSR register
will co ntinue to shift in the signal pre sent on the SDI pin
at the programmed clock rate. As each byte is
received, it will be loaded into the SSPBUF register as
if a normal received byte (interrupts and Status bits
appropriately set). This could be useful in receiver
applications as a “Line Activity Monitor” mode.
The clock polarity is selected by appropriately
programming the CKP bit of the SSPCON1 register.
This then, would give waveforms for SPI
communication as shown in Figure 17-3, Figure 17-5
and Figure 17-6, where the MSB is transmitted first. In
Master mode, the SPI clock rate (bit rate) is user
programmable to be one of the following:
•F
OSC/4 (or TCY)
•FOSC/16 (or 4 • TCY)
•F
OSC/64 (or 16 • TCY)
• Timer2 output/2
This allows a maximum data rate (at 64 MHz) of
16.00 Mbps.
Figure 17-3 shows the waveforms for Master mode.
When the CKE bit is set, the SDO da ta is valid before
there is a clock edge on SCK. The change of the input
sample is shown based on the st ate of the SMP bit. The
time when the SSPBUF is loaded with the received
dat a is shown.
FIGURE 17-3: SPI MODE WAVEFORM (MASTER MODE)
SCK
(CKP = 0
SCK
(CKP = 1
SCK
(CKP = 0
SCK
(CKP = 1
4 Clock
Modes
Input
Sample
Input
Sample
SDI bit 7 bit 0
SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
bit 7
SDI
SSPIF
(SMP = 1)
(SMP = 0)
(SMP = 1)
CKE = 1)
CKE = 0)
CKE = 1)
CKE = 0)
(SMP = 0)
Write to
SSPBUF
SSPSR to
SSPBUF
SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
(CKE = 0)
(CKE = 1)
Next Q4 Cycl e
after Q2
bit 0
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17.3.6 SLAVE MODE
In Slave m ode , the data is transmitted and rece iv ed as
the external clock pulses appear on SCK. When the
last bit is latched, the SSPIF interrupt flag bit is set.
Before enabling the module in SPI Slave mode, the clock
line must match the proper Idle state. The clock line can
be observed by reading the SCK pin. The Idle state is
determined by the CKP bit of the SSPCON1 register .
While in Slave mode, the external clock is supplied by
the external clock source on the SCK pin. This external
clock must meet the minimum high and low times as
specified in the electrical specifications.
While in Sleep mode, the slave can transmit/receive
data. When a byte is received, the device will wake-up
from Sleep.
17.3.7 SLAVE SELECT
SYNCHRONIZATION
The SS pin allows a Synchronous Slave mode. The
SPI must be in Slave mode wit h SS pin control ena bled
(SSPCON1<3:0> = 04h). The pin must not be driven
low for the SS pin to function as an input. The dat a latch
must be high. When the SS pin is low , transmission and
receptio n are enab led and the SDO pin is driven. When
the SS pin goes hi gh , th e SD O pin is no lo n ge r dr iv en ,
even if in the middle of a tran smitted byte an d becomes
a floating output. External pull-up/pull-down resistors
may be desirable depending on the application.
When the SPI module resets, the bit counter is forced
to ‘0’. This can be done by either forcing the SS pin to
a high level or clearing the SSPEN bi t.
To emulate two-wire communication, the SDO pin can
be connected to the SDI pin. When the SPI needs to
operate as a receiver, the SDO pin can be configured
as an in put. This d isables transmissi ons from th e SDO.
The SDI can always be left as an input (SDI function)
since it can not cre ate a bus con f li ct .
FIGURE 17-4: SLAVE SYNCHRONIZA TION WAVEFORM
Note 1: When the SPI is in Slave mode with SS pin
control enabled (SSPCON<3:0> = 0100),
the SPI module will reset if the SS pin is
set to VDD.
2: When the SPI is us ed in Slav e mode with
CKE set the SS pin control must also be
enabled.
SCK
(CKP = 1
SCK
(CKP = 0
Input
Sample
SDI bit 7
SDO bit 7 bit 6 bit 7
SSPIF
Interrupt
(SMP = 0)
CKE = 0)
CKE = 0)
(SMP = 0)
Write to
SSPBUF
SSPSR to
SSPBUF
SS
Flag
bit 0
bit 7 bit 0
Next Q4 Cycle
after Q2
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PIC18F2XK20/4XK20
FIGURE 17-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0)
FIGURE 17-6: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1)
SCK
(CKP = 1
SCK
(CKP = 0
Input
Sample
SDI bit 7
SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
SSPIF
Interrupt
(SMP = 0)
CKE = 0)
CKE = 0)
(SMP = 0)
Write to
SSPBUF
SSPSR to
SSPBUF
SS
Flag
Optional
Next Q4 Cycle
after Q2
bit 0
SCK
(CKP = 1
SCK
(CKP = 0
Input
Sample
SDI bit 7 bit 0
SDO bit 7 bit 6 bit 5 bi t 4 bit 3 bit 2 bit 1 bit 0
SSPIF
Interrupt
(SMP = 0)
CKE = 1)
CKE = 1)
(SMP = 0)
Wr i te to
SSPBUF
SSPSR to
SSPBUF
SS
Flag
Not Optional
Next Q4 Cycle
after Q2
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DS40001303H-page 188 2010-2015 Microchip Technology Inc.
17.3.8 OPE RATION IN POWE R-MANAGED
MODES
In SPI Master mo de, modu le clo cks may be op erati ng
at a different speed than when in Full-Power mode; in
the case of the Sleep mode, all clocks are halted.
In all Idle mo des, a clock is prov ided to the peri pherals.
That clock could be from the primary cloc k source, the
secondary clock (Timer1 oscillator at 32.768 kHz) or
the INTOSC source. See Section 3.0 “Power-Man-
aged Mod es” for additional information.
In most cases, the speed that the master clocks SPI
data is not important; however, this should be
evaluated for each system.
When MSSP interrupts are enabled, after the master
completes sending data, an MSSP interrupt will wake
the controller:
• from Sleep, in Slave mode
• from Idle, in Slave or Master mode
If an ex it from Sleep or Idl e mode i s not desire d, MSSP
interrupts should be disabl ed.
In SPI master mode, when the Sleep mode is selected,
all module clocks are halted and the transmis-
sion/rec ep tio n w il l rem ai n in t hat s tate until the de vi ce s
wakes . Afte r the devi ce return s to Ru n mode, th e mod-
ule will resume transmitting and receiving data.
In SPI Slave mode, the SPI Transmit/Receive Shift
register operates asynchronously to the device. This
allows the device to be placed in any power-managed
mode and data to be shifted into the SPI
Transmit/Receive Shift register. When all eight bits
have been received, the MSSP interrupt flag bit will be
set and if enabled, will wake the device.
17.3.9 EFFECTS OF A RESET
A Reset disables the MSSP module and terminat es the
current transfer.
17.3.10 BUS MODE COMPATIBILITY
Table 17-1 shows the compatibility between the
standard SPI modes and the states of the CKP and
CKE control bits.
TABLE 17-1: SPI BUS MODES
There is also an SMP bit which controls when the data
is sampled.
TABLE 17-2: REGISTERS ASSOCIATED WITH SPI OPERATION
Standard SPI Mode
Terminology
Control Bits Sta te
CKP CKE
0, 0 0 1
0, 1 0 0
1, 0 1 1
1, 1 1 0
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 56
PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 59
PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 59
IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 59
TRISA TRISA7(2) TRISA6(2) TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 59
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 59
SSPBUF SSP Receive Buffe r/Transmit Register 57
SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 57
SSPSTAT SMP CKE D/A P S R/W UA BF 57
Legend: Shaded cells are not used by the MSSP in SPI mode.
Note 1: These bits are unimplemented in 28-pin devices; always maintain these bits clear.
2: PORTA<7:6> and their direction bits are individually configured as port pins based on various primary
oscillator modes. When disabled, these bits read as ‘0’.
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17.4 I2C Mode
The MSSP module in I2C mode fully implements all
master and slave functions (including general call
support) and provides interrupts on Start and Stop bits
in hardware to determine a free bus (multi-master
function). The MSSP module implements the standard
mode specifications as well as 7-bit and 10-bit
addressing.
Two pins are used for data transfer:
• Serial clock (SCL) – SCK/SCL
• Serial data (SDA) – SDI/SDA
The user must configure these pins as inputs with the
corresponding TRI S bits.
FIGURE 17-7: MSSP BLOCK DIAGRAM
(I2C™ MODE)
17.4.1 REGISTERS
The MSSP module has seven registers for I2C
operation. These are:
• MSSP Control Register 1 (SSPCON1)
• MSSP Control Register 2 (SSPCON2)
• MSSP STATUS register (SSPSTAT)
• Serial Receive/Transmit Buffer Register
(SSPBUF)
• MSSP Shift Register (SSPSR) – Not directly
accessible
• MSSP Address Register (SSPADD)
• MSSP Address Mask (SSPMSK)
SSPCON1, SSPCON2 and SSPSTAT are the control
and STATUS registers in I2C mode operation. The
SSPCON1 and SSPCON2 registers are readable and
writable. The lower six bits of the SSPSTAT are
read-only. The upper two bits of the SSPSTAT are
read/write.
SSPSR is the shift register used for shifting data in or
out. SSPBUF is the buffer register to which data bytes
are written to or read from.
When the SSP is configured in Master mode, the lower
seven bits of SSPADD act as the Baud Rate Generator
reload value. When the SSP is configured for I2C slave
mode the SSPADD register holds the slave device
address. The SSP can be configured to respond to a
range of addresses by qualifying selected bits of the
address register with the SSPMSK register .
In receive operations, SSPSR and SSPBUF together
create a double-buffered receiver. When SSPSR
receives a complete byte, it is transferred to SSPBUF
and the SSPIF interrupt is set.
During transmission, the SSPBUF is not
double-buffered. A write to SSPBUF will write to both
SSPBUF and SSPSR.
Read Write
SSPSR Reg
Match Detect
SSPADD Reg
Start and
Stop bit Detect
SSPBUF Reg
Internal
Data Bus
Addr Match
Set, Reset
S, P bits
(SSPSTAT Reg)
SCK/SCL
SDI/SDA
Shift
Clock
MSb LSb
SSPMSK Reg
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REGISTER 17-3: SSPADD: MSSP ADDRESS AND BAUD RATE REGISTER (I2C MODE)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Master mode
bit 7-0 ADD<7:0>: Baud Rate Clock Divider bits
SCL pin clock period = ((ADD<7:0> + 1) *4)/FOSC
10-Bit Slave mode: Most significant address by te
bit 7-3 Not used: Unused fo r most si gnifican t address byte. Bit st ate of th is regis ter is a don’t care. Bit patter n
sent by master is fixed by I2C spec ification and must be equal to ‘11110’. How ever, those bits are
compared by hardware and are not affected by the value in this register.
bit 2-1 ADD<9:8>: Two Most Significant bits of 10-bit Address
bit 0 Not used: Unused in this mode. Bit state is a “don’t care”.
10-Bit Slave mode: Least significant address by te
bit 7-0 ADD<7:0>: Eight Least Significant bits of 10-bit Address
7-Bi t Slave mode
bit 7-1 ADD<7:1>: 7-bit address
bit 0 Not used: Unused in this mode. Bit state is a “don’t care”.
2010-2015 Microchip Technology Inc. DS40001303H-page 191
PIC18F2XK20/4XK20
REGISTER 17-4: SSPSTAT: MSSP STATUS REGISTER (I2C MODE)
R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0
SMP CKE D/A P(1) S(1) R/W(2, 3) UA BF
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 SMP: Slew Rate Control bit
In Master or Slave mode:
1 = Slew rate control disabled for Standard Speed mode (100 kHz and 1 MHz)
0 = Slew rate control enabled for High-Speed mode (400 kHz)
bit 6 CKE: SMBus Select bit
In Master or Slave mode:
1 = Enable SMBus specific inputs
0 = Disable SMBus specific inputs
bit 5 D/A: Data/Address bit
In Master mode:
Reserved.
In Slave mode:
1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received or transmitted was address
bit 4 P: Stop bit(1)
1 = Indicates that a Stop bit has been detected last
0 = Stop bit was not detected last
bit 3 S: Start bit(1)
1 = Indicates that a Start bit has been detected last
0 = Start bit was not detected last
bit 2 R/W: Read/Write Information bit (I2C mode only)(2, 3)
In Slave mode:
1 = Read
0 = Write
In Master mode:
1 = Transmit is in progress
0 = Transmit is not in progress
bit 1 UA: Update Address bit (10-bit Slave mod e only )
1 = Indicates that the user needs to update the address in the SSPADD register
0 = Address does not need to be updated
bit 0 BF: Buffer Full Status bit
In Transmit mode:
1 = SSPBUF is full
0 = SSPBUF is empty
In Receive mode:
1 = SSPBUF is full (does not include the ACK and Stop bits)
0 = SSPBUF is empty (does not include the ACK and Stop bits)
Note 1: This bit is cleared on Reset and when SSPEN is cleared.
2: This bit holds the R/W bit information following the last address match. This bit is only valid from the
address match to the next Start bit, Stop bit or not ACK bit.
3: ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Active mode.
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DS40001303H-page 192 2010-2015 Microchip Technology Inc.
REGISTER 17-5: SSPCON1: MSSP CONTROL 1 REGISTER (I2C MODE)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 WCOL: Write Collision Detect bit
In Master Transmit mode:
1 = A write to the SSPBUF register was attempte d while the I2C conditions were not valid for a trans-
mission to be started (must be cleared by software)
0 = No coll isi o n
In Slave Transmit mode:
1 = The SSPBUF re gis ter is writte n wh ile it is sti ll tran sm itt ing the pre vi ous wor d (m ust be cl ea red by
software)
0 = No coll isi o n
In Receive mode (Master or Slave modes):
This is a “don’t care” bit.
bit 6 SSPOV: Receive Overflow Indicator bit
In Receive mode:
1 = A byte is received whil e the SSPBUF register is still holding the previous byte (must be cleared
by software)
0 = No overflow
In Transmit mode:
This is a “don’t care” bit in Transmit m ode.
bit 5 SSPEN: Synchronous Serial Port Enable bit
1 = Enables the serial port and configures the SDA and SCL pins as the serial port pins. When
enabled, the SDA and SCL pins must be configured as inputs.
0 = Disables serial port and configures these pins as I/O port pins
bit 4 CKP: SCK Release Control bit
In Slave mode:
1 = Release clo ck
0 = Holds clock low (clock stretch), used to ensure data setup time
In Master mode:
Unused in this mode.
bit 3-0 SSPM<3:0>: Synchronous Serial Port Mode Select bits
1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled
1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled
1011 = I2C Fi rmware Controlled Master mode (Slave Idle)
1000 = I2C Master mode, clock = FOSC/(4 * (SSPADD + 1))
0111 = I2C Slave mode, 10-bit address
0110 = I2C Slave mode, 7-bit address
Bit combinations not specifically listed here are either reserved or implemented in SPI mode only.
2010-2015 Microchip Technology Inc. DS40001303H-page 193
PIC18F2XK20/4XK20
REGISTER 17-6: SSPCON2: MSSP CONTROL REGISTER (I2C MODE)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
GCEN ACKSTAT ACKDT(2) ACKEN(1) RCEN(1) PEN(1) RSEN(1) SEN(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 GCEN: General Call Enable bi t (Slave mode only)
1 = Generate interrupt when a general call address (0000h) is received in the SSPSR
0 = General call address disabled
bit 6 ACKSTAT: Acknowledge Status bit (Master Transmit mode only)
1 = Acknowledge was not received from slave
0 = Acknowledge was received from slave
bit 5 ACKDT: Acknowledge Data bit (Master Receive mode only)(2)
1 = Not A cknowledge
0 = Acknowle dge
bit 4 ACKEN: Acknowledge Sequence Enable bit (Master Receive mode only)(1)
1 = Initiate Acknowledge sequence on SDA and SCL pins and transmit ACKDT data bit.
Automatically cleared by hardware.
0 = Acknowl edge sequen ce Idl e
bit 3 RCEN: Receive Enable bit (Master mode only)(1)
1 = Enables Receive mode for I2C
0 = Rece ive Idle
bit 2 PEN: Stop Condition Enable bit (Master mode only)(1)
1 = Initia te Stop condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Stop condition Idle
bit 1 RSEN: Repeated Start Condition Enable bit (Master mode only)(1)
1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Repeated Start condition Idle
bit 0 SEN: Start Conditio n Enabl e/Stret ch Enable bit(1)
In Master mode:
1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Start condition Idle
In Slave mode:
1 = Clock stretching is enabled for both slav e transmit and slave receive (stretch enabled)
0 = Clock stretching is disabled for slave received. Slave transmit clock stretching remains enabled.
Note 1: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the Idle mode, these bits may not
be set (no spooling) and the SSPBUF may not be written (or writes to the SSPBUF are disabled).
2: Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive.
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DS40001303H-page 194 2010-2015 Microchip Technology Inc.
17.4.2 OPERATION
The MSSP module functions are enabled by setting
SSPEN bit of the SSPCON1 register.
The SSPCON1 register allows control of the I2C
operation. Four mode selection bits of the SSPCON1
register allow one of the following I2C modes to be
selected:
•I
2C Master mode, cl ock = (FOSC/(4 x
(SSPADD + 1))
•I
2C Slave mode (7-bit address)
•I
2C Slave mode (10-bit address)
•I
2C Slave mode (7-bit address) with Start and
Stop bit interrupts enabled
•I
2C Slave mode (10-bit address) with Start and
Stop bit interrupts enabled
•I
2C Firmware Controlled Master mode, slave is
Idle
Selection of any I2C mode with the SSPEN bit set,
forces the SCL and SDA pins to be open-drain,
provided these pins are programmed to inputs by
setting the appropriate TRIS bits. To ensure proper
operation of the module, pull-up resistors must be
provided externally to the SCL and SDA pins.
17.4.3 SLAVE MODE
In Slave mod e, the SCL and SDA pins mu st be co nfi g-
ured as inputs. The MSSP module will override the
input state with the output data when required
(slave-transmitter).
The I2C Slave m od e h ardw a re w i ll alwa ys generate an
interrupt on an address match. Through the mode
select bits, the user can also choose to interrupt on
Start and Stop bits
When an add ress is matched, or the data transfer af ter
an address match is received, the hardware
automatically will generate the Acknowledge (ACK)
pulse and load the SSPBUF register with the received
value currently in the SSPSR register.
Any combination of the following conditions will cause
the MSSP module not to give this ACK pulse:
• The Buffer Full bit, BF bit of the SSPSTAT
register, is set before the transfer is received.
• The overflow bit, SSPOV bit of the SSPCON1
register, is set before the transfer is received.
In this case, the SSPSR register value is not loaded
into the SSPBUF, but bit SSPIF of the PIR1 register is
set. The BF bit is cleared by reading the SSPBUF
register, while bit SSPOV is cleared through software.
The SCL clock input must have a minimum high and
low fo r pro per op eration. The high an d l ow ti me s o f th e
I2C specification, as well as the requirement of the
MSSP module, are sh own in timing para meter 100 and
parameter 101 (See Table 26-20).
17.4.3.1 Addressing
Once the MSSP module has been enabled, it waits for
a S t art conditio n to occur. Foll owing the S t art condi tion,
the 8 bits are shifted into the SSPSR register. All
incoming bits are sampled with the rising edge of the
clock (SCL) line. The value of register SSPSR<7:1> is
compared to the value of the SSPADD register. The
address is compared on the falling edge of the eighth
clock (SCL) pulse. If the addresses match and the BF
and SSPOV bits are clear, the following events occur:
1. The SSPSR register value is loaded into the
SSPBUF register.
2. The Buffer Full bit, BF, is set.
3. An ACK pulse is generated.
4. MSSP Interrupt Flag bi t, SSPIF of the PIR1 reg-
ister , is set (interru pt is generated, if enabled ) on
the falling edge of the ninth SCL pulse.
In 10-bit Address mode, two address bytes need to be
received by the slave. The five Most Significant bits
(MSbs) of the first address byte specify if this is a 10-bit
address. Bit R/W of the SSPSTAT register must specify
a write so the slave device will receive the second
address byte. For a 10-bit address, the first byte would
equal ‘11110 A9 A8 0’, where ‘A9’ and ‘A8’ are the two
MSbs of the address. The sequence of events for 10-bit
address is as follows, with steps 7 through 9 for the
slave-transmitter:
1. Receive first (high) byte of address (bits SSPIF,
BF and UA (of the SSPSTAT register are set).
2. Update the SSPADD regi ster with second (low)
byte of address (clears bit UA and releases the
SCL line).
3. Read the SSPBUF register (clears bit BF) and
clear flag bit, SSPIF.
4. Receive second (low) byte of address (bits
SSPIF, BF and UA are set). If the address
matches then the SCL is held until the next step.
Otherwise the SCL line is not held.
5. Update t he SSPADD register w ith the f irst (high)
byte of address. (This will clear bit UA and
release a hel d SCL line.)
6. Read the SSPBUF register (clears bit BF) and
clear flag bit, SSPIF.
7. Receive Repeated Start condition.
8. Receive first (high) byte of address (bits SSPIF
and BF are set).
9. Read the SSPBUF register (clears bit BF) and
clear flag bit, SSPIF.
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PIC18F2XK20/4XK20
17.4.3.2 Reception
When the R/W bit of the address byte is clear and an
address match occurs, the R/W bit of the SSPSTAT
register is cleare d. The re ceived ad dre ss is loa ded in to
the SSPBUF register and the SDA line is held low
(ACK).
When the address byte overflow condition exists, then
the no Ack no w led ge (ACK) pulse is given. An ov erfl ow
conditi on is define d as either bit BF bit of the SSPST AT
register is set, or bit SSPOV bit of the SSPCON1
register is set.
An MSSP interrupt is generated for each data transfer
byte. Flag bit, SSPIF of the PIR1 register, must be
cleared by software. The SSPSTAT register is used to
determine the status of the byte.
When the SEN bit of the SSPCON2 register is set,
SCK/SCL will be held low (clock stretch) following
each data transfer. The clock must be released by
setting the CKP bit of the SSPCON1 register. See
Section 17.4.4 “Clock Stretching” for more detail.
17.4.3.3 Transmission
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPSTAT register is set. The received address is
loaded into the SSPBUF register. The ACK pulse will
be sent on the ninth bit and pin SCK/SCL is held low
regardless of SEN (see Section 17.4.4 “Clock
Stretching” for more detail). By stretching the clock,
the master will be unable to assert another clock pulse
until the s lav e is don e preparing the transm it da t a. The
transmit data mus t be loaded i nto the SSPBUF reg ister
which also loads the SSPSR register. Then pin
SCK/SCL should be enabled by setting the CKP bit of
the SSPCON1 register. The eight data bits are shifted
out on the falling edge of the SCL input. This ensures
that the SDA signal is valid during the SCL high time
(Figure 17-9).
The ACK pulse from the master-receiver is latched on
the rising edge of the nin th SCL input pu lse. If the SDA
line is high (not ACK), then the data transfer is
comple te. In thi s case , when the ACK is latched by the
slave, the slave logic is reset (resets SSPSTAT
register) an d the slave monito rs for another occurre nce
of the Start bit. If the SDA line was low (ACK), the next
transmit da ta must be loaded into the SSPBUF register .
Again, pin SCK/SCL must be enabled by setting bit
CKP.
An MSSP interrupt is generated for each data transfer
byte. The SSPIF bit must be cleared by software and
the SSPSTAT register is used to determine the status
of the byte. The SSPIF bit is set on the falling edge of
the ninth clock pulse.
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DS40001303H-page 196 2010-2015 Microchip Technology Inc.
FIGURE 17-8: I2C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESS)
SDA
SCL
SSPIF
BF (SSPSTAT< 0>)
SSPOV (SSPCON1<6>)
S
12345678912345678912345 789 P
A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D1 D0
ACK
Receiving Data
ACK
Receiving Data
R/W = 0
ACK
Receiving Address
Cleared by software
SSPBUF is read
Bus master
terminates
transfer
SSPOV is set
because SSPBUF is
still full. ACK is not sent.
D2
6
(PIR1<3>)
CKP
(CKP does not reset to ‘0’ when SEN = 0)
2010-2015 Microchip Technology Inc. DS40001303H-page 197
PIC18F2XK20/4XK20
FIGURE 17-9: I2C™ SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS)
SDA
SCL
SSPIF (PIR1<3>)
BF (SSPSTAT<0>)
A6 A5 A4 A3 A2 A1 D6 D5 D4 D3 D2 D1 D0
1 2 3 4 5 6 7 8 2 3 4 5 6 7 8 9
SSPBUF is wr itten by softwar e
Cleared by software From SSPIF ISR
Data in
sampled
S
ACK
Transmitting Data
R/W = 0
ACK
Receiving Address
A7 D7
9 1
D6 D5 D4 D3 D2 D1 D0
2 3 4 5 6 7 8 9
SSPBUF is written by software
Cleared by software From SSPIF ISR
Transmitting Data
D7
1
CKP
P
ACK
CKP is set by software CKP is set by software
SCL held low
while CPU
responds to SSPIF
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DS40001303H-page 198 2010-2015 Microchip Technology Inc.
FIGURE 17-10 : I2C™ SLAV E MO DE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESS)
SDA
SCL
SSPIF
BF (SSPSTAT<0> )
S123456789 123456789 12345 789 P
1 1 1 1 0 A9A8 A7 A6A5A4A3A2A1A0 D7 D6D5D4D3 D1D0
Receive Data Byte
ACK
R/W = 0
ACK
Receive First Byte of Address
Clear ed by software
D2
6
(PIR1<3>) Cleared by software
Receive Second Byte of Address
Cleared by hardware
when SSPADD is updated
with low byte of address
UA (SSPSTAT<1>)
Clock is held low until
update of SSPADD has
taken place
UA is set indicating that
the SSPADD needs to be
updated
UA is set indicating that
SSPADD needs to be
updated
Cleared by hardware when
SSPADD is updated with high
byte of addre ss
SSPBUF is written with
contents of SSPSR Dummy read of SSPBUF
to clear BF flag
ACK
CKP
12345 789
D7 D6 D5 D4 D3 D1 D0
Receive Data Byte
Bus master
terminates
transfer
D2
6
ACK
Cleared by software Cleared by software
SSPOV (SSPCON1<6>)
SSPOV is set
because SSPB UF is
still full. ACK is not sent.
(CKP does not reset to ‘0’ when SEN = 0)
Clock is held low until
update of SSPADD has
taken place
2010-2015 Microchip Technology Inc. DS40001303H-page 199
PIC18F2XK20/4XK20
FIGURE 17-11: I2C™ SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS)
SDA
SCL
SSPIF
BF (SSPSTAT<0>)
S123456789 123456789 12345 789 P
1 1 1 1 0 A9A8 A7 A6A5A4A3A2A1A0 1 1 1 1 0 A8
R/W=1
ACK
ACK
R/W = 0
ACK
Receive First Byte of Address
Cleared by software
Bus master
terminates
transfer
A9
6
(PIR1<3>)
Receive Second Byte of Address
Cleared by hardware when
SSPADD is updated with low
byte of address
UA (SSPSTAT<1>)
Clock is held low until
update of SSPADD has
taken place
UA is set indicating that
the SSPADD needs to be
updated
UA is set indicating that
SSPADD needs to be
updated
Cleared by hardware when
SSPADD is updated with high
byte of address.
SSPBUF is written with
contents of SSPSR Dummy read of SSPBUF
to clear BF flag
Receive First Byte of Address
12345 789
D7 D6 D5 D4 D3 D1
ACK
D2
6
Tran smitting Data Byte
D0
Dummy read of SSPBUF
to clear BF flag
Sr
Cleared by software
Write of SSPBUF
initiates transmit
Clear ed by software
Completion of
clears BF flag
CKP (SSPCON1<4>)
CKP is set by software
CKP is automatically cleared by hardware, holding SCL low
Clock is held low until
update of SSPADD has
taken place
data transmission
Clock is held low until
CKP is set to ‘1’
third address sequence
BF flag is clear
at the end of the
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17.4.3.4 SSP Mask Register
An SSP Mask (SSPMSK) register is available in I2C
Slave mode as a mask for the value held in the
SSPSR register during an address comparison
operation. A zero (‘0’) bit in the SSPMSK register has
the effect of making the corresponding bit in the
SSPSR register a “don’t care”.
This register is reset to all ‘1’s upon any Reset
condition and, therefore, has no effect on standard
SSP operation until written with a mask value.
This register must be initiated prior to setting
SSPM<3:0> bits to select the I2C Slave mode (7-bit or
10-bit address).
The SSP Mask register is active during:
• 7-bit Address mode: address compare of A<7:1>.
• 10-bi t Address mode: ad dress comp are of A<7:0>
only. The SSP mask has no effect during the
reception of the first (high) byte of the address.
REGISTER 17-7: SSPMSK: SSP MASK REGISTER
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-1 MSK<7:1>: Mask bits
1 = The received address bit n is compared to SSPADD<n> to detect I2C address match
0 = The received address bit n is not used to detect I2C address match
bit 0 MSK<0>: Mask bit for I2C Slave mode, 10-bit Address(1)
I2C Slave mode, 10-bit Address (SSPM<3:0> = 0111):
1 = The received address bit 0 is compared to SSPADD<0> to detect I2C address match
0 = The received address bit 0 is not used to detect I2C address match
Note 1: The MSK0 bit is used only in 10-bit slave mode. In all other modes, this bit has no effect.
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PIC18F2XK20/4XK20
17.4.4 CLOCK STRETCHING
Both 7-bit and 10-bit Slave modes implement
automatic clock stre tch ing during a transmit sequence.
The SEN bit of the SSPCON2 register allows clock
stretching to be enabled during receives. Setting SEN
will cause the SCL pin to be held low at the end of
each data receive sequence.
17.4.4.1 Clock Stretching for 7-bit Slave
Receive Mode (SEN = 1)
In 7-bit Slave Receive mode, on the falling edge of the
ninth clock at the end of the ACK sequence if the BF
bit is set, the CKP bit of the SSPCON1 register is
automatically cleared, forcing the SCL output to be
held low. The CKP being cleared to ‘0’ will assert the
SCL line low. The CKP bit must be set in the user’s
ISR befo re recep tion i s allo wed to co ntinue . By hol ding
the SCL line low, the user has time to service the ISR
and read the contents of the SSPBUF before the
master device can initiate another data transfer
sequence. This will prevent buffer overruns from
occurring (see Figure 17-13).
17.4.4.2 Clock Stretching for 10-bit Slave
Receive Mode (SEN = 1)
In 10-bit Slave Receive mode during the address
sequence, clock stretching automatically takes place
but CKP is not c lea red . Duri ng t his time, if th e UA b it i s
set after the ninth clock, clock stretching is initiated.
The UA bit is set after receiving the upper byte of the
10-bit address and following the receive of the second
byte of the 10-bit address with the R/W bit cleared to
‘0’. The release of the clock line occurs upon updating
SSPADD. Clock stretching will occur on each data
receive sequence as described in 7-bit mode.
17.4.4.3 Clock Stretching for 7-bit Slave
Transmit Mode
7-bit Sl ave Transmit mode i mplem ent s clo ck str etchin g
by clearing the CKP bit after the falling edge of the
ninth clock if the BF bit is clear. This occurs regardless
of the state of the SEN bit.
The user’s ISR must set the CKP bit before transmis-
sion is allowed to continue. By holding the SCL line
low, the user has time to service the ISR and load the
contents of the SSPBUF before the master device can
initiate another data transfer sequence (see
Figure 17-9).
17.4.4.4 Clock Stretching for 10-bit Slave
Transmit Mode
In 10-bit Slave Transmit mode, clock stretching is con-
trolled during the first two address sequences by the
state of the UA bit, just as it is in 10-bit Slave Receive
mode. The first two addresses are followed by a third
address sequence which contains the high-order bits
of the 10-bit address and the R/W bit set to ‘1’. After
the third address sequence is performed, the UA bit is
not set, the module is now configured in Transmit
mode and clock stretching is controlled by the BF flag
as in 7-bit Slave Transmit mode (see Figure 17-11).
Note 1: If the user reads the contents of the
SSPBUF before the falling edge of the
ninth clock, thus clearing the BF bit, the
CKP bit will not be cleared and clock
stretching will not occur.
2: The CKP bit can be set by software
regardless of the state of the BF bit. The
user should be careful to clear the BF bit
in the ISR before the next receive
sequence in order to prevent an overflow
condition.
Note: If the us er polls the UA bit and clears it by
updating the SSPADD register before the
falling edge of the n inth clock occurs an d if
the user hasn’t cleared the BF bit by read-
ing the SSPBUF register before that time,
then the C KP bi t will sti ll NO T be asserte d
low. Clock stretching on the basis of the
state of the BF bit only occurs during a
dat a seq uence , not an a ddress seque nce.
Note 1: If th e user loads the con tents of SSPBUF,
setting the BF bit before the falling edge
of the ninth clock, the CKP bit will not be
cleared and clock stretching will not
occur.
2: The CKP bit can be set by software
regardless of the state of the BF bit.
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DS40001303H-page 202 2010-2015 Microchip Technology Inc.
17.4.4.5 Clock Synchronization and
the CKP bit
When the CKP bit is cleared, the SCL output is forced
to ‘0’. However, clearing the CKP bit will not assert the
SCL output low until the SCL output is already sam-
pled low. Therefore, the CKP bit will not assert the
SCL line until an external I2C master device has
already asserted the SCL line. The SCL output will
remain low until the CKP bit is set and all other
devices on the I2C bus have deasserted SCL. This
ensures that a write to the CKP bit will not violate the
minimum high time requirement for SCL (see
Figure 17-12).
FIGURE 17-12: CLOCK SYNCHRONIZATION TIMING
SDA
SCL
DX – 1DX
WR
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SSPCON1
CKP
Master device
deasserts clock
Master device
asserts clock
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FIGURE 17-13 : I2C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS)
SDA
SCL
SSPIF
BF (SSPSTAT<0> )
SSPOV (SSPCON1<6>)
S123456789 1 2345 6789 12345 789 P
A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D1 D0
ACK
Receiving Data
ACK
Receiving Data
R/W = 0
ACK
Receiving Address
Cleared by software
SSPBUF is read
Bus master
terminates
transfer
SSPOV is set
because SSPBUF is
still full. ACK is not sent.
D2
6
(PIR1<3>)
CKP
CKP
written
to ‘1’ in
If BF is cleared
prior to the falling
edge of the 9th clock,
CKP will not be reset
to ‘0’ and no clock
stretching will occur
software
Clock is held low until
CKP is set to ‘1’
Clock is not held low
because buffer full bit is
clear prior to falling edge
of 9th clock Clock is not held low
because ACK =
1
BF is set after falling
edge of the 9th clock,
CKP is reset to ‘0’ and
clock stretching occurs
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DS40001303H-page 204 2010-2015 Microchip Technology Inc.
FIGURE 17-14 : I2C™ SLAV E MO DE TIMING WITH SEN = 1 (RECEPTION, 10-BIT ADDRESS)
SDA
SCL
SSPIF
BF (SS PSTAT<0>)
S123456789 123456789 12345 789 P
1 1 1 1 0 A9A8 A7 A6A5A4A3A2A1A0 D7D6D5D4D3 D1D0
Receive Data Byte
ACK
R/W = 0
ACK
Receive First Byte of Address
Clear ed by software
D2
6
(PIR1<3>) Cleared by software
Receive Second Byte of Address
Cleared by hardware when
SSPADD is updated with low
byte of address after falling edge
UA (SSPSTAT<1>)
Clock is held low until
update of SSPADD has
taken place
UA is set indicating that
the SSPADD needs to be
updated
UA is set indicating that
SSPADD needs to be
updated
Cleared by hardware when
SSPADD is updated with high
byte of address after falling edge
SSPBUF is writ ten with
contents of SSPSR Dummy read of SSPBUF
to clear BF flag
ACK
CKP
12345 789
D7 D6 D5 D4 D3 D1 D0
Receive Data Byte
Bus master
terminates
transfer
D2
6
ACK
Cleared by software Clea red by softw are
SSPOV (SSPCON1<6>)
CKP written to
‘
1
’
Note: An update of the SSP ADD register before
the falling edge of the ninth clock will have
no effect on UA and UA will remain set.
Note: An update of the SSPADD
register before the falling
edge of the ninth clock will
have no effect on UA and
UA will remain set. by softw are
Clock is held low until
update of SSPADD has
taken place
of ninth clock
of ninth clock
SSPOV is set
because SSPBUF is
still full. ACK is not sent.
Dummy read of SSPBUF
to clear BF flag
Clock is held low until
CKP is set to
‘
1
’
Clock is not held low
because ACK =
1
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17.4.5 GENERAL CALL ADDRESS
SUPPORT
The addressing procedure for the I2C bus is such that
the first byte after the Start condition usually
determines which device will be t he slave addressed by
the master. The exception is the general call address
which can address all devices. When this address is
used, all devices should, in theory, respond with an
Acknowledge.
The general call address is one of eight addresses
reserved for specific purposes by the I2C protocol. It
consists of all ‘0’s with R/W = 0.
The general call address is recognized when the
GCEN bit of the SSPCON2 is set. Following a Start bit
detect, eight bits are shifted into the SSPSR and the
address is compared against the SSPADD. It is also
compared to the general call address and fixed in hard-
ware.
If the general call address matches, the SSPSR is
transferre d to the S SPBUF, the BF flag bi t is set (ei ghth
bit) and on the falling edg e of the ninth bit (ACK bit), the
SSPIF interrupt flag bit is set.
When the interrupt is serviced, the source for the
interr upt can be checke d by readi ng the con tents of the
SSPBUF. The value can be used to determine if the
address was device specific or a general call address.
In 10-bit mode, the SSPADD is required to be updated
for the seco nd half of the addre ss to match an d the UA
bit of the SSPSTAT register is set. If the general call
address is sampled w hen the GCEN bi t is set, whil e the
slave is configured in 10-bit Address mode, then the
second half of the a ddress is not nec es sa ry, the UA bit
will not be set and the slave will begin receiving data
after the Acknowledge (Figure 17-15).
FIGURE 17-15: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE
(7 OR 10-BIT ADDRESS MODE)
SDA
SCL S
SSPIF
BF (SSPSTAT<0>)
SSPOV (SSPCON1<6>)
Cleared by software
SSPBUF is read
R/W = 0ACK
General Call Address
Address is compared to General Call Address
GCEN (SSPCON2<7>)
Receiving Data ACK
123456789123456789
D7 D6 D5 D4 D3 D2 D1 D0
after ACK, set interrupt
‘0’
‘1’
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17.4.6 MASTER MODE
Master mode is enabled by setting and clearing the
appropri ate SSPM bit s in SSPCON1 and by set ting the
SSPEN bit. In Master mode, the SCL and SDA lines
are manipulated by the MSSP hardware.
Master mode of operation is supported by interrupt
generation on the detection of the Start and Stop con-
ditions . The S t op (P) and S t art (S) bit s are clea red fro m
a Reset o r when the MSSP m odule is di sabled. Control
of the I2C bus ma y be tak en when th e P bit is set, or the
bus is Idle, with both the S and P bits clear.
In Firmware Controlled Master mode, user code
conducts all I2C bus operations based on Start and
Stop bit conditions.
Once Master mode is enabled, the user has six
options.
1. Assert a Start condition on SDA and SCL.
2. Assert a Repeated Start condition on SDA and
SCL.
3. Write to the SSPBUF register initiating
transmission of data/address.
4. Configure th e I2C port to receive data.
5. Generate an Acknowledge condition at the end
of a received byte of data.
6. Generate a Stop condition on SDA and SCL.
The following events will cause the SSP Interrupt Flag
bit, SSPIF, to be set (SSP interrupt, if enabled):
• Start condition
• Stop condition
• Data transfer byte transmitted/received
• Acknowledge transmit
• Repeat ed Sta rt
FIGURE 17-16: MSSP BLOCK DIAGRAM (I2C™ MASTER MODE)
Note: The MSSP module, when configured in
I2C Master mode, does not allow queuing
of events. For instance, the user is not
allowed to initiate a Start condition and
immediatel y write the SSPBUF register to
initiate transmission before the Start
condition is complete. In this case, the
SSPBUF will not be written to and the
WCOL bi t will be set, indi cating that a write
to the SSPBUF did not occur.
Read Write
SSPSR
S tart bit, Stop bit,
SSPBUF
Internal
Data Bus
Set/Reset, S, P, WCOL (SSPSTAT)
Shift
Clock
MSb LSb
SDA
Acknowledge
Generate
Stop bit Detect
Write Collision Detect
Clock Arbitration
State Counter for
end of XMIT/RCV
SCL
SCL In
Bus Collision
SDA In
Receive Enable
Clock Cntl
Clock Arbitrate/WCOL Detect
(hold off clock source)
SSPADD<7:0>
Baud
Set SSP IF, BCLIF
Reset ACKSTAT, PEN (SSPCON2)
Rate
Generator
SSPM<3:0>
Start bi t D e tect
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17.4.6.1 I2C Master Mode Operation
The master device generates all of the serial clock
pulses and the S t a rt and Stop con dition s. A trans fer is
ended with a Stop condition or with a Repeated Start
condition. Since the Repeated Start condition is also
the beginning of the next serial transfer , the I2C bus will
not be releas ed.
In Master Transmitter mode, serial data is output
through SDA, while SCL outputs the serial clock. The
first byte transmitted contains the slave address of the
recei vin g dev ice ( 7 bits) and the Rea d/Writ e (R/W) bit.
In this case, the R/W bi t will be logic ‘ 0’. Se rial da ta is
transmi tted eight bits a t a time. Af ter each byte is trans-
mitted, an Acknowledge bit is received. Start and Stop
conditions are output to indicate the beginning and the
end of a seria l transfer.
In Master Rec eive mode , the first byte transm itted con-
tains the slave address of the transmitting device
(7 bits) and th e R/W bit. In this case, the R/W bit wil l be
logic ‘ 1’. Thus, the first byte transmitted is a 7-bit slave
address followed by a ‘1’ to indicate the receive bit.
Serial data is received via SDA, while SCL outputs the
serial clock. Serial data is received eight bits at a time.
After each byte is received, an Acknowledge bit is
transmitted. Start and Stop conditions indicate the
beginning and end of transmission.
The Baud Rate Generator used for the SPI mode
operation is used to set the SCL clock frequency for
either 100 kHz, 400 kHz or 1 MHz I2C operation. See
Section 17.4.7 “Baud Rate ” for more detail.
A typical transmit sequence would go as follows:
1. The user generates a Start condition by setting
the SEN bit of the SSPCON2 register.
2. SSPIF is set. The MSSP module will wait the
required start time before any other operation
takes place.
3. The user loads the SSPBUF with the slave
address to transmit.
4. Address is shifted out the SDA pin until all eight
bits are transmitted.
5. The MSSP module shif t s in the ACK bit f rom th e
slave device and writes its value into the
ACKSTAT bit of the SSPCON2 register.
6. The MSSP mo dule g enerate s an interrup t at th e
end of th e ninth c lock cyc le by settin g the SSPIF
bit.
7. The user loads the SSPBUF with eight bits of
data.
8. Data is shif ted out the SDA pi n until a ll eigh t bit s
are transmitted.
9. The MSSP module shif t s in the ACK bit f rom th e
slave device and writes its value into the
ACKSTAT bit of the SSPCON2 register.
10. The MSSP modul e gene rates an int errupt a t the
end of th e ninth c lock cyc le by settin g the SSPIF
bit.
11. The user generates a Stop condition by setting
the PEN bit of the SSPCON2 register.
12. Interrupt is ge nerated once the S t op cond ition i s
complete.
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17.4.7 BAUD RATE
In I2C Master mode, the Baud Rate Generator (BRG)
reload value is placed in the SSPADD register
(Figure 17-17). When a write occurs to SSPBUF, the
Baud Ra te Generator wil l automaticall y begin countin g.
The BRG counts down to ‘0’ and stops until another
reload has taken place. The BRG count is decre-
mented tw ice per instru cti on cycle (TCY) on th e Q2 an d
Q4 clocks. In I2C Master mode, the BRG is reloaded
automatically. One half of the SCL period is equal to
[(SSPADD+1) 2]/FOSC. Therefore SSPADD =
(FCY/FSCL) -1.
Once the given operation is complete (i.e.,
transmission of the last data bit is followed by ACK), the
internal clock will automatically stop counting and the
SCL pin will remain in its last state.
Table 17-3 demonstrates clock rates based on
instruction cycles and the BRG value loaded into
SSPADD.
The minimum SSPADD value for baud rate generation
is 0x03.
FIGURE 17-17: BAUD RATE GENER ATOR BLOCK DIAGRAM
TABLE 17-3: I2C™ CLOCK RATE W/BRG
SSPM<3:0>
BRG Down Counter
CLKOUT FOSC/2
SSPADD<7:0>
SSPM<3:0>
SCL
Reload
Control Reload
FOSC FCY BRG Value FSCL
(2 Rollovers of BRG)
64 MHz 16 MHz 27h 400 kHz(1)
64 MHz 16 MHz 32h 313.7 kHz
64 MHz 16 MHz 3Fh 250 kHz
40 MHz 10 MHz 18h 400 kHz(1)
40 MHz 10 MHz 1Fh 312.5 kHz
40 MHz 10 MHz 63h 100 kHz
16 MHz 4 MHz 09h 400 kHz(1)
16 M Hz 4 MHz 0Ch 308 kH z
16 MHz 4 MHz 27h 100 kHz
4 MHz 1 MHz 09h 100 kHz
Note 1: The I2C interface does not conform to the 400 kHz I2C specification (which applies to rates greater than
100 kHz) in all details, but may be used with care where higher rates are required by the application.
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17.4.7.1 Clock Arbitration
Clock arbitration occurs when the master, during any
receive, transmit or Repeated Start/Stop condition,
deasserts the SCL pin (SCL allowed to float high).
When the SCL pin is allowed to float high, the Baud
Rate Generator (BRG) is suspended from counting
until the SCL pin is actually sampled high. When the
SCL pin is sampled high, the Baud Rate Generator is
reloaded with the contents of SSPADD<7:0> and
begins counting. This ensures that the SCL high time
will always be at least one BRG rollover count in the
event that the clock is held low by an external device
(Figure 17-18).
FIGURE 17-18: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
SDA
SCL
SCL deasserted but slave holds
DX – 1DX
BRG
SCL is sampled high, reload takes
place and BRG starts its count
03h 02h 01h 00h (hold off) 03h 02h
Reload
BRG
Value
SCL low (clock arbitration) SCL allowed to transition high
BRG decrements on
Q2 and Q4 cycles
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17.4.8 I2C MASTER MODE START
CONDITION TIMING
To initiate a Start condition, the user sets the Start
Enable bit, SEN bit of the SSPCON2 register. If the
SDA and SCL pins are sampled high, the Baud Rate
Generator is reloaded with the contents of
SSPADD <6:0> and st arts it s co unt. If SCL an d SDA are
both sampled high when the Baud Rate Generator
times out (TBRG), the SDA pin is driven low. The action
of the SDA being driven low while SCL is high is the
Start condition and causes the S bit of the SSPSTAT1
register to be set . Follow ing this, the Baud Rat e Gener-
ator is reloaded with the contents of SSPADD<7:0>
and res umes it s co unt. When the Baud Rate G enerator
times out (T BRG), the SEN bit of th e SSPCON2 regis ter
will be automatically cleared by hardware; the Baud
Rate Generator is suspended, leaving the SDA line
held low and the Start condition is complete.
17.4.8.1 WCOL Status Flag
If the user writes the SSPBUF when a Start sequence
is in progress, the WCOL is set and the contents of the
buffer are unchanged (the write does not occur).
FIGURE 17-19: FIRST START BIT TIMING
Note: If at the beginning of the Start condition,
the SDA and SCL pins are already sam-
pled low, or if during the Start condition,
the SCL line is sampled low before the
SDA line is driven low, a bus collision
occurs, the Bus Collision Interrupt Flag,
BCLIF, is s et, the S tart co ndition is ab orted
and the I2C module is reset into its Idle
state.
Note: Becau se queuing of ev ents is not a llowed,
writing to the lower five bits of SSPCON2
is disabled until the Start condition is
complete.
SDA
SCL
S
TBRG
1st bit 2nd bit
TBRG
SDA = 1, At completion of Start bit,
SCL = 1
Write to SSPBUF occurs here
TBRG
hardware clears SEN bit
TBRG
Write to SEN bit occurs here Set S bit (SSPSTAT<3>)
and sets SSPIF bit
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17.4.9 I2C MASTER MODE REP EA TED
START CONDITION TIMING
A Repeated Start condition occurs when the RSEN bit
of the SSPCON2 register is programmed high and the
I2C logi c module is in the Idle st ate. When th e RSEN bit
is set, the SCL pin is asserted low. When the SCL pin
is samp led low , the Baud Rate Generator is loaded with
the contents of SSPADD<5:0> and begins counting.
The SDA pin is released (brought high) for one Baud
Rate Generator count (TBRG). When the Baud Rate
Generator times out, if SDA is sampled high, the SCL
pin will be deasserted (brought high). When SCL is
sampled high, the Baud Rate Generator is reloaded
with the contents of SSPADD<7:0> and begins count-
ing. SDA and SCL mu st be sampled high for one TBRG.
This ac tion is then followed by assertio n of the SDA pin
(SDA = 0) for one TBRG while SCL is high. Following
this, the RSEN bit of the SSPCON2 register will be
automat ically cleared and the Baud Rate Generator will
not be reload ed, leavin g the SDA pin held low. As soo n
as a Start condition is detected on the SDA and SCL
pins, the S bit of the SSPSTAT register will be set. The
SSPIF bit will n ot be set until th e Baud Rate Gen era tor
has timed out.
Immediately following the SSPIF bit getting set, the user
may write the SSPBUF with the 7-bit address in 7-bit
mode or the default first address in 10-bit mode. After the
first eight bits are transmitted and an ACK is received,
the user may then transmit an additional eight bits of
address (10-bit mode) or eight bit s of dat a (7-bit mode).
17.4.9.1 WCOL Status Flag
If the user writes the SSPBUF when a Repeated Start
sequence is in progress, the WCOL is set and the
contents of the buffer are unchanged (the write does
not occur).
FIGURE 17-20: REPEAT START CONDITION WAVEFORM
Note 1: If RSEN is programmed while any other
event is i n prog res s, it wi ll no t t ak e ef f ec t.
2: A bus co ll is io n du ri ng t he Re pe ate d Start
conditi on occ urs if:
• SDA is s ampled low when SCL goes
from low-to-high.
• SCL goes low before SDA is
asserted low. This may indicate that
another master is attempting to
transmit a data ‘1’.
Note: Becau se queuing of ev ents is not a llowed,
writing of the lower 5 bits of SSPCON2 is
disabled until the Repeated S tart condition
is complete.
SDA
SCL
Sr = Repeated Start
Write to SSPCON2
Write to SSPBUF occurs here
on falling edge of ninth clock,
end of Xmit
At completion of Start bit,
hardw are clea rs R SEN bi t
1st bit
S bit set by hardware
TBRG
TBRG
SDA = 1,
SDA = 1,
SCL (no change). SCL = 1
occurs here.
TBRG TBRG TBRG
and sets SSPIF
RSEN bit set by hardware
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17.4.10 I2C MASTER MODE
TRANSMISSION
Transmission of a data byte, a 7-bit address or the
other half of a 10-bit address is accomplished by simpl y
writing a value to the SSPBUF register. This action will
set the Buf fer Ful l flag bi t, BF and allo w the Baud Rate
Generator to begin counting and start the next trans-
mission. Each bit of address/data will be shifted out
onto the SDA pin after the falling edge of SCL is
asserted (see data hold time specification
parameter 106). SCL is held low for one Baud Rate
Generator rollover count (TBRG). Data should be valid
befor e SCL is rele ased high (see dat a setup time spec-
ificati on par ameter 107). Whe n the SCL pin is release d
high, it is held that way for TBRG. The data on the SDA
pin must rem ain st abl e for that duratio n and some hol d
time after the next falling edge of SCL. After the eighth
bit is shifted out (the falling edge of the eighth clock),
the BF flag is cleared and the master releases SDA.
This allows the slave device being addressed to
respond with an ACK bit duri ng th e nint h bit ti me if an
addr es s m at c h oc cu r red , o r if d a ta wa s rec ei v ed p rop -
erly . The status of ACK is written i nto the A CKDT bi t on
the falli ng edge of the ninth clock. If the master receives
an Acknowledge, the Acknowledge Status bit,
ACKSTAT, is cleared. If not, the bit is set. After t he ninth
clock, the SSPIF bit is set and the master clock (Baud
Rate Generator) is suspended until the next data byte
is loaded into the SSPBUF, leaving SCL low and SDA
unchanged (Figure 17-21).
After the write to the SSPBUF, each bit of the address
will be shifted out on the falling edge of SCL until all
seven address bits and the R/W bit are completed. On
the falling edge of the eighth clock, the master will
deassert the SDA pin, allowing the slave to respond
with an Acknowledge. On the falling edge of the ninth
cloc k, the mast er wil l sam ple the SDA pin to see if t he
address was recognized by a slave. The status of the
ACK bit is loaded into the ACKSTAT Status bit of the
SSPCON2 register. Following the falling edge of the
ninth clock transmission of the address, the SSPIF is
set, the BF flag is cleared and the Baud Rate Generator
is turned off until another write to the SSPBUF takes
place, holding SCL low and allowing SDA to float.
17.4.10.1 BF Status Flag
In Transmit mode, the BF bit of the SSPSTAT register
is set when the CPU writes to SSPBUF and is cleared
when all 8 bits are shifted out.
17.4.10.2 WCOL Status Flag
If the user writes the SSPBUF when a transmit is
already in progress (i.e., SSPSR is still shifting out a
data byte), the WCOL is set and the contents of the
buffer are unchanged (the write does not occur).
WCOL must be cleared by software.
17.4.10.3 ACKSTAT Status Flag
In Transmit mode, the ACKSTAT bit of the SSPCON2
register is cleared when the slave has sent an Acknowl-
edge (ACK =0) and is set when the slave does not
Acknowledge (ACK = 1). A slave sends an Acknowl-
edge when it has recognized its address (including a
general call), or when the slave has properly received
its data.
17.4.11 I2C MASTER MODE RECEPTI ON
Master mode recepti on is enabl ed by progra mmin g the
Receive Enable bit, RCEN bit of the SSPCON2
register.
The Baud Rate Generator begins counting and on each
rollover, the state of the SCL pin changes
(high-to-low/low-to-high) and data is shifted into the
SSPSR. After the falling edge of the eighth clock, the
receive enable flag is automatically cleared, the con-
tents of the SSPSR are loaded into the SSPBUF, the
BF flag bit is set, the SSPIF flag bi t is set and the Baud
Rate Generator is suspended from counting, holding
SCL low. The MSSP is now in Idle state awaiting the
next command. When the buffer is read by the CPU,
the BF flag bit is automatically cleared. The user can
then send an Acknowledge bit at the end of reception
by setti ng the Acknowl edge Sequence Ena ble, ACKEN
bit of the SSPCON2 register.
17.4.11.1 BF Status Flag
In receiv e op eration, the BF bit is s et whe n an add r es s
or data byte is loaded into SSPBUF from SSPSR. It is
cleared when the SSPBUF register is read .
17.4.11.2 SSPOV Status Flag
In receive operation, the SSPOV bit is set when eight
bits are received into the SSPSR and the BF flag bit is
already set fr om a previo us reception.
17.4.11.3 WCOL Status Flag
If the user writes the SSPBUF when a receive is
already in progress (i.e., SSPSR is still shif ting in a data
byte), th e WCOL bi t is set an d the conte nts of th e buffer
are unchanged (the write does not occur).
Note: The MSSP module must be in an Idle
state before the RCEN bit is set or the
RCEN bit will be di sregarded.
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PIC18F2XK20/4XK20
FIGURE 17-21 : I2C™ MASTER MODE WAVEFORM (T RANSMISSION, 7 OR 10-BIT ADDRESS)
SDA
SCL
SSPIF
BF (SSPSTAT<0>)
SEN
A7 A6 A5 A4 A3 A2 A1 ACK = 0D7 D6 D5 D4 D3 D2 D1 D0
ACK
Transmitting Data or Second Half
R/W = 0Transmit Address to Slave
123456789 123456789 P
Cleared by software service routine
SSPBUF is written by software
from SSP interrup t
After Start condition, SEN cleared by hardware
S
SSPBUF written with 7-bit address and R/W
start transmit
SCL held low
while CPU
responds to SSPIF
SEN = 0
of 10-bit Address
Write SSPCON2<0> SEN = 1
Start condition begins From slave, clear ACKSTAT bit SSPCON2<6>
ACKSTAT in
SSPCON2 = 1
Cleared by software
SSPBUF written
PEN
R/W
Cleared by softwa r e
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FIGURE 17-22 : I2C™ MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS)
P
9
87
6
5
D0
D1
D2
D3D4
D5
D6D7
S
A7 A6 A5 A4 A3 A2 A1
SDA
SCL 12345678912345678 9 1234
Bus master
terminates
transfer
ACK Receiving Data from Slave
Receiving Data from Slave D0
D1
D2
D3D4
D5
D6D7
ACK
R/W = 0
Transmit Address to Slave
SSPIF
BF
ACK is not sent
Write to SSPCON2<0> (SEN = 1),
Write to SSPBUF occurs here, ACK from Slav e
Master configured as a receiver
by programming SSPCON2<3> (RCEN = 1)PEN bit = 1
written here
Data shifted in on falling edge of CLK
Cleared by software
start XMIT
SEN = 0
SSPOV
SDA = 0, SCL = 1
while CPU
(SSPSTAT<0>)
ACK
Cleared by software
Clear ed by software
Set SSPIF interrupt
at end of receive
Set P bit
(SSPSTAT<4>)
and SSPIF
Cleared in
software
ACK from Master
Set SS PIF at end
Set SSPIF interrupt
at end of Acknowledge
sequence
Set SSPIF interrupt
at end of Acknow-
ledge sequence
of receive
Set ACKEN, start Acknowledge sequence
SSPOV is set because
SSPBUF is still full
SDA = ACK D T = 1
RCEN cleared
automatically
RCEN = 1, start
next receive
Write to SSPCON2<4>
to start Acknowledge sequence
SDA = ACKDT (SSPCON2<5>) = 0
RCEN cleared
automatically
responds to SSPIF
ACKEN
begin Start condition
Cleared by software
SDA = ACKDT = 0
Last bit is shifted into SSPSR and
contents are unloaded into SSPBUF
2010-2015 Microchip Technology Inc. DS40001303H-page 215
PIC18F2XK20/4XK20
17.4.12 ACKNOWLEDGE SEQUENCE
TIMING
An Acknowledge sequence is enabled by setting the
Acknowledge Sequence Enable bit, ACKEN bit of the
SSPCON2 register. When this bit is set, the SCL pin is
pulled low and the contents of the Acknowledge data bit
are presented on the SDA pin. If the user wish es to gen-
erate an Acknowledge, then the ACKDT bit should be
cleared. If not, the user should set the ACKDT bit before
starting an Acknowledge sequence. The Baud Rate
Generator then counts for one rollover period (TBRG)
and the SCL pin is deasserted (pulled high). When the
SCL pin is sampled high (clock arbitration), the Baud
Rate Generator counts for TBRG. The SCL pin is then
pulled low . Following this, the ACKEN bit is a utomatically
cleared, the Baud Rate Generator is turned off and the
MSSP module then goes into Idle mode (Figure 17-23).
17.4.12.1 WCOL Status Flag
If the user writes the SSPBUF when an Acknowledge
sequence is in progress, then WCOL is set and the
contents of the buffer are unchanged (the write does
not occur ).
17.4.13 STOP CONDITION TIMING
A Stop bit is asserted on the SDA pin at the end of a
receive/transmit by setting the Stop Sequence Enable
bit, PEN bit of the SSPCON2 register. At the end of a
receive/transmit, the SCL line is held low after the
falling edge of th e ninth cl ock. Wh en the PEN bi t is se t,
the master will assert the SDA li ne low. When the SD A
line is sampled low, the Baud Rate Generator is
reloaded and counts down to ‘0’. When the Baud Rate
Gener ator ti mes out, t he SCL pin will be brou ght high
and one TBRG (Baud Rate Generator rollover count)
later, the SDA pin will be deasserted. When the SDA
pin is sampled high while SCL is high, the P bit of the
SSPSTAT register is set. A TBRG later, the PEN bit is
cleared and the SSPIF bit is set (Figure 17-24).
17.4.13.1 WCOL Status Flag
If the user writes the SSPBUF when a Stop sequence
is in progress, then the WCOL bit is set and the
contents of the buffer are unchanged (the write does
not occur).
FIGURE 17-23: ACKNOWLEDGE SEQUEN CE WAVEFORM
FIGURE 17-24: STOP CONDITION RECEIVE OR TRANSMIT MODE
Note: TBRG = one Baud Rate Generator period.
SDA
SCL
SSPI F set at
Acknowledge sequence starts here,
write to SSPCON2 ACKEN automatically cleared
Cleared in
TBRG TBRG
the end of receive
8
ACKEN = 1, ACKDT = 0
D0
9
SSPIF
software SSPIF set at the end
of Acknowledge sequence
Cleared in
software
ACK
SCL
SDA
SDA asserted low before rising edge of clock
Write to SSPCON2,
set PEN
Falling edg e of
SCL = 1 for TBRG, followed by SDA = 1 for TBRG
9th clock
SCL brought high after TBRG
Note: TBRG = one Baud Rate Generator period.
TBRG TBRG
after SDA sampled high. P bit (SSPSTAT<4>) is set.
TBRG
to setup Stop condition
ACK
P
TBRG
PEN bit (SSPCON2<2>) is clea red by
hardware and the SSPIF bit is set
PIC18F2XK20/4XK20
DS40001303H-page 216 2010-2015 Microchip Technology Inc.
17.4.14 SLEEP OPERATION
While in Sleep mode, the I2C module can receive
address es or data and when an addr ess match or com-
plete byte transfer occurs, wake the processor from
Sleep (if the MSSP interrupt is enabled).
17.4.15 EFFECTS OF A RESET
A Reset disable s the MSSP module and termina tes the
current transfer.
17.4.16 MULTI-MAS TER MO DE
In Multi-Master mode, the interrupt generation on the
detection of the Start and Stop conditions allows the
deter mination of when the bus i s free. The S top (P) and
Start (S) bits are cleared from a Reset or when the
MSSP module is disabled. Control of the I2C bus may
be tak en when the P bit of the SSPSTA T register is set,
or the b us is Idle , with both t he S and P b its cle ar . When
the bus is busy, enabling the SSP interrupt will gener-
ate the in terrupt when the Stop condition occurs.
In multi-master operation, the SDA line must be
monitored for arbitration to see if the signal level is the
expected output level. This check is performed by
hardware with the result placed in the BCLIF bit.
The states where arbitration can be lost are:
• Address Transfer
• Data Tran sfer
• A Start Condition
• A Repeated Start Condition
• An Acknowledge Condition
17.4.17 MU L TI -M A STER COMMUNICATI O N ,
BUS COLLI SION AND BU S
ARBITRATION
Multi-Master mode support is achieved by bus arbitra-
tion. When the master outputs address/data bits onto
the SDA pin, arbitration takes place when the master
outputs a ‘1’ on SDA, by letting SDA float high and
another master asserts a ‘0’. When the SCL pin floats
high, data should be stable. If the expected data on
SDA is a ‘1’ and the da t a s am ple d on th e SD A pin = 0,
then a bus collision has taken pl ace. The master wil l set
the Bus Collision Interrupt Flag, BCLIF and reset the
I2C port to its Idle state (Figure 17-25).
If a transmit was in progress when the bus collision
occurred, the transmission is halted, the BF flag is
cleared, the SDA and SCL lines are deasserted and the
SSPBUF can b e written to. Wh en the user ser vices th e
bus collision Interrupt Service Routine and if the I2C
bus is free, the user can resume communication by
asserting a Start condition.
If a Start, Repeated Start, Stop or Acknowledge condi-
tion was in progress when the bus collision occurred, the
condition is aborted, the SDA and SCL lines are deas-
serted and the respective control bits in the SSPCON2
register are cleared. When the us er services the b us col-
lision Interrupt Service Routine and if the I2C bus is free,
the user can res ume communication by asserting a S tart
condition.
The master will continue to monitor the SDA and SCL
pins. If a Stop condition occurs, the SSPIF bit will be set.
A write to the SSPBUF will start the transmission of
data at the first data bit, regardless of where the
transmitter left off when the bus collision occurred.
In Multi-Master mode, the interrupt generation on the
detectio n o f Start a nd Sto p c ond iti ons al lows the deter-
minatio n of wh en the b us is fre e. Contro l of the I2C bus
can be taken when the P bit is set in the SSPSTAT
register, or the bus is Idle and the S and P bits are
cleared.
FIGURE 17-25: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE
SDA
SCL
BCLIF
SDA released
SDA line pulled low
by another source
Sample SDA. While SCL is high,
data does not match what is driven
Bus collision has occurred.
Set bus collision
interrupt (BCLIF)
by the master.
by master
Data changes
while SCL = 0
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PIC18F2XK20/4XK20
17.4.17.1 Bus Collision During a Start
Condition
During a Start condition, a bus collision occurs if:
a) SDA or SCL are sam pled low at th e beginning of
the Start condition (Figure 17-26).
b) SCL is sampled l ow before SDA is asserted low
(Figure 17-27).
During a Start condition, both the SDA and the SCL
pins are monitored.
If the SDA pin is already low, or the SCL pin is already
low, then all of the following occur:
• the Start condition is aborted,
• the BCLIF flag is set and
• the MSSP module is reset to its Idle state
(Figure 17-26).
The Start condition begins with the SDA and SCL pins
deasserted. When the SDA pin is sampled high, the
Baud Rate Generator is loaded from SSPADD<7:0>
and counts down to 0. If the SCL pin is sampled low
while SDA is high, a bus collision occurs becaus e it is
assumed that another master is attempting to drive a
data ‘ 1’ dur ing the Start condi tion.
If the SDA pin is sampled low during this count, the
BRG is reset and the SDA line is asserted early
(Figure 17-28). If, however , a ‘1’ is sampled on the SDA
pin, the SDA pin is assert ed low at the end of the B RG
count. The Baud Rate Generator is then reloaded and
counts down to 0; if the SCL pin is sampled as ‘0’
duri ng this time , a bus colli sion does n ot occur. At the
end of t he BRG co unt , the SCL pin is a ss erte d lo w.
FIGURE 17-26: BUS COLLISION DURING START CONDITION (SDA ONLY)
Note: The reason that bus collision is not a fac-
tor during a Start condition is that no two
bus masters can assert a Start condition
at the exact same time. Therefore, one
maste r will always a ssert SDA be fore the
other. Thi s condition does not cause a b us
collision beca use the two masters must be
allowed to arbitrate the first address fol-
lowing the S tart condi tion. If the addre ss is
the same, arbitration must be allowed to
continue into the data portion, Repeated
Start or Stop conditions.
SDA
SCL
SEN SDA sampled low before
SDA goes low before the SEN bit is set.
S bit and SSPIF set because
SSP module reset into Idle state.
SEN cleared automatically because of bus collision.
S bit and SSPIF set because
Set SEN, enable Start
condition if SDA = 1, SCL = 1
SDA = 0, SCL = 1.
BCLIF
S
SSPIF
SDA = 0, SCL = 1.
SSPIF and BCLIF are
cleared by software
SSPIF and BCLIF are
cleared by software
Set BCLIF,
S tart condition. Set BCLIF.
PIC18F2XK20/4XK20
DS40001303H-page 218 2010-2015 Microchip Technology Inc.
FIGURE 17-27: BUS COLLISION DURING START CONDITION (SCL = 0)
FIGURE 17-28: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION
SDA
SCL
SEN bus collision occurs. Set BCLIF.
SCL = 0 before SDA = 0,
Set SEN, enable Start
sequence if SDA = 1, SCL = 1
TBRG TBRG
SDA = 0, SCL = 1
BCLIF
S
SSPIF
Interrupt cleared
by softw a r e
bus collision occurs. Set BCLIF.
SCL = 0 bef ore BRG time-out,
‘0’‘0’
‘0’‘0’
SDA
SCL
SEN
Set S
Less th an TBRG TBRG
SDA = 0, SCL = 1
BCLIF
S
SSPIF
S
Interrupts cleared
by software
set SS PIF
SDA = 0, SCL = 1,
SCL pulled low after BRG
time-out
Set SS PIF
‘0’
SDA pulled low by other master .
Reset BRG and assert SDA.
Set SEN, enable START
sequence if SDA = 1, SCL = 1
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PIC18F2XK20/4XK20
17.4.17.2 Bus Collision During a Repeated
Start Condition
During a Repeated Start condition, a bus collision
occu rs if:
a) A low level is sampled on SDA when SCL goes
from low level to high level.
b) SCL goes low before SDA is asserted low,
indicating that another master is attempting to
transmit a data ‘1’.
When the user dea sserts SDA and the pin is a llowed to
float high, the BRG is loaded with SSPADD<7:0> and
counts down to 0. The SCL pin is then deasserted and
when sampled high, the SDA pin is sampled.
If SDA is low, a bus collision has occurred (i.e., another
master is attempting to transmit a data ‘0’, Figure 17-29).
If SDA is sampled high, the BRG is relo aded and begins
counting. If SDA goes from high-to-low before the BRG
times out, no bus collision occurs because no two
masters can assert SDA at exa ctly the s ame time .
If SCL goes from high-to-low before the BRG times out
and SDA has not already been asserted, a bus collision
occurs. In this case, another master is attempting to
transmi t a data ‘1’ during the R e pea ted St art co ndi tion,
see Figure 17-30.
If, at the end of the BRG time-out, both SCL and SDA
are still high, the SDA pin is driven low and the BRG is
reloaded and begins counting. At the end of the count,
regardless of the status of the SCL pin, the SCL pin is
driven low and the Repeated Start condition is
complete.
FIGURE 17-29: BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)
FIGURE 17-30: BUS COLLISION DURING REPEATED START CONDITION (CASE 2)
SDA
SCL
RSEN
BCLIF
S
SSPIF
Sample SDA when SCL goes high.
If SDA = 0, set BCLIF and release SDA and SCL.
Cleared by software
‘0’
‘0’
SDA
SCL
BCLIF
RSEN
S
SSPIF
Interrupt cleared
by software
SCL goes low before SDA,
set BCLIF. Release SDA and SCL.
TBRG TBRG
‘0’
PIC18F2XK20/4XK20
DS40001303H-page 220 2010-2015 Microchip Technology Inc.
17.4.17.3 Bus Collision During a Stop
Condition
Bus collision occurs during a Stop condition if:
a) After the SDA pin has been deasserted and
allowed to float high, SDA is sampled low after
the BRG has timed out.
b) After the SCL pin is deass erted, SCL is sampled
low before SDA goes high.
The Stop condition begins with SDA asserted low.
When SDA is sampled low, the SCL pin is allowed to
floa t. Wh en t he p in i s sa mpled hig h (c loc k arbi tr atio n),
the Baud R ate Generator is load ed with SSPADD<7:0 >
and cou nt s d own to 0 . After the BRG times o ut, SDA i s
sampled. If SDA is sampled low, a bus collision has
occurred. This is due to another master attempting to
drive a data ‘0’ (Figure 17-31). If the SCL pin is
sampled low before SDA is allowed to float high, a bus
collis ion occ urs. Thi s is anoth er case of a nother m aster
attempting to drive a data ‘0’ (Figure 17-32).
FIGURE 17-31: BUS COLLISION DURING A STOP CONDITION (CASE 1)
FIGURE 17-32: BUS COLLISION DURING A STOP CONDITION (CASE 2)
SDA
SCL
BCLIF
PEN
P
SSPIF
TBRG TBRG TBRG
SDA asserted low
SDA sampled
low after TBRG,
set BCLIF
‘0’
‘0’
SDA
SCL
BCLIF
PEN
P
SSPIF
TBRG TBRG TBRG
Assert SDA SCL goes low before SDA goes high,
set BCLIF
‘0’
‘0’
2010-2015 Microchip Technology Inc. DS40001303H-page 221
PIC18F2XK20/4XK20
TABLE 17-4: SUMMARY OF REGISTERS ASSOCIATED WITH I2C™
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset
V al ues on
page
IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 59
PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 59
PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 59
IPR2 OSCFIP C1IP C2IP EEIP BCLIP HLVDIP TMR3IP CCP2IP 59
PIR2 OSCFIF C1IF C2IF EEIF BCLIF HLVDIF TMR3IF CCP2IF 59
PIE2 OSCFIE C1IE C2IE EEIE BCLIE HLVDIE TMR3IE CCP2IE 59
SSPADD SS P Addres s Register in I2C™ Slave Mode. SSP Baud Rate Reload Register in I2C Master Mode. 57
SSPBUF SS P Receive Buffer/Transmit Register 57
SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 57
SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 57
SSPMSK MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0 60
SSPSTAT SMP CKE D/A PSR/WUA BF 57
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 59
Legend: — = unimplemented, read as ‘0’. Shad ed cells are not used by I2C.
Note 1: N o t implemented on PIC18F2XK20 devices
PIC18F2XK20/4XK20
DS40001303H-page 222 2010-2015 Microchip Technology Inc.
18.0 ENHANCED UNIVERSAL
SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (EUSART)
The Enhanced Universal Synchronous Asynchronous
Receiver Transmitter (EUSART) module is a serial I/O
communications peripheral. It contains all the clock
generators, shift registers and data buffers necessary
to perform an input or output serial data transfer
independent of device program execution. The
EUSART, also known as a Serial Communications
Interface (SCI), can be configured as a full-duplex
asynchronous system or half-duplex synchronous
system. Full-Duplex mode is useful for
communications with peripheral systems, such as CRT
terminals and personal computers. Half-Duplex
Synchronous mode is intended for communications
with peripheral devices, such as A/D or D/A integrated
circuits, serial EEPROMs or other microcontrollers.
These device s typ icall y do n ot have inter nal cl ocks for
baud rate generation and require the external clock
signal provided by a master synchronous device.
The EUSART m odule includes the follow ing capabilities:
• Full-duplex asynchronous transmit and receive
• Two-character input buffer
• One-ch arac ter out put buffer
• Programmable 8-bit or 9-bit character length
• Address detection in 9-bi t mode
• Input buffer overrun error detection
• Received character framing error detection
• Half-du ple x sy nc hron ous master
• Half-du ple x sy nc hron ous slave
• Programmable clock and data polarity
The EUSART module implements the following
additional features, making it ideally suited for use in
Local Interconnect Network (LIN) bus systems:
• Automatic detection and cali bration of the baud rate
• Wake-up on Break reception
• 13-bit Break cha r ac ter transm it
Block diagrams of the EUSART transmitter and
receiver are shown in Figure 18-1 and Figure 18-2.
FIGURE 18-1: EUSART TRANSMI T BLOCK DIAGRAM
TXIF
TXIE
Interrupt
TXEN
TX9D
MSb LSb
Data Bus
TXREG Register
Transmit Shift Register (TSR)
(8) 0
TX9
TRMT
TX/CK pin
Pin Buffer
and Control
8
SPBRGSPBRGH
BRG16
FOSC ÷ n
n
+ 1 Multiplier x4 x16 x64
SYNC 1X00 0
BRGH X110 0
BRG16 X101 0
Baud Rate Generator
•••
2010-2015 Microchip Technology Inc. DS40001303H-page 223
PIC18F2XK20/4XK20
FIGURE 18-2: EUSART RECEIVE BLOCK DIAGRAM
The operation of the EUSART module is controlled
through th ree registers:
• Transmit Status and Control (TXSTA)
• Receive Status and Control (RCSTA)
• Baud Rate Control (BAUDCON)
These registers are detailed in Register 18-1,
Register 18-2 an d Register 18-3, respectively.
For all modes of EUSART operation, the TRIS control
bits corresponding to the RX/DT and TX/CK pins should
be set to ‘1’. The EUSART control will automatically
recon fig ure the pin from in pu t to output, as ne ed ed .
When the receiv er or transmitter sec tion is not enabled
then the corresponding RX or TX pin may be used for
general purpose input and output.
RX/DT pin
Pin Buffer
and Control Data
Recovery
CREN OERR
FERR
RSR Register
MSb LSb
RX9D RCREG Register FIFO
Interrupt
RCIF
RCIE
Data Bus
8
Stop START
(8) 7 1 0
RX9
• • •
SPBRGSPBRGH
BRG16
RCIDL
FOSC ÷ n
n
+ 1 Multiplier x4 x16 x64
SYNC 1X00 0
BRGH X110 0
BRG16 X101 0
Baud Rate Generato r
PIC18F2XK20/4XK20
DS40001303H-page 224 2010-2015 Microchip Technology Inc.
18.1 EUSART Asynchronous Mode
The EUSART transmits and receives data using the
standard non-return-to-zero (NRZ) format. NRZ is
implemented with two levels: a VOH mark state which
represents a ‘1’ data bit, and a VOL space state which
represents a ‘0’ data bit. NRZ refers to the fact that
consecutively transmitted data bits of the same value
stay at the output l evel of that bit wi thout returning to a
neutral level between each bit transmission. An NRZ
transmission port idles in the mark state. Each character
transmission consists of one Start bit followed by eig ht
or nine data bits and is always terminated by one or
more Stop bi ts. The Start bit is always a space and the
Stop bits are always marks. The most common data
format is 8 bits. Each transmitted bit persists for a period
of 1/(Baud Rate). An on-chip dedicated 8-bit/16-bit Baud
Rate Generator is used to derive standard baud rate
frequencies from the system oscillator. See Table 18-5
for examples of baud rate configurations.
The EUSART transmits and receives the LSb first. The
EUSART’s transmitter and receiver are functionally
indepen dent, but share th e sa me dat a format and bau d
rate. Parity is not supported by the hardware, but can
be implemented in software and stored as the ninth
data b it.
18.1.1 EUSART ASYNCHRONOUS
TRANSMITTER
The EUSART transmitter block diagram is shown in
Figure 18-1. The heart of the transmitter is the serial
Transmit Shift Register (TSR), which is not directly
accessible by software. The TSR obtains its data from
the transmit buffer, which is the TXREG register.
18.1.1.1 Enabling the Transmitter
The EUSART transmitter is enabled for asynchronous
operations by configuring the following three control
bits:
•TXEN = 1
• SYNC = 0
• SPEN = 1
All other EUSART control bits are assumed to be in
their default state.
Setting the TXEN bit of the TXSTA register enables the
transmitter circuitry of the EUSART. Clearing the SYNC
bit of the TXSTA register configures the EUSART for
asynchronous operation. Setting the SPEN bit of the
RCST A register enables the EUSART and automatically
configures the TX/CK I/O pin as an output. If the TX/CK
pin is shared with an analog peripheral the analog I/O
function must be disabled by clearing the corresponding
ANSEL bit.
18.1.1.2 Transmitting Data
A transmission is initiated by writing a character to the
TXREG register. If this is the first character, or the
previous character has been completely flushed from
the TSR, the data in the TXREG is immediately
transferred to the TSR register. If the TSR still contains
all or part of a previous character, the new character
data is held in the TXREG until the Stop bit of the
previous character has been transmitted. The pending
character in the TXREG is then tran sferred to the TSR
in one TCY immediately following the Stop bit
transmission. The transmission of the S tart bit, data bit s
and Stop bit sequence commences immediately
following the transfer of the data to the TSR from the
TXREG.
18.1.1.3 Transmit Data Polarity
The polarity of the transmit data can be controlled with
the CKTXP bit of the BAUDCON register. The default
state of this bit is ‘0’ which selects high true transmit
idle and data bits. Setting the CKTXP bit to ‘1’ will invert
the trans mit dat a resultin g in low true i dle and da ta b its.
The CKTXP bit controls transmit data polarity only in
Asynchronous mode. In Synchronous mode the
CKTXP bit has a dif ferent function.
18.1.1.4 Transmit Interrupt Flag
The TXIF interrupt flag bit of the PIR1 register is set
whenever the EUSART transmitter is enabled and no
character is being held for transmission in the TXREG.
In other words, the TXIF bit is only clear when the TSR
is busy with a character and a new char acter ha s been
queued for transmission in the TXREG. The TXIF flag bit
is not cleared immediately upon writing TXREG. TXIF
becomes valid in the second instruction cycle following
the write execut ion. Polling TXIF immediately following
the TXREG write will return invalid results. The TXIF bit
is read-only, it cannot be set or cleared by software.
The TXIF interrupt can be enabled by setting the TXIE
interrupt enable bit of the PIE1 register. However, the
TXIF flag bit will be set whenever the TXREG is empty,
regardless of the state of TXIE enable bit.
To use interrupts when transmitting data, set the TXIE
bit only when there is more data to send. Clear the
TXIE i nterrupt en able bi t upon w riting the last charact er
of the transmission to the TXREG.
Note: The TXIF transmitter interrupt flag is set
when the TXEN enable bit is set.
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PIC18F2XK20/4XK20
18.1.1.5 TSR Status
The TRMT bit of the TXSTA register indicates the
status of the TSR register. This is a read-only bit. The
TRMT bit is set when the TSR register is empty and is
cleared when a character is transferred to the TSR
register from the TXREG. The TRMT bit remains clear
until all bits have been shifted out of the TSR register.
No int errupt lo gic i s tied to this bi t, so th e user needs to
poll this bit to determine the TSR status.
18.1.1.6 Transmitting 9-Bit Characters
The EUSART supports 9-bit character transmissions.
When the TX9 bit of the TXSTA register is set the
EUSAR T will shift nine bits out for each character trans-
mitted. Th e TX9D bit of the TXSTA register is the nint h,
and Most Significant, data bit. When transmitting 9-bit
data, the TX9D data bit must be written before writing
the eigh t Leas t Signi ficant bit s into the TXRE G. All nin e
bits of d ata wi ll be tran sfer red to th e TSR shift regist er
immediately after the TXREG is written.
A special 9-bit Address mode is available for use with
multiple receivers. See Section 18.1.2.8 “Address
Detection” for more in formation on the Addre ss mode.
18.1.1.7 Asynchronous Transmission Set-up:
1. Initialize the SPBRGH:SPBRG register pair and
the BRGH and BRG16 bits to achieve the desired
baud rate (see Section 18.3 “EUSART Baud
Rate Generator (BRG)”).
2. Set the RX/DT and TX/CK TRIS controls to ‘1’.
3. Enable the asy nch ron ous seri al port by clearin g
the SYNC bit and setting the SPEN bit.
4. If 9-bit tran sm ission is desired, s et th e TX9 co n-
trol bit. A set ninth data bit will indicate that the
eight Least Significant data bits are an address
when the receiver is set for address detection.
5. Set the CKTXP control bit if inverted transmit
data polarity is desired.
6. Enable the transmission by setting the TXEN
contr ol bit . Thi s wi ll c aus e th e TXI F i nte rrup t bi t
to be set.
7. If interrupts are desired, set the TXIE interrupt
enable bit. An interrupt will occur immediately
provided that the GIE and PEIE bits of the
INTCON register are also set.
8. If 9-bit transmission is selected, the ninth bit
should be loaded into the TX9D data bit.
9. Load 8-bit data into the TXREG register. This
will start the transmission.
FIGURE 18-3: ASYNCHRONOUS TRANSMISSION
Note: The TSR register is not mapped in data
memory, so it is not available to the user.
Word 1 Stop bit
Word 1
Transmit Shift Reg
Start bit bit 0 bit 1 bit 7/8
Write to TXREG Word 1
BRG Output
(Shift Clock)
RC4/C2OUT/TX/CK
TXIF bit
(Transmit Buffer
Reg. Empty Flag)
TRMT bit
(Tran smi t Shi ft
Reg. Empty Flag)
1 TCY
pin
PIC18F2XK20/4XK20
DS40001303H-page 226 2010-2015 Microchip Technology Inc.
FIGURE 18-4: ASYNCHR ONOUS TRANSM ISSION (BACK-TO-BACK)
TABLE 18-1: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 56
PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 59
PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 59
IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 59
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 58
TXREG EUSART Transmit Register 58
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 58
BAUDCON ABDOVF RCIDL DTRXP CKTXP BRG16 —WUE ABDEN 58
SPBRGH EUSART Baud Rate Generator Register, High Byte 58
SPBRG EUSART Baud Rate Generator Register, Low Byte 58
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission.
Note 1: Reserved in PIC18F2XK20 devices; always maintain these bits clear.
Transmit Shift Reg
Write to TXREG
BRG Output
(Shift Clock)
RC4/C2OUT/TX/CK
TXIF bit
(Interrupt Reg. Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Word 1 Word 2
Word 1 Word 2
Start bit Stop bit Start bit
Transmit Shift Reg
Word 1 Word 2
bit 0 bit 1 bit 7/8 bit 0
Note: This timing diagram shows two consecutive transmissions.
1 TCY
1 TCY
pin
2010-2015 Microchip Technology Inc. DS40001303H-page 227
PIC18F2XK20/4XK20
18.1.2 EUSART ASYNCHRONOUS
RECEIVER
The Asynchronous mode would typically be used in
RS-232 s y ste ms . Th e rec ei ve r bl ock di agram is shown
in Figure 18-2. The data is received on the RX/DT pin
and drives the data recovery block. The data recovery
block is actually a high-speed shifter operating at 16
times the baud rate, whereas the serial Receive Shift
Register (RSR) operates at the bit rate. When all eight
or nine bits of the character have been shifted in, they
are immediately transferred to a two character
First-In-First-Out (FIFO) memory. The FIFO buffering
allows reception of two complete characters and the
start of a third character before software must start
servicing the EUSART receiver. The FIFO and RSR
registers are not directly accessible by software.
Access to the received data is via the RCREG register .
18.1.2.1 Enabling the Receiver
The EUSART receiver is enabled for asynchronous
operatio n by configuring the fol lowing three control bits:
• CREN = 1
• SYNC = 0
• SPEN = 1
All other EUSART control bits are assumed to be in
their default state.
Setting the CREN bit of the RCST A register enables the
receiver circuitry of the EUSART. Clearing the SYNC bit
of the TXSTA register configures the EUSART for
asynchronous operation. Setting the SPEN bit of the
RCSTA register enables the EUSART. The RX/DT I/O
pin must be configured as an input by setting the
corresponding TRIS control bit. If the RX/DT pin is
shared with an analog peripheral the analog I/O function
must be disabled by clearing the corresponding ANSEL
bit.
18.1.2.2 Receiving Data
The receiver data recovery circuit initiates character
receptio n o n the fallin g edge of the first bit. The f irst bi t,
also known as the Start bit, is alw ays a zero. The data
recovery circuit co unt s one-h alf bi t time to the c enter of
the Start bit and verifies that the bit is still a zero. If it is
not a zero then the data recovery circuit aborts
character reception, without generating an error, and
resumes looking for the falling edge of the Start bit. If
the Start bit zero verification succeeds then the data
recovery circuit c ounts a full bit time to the ce nter of the
next bit. The bit is then sampled by a majority detect
circuit and the resultin g ‘0’ or ‘1’ is shif ted into the RS R.
This repeats until all data bits have been sampled and
shif ted into the RSR. One final bit time is measured and
the le ve l samp le d . Thi s is th e Stop bi t , wh ic h is alwa ys
a ‘1’. If the data recovery circuit samples a ‘0’ in the
Stop bit position then a framing error is set for this
charact er , otherwise th e framing error is c leared for thi s
character. See Section 18.1.2.5 “Receive Framing
Error” for more information on framing errors.
Immediately after all data bits and the Stop bit have
been received, the character in the RSR is transferred
to the EUSART receive FIFO and the RCIF interrupt
flag bit of the PIR1 register is set. The top character in
the FIFO is transferred out of the FIFO by reading the
RCREG register.
18.1.2.3 Receive Data Polarity
The polarity of the receive data can be controlled with
the DTRXP bit of the BAUDCON register. The default
state of this b it is ‘0’ wh ich select s h igh true recei ve idle
and dat a bits. Setting the DTRXP bit to ‘1’ will invert the
receive data re sulting in low true i dle and da ta bit s. The
DTRXP bit controls receive data polarity only in
Asynchronous mode. In synchronous mode the
DTRXP bit has a different function.
Note: If the receive FIFO is overrun, no additional
characters will be received until the overrun
condition is cleared. See Section 18.1.2.6
“Receive Overrun Error” for more
information on overrun errors.
PIC18F2XK20/4XK20
DS40001303H-page 228 2010-2015 Microchip Technology Inc.
18.1.2.4 Receive Interrupts
The RCIF interrupt flag bit of the PIR1 register is set
whene ver the EUSAR T receiv er is enabl ed and there is
an unread character in the receive FIFO. The RCIF
inter rupt fla g bit is rea d-only, it cann ot be set or cl eared
by software.
RCIF interrupts are enabled by setting the following
bits:
• RCIE interrupt enable bit of the PIE1 register
• PEIE periphe ral interrupt enable bit of the
INTCON register
• GIE global interrupt enable bit of the INTCON
register
The RCIF interrupt flag bit will be set when there is an
unread c haract er in the FIF O, regardless of the st ate of
interrupt enable bits.
18.1.2.5 Receive Framing Error
Each character in the receive FIFO buffer has a
corresponding framing error Status bit. A framing error
indic ates t hat a Stop bit was not se en at t he expec ted
time. The framing error status is accessed via the
FERR bit of the RCSTA register. The FERR bit
represen ts the s ta tus o f the top u nread charac ter in the
receive FIFO. Therefore, the FERR bit must be read
before reading the RCREG.
The FERR bit is read-only and only applies to the top
unread character in the receive FIFO. A framing error
(FERR = 1) does not preclude reception of additional
characters. It is not necessary to clear the FERR bit.
Reading the next character from the FIFO buffer will
advance the FIFO to the next character and the next
corresponding framing error.
The FERR bit can be forced clear by clearing the SPEN
bit of the RCSTA register which resets the EUSART.
Clearing the CREN bit of the RCSTA register does not
affect the FERR bit. A framing error by itself does not
generate an interrupt.
18.1.2.6 Receive Overrun Error
The receive FIFO buffer can hold two characters. An
overrun erro r will be generated If a thi rd character, in it s
entirety , is received before the FIFO is accessed. When
this happens the OERR bit of the RCST A re gister is set.
The characters already in the FIFO buffer can be read
but no additional characters will be received until the
error is cleared. The error must be cleared by either
clearing the CREN bit of the RCSTA register or by
resetting the EUSART by clearing the SPEN bit of the
RCSTA register.
18.1.2.7 Receiving 9-bit Characters
The EUSAR T support s 9-bit chara cter receptio n. When
the RX9 bit of the RCSTA register is set, the EUSART
will shift nine bits into the RSR for each character
received. The RX9D bit of the RCSTA register is the
ninth and Most Significant data bit of the top unread
charact er i n t he rec eiv e FIFO . Whe n r ead ing 9-bit data
from the receive FIFO buffer, the RX9D data bit must
be read before reading the eight Least Significant bits
from the RCREG.
18.1.2. 8 Address Detection
A special Address Detection mode is available for use
when multiple receivers share the same transmission
line, such as in RS-485 systems. Address detection is
enabled by setting the ADDEN bit of the RCSTA
register.
Address detection requires 9-bit character reception.
When address detection is enabled, only characters
with the ninth data bit set will be transferred to the
rece iv e FI F O bu ffe r, there by s et t i ng th e R CI F i nte r r up t
bit. All other charac ters will be ignored.
Upon receiving an address character, user software
determines if the address matches its own. Upon
address match, user software must disable address
detection by clearing the ADDEN bit before the next
Stop bit oc cu rs. When user sof tware detect s th e end of
the message, determined by the message protocol
used, software places the receiver back into the
Address Detection mode by setting the ADDEN bit.
Note: If all receive characters in the receive
FIFO hav e fram ing erro rs, repe ated rea ds
of the RCREG will not clear the FERR bit.
2010-2015 Microchip Technology Inc. DS40001303H-page 229
PIC18F2XK20/4XK20
18.1.2.9 Asynchronous Reception Set-up:
1. Initialize the SPBRGH:SPBRG register pair and
the BRGH and BRG16 bits to achieve the
des i red baud rat e (see Section 18.3 “EUSART
Baud Rate Generator (BRG)”).
2. Set the RX/DT and TX/CK TRIS controls to ‘1’.
3. Enable the serial port by setting the SPEN bit
and the R X/DT pin TR IS bit. The SYN C bit mus t
be clear for asynchronous operation.
4. If interrupts are desired, set the RCIE interrupt
enable bit and set the GIE and PEIE bits of the
INTCON register.
5. If 9-bit reception is desired, set the RX9 bit.
6. Set the DTRXP if inverted receive polarity is
desired.
7. Enable reception by setting the CREN bit.
8. The RCIF interrupt flag bit will be set when a
character is transferred from the RSR to the
receive buffer. An interrupt will be generated if
the RCIE interrupt enable bit was also set.
9. Read the RCSTA register to get the error flags
and, if 9-bit data reception is enabled, the ninth
data b it.
10. Get the received eight Least Significant data bit s
from the receive buffer by reading the RCREG
register.
11. If an overrun occurred, clear the OERR flag by
clearing the CREN receiver enable bit.
18.1.2.10 9-bit Address Detection Mode Set-up
This mode would typically be used in RS-485 systems.
To set up an Asynchronous Reception with Address
Detect Enable:
1. Initialize the SPBRGH, SPBRG reg ister pair and
the BRGH and BRG16 bits to achieve the
desired baud rate (see Section 18.3 “EUSART
Baud Rate Generator (BRG)”).
2. Set the RX/DT and TX/CK TRIS controls to ‘1’.
3. Enable the serial port by setting the SPEN bit.
The SYNC bit must be clear for asynchronous
operation.
4. If interrupts are desired, set the RCIE interrupt
enable bit and set the GIE and PEIE bits of the
INTCON register.
5. Enable 9-bit reception by setting the RX9 bit.
6. Enable a ddress d etection by setting the ADDEN
bit.
7. Set the DTRXP if inverted receive polarity is
desired.
8. Enable reception by setting the CREN bit.
9. The RCIF interrupt flag bit will be set when a
character with the ninth bit set is transferred
from the RSR to the receive buffer. An interrupt
will b e gener ated if t he RCIE inte rrupt en able b it
was also set.
10. Read the RCSTA register to get the error flags.
The ninth data bit will always be set.
1 1. Get the received eig ht Least Significant da ta bits
from the receive buffer by reading the RCREG
register. Software determines if this is the
device’s address.
12. If an overrun occurred, clear the OERR flag by
clearing the CREN receiver enable bit.
13. If the device has been addressed, clear the
ADDEN bit to allow all received data into the
receive buffer and generate interrupts.
PIC18F2XK20/4XK20
DS40001303H-page 230 2010-2015 Microchip Technology Inc.
FIGURE 18-5: ASYNCHRONOUS RECEPTION
TABLE 18-2: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 56
PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 59
PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 59
IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 59
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 58
RCREG EUSART Receive Register 58
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 59
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 58
BAUDCON ABDOVF RCIDL DTRXP CKTXP BRG16 — WUE ABDEN 58
SPBRGH EUSART Baud Rate Generator Register, High Byte 58
SPBRG EUSART Baud Rate Generator Register, Low Byte 58
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
Note 1: Reserved in PIC18F2XK20 devices; always maintain these bits clear.
Start
bit bit 7/8
bit 1bit 0 bit 7/8 bit 0Stop
bit
Start
bit Start
bit
bit 7/8 Stop
bit
RX/DT pin
Reg
Rcv Buffer Reg
Rcv Shift
Read Rcv
Buffer Reg
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
Word 1
RCREG Word 2
RCREG
Stop
bit
Note: This timin g diagram sho ws three words appearing on the RX input. The RCREG (receive buffer) is r ead after the third word,
causing the OERR (overrun) bit to be set.
RCIDL
2010-2015 Microchip Technology Inc. DS40001303H-page 231
PIC18F2XK20/4XK20
18.2 Clock Accuracy with
Asynchronous Operation
The factory calibrates the internal oscillator block out-
put (HFINTOSC). However, the HFINTOSC frequency
may drift as VDD or temperature changes, and this
directly affec ts the asy nchronou s baud rate. Two me th-
ods may be used to adjus t the baud rate cl ock, but both
require a reference clock source of some kind.
The first (preferred) method uses the OSCTUNE
register to adjust the HFINTOSC output. Adjusting the
value in the OSCTUNE register allows for fine resolution
changes to the system clock source. See Section 2.5
“Internal Clock Modes” for more information.
The other method adjusts the value in the Baud Rate
Generator. This can be done automatically with the
Auto-Baud Detect feature (see Section 18.3.1
“Auto-Baud Detect”). There may not be fine enough
resolution when adjusting the Baud Rate Generator to
compensate for a gradual change in the peripheral
clock frequency.
REGISTER 18-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-1 R/W-0
CSRC TX9 TXEN(1) SYNC SENDB BRGH TRMT TX9D
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 CSRC: Clock Source Select bit
Asynchronous mode:
Don’t care
Synchronous mode:
1 = M aster mode (clock generated internally from BRG)
0 = Slav e mode (clock from external so urce)
bit 6 TX9: 9-bit Transmit Enable bit
1 = Selec ts 9-bit transmission
0 = Selec ts 8-bit transmission
bit 5 TXEN: Transmit Enable bit(1)
1 = Transmit enabled
0 = Transmit disabled
bit 4 SYNC: EUSART Mode Select bit
1 = S ync hronous mode
0 = A sy nchronous mode
bit 3 SENDB: Send Break Character bit
Asynchronous mode:
1 = S end Sync Break on next transmission (cleared by hardware upon completion)
0 = S ync Break transmiss i on completed
Synchronous mode:
Don’t care
bit 2 BRGH: High Baud Rat e Select bit
Asynchronous mode:
1 = H igh speed
0 = L ow speed
Synchronous mode :
Unused in this mode
bit 1 TRMT: Transmit Shift Register Status bit
1 = TS R empty
0 = TSR full
bit 0 TX9D: Ninth bit of Transm it Data
Can be address/data bit or a parity bit.
Note 1: SREN/CREN overrides TXEN in Sync mode.
PIC18F2XK20/4XK20
DS40001303H-page 232 2010-2015 Microchip Technology Inc.
REGISTER 18-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER(1)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x
SPEN RX9 SREN CREN ADDEN FERR OERR RX9D
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 SPEN: Serial Port Enable bit
1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins)
0 = Serial port disabled (held in Reset)
bit 6 RX9: 9-bit Receive Enable bit
1 = Selects 9-bit reception
0 = Selects 8-bit reception
bit 5 SREN: Single Receive Enable bit
Asynchronous mode:
Don’t care
Synchronous mode – Master:
1 = Enables single receive
0 = Disables single receive
This bit is cleared after reception is complete.
Synchronou s mode – Slave
Don’t care
bit 4 CREN: Continuous Receiv e Enab le bit
Asynchronous mode:
1 = Enables receiver
0 = Disables receiver
Synchronous mode:
1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0 = Disable s con tinuous receive
bit 3 ADDEN: Address Detect Enable bit
Asynchronous mode 9-bit (RX9 = 1):
1 = Enables address detection, enable interrupt and load the receive buffer when RSR<8> is set
0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit
Asynchronous mode 8-bit (RX9 = 0):
Don’t care
bit 2 FERR: Framing Error bit
1 = Framing error (can be updated by reading RCREG register and receive next valid byte)
0 = No framing error
bit 1 OERR: Overrun Error bit
1 = Overrun error (can be cleared by clearing bit CREN)
0 = No overrun error
bit 0 RX9D: Ninth bit of Received D ata
This can be address/data bit or a parity bit and must be calculated by user firmware.
2010-2015 Microchip Technology Inc. DS40001303H-page 233
PIC18F2XK20/4XK20
REGISTER 18-3: BAUDCON: BAUD RATE CONTROL REGISTER
R/W-0 R-1 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0
ABDOVF RCIDL DTRXP CKTXP BRG16 — WUE ABDEN
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unim plem ented bit, rea d as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is clear ed x = Bi t is unk nown
bit 7 ABDOVF: Auto-Baud Detect Overflow bit
Asy nchronous mod e:
1 = Auto-baud timer overflowed
0 = Auto - baud ti m er did not ov erflow
Syn chr on ous mode:
Don’t care
bit 6 RCIDL: Receive Id l e Flag bi t
Asy nchronous mod e:
1 = Receiver is Idle
0 = Start bit has been d et ect ed and the re cei ver is activ e
Syn chr on ous mode:
Don’t care
bit 5 DTRXP: Data/Rece i ve P o larity Sele ct bi t
Asy nchronous mod e:
1 = Receive data (RX) is inverted (active-low)
0 = Receive data (RX) is not inverted (active-high)
Syn chr on ous mode:
1 = Data (DT) is inverted (active-low)
0 = Data (DT) is not inverted (active-high)
bit 4 CKTXP: Clock/Transmit Polarity Select bit
Asy nchronous mod e:
1 = Idle state for transmit (TX) is low
0 = Idle state for transmit (TX) is high
Syn chr on ous mode:
1 = Data changes on the fall in g edge of the clock and is sam pled on the risi ng edge of the cl ock
0 = Data changes on the risin g edge of the clock and is sampled on the falling edge of the cl ock
bit 3 BRG16: 16-bit Baud Rate Ge ner at or bi t
1 = 16-bit Baud Rate Generator is used (SPBRGH:SPBRG)
0 = 8-bit Baud Ra te Gene rator is used (SPBRG)
bit 2 Unimplemen ted: Read as ‘0’
bit 1 WUE: W ake-up Enable bit
Asy nchronous mod e:
1 = Receiver is waiting for a falling edge. No character will be received but RCIF will be set on the falling
edge. WUE will automatically clear on the rising edge.
0 = Receiver is operating normally
Syn chr on ous mode:
Don’t care
bit 0 ABDEN: Auto-Baud Dete ct Enable bit
Asy nchronous mod e:
1 = A ut o- Baud Detec t mode is enabled (clear s when auto-b aud is complet e)
0 = A ut o- Baud Detec t mode is disabl ed
Syn chr on ous mode:
Don’t care
PIC18F2XK20/4XK20
DS40001303H-page 234 2010-2015 Microchip Technology Inc.
18.3 EUSART Baud Rate Generator
(BRG)
The Baud Rate Generator (BRG) is an 8-bit or 16-bit
timer that is dedicated to the support of both the
asynchronous and synchronous EUSART operation.
By defau lt, the BRG ope rates in 8-bit mode . Setting th e
BRG16 bit of the BAUDCON register selects 16-bit
mode.
The SPBRGH:SPBRG register pair determines the
period of the free running baud rate timer. In
Asynchronous mode the multiplier of the baud rate
period is determined by both the BRGH bit of the TXST A
register and the BRG1 6 bit of the BAUDCON register. In
Synchronous mode, the BRGH bit is ignored.
Table 18-3 contains the formulas for determining the
baud rate . Example 18-1 provides a s ample calcul ation
for determining the baud rate and baud rate error.
Typical baud rates and error values for various
asynchronous modes have been computed for your
convenience and are shown in Table 18-5. It may be
advantageous to use the high baud rate (BRGH = 1),
or the 16-bit BRG (BRG16 = 1) to reduce the b aud ra te
error. The 16-bit BRG mode is used to achieve slow
baud rates for fast oscillator frequencies.
Writing a new value to the SPBRGH, SPBRG register
pair c auses the BRG timer to be reset (or cleared). Thi s
ensures that the BRG do es not wait fo r a timer overf low
before outputting the new baud rate.
If the s ys tem c lo ck is changed during an active receiv e
operation, a receive error or data loss may result. To
avoid thi s problem , check the status of the RCID L bit to
make sure that the receive operation is Idle before
changing the system clock.
EXAMPLE 18-1: CALCULATIN G BAUD
RATE ERROR
TABLE 18-3: BAUD RATE FORMULAS
TABLE 18-4: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
For a devi ce w ith FOSC of 16 MHz, desired baud rate
of 9600, Asynch ronous mode, 8-bit BRG:
Solving for SPBRGH:SPBRG:
X
FOSC
Desired Ba ud R at e
---------------------------------------------
64
--------------------------------------------- 1–=
Desired Baud Rate FOSC
64 [SPBRGH:SPBRG] 1+
---------------------------------------------------------------------=
16000000
9600
------------------------
64
------------------------1–=
25.04225==
Calculated Baud Rate 16000000
64 25 1+
---------------------------=
9615=
Error Calc. Bau d Rate Desired B aud Rate –
Desired Baud Rate
--------------------------------------------------------------------------------------------=
9615 9600–
9600
---------------------------------- 0. 16 %==
Configuration Bits BRG/EUSART Mode Baud Rate For m ula
SYNC BRG16 BRGH
000 8-bit/Asynchronous FOSC/[64 (n+1)]
001 8-bit/Asynchronous FOSC/[16 (n+1)]
010 16-bit/Asynchronous
011 16-bit/Asynchronous
FOSC/[4 (n+1)]10x 8-bit/Synchronous
11x 16-bit/Synchronous
Legend: x = Don’t care, n = value of SPBRGH, SPBRG register pair
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset V alues
on page
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 58
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 58
BAUDCON ABDOVF RCIDL DTRXP CKTXP BRG16 —WUE ABDEN 58
SPBRGH EUSART Baud Rate Generator Register, High Byte 58
SPBRG EUSART Baud Rate Generator Register, Low Byte 58
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the BRG.
2010-2015 Microchip Technology Inc. DS40001303H-page 235
PIC18F2XK20/4XK20
TABLE 18-5: BAUD RATES FOR ASYNCHRONOUS MODES
BAUD
RATE
SYNC = 0, BRGH = 0, BRG16 = 0
FOSC = 64.000 MHz FOSC = 18.432 MHz F OSC = 16.000 MHz FOSC = 11.0592 MHz
Actual
Rate %
Error
SPBRG
value
(decimal)
Actual
Rate %
Error
SPBRG
value
(decimal)
Actual
Rate %
Error
SPBRG
value
(decimal)
Actual
Rate %
Error
SPBRG
value
(decimal)
300—— — —— — —— — —— —
1200 —— —1200 0.00 239 1202 0.16 207 1200 0.00 143
2400 —— —2400 0.00 119 2404 0.16 103 2400 0.00 71
9600 9615 0.16 103 9600 0.00 29 9615 0.16 25 9600 0.00 17
10417 10417 0.00 95 10286 -1.26 27 10417 0.00 23 10165 -2.42 16
19.2k 19.23k 0.16 51 19.20k 0.00 14 19.23k 0.16 12 19.20k 0.00 8
57.6k 58.82k 2.12 16 57.60k 0.00 7—— —
57.60k 0.00 2
115.2k 111.11k -3.55 8 — — — — — — — — —
BAUD
RATE
SYNC = 0, BRGH = 0, BRG16 = 0
FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz
Actual
Rate %
Error
SPBRG
value
(decimal)
Actual
Rate %
Error
SPBRG
value
(decimal)
Actual
Rate %
Error
SPBRG
value
(decimal)
Actual
Rate %
Error
SPBRG
value
(decimal)
300 — — — 300 0.16 207 300 0.00 191 300 0.16 51
1200 1202 0.16 103 1202 0.16 51 1200 0.00 47 1202 0.16 12
2400 2404 0.16 51 2404 0.16 25 2400 0.00 23 — — —
9600 9615 0.16 12 — — — 9600 0.00 5 — — —
10417 10417 0.00 11 10417 0.00 5 — — — — — —
19.2k — — — — — — 19.20k 0.00 2 — — —
57.6k — — — — — — 57.60k 0.00 0 — — —
115.2k — — — — — — — — — — — —
BAUD
RATE
SYNC = 0, BRGH = 1, BRG16 = 0
FOSC = 64.000 MHz FOSC = 18.432 MHz F OSC = 16.000 MHz FOSC = 11.0592 MHz
Actual
Rate %
Error
SPBRG
value
(decimal)
Actual
Rate %
Error
SPBRG
value
(decimal)
Actual
Rate %
Error
SPBRG
value
(decimal)
Actual
Rate %
Error
SPBRG
value
(decimal)
300 —— — —— — —— — —— —
1200 — — — — — — — — — — — —
2400 — — — — — — —— — —— —
9600 — — — 9600 0.00 119 9615 0.16 103 9600 0.00 71
10417 — — — 10378 -0.37 110 10417 0.00 95 10473 0.53 65
19.2k 19.23k 0.16 207 19.20k 0.00 59 19.23k 0.16 51 19.20k 0.00 35
57.6k 57.97k 0.64 68 57.60k 0.00 19 58.82k 2.12 16 57.60k 0.00 11
115.2k 114.29k -0.79 34 115.2k 0.00 9 111.1k -3.55 8 115.2k 0.00 5
PIC18F2XK20/4XK20
DS40001303H-page 236 2010-2015 Microchip Technology Inc.
BAUD
RATE
SYNC = 0, BRGH = 1, BRG16 = 0
FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz
Actual
Rate %
Error
SPBRG
value
(decimal)
Actual
Rate %
Error
SPBRG
value
(decimal)
Actual
Rate %
Error
SPBRG
value
(decimal)
Actual
Rate %
Error
SPBRG
value
(decimal)
300 —— — — — — — — — 300 0.16 207
1200 — — — 1202 0.16 207 1200 0.00 191 1202 0.16 51
2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25
9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 — — —
10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5
19.2k 19231 0.16 25 19.23k 0.16 12 19.2k 0.00 11 — — —
57.6k 55556 -3.55 8 — — — 57.60k 0.00 3 — — —
115.2k — — — — — — 115.2k 0.00 1 — — —
BAUD
RATE
SYNC = 0, BRGH = 0, BRG16 = 1
FOSC = 64.000 MHz FOSC = 18.432 MHz F OSC = 16.000 MHz FOSC = 11.0592 MHz
Actual
Rate %
Error
SPBRGH
:SPBRG
(decimal)
Actual
Rate %
Error
SPBRGH
:SPBRG
(decimal)
Actual
Rate %
Error
SPBRGH
:SPBRG
(decimal)
Actual
Rate %
Error
SPBRGH
:SPBRG
(decimal)
300 300.0 0.00 13332 300.0 0.00 3839 300.03 0.01 3332 300.0 0.00 2303
1200 1200.1 0.01 3332 1200 0.00 959 1200.5 0.04 832 1200 0.00 575
2400 2399 -0.02 1666 2400 0.00 479 2398 -0.08 416 2400 0.00 287
9600 9592 -0.08 416 9600 0.00 119 9615 0.16 103 9600 0.00 71
10417 10417 0.00 383 10378 -0.37 110 10417 0.00 95 10473 0.53 65
19.2k 19.23k 0.16 207 19.20k 0.00 59 19.23k 0.16 51 19.20k 0.00 35
57.6k 57.97k 0.64 68 57.60k 0.00 19 58.82k 2.12 16 57.60k 0.00 11
115.2k 114.29k -0.79 34 115.2k 0.00 9 111.11k -3.55 8 115.2k 0.00 5
BAUD
RATE
SYNC = 0, BRGH = 0, BRG16 = 1
FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz
Actual
Rate %
Error
SPBRGH
:SPBRG
(decimal)
Actual
Rate %
Error
SPBRGH
:SPBRG
(decimal)
Actual
Rate %
Error
SPBRGH
:SPBRG
(decimal)
Actual
Rate %
Error
SPBRGH
:SPBRG
(decimal)
300 299.9 -0.02 1666 300.1 0.04 832 300.0 0.00 767 300.5 0.16 207
1200 1199 -0.08 416 1202 0.16 207 1200 0.00 191 1202 0.16 51
2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25
9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 — — —
10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5
19.2k 19.23k 0.16 25 19.23k 0.16 12 19.20k 0.00 11 — — —
57.6k 55556 -3.55 8 — — — 57.60k 0.00 3 — — —
115.2k — — — — — — 115.2k 0.00 1 — — —
TABLE 18-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)
2010-2015 Microchip Technology Inc. DS40001303H-page 237
PIC18F2XK20/4XK20
BAUD
RATE
SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1
FOSC = 64.000 MHz FOSC = 18.432 MHz F OSC = 16.000 MHz FOSC = 11.0592 MHz
Actual
Rate %
Error
SPBRGH
:SPBRG
(decimal)
Actual
Rate %
Error
SPBRGH
:SPBRG
(decimal)
Actual
Rate %
Error
SPBRGH
:SPBRG
(decimal)
Actual
Rate %
Error
SPBRGH
:SPBRG
(decimal)
300 300 0.00 53332 300.0 0.00 15359 300.0 0.00 13332 300.0 0.00 9215
1200 1200 0.00 13332 1200 0.00 3839 1200.1 0.01 3332 1200 0.00 2303
2400 2400 0.00 6666 2400 0.00 1919 2399.5 -0.02 1666 2400 0.00 1151
9600 9598.1 -0.02 1666 9600 0.00 479 9592 -0.08 416 9600 0.00 287
10417 10417 0.00 1535 10425 0.08 441 10417 0.00 383 10433 0.16 264
19.2k 19.21k 0.04 832 19.20k 0.00 239 19.23k 0.16 207 19.20k 0.00 143
57.6k 57.55k -0.08 277 57.60k 0.00 79 57.97k 0.64 68 57.60k 0.00 47
115.2k 115.11k -0.08 138 115.2k 0.00 39 114.29k -0.79 34 115.2k 0.00 23
BAUD
RATE
SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1
FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz
Actual
Rate %
Error
SPBRGH
:SPBRG
(decimal)
Actual
Rate %
Error
SPBRGH
:SPBRG
(decimal)
Actual
Rate %
Error
SPBRGH
:SPBRG
(decimal)
Actual
Rate %
Error
SPBRGH
:SPBRG
(decimal)
300 300.0 0.00 6666 300.0 0.01 3332 300.0 0.00 3071 300.1 0.04 832
1200 1200 -0.02 1666 1200 0.04 832 1200 0.00 767 1202 0.16 207
2400 2401 0.04 832 2398 0.08 416 2400 0.00 383 2404 0.16 103
9600 9615 0.16 207 9615 0.16 103 9600 0.00 95 9615 0.16 25
10417 10417 0.00 191 10417 0.00 95 10473 0.53 87 10417 0.00 23
19.2k 19.23k 0.16 103 19.23k 0.16 51 19.20k 0.00 47 19.23k 0.16 12
57.6k 57.14k -0.79 34 58.82k 2.12 16 57.60k 0.00 15 — — —
115.2k 117.6k 2.12 16 111.1k -3.55 8 115.2k 0.00 7 — — —
TABLE 18-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)
PIC18F2XK20/4XK20
DS40001303H-page 238 2010-2015 Microchip Technology Inc.
18.3.1 AUTO-BAUD DETECT
The EUSART module supports automatic detection
and calibration of the baud rate.
In the Auto-Baud Detect (ABD) mode, the clock to the
BRG is reversed. Rather than the BRG clocking the
incoming RX signal, the RX signal is timing the BRG.
The Baud Rate Generator is used to time the period of
a receiv ed 55h (ASCII “U ”) which is the Sync character
for the LIN bus. The unique feature of this character is
that it has five rising edges in cluding the S top bit ed ge.
Setting the ABDEN bit of the BAUDCON register starts
the auto-baud calibration sequence (Figure 18.3.2).
While the ABD sequence takes place, the EUSART
state machine is held in Idle. On the first rising edge of
the receive line, after the Start bit, the SPBRG begins
counting up using the BRG counter clock as shown in
Table 18-6. Th e fifth rising edge wil l occur on the RX pin
at the end of the eighth bit period. At that time, an
accumulated value totaling the proper BRG period is
left in the SPBRGH:SPBRG register pair, the ABDEN
bit is automatically clea red, and the RCIF interrupt flag
is set. A read operation on the RCREG needs to be
performed to clear the RCIF interrupt. RCREG content
should be discarded. When calibrating for modes that
do not use the SPBRGH register the user can verify
that the SPBRG register did not overflow by checking
for 00h in the SPBRGH register.
The BRG au to-baud clock is d etermined by the BRG1 6
and BRGH bits as shown in Table 18-6. During ABD,
both the SPBRGH and SPBRG registers are used as a
16-bit counter, independent of the BRG16 bit setting.
While calibrating the baud rate period, the SPBRGH
and SPBRG registers are clocked at 1/8th the BRG
base clo ck rate. The resu lting byte meas urement is the
average bit time when clocked at full speed.
TABLE 18-6: BRG COUNTER CLOCK RATES
FIGURE 18-6: AUTOMATIC BAUD RATE CALIBRATION
Note 1: If the WUE bit is set with the ABDEN bit,
auto-bau d detection will occur on the byte
following the Break character (see
Section 18.3.3 “Auto-Wake-up on
Break”).
2: It is up to the user to determine that the
incoming character baud r ate is within the
range of the selected BRG clock source.
Some combinations of oscillator frequency
and EUSART baud rates are not possible.
3: During the auto-baud process, the
auto-baud counter starts counting at 1.
Upon completion of the auto-baud
sequence, to achieve maximum accuracy,
subtract 1 from the SPBRGH:SPBRG
register pair.
BRG16 BRGH BRG Base
Clock BRG ABD
Clock
00FOSC/64 FOSC/512
01FOSC/16 FOSC/128
10FOSC/16 FOSC/128
11 FOSC/4 FOSC/32
Note: During the ABD sequence, SPBRG and
SPBRGH registers are both used as a 16-bit
counter , independent of BRG16 setting.
BRG Value
RX pin
ABDEN bit
RCIF bit
bit 0 bit 1
(Interrupt)
Read
RCREG
BRG Clock
Start
Auto Cleared
Set by User
XXXXh 0000h
Edge #1 bi t 2 bit 3
Edge #2 bit 4 bit 5
Edge #3 bit 6 bit 7
Edge #4 Stop bit
Edge #5
001Ch
Note 1: The A BD seq uen ce requ ire s the EUSART mo dule to be configur ed i n Asynchr ono us mod e.
SPBRG XXh 1Ch
SPBRGH XXh 00h
RCIDL
2010-2015 Microchip Technology Inc. DS40001303H-page 239
PIC18F2XK20/4XK20
18.3.2 AUTO-BAUD OVERFLOW
During the course of automatic baud detection, the
ABDOVF bit of the BAUDCON register wi ll be set if th e
baud rat e c ou nte r ov erf low s b efore th e fif th rising edge
is detected on the RX pin. The ABDOVF bit indicates
that the cou nter has exceeded th e maximum co unt that
can fit in the 16 bits of the SPBRGH:SPBRG register
pair. After the ABDOVF has been set, the counter con-
tinues to count until the fifth rising edge is detected on
the RX pin. Upo n det ecting the fif th RX edge , the hard-
ware will set the RCIF interrupt flag and clear the
ABDEN bit of the BAUDCON register. The RCIF flag
can be subsequently cleared by reading the RCREG.
The ABDOVF flag can be cleared by software directly.
To terminate the auto-baud process before the RCIF
flag is set, clear the ABDEN bit then clear t he ABDOVF
bit. The ABDOVF bit will rem ain s et i f th e ABDEN b it is
not cleared first.
18.3.3 AUTO-WAKE-UP ON BREAK
During Sleep mode, all clocks to the EUSART are
suspended. Because of this, the Baud Rate Generator
is inactive and a proper character reception cannot be
performed. The Auto-Wake-up feature allows the
controll er to w ake -up due to ac tiv ity on the R X/DT line.
This feature is available only in Asynchronous mode.
The Auto-Wake-up feature is enabled by setting the
WUE bit o f the BAUDCON register . Once set, the normal
receive sequence on RX/DT is disabled, and the
EUSART remains in an Idle state, monitoring for a
wake-up event independent of the CPU mode. A
wake-up ev ent c onsist s o f a hi gh-to-low trans ition o n the
RX/DT line. (This coincides with the start of a Sync Break
or a wak e-up sig nal ch arac ter fo r the L IN prot oco l.)
The EUSART module generates an RCIF interrupt
coincident with the wake-up event. The interrupt is
generated s ynchronously to the Q clocks in normal CPU
operating modes (Figure 18-7), and asynchronously if
the device is in Sleep mode (Figure 18-8). The interrupt
condition is cleared by read ing the R CREG regis ter.
The WUE bit is automatically cleared by the low-to-high
transition on the RX line at the end of the Break. This
signals to the user that the Break event is over. At this
point, the EUSART module is in Idle mode waiting to
receive the next character.
18.3.3.1 Special Considerations
Brea k Character
To avoid character errors or character fragments during
a wake-up event, the wake-up character must be all
zeros.
When the wake-up is enabled the function works
independent of the low time on the data stream. If the
WUE bit is set and a valid non-zero character is
receive d, the low time from the S tart bit to the first ris ing
edge will be interpreted as the wake-up event. The
remaining bits in the character will be received as a
fragmented character and subsequent characters can
result in framing or overrun errors.
Therefore, the ini tial cha racter in the transmi ssion mus t
be all ‘0’s. This must be ten or more bit times, 13-bit
times recommended for LIN bus, or any number of bit
times for standard RS-232 devices.
Oscillator Startup Ti me
Oscillator start-up time must be considered, especially
in applications using oscillators with longer start-up
intervals (i.e., LP, XT or HS/PLL mode). The Sync
Break (or wake-up signal) character must be of
sufficient length, and be followed by a sufficient
interval , to allow eno ugh ti me fo r the se lecte d osc illat or
to start and provide proper initialization of the EUSART .
WUE Bit
The wake-up event causes a receive interrupt by
setting the RCIF bit. The WUE bit is cleared by
hardware by a rising edge on RX/DT. The interrupt
condition is then cleared by software by reading the
RCREG register and discarding its contents.
To ensure that no actual data is lost, check the RCIDL
bit to verify that a receive operation is not in process
before set ting the WU E bit. If a recei ve opera tion is n ot
occurring, the WUE bit may then be set just prior to
entering the Sleep mode.
PIC18F2XK20/4XK20
DS40001303H-page 240 2010-2015 Microchip Technology Inc.
FIGURE 18-7: AUTO-WAKE-UP BIT (WUE) TIMING DURING NORMAL OPERATION
FIGURE 18-8: AUTO-WAKE -UP B IT (WUE) TIMINGS DURING SLEEP
Q1 Q2Q3Q4Q1 Q2Q3Q4 Q1Q2 Q3Q4 Q1Q2 Q3Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3Q4 Q1Q2 Q3Q4 Q1 Q2Q3Q4 Q1Q2 Q3Q4
OSC1
WUE bit
RX/DT Line
RCIF
Bit set by user Auto Cleared
Cleared due to User Read of RCREG
Note 1: The EUSART remains in Idle while the WUE bit is set.
Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4 Q1 Q2 Q3Q4 Q1Q2Q3Q4 Q1Q2 Q3Q4Q1Q2Q3Q4 Q1Q2Q3Q4
OSC1
WUE bit
RX/DT Line
RCIF
Bit Set by User Auto Clear ed
Cleared due to User Read of RCREG
Sleep Command Executed
Note 1
Note 1: If the wake-up even t requires long o scillator warm-up t ime, the a utomatic clear ing of the WUE bit can o ccur while the stposc signal is
still active. This sequence should not depend on the presence of Q clocks.
2: The EUSART remains in Idle while the WUE bit is set.
Sleep Ends
2010-2015 Microchip Technology Inc. DS40001303H-page 241
PIC18F2XK20/4XK20
18.3.4 BREAK CHARACTER SEQUENCE
The EUSART module ha s t he c apability of s en din g th e
special Break character sequ ences that are required by
the LIN bus standard. A Break character consists of a
Start bit, follo w ed by 12 ‘0’ bits and a Stop bit.
To send a Break character, set the SENDB and TXEN
bits of the TXSTA register. The Break character trans-
mission is then initiated by a write to the TXREG. The
value of data written to TXREG will be ignored and all
‘0’s will be transmitted.
The SENDB bit is automatically reset by hardware af ter
the corresponding Sto p b it is s ent . Th is al lows the user
to preloa d the trans mit FIFO with the n ext transm it byte
following the Break character (typically, the Sync
character in the LIN specification).
The TRMT bit of the TXSTA register indicates when the
transmit operation is active or Idle, jus t as it does during
normal transmission. See Figure 18-9 for the timing of
the Break character sequence.
18.3.4.1 Break and Sync Transmi t Seque nc e
The following sequence will start a message frame
header made up of a Break, followed by an auto-baud
Sync byte. This sequence is typical of a LIN bus
master.
1. Conf igur e the EUSART for the desired mode.
2. Set the TXEN and SENDB bits to enable the
Break sequence.
3. Load the TXREG with a dummy character to
initiate transmission (the value is ignored).
4. Write ‘55h’ to TXREG to load the Sync character
into the transm it FIFO buf f er.
5. After the Break has been se nt, the SEND B bit is
reset by hardware and the Sync character is
then transm itte d.
When the TXR EG b ec om es em pty, as indica ted by the
TXIF, the next data byte can be written to TXREG.
18.3.5 RECEIVING A BREAK CHARACTER
The Enhanced EUSART module can receive a Break
character in two ways.
The first method to detect a Break character uses the
FERR bit of the RCSTA register and the Rece ived dat a
as indicated by RCREG. The Baud Rate Generator is
assum ed to ha ve been initialize d to the exp ec ted baud
rate.
A Break character has been received when;
• RCIF bit is set
• FERR bit is set
• RCREG = 00h
The second method uses the Auto-Wake-up feature
described in Section 18.3.3 “Auto-Wake-up on
Break”. By enabling this feature, the EUSART will
sample the next two transitions on RX/DT, cause an
RCIF interru pt, and receive th e n ext d at a byte followed
by another interrupt.
Note that following a Break character, the user will
typically want to enable the Auto-Baud Detect feature.
For both methods, the user can set the ABDEN bit of
the B AUD CON reg ist er bef ore plac ing th e EUS ART in
Sleep mode.
FIGURE 18-9: SEND BREAK CHARACTER SEQUENCE
Write to TXREG Dummy Write
BRG Output
(Shift Clock)
S tart bit bit 0 bit 1 bit 11 Stop bit
Break
TXIF bit
(Transmit
interrupt Flag)
TX (pin)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
SENDB
(send Break
control bit)
SENDB Sam ple d Here Auto Cleared
PIC18F2XK20/4XK20
DS40001303H-page 242 2010-2015 Microchip Technology Inc.
18.4 EUSART Synchronous Mode
Synchronous serial communications are typically used
in systems with a single master and one or more
slaves. The master device contains the necessary
circuit ry for b aud rate ge neration and supplies the clock
for all devices in the system. Slave devices can take
advantage of the master clock by eliminating the
internal clock generation circuitry.
There are two signal lines in Synchronous mode: a
bidirectional data line and a clock line. Slaves use the
external clock supplied by the master to shift the serial
data into and out of their respective receive and
transmit shift registers. Since the data line is
bidirectional, synchronous operation is half-duplex
only. Half-duplex refers to the fact that master and
slave devices can receive and transmit data but not
both simultaneously. The EUSART can operate as
either a master or slave device.
Start and Stop bits are not used in synchronous
transmissions.
18.4.1 SYNCHRONOUS MASTER MODE
The following bits are used to configure the EUSART
for Synchronous Master operation:
• SYNC = 1
• CSRC = 1
• SREN = 0 (for transmit); SREN = 1 (for receive)
• CREN = 0 (for transmit); CREN = 1 (for receive)
• SPEN = 1
Setting the SYNC bit of the TXSTA register configures
the de vi c e f or sy n ch ronous operat i on . Se tt ing the CSRC
bit of the TXSTA register configures the device as a
master. Clearing the SREN and CREN bits of the RCST A
regis ter ensures that the device i s in th e Transm it mo de,
otherwise the device will be configured to receive. Setting
the SPEN bit of the RCSTA register enables the
EUSAR T. If the RX/DT or TX/CK pi ns are shared with an
analog peripheral the analog I/O functions must be
disab le d by c le aring the corresp on di ng ANSEL bit s.
The TRIS bits corresponding to the RX/DT and TX/CK
pins should be set.
18.4.1.1 Master Clock
Synchronous data transfers use a separate clock line,
which is synchronous wi th the data. A device configured
as a master transmits the clock on the TX/CK line. The
TX/CK pin output driver is automatically enabled when
the EUSART is configured for synchronous transmit or
receive operation. Serial dat a bits change on the leading
edge to ensure they are valid at the trailing edge of each
clock. One clock cycle is generated for each data bit.
Only as many clock cycles are generated as there are
da ta bits.
18.4.1.2 Clock Polarity
A clock polarity option is provided for Microwire
comp atibilit y. Clo ck polarity is selec ted with the CKTXP
bit of the BAUDCON register. Setting the CKTXP bit
sets the clock Idle state as high. When the CKTXP bit
is set, the data changes on the falling edge of each
clock and is sampled on the rising edge of each clock.
Clearing th e CKTXP bit sets the Idle state as low . When
the CKTXP bit is cleared, the data changes on the
rising edge of each clock and is sampled on the falling
edge of ea ch clock.
18.4.1.3 Synchronous Master Transmission
Data is transferred out of the device on the RX/DT pin.
The RX/DT and TX/C K pi n outp ut driv ers ar e aut oma t-
ically enabled when the EUSART is configured for
synchronous master transmit operation.
A transmission is initiated by writing a character to the
TXREG reg is ter. If the TSR st ill co ntains all or p art o f a
previous character the new character data is held in the
TXREG until the last bit of the previous character has
been tr ansmitted. If this i s the first charac ter , or the pre-
vious character has been completely flushed from the
TSR, the d ata in th e TXREG is im mediatel y transferre d
to the TSR. The transmission of the character com-
mences immediately following the transfer of the data
to the TSR from the TXREG.
Each data bit changes on the leading edge of the
master clock and remains valid until the subsequent
leading clock edge.
18.4.1.4 Data Polarity
The polarity of the transmit and receive data can be
controlled with the DTRXP bit of the BAUDCON regis-
ter. The defau lt st a te of thi s bi t is ‘0’ which selects high
true transmit and receive data. Setting the DTRXP bit
to ‘1’ will invert the data resulting in low true transmit
and receive data.
Note: The TSR register is not mapped in data
memory, so it is not available to the user.
2010-2015 Microchip Technology Inc. DS40001303H-page 243
PIC18F2XK20/4XK20
18.4.1.5 Synchronous Master Transmission
Set-up:
1. Initialize the SPBRGH, SPBRG reg ister pair and
the BRGH and BRG16 bits to achieve the
des i red baud rat e (see Section 18.3 “EUSART
Baud Rate Generator (BRG)”).
2. Set the RX/DT and TX/CK TRIS controls to ‘1’.
3. Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC. Set the
TRIS bits corresponding to the RX/DT and
TX/CK I/O pins.
4. Disable Receive mode by clearing bits SREN
and CREN.
5. Enable Transmit mode by setting the TXEN bit.
6. If 9-bit transmission is desired, set the TX9 bit.
7. If interrupts are desired, set the TXIE, GIE and
PEIE interrupt enable bits.
8. If 9-bit transmission is selected, the ninth bit
should be loaded in the TX9D bit.
9. S tart transmission b y loading data to the TXREG
register.
FIGURE 18-10: SYNCHRONOUS TRANSMISSION
FIGURE 18-11: SYNCHRONOUS TRANSM ISSION (THROUGH TXEN)
bit 0 bit 1 bit 7
Word 1 bit 2 bit 0 bit 1 bit 7
RX/DT
Write to
TXREG Reg
TXIF bit
(Interrupt Flag)
TXEN bit ‘1’ ‘1’
Word 2
TRMT bi t
Write Word 1 Write Word 2
Note: Sync Master mode, SPBRG = 0, continuous transmission of two 8-bit words.
pin
TX/CK p in
TX/CK pin
(SCKP = 0)
(SCKP = 1)
RX/DT pin
TX/CK pin
Write to
TXREG reg
TXIF bit
TRMT bit
bit 0 bit 1 bit 2 bit 6 bit 7
TXEN bi t
PIC18F2XK20/4XK20
DS40001303H-page 244 2010-2015 Microchip Technology Inc.
TABLE 18-7: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 56
PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 59
PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 59
IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 59
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 58
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 59
TXREG EUSART Transmit Regis ter 58
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 58
BAUDCON ABDOVF RCIDL DTRXP CKTXP BRG16 —WUE ABDEN 58
SPBRGH EUSART Baud Rate Generator Register, High Byte 58
SPBRG EUSART Baud Rate Generator Register, Low Byte 58
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used fo r synchronous master transmission.
Note 1: Reserved in PIC18F2XK20 devices; always maintain these bits clear.
2010-2015 Microchip Technology Inc. DS40001303H-page 245
PIC18F2XK20/4XK20
18.4.1.6 Synchronous Master Reception
Data is received at the RX/DT pin. The RX/DT pin
output driver must be disabled by setting the
corresponding TRIS bits when the EUSART is
configured for synchronous master receive operation.
In Synchronous mode, reception is enabled by setting
either the Single Receive Enable bit (SREN of the
RCSTA register) or the Continuous Receive Enable bit
(CREN of the RCSTA register).
When SREN is set and CREN is clear, only as many
clock cycles are generated as there are data bits in a
single character . The SREN bit is automatically cleared
at the com pletio n of one c har acter. When CREN is set,
clocks are continuously generated until CREN is
cleared . If CREN is cleared in the middle of a c haracter
the CK clo ck sto p s imm ed iat ely and t he p a rtia l charac-
ter is discarded. If SREN and CREN are both set, then
SREN is cl eared at the co mpletion of the first cha racter
and CREN takes precedence.
To initiate reception, set either SREN or CREN. Data is
sampled at the RX/DT pin on the trailing edge of the
TX/CK clock pin and is shifted into the Receive Shift
Register (RSR). When a complete character is
received into the RSR, the RCIF bit is set and the
character is automatically transferred to the two
charact er receive FIFO. Th e Least Signifi cant eight bit s
of the top character in the receive FIFO are available in
RCREG. The RCIF bit remains set as long as there are
un-read character s in th e receive FIFO.
18.4.1.7 Slave Clock
Synchronous data transfers use a separate clock line,
which is synchronous wi th the data. A device configured
as a slave receives the clock on the TX/CK line. The
TX/CK pin output driver must be disabled by setting the
associated TRIS bit when the device is configured for
synchronous slave transmit or receive operation. Serial
data bits change on the leading edge to ensure they are
valid at the trailing edge of each clock. One data bit is
transferred for each clock cycle. Only as many clock
cycles should be received as there are dat a bit s.
18.4.1.8 Receive Overrun Error
The receive FIFO buffer can hold two characters. An
overrun e rror will be genera ted if a th ird charac ter , in it s
entirety, is received before RCREG is read to access
the FIFO. When this happens the OERR bit of the
RCSTA register is set. Previous data in the FIFO will
not be overwritten. The two characters in the FIFO
buffer can be read, however, no additional characters
will be recei ved until the error is cle ared. The OERR bit
can on ly be clear ed by cl eari ng the o verr un con dition .
If the overrun error occurred when the SREN bit is set
and CREN is clear then the error is cleared by reading
RCREG. If the overrun occurred when the CREN bit is
set then th e error conditi on is cleared b y either clearin g
the CREN bit of the RCSTA register or by clearing the
SPEN bit which resets the EUSART.
18.4.1.9 Receiving 9-bit Characters
The EUSAR T support s 9-bit chara cter receptio n. When
the RX9 bit of the RCSTA register is set the EUSART
will shift 9-bits into the RSR for each character
received. The RX9D bit of the RCSTA register is the
ninth, and Most Significant, data bit of the top unread
charact er i n t he rec eiv e FIFO . Whe n r ead ing 9-bit data
from the receive FIFO buffer, the RX9D data bit must
be read before reading the eight Least Significant bits
from the RCREG.
18.4.1.10 Synchronous Master Reception
Set-up:
1. Initialize the SPBRGH, SPBRG register pair for
the appropriate baud rate. Set or clear the
BRGH and BRG16 bits, as required, to achieve
the desired baud rate.
2. Set the RX/DT and TX/CK TRIS controls to ‘1’.
3. Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC. Disable
RX/DT and TX/CK output drivers by setting the
corresponding TRIS bits.
4. Ensure bits CREN and SREN are clear.
5. If using interrupts, set the GIE and PEIE bits of
the INTCON register and set RCIE.
6. If 9-bit reception is desired, set bit RX9.
7. Start reception by setting the SREN bit or for
continuous reception, set the CREN bit.
8. Interrupt fla g bit RCIF will be se t when receptio n
of a character is complete. An interrupt will be
generated if the enable bit RCIE was set.
9. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
10. Read the 8-bit received data by reading the
RCREG register.
11. If an overrun error occurs, clear the error by
either clearing the CREN bit of the RCSTA
register o r by clearing the SPEN bit which res ets
the EUSART.
PIC18F2XK20/4XK20
DS40001303H-page 246 2010-2015 Microchip Technology Inc.
FIGURE 18-12: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
TABLE 18-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 56
PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 59
PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 59
IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 59
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 58
RCREG E USART Receive Register 58
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 58
BAUDCON ABDOVF RCIDL DTRXP CKTXP BRG16 —WUE ABDEN 58
SPBRGH EUSART Baud Rate Generator Register, High Byte 58
SPBRG EUSART Baud Rate Generator Register, Low Byte 58
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception.
Note 1: Reserved in 28-pin devices; always maintain these bits clear.
CREN bit
RX/DT
Write to
bit SREN
SREN bit
RCIF bit
(Interrupt)
Read
RXREG
‘0’
bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7
‘0’
Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
TX/CK pin
TX/CK pin
pin
(SCKP = 0)
(SCKP = 1)
2010-2015 Microchip Technology Inc. DS40001303H-page 247
PIC18F2XK20/4XK20
18.4.2 SYNCHRONOUS SLAVE MODE
The following bits are used to configure the EUSART
for Synchronous slave operation:
• SYNC = 1
• CSRC = 0
• SREN = 0 (for transmit); SREN = 1 (for receive)
• CREN = 0 (for transmit); CREN = 1 (for receive)
• SPEN = 1
Setting the SYNC bit of the TXSTA register configures the
device for synchronous operation. Clearing the CSRC bit
of the TX STA register conf igures the devi ce as a slave.
Clearing the SREN and CREN bits of the RCST A register
ensures that the device is in the Transmit mode,
otherwise the device will be configured to receive. Setting
the SPEN bit of the RCSTA register enables the
EUSART. If the RX/DT or TX/CK pins are shared with an
analog peripheral the analog I/O functions must be
disabled by clearing the corresponding ANSEL bits.
RX/DT and TX/CK pin output drivers must be disabled
by setting the corresponding TRIS bits.
18.4.2.1 EUSART Synchronous Slave
Transmit
The operation of the Synchronous Master and Slave
modes are identical (see Section 18.4.1.3
“Synchronous Master Transmission”), except in the
case of the Sleep mode.
If two words are written to the TXREG and then the
SLEEP instruction is executed, the following will occur:
1. The first character will immediately transfer to
the TSR register and transmit.
2. The seco nd word will rem ain in TXRE G registe r .
3. The TXIF bit will not be set.
4. After the first character has been shifted out of
TSR, the TXREG register will transfer the second
character to the TSR and the TXIF bit will now be
set.
5. If the PEIE and TXIE bits are set, the interrupt
will wa ke the dev ice from Sleep and e xecute the
next instruction. If the GIE bit is also set, the
program will call the Interrupt Service Routine.
18.4.2.2 Synchronous Slave Transmission
Set-up:
1. Set the SYNC and SPEN bits and clear the
CSRC bit.
2. Set the RX/DT and TX/CK TRIS controls to ‘1’.
3. Clear the CREN and SREN bits.
4. If using interrup ts, ensu re that the GIE and PEIE
bits of the INTCON register are set and set the
TXIE bit.
5. If 9-bit transmission is desired, set the TX9 bit.
6. Enable transmission by setting the TXEN bit.
7. If 9-bit transmission is selected, insert the Most
Significant bit into the TX9D bit.
8. Start transmission by writing the Least
Significant 8 bits to the TXREG register.
TABLE 18-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 56
PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 59
PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 59
IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 59
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 58
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 59
TXREG EUSART Transmit Regis ter 58
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 58
BAUDCON ABDOVF RCIDL DTRXP CKTXP BRG16 —WUE ABDEN 58
SPBRGH EUSART Baud Rate Generator Register, High Byte 58
SPBRG EUSART Baud Rate Generator Register, Low Byte 58
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission.
Note 1: Reserved in PIC18F2XK20 devices; always maintain these bits clear.
PIC18F2XK20/4XK20
DS40001303H-page 248 2010-2015 Microchip Technology Inc.
18.4.2.3 EUSART Synchronous Slave
Reception
The operation of the Synchronous Master and Slave
modes is identical (Section 18.4.1.6 “Synchronous
Master Reception” ), with the following exceptions:
• Sleep
• CREN bit is always set, therefore the receiver is
nev er Idle
• SR EN bit, which is a “don't care ” in Slave mode
A character may be received while in Sleep mode by
setting the CREN bit prior to entering Sleep. Once the
word is rec eived, th e RSR regist er will tran sfer the da ta
to the RCREG register . If the RCIE enable bit is set, the
interrupt generated will wake the device from Sleep
and execute the next instruction. If the GIE bit is also
set, the program will branch to the interrupt vector.
18.4.2.4 Synchronous Slave Reception
Set-up:
1. Set the SYNC and SPEN bits and clear the
CSRC bit.
2. Set the RX/DT and TX/CK TRIS controls to ‘1’.
3. If using interrup ts, ensu re that the GIE and PEIE
bits of the INTCON register are set and set the
RCIE bit.
4. If 9-bit reception is desired, set the RX9 bit.
5. Set the CREN bit to enable reception.
6. The RCIF bit will be set when reception is
complete. An interrupt will be generated if the
RCIE bit was set.
7. If 9-bit mode is enabled, retrieve the Most
Significant bit from the RX9D bit of the RCSTA
register.
8. Retrieve t he eig ht Leas t Sign ifican t bit s from the
receive FIFO by reading the RCREG register.
9. If an overrun error occurs, clear the error by
either clearing the CREN bit of the RCSTA
register o r by clearing the SPEN bit which res ets
the EUSART.
TABLE 18-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 56
PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 59
PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 59
IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 59
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 58
RCREG EUSART Receive Register 58
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 58
BAUDCON ABDOVF RCIDL DTRXP CKTXP BRG16 —WUE ABDEN 58
SPBRGH EUSART Baud Rate Generator Register, High Byte 58
SPBRG EUSART Baud Rate Generator Register, Low Byte 58
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception.
Note 1: Reserved in 28-pin devices; always maintain these bits clear.
2010-2015 Microchip Technology Inc. DS40001303H-page 249
PIC18F2XK20/4XK20
19.0 ANALOG-TO-DIGITAL
CONVERTER (ADC) MODULE
The Analog-to-Digital Converter (ADC) allows
conversion of an analog input signal to a 10-bit binary
representation of that signal. This device uses analog
inputs, which are multiplexed into a single sample and
hold circuit. The output of the sample and hold is
connected to the input of the converter. The converter
generates a 10-bit binary result via successive
approximation and stores the conversion result into the
ADC result registers (ADRESL and ADRESH).
The ADC voltage reference is software selectable to
either VDD or a v olt age appli ed to the external reference
pins.
The ADC can generate an interrupt upon completion of
a conversion. This interrupt ca n be used to wake-up the
device from Sleep.
Figure 19-1 shows the block diagram of the ADC.
FIGURE 19-1: ADC BLOCK DIAGRAM
AN0
ADC
AN1
AN2
AN4
AVDD
VREF+
ADON
GO/DONE
VCFG0 = 1
VCFG0 = 0
CHS<3:0>
ADRESH ADRESL
10
10
ADFM
VSS
AN5
AN6
AN7
AN3
AN8
AN9
AN10
AN11
AN12
AVSS
VREF-VCFG1 = 1
VCFG1 = 0
FVR
0000
0001
0010
0011
0100
0101
0111
0110
1000
1001
1010
1011
1100
1101
1110
1111
Unused
Unused
0 = Left Justify
1 = Right Justify
PIC18F2XK20/4XK20
DS40001303H-page 250 2010-2015 Microchip Technology Inc.
19.1 ADC Configuration
When configuring and using the ADC the following
functio ns must be consi dere d:
• Port configuration
• Channel selection
• ADC voltage reference selection
• ADC co nversion cl ock sou rce
• Interrupt control
• Results formatting
19.1.1 PORT CONFIGURATION
The ANSEL, ANSELH, TRISA, TRISB and TRISE reg-
isters all configure the A/D port pins. Any port pin
needed a s an an alog inpu t should ha ve its correspon d-
ing ANSx bit set to disable the digital input buffer and
TRISx bit set to disable the digital output driver. If the
TRISx bit is cleared, the digital output level (VOH or
VOL) will be conve rted .
The A/D operation is independent of the state of the
ANSx bits and the TRIS bits.
19.1.2 CHANNEL SELECTION
The CHS bits of the ADCON0 r egister det ermine whic h
channel is connected to the sample and hold circuit.
When changing channels, a delay is required before
starting the next conversion. Refer to Section 19.2
“ADC Operation” for more information.
19.1.3 ADC VOLTAGE REFERENCE
The VCFG bits of the ADCON1 register provide
independent control of the positive and negative
voltage references. The positive vol tage re ference can
be eit her VDD or an external voltage source. Likewise,
the negative voltage reference can be either VSS or an
external voltage source.
19.1.4 SELECTING AND CONFIGURING
ACQUISITIO N TIME
The ADCON2 register allows the user to select an
acquisition time that occurs each time the GO/DONE
bit is set.
Acquisition time is set with the ACQT<2:0> bits of the
ADCON2 register. Acquisition delays cover a range of
2 to 20 TAD. When the GO/DONE bit is set, the A/D
module continues to sample the input for the selected
acquisition time, then automatically begins a conver-
sion. Since the a cquisition ti me is pro grammed, th ere is
no need to wait for an acquisition time between select-
ing a channel and setting the GO/DONE bit.
Manual acquisition is selected when
ACQT<2:0> = 000. When the GO/DONE bit is set,
sampli ng is stoppe d and a conv ersion begins. The user
is responsible for ensuring the required acquisition time
has passed between selecting the desired input
channel and setting the GO/DONE bit. This option is
also the defaul t Res et st ate o f the AC QT<2:0> b it s and
is compatible with devices that do not offer
progra mmable acquisition times .
In either case, when the conversion is completed, the
GO/DONE bit is cleared, the ADIF flag is set and the
A/D begins sampling the currently selected channel
again. When an acquisition time is programmed, there
is n o indic ation of wh en th e acqu isit ion ti me en ds and
the conversion begins.
19.1.5 CONVERSION CLOCK
The source of the conversion clock is software select-
able via the ADCS bits of the ADCON2 register. There
are seven possible clock options:
•F
OSC/2
•F
OSC/4
•FOSC/8
•F
OSC/16
•F
OSC/32
•F
OSC/64
•FRC (dedicated internal oscillator)
The time to complete one bit conversion is defined as
TAD. One ful l 1 0-bit conversion requ ire s 11 TAD periods
as shown in Figure 19-3.
For correct conversi on, the appropriate TAD specification
must be met. See A/D conversion requirements in Table
for more information. Table 19-1 gives examples of
appropriate ADC clock selections.
Note 1: When reading the PO RT register, a ll pi ns
with their corresponding ANSx bit set
read as cleared (a low level). However,
analog conversion of pins configured as
digital inputs (ANSx bit cleared and
TRISx bit set) will be accurately
converted.
2: Analog levels on any pin with the
corresponding ANSx bit cleared may
cause the digital input buffer to consume
current out of the device’s specification
limits.
3: The PBADEN bit in Configuration
Register 3H configures PORTB pins to
reset as analog or digital pins by
controlling how the bits in ANSELH are
reset.
Note: Unless using the FRC, any changes in the
system clock frequency will change the
ADC clock frequency, which may
adversely affect the ADC result.
2010-2015 Microchip Technology Inc. DS40001303H-page 251
PIC18F2XK20/4XK20
19.1.6 INTERRUPTS
The ADC module allows for the ability to generate an
interrupt upon completion of an Analog-to-Digital
Conversion. The ADC interrupt flag is the ADIF bit in
the PIR1 register . The ADC interrupt enable is the ADIE
bit in the PIE1 register. The ADIF bit must be cleared by
software.
This interrupt can be generated while the device is
operatin g or while in Slee p. If the device is in Slee p, the
interrupt will wake-up the device. Upon waking from
Sleep, the next instruction following the SLEEP
instruction is always executed. If the user is attempting
to wake-up from Sleep and resume in-line code
execution, the global interrupt must be disabled. If the
global interrupt is enabled, execution will switch to the
Interrupt Service Routine. Please see Section 19.1.6
“Interrupts” for more information.
TABLE 19-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES
19.1.7 RES ULT FORMATTING
The 10-bit A/D conversion res ult can be supplied in two
formats, left justified or right justified. The ADFM bit of
the ADCON2 register controls the output format.
Figure 19-2 shows the two output formats.
FIGURE 19-2: 10-BIT A/D CONVERSION RESULT FORMAT
Note: The ADIF bit is set at the completion of
every conversion, regardless of whether
or not the ADC interrupt is enabled.
ADC Clock Period (TAD) Device Frequency (FOSC)
ADC Clock Source ADCS<2:0> 64 MHz 16 MHz 4 MHz 1 MHz
FOSC/2 000 31.25 ns(2) 125 ns(2) 500 ns(2) 2.0 s
FOSC/4 100 62.5 ns(2) 250 ns(2) 1.0 s4.0 s(3)
FOSC/8 001 400 ns(2) 500 ns(2) 2.0 s8.0 s(3)
FOSC/16 101 250 ns(2) 1.0 s4.0 s(3) 16.0 s(3)
FOSC/32 010 500 ns(2) 2.0 s8.0 s(3) 32.0 s(3)
FOSC/64 110 1.0 s4.0 s(3) 16.0 s(3) 64.0 s(3)
FRC x11 1-4 s(1,4) 1-4 s(1,4) 1-4 s(1,4) 1-4 s(1,4)
Legend: Shaded cells are outside of recommended range.
Note 1: The FRC source has a typical TAD time of 1.7 s.
2: These values violate the minimum required TAD time.
3: For faster conversion times, the selection of another clock source is recommended.
4: When the device frequency is greater than 1 MHz, the FRC clock source is only recommended if the
conversion will be perf ormed during Sleep.
ADRESH ADRESL
(ADFM = 0)MSB LSB
bit 7 bit 0 bit 7 bit 0
10-bit A/D Result Unimplemented: Read as ‘0’
(ADFM = 1)MSB LSB
bit 7 bit 0 bit 7 bit 0
Unimplemented: Read as ‘0’ 10-bit A/D Result
PIC18F2XK20/4XK20
DS40001303H-page 252 2010-2015 Microchip Technology Inc.
19.2 ADC Operation
19.2.1 STARTING A CONVERSION
To enable the ADC module, the ADON bit of the
ADCON0 register must be set to a ‘1’. Setting the GO/
DONE bit of the ADCON0 regis ter to a ‘1’ wil l, depend-
ing on the ACQT bits of the ADCON2 register, either
immediately start the Analog-to-Digital conversion or
start an acquisition delay followed by the Analog-to-
Digital conversion.
Figure 19-3 shows the operation of the A/D converter
after the GO bit has been set and the ACQT<2:0> bits
are cleared. A conversion is started after the following
instruction to allow entry into SLEEP mode before the
conversion begins.
Figure 19-4 shows the operation of the A/D converter
after the GO bit has been set and the ACQT<2:0> bits
are set to ‘010’ which se lec ts a 4 TAD acquisition time
before the conversion starts.
FIGURE 19-3: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0)
FIGURE 19-4: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD)
Note: The G O/DONE bit s hould not b e set in the
same instruction that turns on the ADC.
Refer to Section 19.2.9 “A/D Conver-
sion Procedure”.
TAD1TAD2TAD3TAD4 TAD5TAD6 TAD7TAD8 TAD11
Set GO bit
Holding capacitor is disconnected from analog input (typically 100 ns)
TAD9 TAD10
TCY - TAD
ADRESH:ADRESL is loaded, GO bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
Conve r si on starts
b0
b9 b6 b5 b4 b3 b2 b1
b8 b7
On the follow i ng cy cl e:
2 TAD
Discharge
123 4 5 67811
Set GO bit
(Holding capacitor is disconnected from analog input)
910
Conversion starts
123 4
(Holding capacitor continues
acquiring input)
TACQT Cycles TAD Cycles
Automatic
Acquisition
Time
b0b9 b6 b5 b4 b3 b2 b1
b8 b7
ADRESH:ADRESL is loaded, GO bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
On the following cycle:
2 TAD
Discharge
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PIC18F2XK20/4XK20
19.2.2 COMPLETION OF A CONVERSION
When the conversion is complete, the ADC m odule will:
• Clear the GO/DONE bit
• Set the ADIF flag bit
• Update the ADRESH: ADRESL regis ters with new
conversion result
19.2.3 DISCHARGE
The discharge phase is used to initialize the value of
the cap acitor array. The array is discharge d afte r every
sample. This feature helps to optimize the unity-gain
amplifier, as the circuit always needs to charge the
capacitor array, rather than charge/discharge based on
previous meas ure va lues.
19.2.4 TERMINATING A CONVERSION
If a conversion must be terminated before completion,
the GO/DONE bit can be cleared by software. The
ADRESH:ADRESL registers will not be updated with
the partially complete Analog-to-Digital conversion
sample. Instead, the ADRESH:ADRESL register pair
will retain the value of the previous conversion.
19.2.5 DELAY BETWEEN CONVERSIONS
After the A/D conversion is completed or aborted, a
2T
AD wait is required before the next acquisition can
be started. After this wait, the currently selected
channel is reconnected to the charge holding capacitor
comm encing the next acquisiti on.
19.2.6 ADC OPERATION IN POWER-
MANAGED MODES
The selection of the automatic acquisition time and A/D
conversion clock is determined in part by the clock
source and frequency while in a power-managed mode.
If the A/D is expected to operate while the device is in
a power-managed mode, the ACQT<2:0> and
ADCS<2:0> bits in ADCON2 should be updated in
accordance with the clock source to be used in that
mode. After entering the mode, an A/D acquisition or
conversion may be started. Once started, the device
should continue to be clocked by the same clock
sour ce unt il the con ve r si on has been co mpl ete d.
If desired, the device may be placed into the
corr espondi ng Idle m ode dur ing the convers ion. I f the
devi ce clock fre quency is l ess than 1 MHz, the A/ D FRC
clock source should be selected.
19.2.7 ADC OPERATION DURING SLEEP
The ADC module can operate during Sleep. This
requires the ADC clock source to be set to the FRC
option. When the FRC clock source is selected, the
ADC wa its on e addition al instru ction bef ore sta rting the
conversion. This allows the SLEEP instruction to be
executed, which can reduce system noise during the
conversion. If the ADC interrupt is enabled, the device
will wake-up from Sleep when the conversion
completes. If the ADC interrupt is disabled, the ADC
module is turned off after the conversion completes,
although the ADON bit remains set.
When the ADC clock source is something other than
FRC, a SLEEP instruction causes the present conver-
sion to be aborted and the ADC module is turned off,
although the ADON bit remains set.
19.2.8 SPECIAL EVENT TRIGGER
The CCP2 Special Event Trigger allows periodic ADC
measurements without software intervention. When
this trigger occurs, the GO/DONE bit is set by hardware
and the Timer1 or Timer3 counter resets to zero.
Using the S pecial Event T rigger does not assure proper
ADC timi ng. I t is the user’s resp onsib ility t o ensu re that
the ADC timing requirements are met.
See Sec tion 1 1. 3.4 “S pecial Event Trigger” fo r more
information.
Note: A devi ce Rese t forces all registers to th eir
Reset state. Thus, the ADC module is
turned off and any pending conversion is
terminated.
PIC18F2XK20/4XK20
DS40001303H-page 254 2010-2015 Microchip Technology Inc.
19.2.9 A/D CONVERSION PROCEDURE
This is an example procedure for using the ADC to
perform an Analog-to-Digit al conve rsion:
1. Configure Port:
• Disable pin output driver (See TRIS register)
• Configure pin as analog
2. Configure th e ADC module:
• Select ADC co nversion clock
• Configure voltage reference
• Select ADC input channel
• Select result format
• Select ac quisition delay
• Turn on ADC module
3. Configure ADC interrupt (optional):
• Clear ADC interrupt flag
• Enable ADC interrupt
• Enable peripheral interrupt
• Enable global interrupt(1)
4. Wait the required acquisition time(2).
5. Start conversion by setting the GO/DONE bit.
6. Wait for ADC co nvers ion to com ple te b y o ne o f
the following:
• Polling the GO/DONE bit
• Waiting for the ADC interrupt (interrupts
enabled)
7. Read ADC Result
8. Clear the ADC in terrupt flag (re quired if in terrupt
is enabled).
EXAMPLE 19-1: A/D CONVE RSION
Note 1: Th e global interrupt ca n be disabled if the
user is at tempti ng to wake -up from Sle ep
and resume in-line code execution.
2: Software delay required if ACQT bits are
set to z ero de lay. See Section 19.3 “A/D
Acquisition Re qui remen ts”.
;This code block configures the ADC
;for polling, Vdd and Vss as reference, Frc
clock and AN0 input.
;
;Conversion start & polling for completion
; are included.
;
MOVLW B’10101111’ ;right justify, Frc,
MOVWF ADCON2 ; & 12 TAD ACQ time
MOVLW B’00000000’ ;ADC ref = Vdd,Vss
MOVWF ADCON1 ;
BSF TRISA,0 ;Set RA0 to input
BSF ANSEL,0 ;Set RA0 to analog
MOVLW B’00000001’ ;AN0, ADC on
MOVWF ADCON0 ;
BSF ADCON0,GO ;Start conversion
ADCPoll:
BTFSC ADCON0,GO ;Is conversion done?
BRA ADCPoll ;No, test again
; Result is complete - store 2 MSbits in
; RESULTHI and 8 LSbits in RESULTLO
MOVFF ADRESH,RESULTHI
MOVFF ADRESL,RESULTLO
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19.2.10 ADC REGISTER DEFINITIONS
The following registers are used to control the opera-
tion of the ADC.
Note: Analog pin control is performed by the
ANSEL and ANSELH registers. For
ANSEL and ANSELH registers, see
Register 10-2 and Register 10-3,
respectively.
REGISTER 19-1: ADCON0: A/D CONTROL REGISTER 0
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—— CHS3 CHS2 CHS1 CHS0 GO/DONE ADON
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 Unimplemented: Read as ‘0’
bit 5-2 CHS<3:0>: Analog Channel Select bits
0000 = AN0
0001 = AN1
0010 = AN2
0011 = AN3
0100 = AN4
0101 = AN5(1)
0110 = AN6(1)
0111 = AN7(1)
1000 = AN8
1001 = AN9
1010 = AN10
1011 = AN11
1100 = AN12
1101 = Reserv ed
1110 = Reserv ed
1111 = FVR (1.2 Volt Fixed Voltage Reference)(2)
bit 1 GO/DONE: A/D Conversion Status bit
1 = A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle.
This bit is automatically cleared by hardware when the A/D conversion has completed.
0 = A/D conversion completed/not in progress
bit 0 ADON: ADC Enable bit
1 = ADC is enabled
0 = ADC is disabled and consumes no operating current
Note 1: These channels are not implemented on PIC18F2XK20 devices.
2: Allow greater than 15 s acquisition time when measuring the Fixed Voltage Reference.
PIC18F2XK20/4XK20
DS40001303H-page 256 2010-2015 Microchip Technology Inc.
REGISTER 19-2: ADCON1: A/D CONTROL REGISTER 1
U-0 U-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0
——VCFG1VCFG0— — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 Unimplemented: Read as ‘0’
bit 5 VCFG1: Negative Voltage Reference select bit
1 = Negative voltage reference supplied externally through VREF- pin.
0 = Negative voltage reference supplied internally by VSS.
bit 4 VCFG0: Positive Voltage Reference select bit
1 = Positive voltage reference supplied externally through VREF+ pin.
0 = Positive voltage reference supplied internally by VDD.
bit 3-0 Unimplemented: Read as ‘0’
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REGISTER 19-3: ADCON2: A/D CONTROL REGISTER 2
R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 ADFM: A/D Conversion Result Format Select bit
1 = Right justified
0 = Left justi fied
bit 6 Unimplemented: Read as ‘0’
bit 5-3 ACQT<2:0>: A/D Acquisition time select bits. Ac quisition time is th e duration that the A/D c harge ho ld-
ing cap ac itor remain s conn ected to A/D ch annel fro m the in st ant th e GO/D ONE b it is se t until c onver-
sions begi ns.
000 = 0(1)
001 = 2 TAD
010 = 4 TAD
011 = 6 TAD
100 = 8 TAD
101 = 12 TAD
110 = 16 TAD
111 = 20 TAD
bit 2-0 ADCS<2:0>: A/D Conversion Clock Select bits
000 = FOSC/2
001 = FOSC/8
010 = FOSC/32
011 = FRC(1) (clock derived from a dedicated internal oscillator = 600 kHz nominal)
100 = FOSC/4
101 = FOSC/16
110 = FOSC/64
111 = FRC(1) (clock derived from a dedicated internal oscillator = 600 kHz nominal)
Note 1: When t he A/D clock s ource is selected as FRC then the start of conversion is delayed by one instruction
cycle after the GO/DONE bit is set to allow the SLEEP instruction to be executed.
PIC18F2XK20/4XK20
DS40001303H-page 258 2010-2015 Microchip Technology Inc.
REGISTER 19-4: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
ADRES9 ADRES8 ADRES7 ADRES6 ADRES5 ADRES4 ADRES3 ADRES2
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 ADRES<9:2>: ADC Result Register bits
Upper eight bits of 10-bit conversion result
REGISTER 19-5: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 0
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
ADRES1 ADRES0 — — — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 ADRES<1:0>: ADC Result Register bits
Lower two bits of 10-bit conversion result
bit 5-0 Reserved: Do not use.
REGISTER 19-6: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
— — — — — — ADRES9 ADRES8
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-2 Reserved: Do not use.
bit 1-0 ADRES<9:8>: ADC Result Register bits
Upper two bits of 10-bit conversion result
REGISTER 19-7: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 1
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
ADRES7 ADRES6 ADRES5 ADRES4 ADRES3 ADRES2 ADRES1 ADRES0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 ADRES<7:0>: ADC Result Register bits
Lower eight bits of 10-bit conversion result
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PIC18F2XK20/4XK20
19.3 A/D Acquisition Requirements
For the A DC t o meet i ts specified accuracy, the charge
holding capacitor (CHOLD) must be allowed to fully
charge to the input channel voltage level. The Analog
Input model is shown in Figure 19-5. The source
impedance (RS) and the internal sampling switch (RSS)
impedance directly affect the time required to charge the
capacitor CHOLD. The sampling switch (RSS) impedance
varies over the device voltage (VDD), see Figure 19-5.
The maximum recommended impedance for analog
sources is 10 k. As the source impedance is
decreased, the acquisition time may be decreased.
After the analog input channel is selected (or changed),
an A/D acquisition must be done before the conversion
can be started. To calculate the minimum acquisition
time, Equation 19-1 may be used. This equation
assumes that 1/2 LSb error is used (1024 steps for the
ADC). The 1/2 LSb erro r is the maximum er ror allow ed
for the ADC to meet its specified resolution.
EQUATION 19-1: ACQUISITION TIME EXAMPLE
TACQ Amplifier Settling Time Hold Capacito r Charging Time Temperatu re Co efficient++=
TAMP TCTCOFF++=
5µs TCTemperature - 25°C0.05µs/°C++=
TCCHOLD RIC RSS RS++ ln (1/2047)–=
13.5pF 1k
700
10k
++– ln(0.000 4885)=
1.20
=µs
TACQ 5µs 1.20µs 50°C- 25°C0.05
s/°C++=
7.45µs=
VAPPLIED 1e
Tc–
RC
---------
–
VAPPLIED 11
2047
------------–
=
VAPPLIED 11
2047
------------–
VCHOLD=
VAPPLIED 1e
TC–
RC
----------
–
VCHOLD=
;[1] VCHOLD charged to within 1/2 lsb
;[2] VCHOLD charge response to VAPPLIED
;combining [1] and [2]
The value for TC can be appro ximated with the following equations:
Solving for TC:
Therefore:
Temperature 50°C and external impedance of 10k
3.0V VDD=
Assumptions:
Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out.
2: The charge holding capacitor (CHOLD) is discharged after each conversion.
3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin
leakage specification.
PIC18F2XK20/4XK20
DS40001303H-page 260 2010-2015 Microchip Technology Inc.
FIGURE 19-5: ANALOG INPUT MODEL
FIGURE 19-6: ADC TRANSFER FUNCTION
CPIN
VA
Rs ANx
5 pF
VDD
I LEAKAGE(1)
RIC 1k
Sampling
Switch
SS Rss
CHOLD = 13.5 pF
VSS/VREF-
2.5V
Rss (k)
2.0V
1.5V
.1 1 10
VDD
Legend: CPIN
I LEAKAGE
RIC
SS
CHOLD
= Input Capacitanc e
= Leakage current at the pin due to
= Interconnect Resistance
= Sampling Switch
= Sample/Hold Capacitance
various junctions
Discharge
Switch
3.0V
3.5V
100
Note 1: See Section 2 6.0 “Electri cal Specifications”.
3FFh
3FEh
ADC Output Code
3FDh
3FCh
004h
003h
002h
001h
000h
Full-Scale
3FBh
1/2 LSB ideal
VSS/VREF-Zero-Scale
Transition VDD/VREF+
Transition
1/2 LSB ideal
Full-Scale Range
Analog Input Voltage
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PIC18F2XK20/4XK20
TABLE 19-2: REGISTERS ASSOCIATED WITH A/D OPERATION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset
Values
on pag e
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 56
PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 59
PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 59
IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 59
PIR2 OSCFIF C1IF C2IF EEIF BCLIF HLVDIF TMR3IF CCP2IF 59
PIE2 OSCFIE C1IE C2IE EEIE BCLIE HLVDIE TMR3IE CCP2IE 59
IPR2 OSCFIP C1IP C2IP EEIP BCLIP HLVDIP TMR3IP CCP2IP 59
ADRESH A/D Result Register, High Byte 58
ADRESL A/D Result Register, Low Byte 58
ADCON0 —— CHS3 CHS2 CHS1 CHS0 GO/DONE ADON 58
ADCON1 ——VCFG1VCFG0— — — —58
ADCON2 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 58
ANSEL ANS7(1) ANS6(1) ANS5(1) ANS4 ANS3 ANS2 ANS1 ANS0 59
ANSELH — — — ANS12 ANS11 ANS10 ANS9 ANS8 59
PORTA RA7(2) RA6(2) RA5 RA4 RA3 RA2 RA1 RA0 59
TRISA TRISA7(2) TRISA6(2) PORTA Data Direction Control Register 59
PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 59
TRISB PORTB Data Direction Control Register 59
LATB PORTB Data Latch Register (Read and Write to Data Latch) 59
PORTE(4) — — — —RE3
(3) RE2 RE1 RE0 59
TRISE(4) IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 59
LATE(4) — — — — — PORTE Dat a Latch Register 59
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
Note 1: These bits are unimplemented on PIC18F2XK20 devices; always maintain these bits clear.
2: PORTA<7:6> and their direction bits are individually configured as port pins based on various primary
oscillator modes. When disabled, these bits read as ‘0’.
3: RE3 port bit is available only as an input pin when the MCLRE Configuration bit is ‘0’.
4: These registe r s are not implemente d on PIC18 F2XK20 devic es.
PIC18F2XK20/4XK20
DS40001303H-page 262 2010-2015 Microchip Technology Inc.
20.0 COMPARATOR MODULE
Comparators are used to interface analog circuits to a
digital circuit by comparing two analog voltages and
providing a digital indication of their relative magnitudes.
The comparators are very useful mixed signal building
blocks because they provide analog functionality
independent of the program execution. The analog
comparator module includes the following features:
• Independent comparator control
• Programmable input selection
• Comparator ou tput is avai lable internall y/externally
• Programmable output polarity
• Interrupt-on-change
• Wake-up from Sleep
• Programmable Speed/Power optimization
•PWM shutdown
• Programmable and Fixed Voltage Reference
20.1 Comp arator Overview
A singl e com pa rato r is shown i n Figure 20-1 along with
the relationship between the analog input levels and
the digital output. When the analog voltage at VIN+ is
less than the analog voltage at VIN-, the output of the
comparator is a digital low level. When the analog
voltage at VIN+ is greater than the analog voltage at
VIN-, the outp ut of the comp arat or is a digit al high le vel.
FIGURE 20-1: SINGLE COMPARATOR
–
+
VIN+
VIN-Output
Output
VIN+
VIN-
Note: The black areas of the output of the
comparator represents the uncertainty
due to input offsets and response time.
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FIGURE 20-2: COMPARATOR C1 SIMPLIFIED BLOCK DIAGRAM
FIGURE 20-3: COMPARATOR C2 SIMPLIFIED BLOCK DIAGRAM
Note 1: When C1ON = 0, the C1 comparator will produce a ‘0’ output to the XOR Gate .
2: Output shown for reference only. See I/O port pin block diagram for more detail.
3: Q1 and Q3 are phases of the four-phase system clock (FOSC).
4: Q1 is held high during Sleep mode.
MUX
C1
C1POL
C1OUT
To PWM Logic
0
1
2
3
C1ON(1)
C1CH<1:0> 2
0
1
C1R C1OE
MUX
RD_CM1CON0
Set C 1IF
To
C1VIN-
C1VIN+
C12IN0-
C12IN1-
C12IN2-
C12IN3-
C1IN+
DQ
EN
Q1 Data Bus
DQ
EN
CL
Q3*RD_CM1CON0
Reset
C1OUT pin(2)
+
-
0
1
MUX
FVR
C1RSEL
CVREF
C1SP
C1VREF
MUX C2
C2POL
C2OUT
To PWM Logic
0
1
2
3
C2ON(1)
C2CH<1:0> 2
C2OE
DQ
EN
DQ
EN
CL
RD_CM2CON0
Q3*RD_CM2CON0
Q1
Set C2IF
To
NRESET
C2VIN-
C2VIN+C2OUT pin(2)
C12IN0-
C12IN1-
C12IN2-
C12IN3-
Data Bus
Note 1: When C2ON = 0, the C2 comparator will produce a ‘0’ output to the XOR Gate.
2: Output shown for reference only . See I/O port pin block diagram for more detail.
3: Q1 and Q3 are phases of the four-phase system clock (FOSC).
4: Q1 is held high during Sleep mode.
0
1
C2R
MUX
C2IN+
0
1
MUX
FVR
C2RSEL
CVREF
C2SP
C2VREF
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DS40001303H-page 264 2010-2015 Microchip Technology Inc.
20.2 Comparator Control
Each comparator has a separate control and Configu-
ration register: CM1CON0 for Comparator C1 and
CM2CON0 for Comparator C2. In addition, Comp arator
C2 has a second control register, CM2CON1, for con-
trolling the interaction with Timer1 and simultaneous
reading of both comparator outputs.
The CM1CON0 and CM2CON0 registers (see Regis-
ters 20-1 and 20-2, respectively) contain the control
and Status bits for the following:
• Enable
• Input selection
• Reference selection
•Output selection
• Output pol arit y
• Speed selection
20.2.1 COMPARATOR ENABLE
Setting the CxON bit of the CMxCON0 register enables
the comparator for operation. Clearing the CxON bit
disables the comparator resulting in minimum current
consumption.
20.2.2 COMPARATOR INPUT SELECTION
The CxCH<1:0> bits of the CMxCON0 register direct
one of four analog input pins to the comparator
inverting input.
20.2.3 COMPARATOR REFERENCE
SELECTION
Setting the CxR bit of the CMxCON0 register directs an
internal voltage reference or an analog input pin to the
non-inverting input of the comparator. See
Section 21.0 “VOLTAGE REFERENCES” for more
information on the Internal Voltage Re ference modu le.
20.2.4 COMPARATOR OUTPUT
SELECTION
The output of the comparator can be monitored by
reading either the CxOUT bit of the CMxCON0 register
or the MCxOUT bit of the CM2CON1 register. In order
to make the outpu t available for an external connection,
the following conditions must be true:
• CxOE bit of the CMxCON0 register must be set
• Corresponding TRIS bit must be cleared
• CxON bit of the CMxCON0 register must be set
20.2.5 COMPARATOR OUTPUT POLARITY
Inverting the output of the comparator is functionally
equivalent to swapping the comparator inputs. The
polarity of the comparator output can be inverted by
setting the CxPOL bit of the CMxCON0 register.
Clearing the CxPOL bit results in a no n-inverted output.
Table 20-1 shows the output state versus input
conditions, including polarity control.
20.2.6 COMPARATOR SPEED SELECTION
The trade-off between speed or power can be opti-
mized d uri ng p rog ram ex ec utio n wi th th e C x SP co ntro l
bit. The default state for this bit is ‘1’ which se le c ts the
normal speed mode. Device power consumption can
be opt imized at the cos t of slower co mparator pro paga-
tion delay by clearing the CxSP bit to ‘0’.
20.3 Comparator Response Time
The comparator output is indeterminate for a period of
time after the change of an input source or the selection
of a new refe rence volta ge. This period is refer red to as
the response time. The response time of the
comparator differs from the settling time of the voltage
reference. Therefore, both of these times must be
considered when determining the total response time
to a comparator input change. See the Comparator and
Voltage Reference Specifications in Section 26.0
“Electrical Specifications” for more details.
Note: To use Cx IN+ and C1 2INx- pins a s analog
inputs, the appropriate bits must be set in
the ANSEL register and the
corresponding TRIS bits must also be set
to disable the output drivers.
Note 1: The CxOE bit overrides the PORT data
latch. Se tting the C xON has n o impa ct on
the port override.
2: The internal output of the comparator is
latched with each instruction cycle.
Unless otherwise specified, external
outputs are not latched.
TABLE 20-1: COMPARATOR OUTPUT
STATE VS. INPUT
CONDITIONS
Input Condition CxPOL CxOUT
CxVIN- > CxVIN+00
CxVIN- < CxVIN+01
CxVIN- > CxVIN+11
CxVIN- < CxVIN+10
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20.4 Comparator Interrupt Operation
The comparator interrupt flag can be set whenever
there is a chang e in the o utput val ue of the compa rator.
Changes are recognized by means of a mismatch
circuit which consists of two latches and an exclusive-
or gat e (see Figure 20-2 and Figure 20-3). One latch i s
updated with the comparator output level when the
CMxCO N0 regi ster is read. This la tc h re tains the valu e
until the next read of the CMxCON0 register or the
occurre nce of a Reset. Th e other latch of the mism atch
circuit is updated on every Q1 system clock. A
mismatch condition will occur when a comparator
output change is clocked through the second latch on
the Q1 clock cycle. At this point the two mismatch
latches have opposite output levels which is detected
by the exclusive-or gate and fed to the interrupt
circuitry. The mismatch condition persists until either
the CMxCON0 register is read or the comparator
output returns to the previous state.
The comparator interrupt is set by the mismatch edge
and not the mismatch level. This means that the inter-
rupt flag can be reset without the additional step of
reading or writing the CMxCON0 register to clear the
mismatch registers. When the mismatch registers are
cleared, an interrupt will occur upon the comparator ’s
return to the previous state, otherwise no interrupt will
be generated.
Software will need to maintain information about the
status of the comparator output, as read from the
CMxCON0 register, or CM2CON1 register , to determine
the actual change that has occurred. See Figures 20-4
and 20-5.
The CxIF bit of the PIR2 register is the comparator
interrupt flag. This bit must be reset by software by
clearing it to ‘0’. Since i t i s also po ssib le t o writ e a ‘1’ to
this register, an interrupt can be generated.
In mid-range Compatibility mode the CxIE bit of the
PIE2 register and the PEIE and GIE bits of the INTCON
register must al l be set to enable com parator in terrupts.
If any of these bits are cleared, the interrupt is not
enabled, although the CxIF bit of the PIR2 register will
still be set if an interrupt condition occurs.
20.4.1 PRESETTING THE MISMATCH
LATCHES
The comparator mismatch latches can be preset to the
desired state before the comparators are enabled.
When the comparator is off the CxPOL bit controls the
CxOUT level. Set the C xPOL bit to the desi red CxOU T
non-inte rrupt lev el w hile th e CxON bi t is clea red. The n,
configu re the de sired CxPO L leve l in the same ins truc-
tion that t he CxON bit is se t. Since all register writes are
performed as a Read-Modify-Write, the mismatch
latches will be cleared during the instruction Read
phase and the actual configuration of the CxON and
CxPOL bits will be occur in the final Write phase.
FIGURE 20-4: COMPARATOR
INTERRUPT TIMING W/O
CMxCON0 READ
FIGURE 20-5: COMPARATOR
INTERRUPT TIMING WITH
CMxCON0 READ
Note 1: A write operation to the CMxCON0
register will also clear the mismatch
condition because all writes include a read
operation at the beginning of the write
cycle.
2: Comparator interrupts will operate
correctly regardless of the state of CxOE.
Note 1: If a change in the CMxCON0 register
(CxOUT) sho uld occur when a re ad oper-
ation is being executed (start of the Q2
cycle), then the CxIF interrupt flag of the
PIR2 register may not get set.
2: When either comparator is first enabled,
bias circuitry in the comparator module
may cause an invalid output from the
comparator until the bias circuitry is
stable. Allow about 1 s for bias settling
then clear the mismatch condition and
interrupt flags before enabling comparator
interrupts.
Q1
Q3
CxIN+
CxOUT
Set CxIF (edge)
CxIF
TRT
reset by software
Q1
Q3
CxIN+
CxOUT
Set CxIF (edge)
CxIF
TRT
reset by software
cleared by CMxCON0 read
PIC18F2XK20/4XK20
DS40001303H-page 266 2010-2015 Microchip Technology Inc.
20.5 Operation During Sleep
The compa rator , if enabled b efore entering Sleep mode,
remains active during Sleep. The additional current
consumed by the comp arator is show n separately in the
Section 26.0 “Electrical Specifications”. If the
comparator is not used to wake the device, power
consumption can be minimized while in Sleep mode by
turning off the comp arator. Each comparator is turned off
by clearing the CxON bit of the CMxCON0 register.
A change to the comparator output can wake-up the
device from Sleep. To enable the comparator to wake
the devic e from Sle ep, the CxIE bit of the PIE2 reg ister
and the PEIE bit of the INTCON register must be set.
The instruction following the SLEEP instru ction always
executes following a wake from Sleep. If the GIE bit of
the INTCON register is also set, the device will then
execute the Interrupt Service Routine.
20.6 Effects of a Reset
A device Reset forces the CMxCON0 and CM2CON1
registers to their Reset states. This forces both
comparators and the voltage references to their Off
states.
2010-2015 Microchip Technology Inc. DS40001303H-page 267
PIC18F2XK20/4XK20
REGISTER 20-1: CM1CON0: COMPARATOR 1 CONTROL REGISTER 0
R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
C1ON C1OUT C1OE C1POL C1SP C1R C1CH1 C1CH0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 C1ON: Comparator C1 Enable bit
1 = Compar ator C1 is enabled
0 = Comparator C1 is disabled
bit 6 C1OUT: Comparator C1 Output bit
If C1POL = 1 (inverted polarity):
C1OUT = 0 when C1VIN+ > C1VIN-
C1OUT = 1 when C1VIN+ < C1VIN-
If C1POL = 0 (non-inverted polarity):
C1OUT = 1 when C1VIN+ > C1VIN-
C1OUT = 0 when C1VIN+ < C1VIN-
bit 5 C1OE: Comparator C1 Output Enable bit
1 = C1OUT is present on the C1OUT pin(1)
0 = C1OUT is internal only
bit 4 C1POL: Comparator C1 Output Polarity Select bit
1 = C1OUT logic is inverted
0 = C1OUT logic is not inverted
bit 3 C1SP: Comparator C1 Speed/Power Select bit
1 = C1 operates in Normal Power, higher speed mode
0 = C1 operates in Low-Power, Low-Speed mode
bit 2 C1R: Comparator C1 Reference Select bit (non-inverting input)
1 = C1VIN+ connects to C1VREF output
0 = C1VIN+ connects to C1IN+ pin
bit 1-0 C1CH<1:0>: Comparator C1 Channel Select bit
00 = C12IN0- pin of C1 connects to C1VIN-
01 = C12IN1- pi n of C 1 connects to C1VIN-
10 = C12IN2- pin of C1 connects to C1VIN-
11 = C12IN3- pin of C1 connects to C1VIN-
Note 1: Comparator output requires the following three conditions: C1OE = 1, C1ON = 1 and corresponding port
TRIS bit = 0.
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DS40001303H-page 268 2010-2015 Microchip Technology Inc.
REGISTER 20-2: CM2CON0: COMPARATOR 2 CONTROL REGISTER 0
R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
C2ON C2OUT C2OE C2POL C2SP C2R C2CH1 C2CH0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 C2ON: Comparator C2 Enable bit
1 = Comparator C2 is enabled
0 = Comparator C2 is disabled
bit 6 C2OUT: Comparator C2 Output bit
If C2POL = 1 (inverted polarity):
C2OUT = 0 when C2VIN+ > C2VIN-
C2OUT = 1 when C2VIN+ < C2VIN-
If C2POL = 0 (non-inverted polarity):
C2OUT = 1 when C2VIN+ > C2VIN-
C2OUT = 0 when C2VIN+ < C2VIN-
bit 5 C2OE: Comparator C2 Output Enable bit
1 = C2OUT is present on C2OUT pin(1)
0 = C2OUT is internal only
bit 4 C2POL: Comparator C2 Output Polarity Select bit
1 = C2OUT logic is inverted
0 = C2OUT logic is not inverted
bit 3 C2SP: Comparator C2 Speed/Power Select bit
1 = C2 operates in Normal Power, higher speed mode
0 = C2 operates in Low-Power, Low-Speed mode
bit 2 C2R: Comparator C2 Reference Select bits (non-inverting input)
1 = C2VIN+ connects to C2VREF
0 = C2VIN+ connects to C2IN+ pin
bit 1-0 C2CH<1:0>: Comparator C2 Channel Select bits
00 = C12IN0- pin of C2 connects to C2VIN-
01 = C12IN1- pin of C2 connects to C2VIN-
10 = C12IN2- pin of C2 connects to C2VIN-
11 = C12IN3- pin of C2 connects to C2VIN-
Note 1: Comparator output requires the following three conditions: C2OE = 1, C2ON = 1 and corresponding port
TRIS bit = 0.
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PIC18F2XK20/4XK20
20.7 Analog Input Connection
Considerations
A simplified circuit for an analog input is shown in
Figure 20-6. Since the analog input pins share their
connection with a digital input, they have reverse
biased ESD protection diodes to VDD and VSS. The
analog in put, therefore, must be between VSS and VDD.
If the input voltage deviates from this range by more
than 0.6V in either direction, one of the diodes is
forward bias ed and a latch-up may occur.
A maximum source impedance of 10 k is recommended
for the analog sources. Also, any external component
connected to an anal og inpu t pin, such as a capacitor or
a Zener diode, should h ave very little leakage curr ent to
minimize inaccuracies introduced.
FIGURE 20-6: ANALOG INPUT MODEL
Note 1: When reading a PORT register, all pins
configu red as analog in puts w ill read as a
‘0’. Pins configured as digital inputs will
convert as an analog input, according to
the input specification.
2: Analog levels on any pin defined as a
digit al input, may cause th e input buffer to
consume more current than is specified.
VA
Rs < 10K
CPIN
5 pF
VDD
RIC
ILEAKAGE(1)
Vss
AIN
Legend: CPIN = Input Capacitance
ILEAKAGE = Leakage Current at the pin due to various junctions
RIC = Interconnect Re sistance
RS= Source I mpedance
VA= Analog Voltage
Note 1: See Section 26.0 “Electrical Spec ifications”.
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DS40001303H-page 270 2010-2015 Microchip Technology Inc.
20.8 Additional Comparator Features
There are two additional co mparator features:
• Simultaneous read of comparator outputs
• Internal refe renc e sel ec tio n
20.8.1 SIMULTANEOUS COMPARATOR
OUTPUT READ
The MC1OUT and MC2OUT bits of the CM2CON1
register are mirror copies of both comparator outputs.
The ability to read both outputs simultaneously from a
single register eliminates the timing skew of reading
separate register s.
20.8.2 INTERNAL REFERENCE
SELECTION
There are two internal voltage references available to
the non-inverting input of each comparator. One of
these is the 1.2V Fixed Voltage Reference (FVR) and
the othe r is the va riable Com parator V o ltage Reference
(CVREF). The CxRSEL bit of the CM2CON register
determines which of these references is routed to the
Comparator Voltage reference output (CXVREF).
Further routing to the comparator is accomplished by
the CxR bit of the CMxCON0 register. See
Section 21.1 “Comparator Voltage Reference” and
Figure 20-2 and Figure 20-3 for more detail.
Note 1: Obtaining the status of C1OUT or
C2OUT by reading CM2CON1 does not
affect the comparator interrupt mismatch
registers.
REGISTER 20-3: CM2CON1: COMPARATOR 2 CONTROL REGISTER 1
R-0 R-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0
MC1OUT MC2OUT C1RSEL C2RSEL — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 MC1OUT: Mirror Copy of C1OUT bit
bit 6 MC2OUT: Mirror Copy of C2OUT bit
bit 5 C1RSEL: Comparator C 1 Reference Sel ect bit
1 = CVREF routed to C1VREF input
0 = FVR (1.2 Volt Fixed Voltage Reference) routed to C1VREF input
bit 4 C2RSEL: Comparator C 2 Reference Sel ect bit
1 = CVREF routed to C2VREF input
0 = FVR (1.2 Volt Fixed Voltage Reference) routed to C2VREF input
bit 3-0 Unimplemented: Read as ‘0’
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PIC18F2XK20/4XK20
TABLE 20-2: REGISTERS ASSOCIATED WITH COMPARATOR MODULE
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset
Values
on page
CM1CON0 C1ON C1OUT C1OE C1POL C1SP C1R C1CH1 C1CH0 59
CM2CON0 C2ON C2OUT C2OE C2POL C2SP C2R C2CH1 C2CH0 59
CM2CON1 MC1OUT MC2OUT C1RSEL C2RSEL — — — —60
CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 58
CVRCON2 FVREN FVRST ——————58
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 56
PIR2 OSCFIF C1IF C2IF EEIF BCLIF HLVDIF TMR3IF CCP2IF 59
PIE2 OSCFIE C1IE C2IE EEIE BCLIE HLVDIE TMR3IE CCP2IE 59
IPR2 OSCFIP C1IP C2IP EEIP BCLIP HLVDIP TMR3IP CCP2IP 59
PORTA RA7(1) RA6(1) RA5 RA4 RA3 RA2 RA1 RA0 59
LATA LATA7(1) LATA6(1) PORTA Data Latch Register (Read and Write to Data Latch) 59
TRISA TRISA7(1) TRISA6(1) PORTA Data Direction Control Register 59
Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the comparator module.
Note 1: PORTA<7:6> and their direction and latch bits are individually configured as port pins based on various
primary oscillator modes. When disabled, these bits read as ‘0’.
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DS40001303H-page 272 2010-2015 Microchip Technology Inc.
21.0 VO LTAGE REFERENCES
There are two independent voltage references
available:
• Programmable Comparator Voltage Reference
• 1.2V Fixed Voltage Reference
21.1 Comparator Voltage Reference
The Comparator Voltage Reference module provides
an internally generated voltage reference for the com-
parators. The following features are available:
• Independent from Comparator operation
• Two 16-level voltage ranges
• Output clamped to VSS
• Ratiometric with VDD
• 1.2 Fixed Reference Voltage (FVR)
The CVRCON register (Register 21-1) controls the
Voltage Reference module shown in Figure 21-1.
21.1.1 INDEPENDENT OPERATION
The comparator voltage reference is independent of
the comp ara tor configur ation. Settin g the CVREN bi t of
the CVR CON reg ister w ill e nable the vo lta ge refer ence
by allowing current to flow in the CVREF voltage d ivider.
When both th e CVREN bit is cleared, current flow in the
CVREF volt age div ider is disabled m inimizi ng the po wer
drain of the voltage reference peripheral.
21.1.2 OUTPUT VOLTAGE SELECTION
The CVREF voltage reference has two ranges with 16
voltage levels in each range. Range selection is
controlled by the CVRR bit of the CVRCON register.
The 16 levels are set with the CVR<3:0> bits of the
CVRCON register.
The CVREF output voltage is determined by the following
equations:
EQUATION 21-1: CVREF OUTPUT VOLTAGE
The full range of VSS to VDD cannot be realized due to
the construction of the module. See Figure 21-1.
21.1.3 OUTPUT CLAMPED TO VSS
The CVREF output voltage can be set to Vss with no
power consumption by configuring CVRCON as
follows:
• CVREN = 0
•CVRR=1
•CVR<3:0>=0000
This allows the comparator to detect a zero-crossing
while not consuming additional CVREF module current.
21.1.4 OUTPUT RATIOMETRIC TO VDD
The comparator voltage reference is VDD derived and
therefore, the CVREF output changes with fluctuations in
VDD. The tested absolute accuracy of the Comparator
Voltage Reference can be found in Section 26.0
“Electr ical Specifications”.
21.1.5 VOLTAGE REFERENCE OUTPUT
The CVREF voltage reference can be output to the
device CVREF pin by setting the CVROE bit of the
CVRCON register to ‘1’. Selecting the reference volt-
age for o utput on the CV REF pin automati cally overrides
the digital output buffer and digital input threshold
detector functions of that pin. Reading the CVREF pin
when it has been configured for reference voltage out-
put will always return a ‘0’.
Due to the limited curren t drive cap abilit y, a buf fer must
be used on the voltage reference output for external
connections to CVREF. Figure 21-2 shows an example
buffering technique.
21.1.6 OPE RATI ON DURING SLEEP
When the device wakes up from Sleep through an
interrupt o r a W a tchdo g T imer tim e-out, the conte nts of
the CVRCON register are not affected. To minimize
current consumption in Sleep mode, the voltage
reference should be disabled.
21.1.7 EFFECTS OF A RESET
A device Reset af fec t s the follow ing:
• Comparator voltage r eference is disabl ed
• Fixed Voltage Reference is disabled
•CV
REF is removed from the CVREF pin
• The high-voltage range is selected
• The CVR<3:0> range select bits are cleared
CVRR 1 (low range):=
CVRR 0 (high range):=
CVREF = (CVRSRC/24) X CVR<3:0> + VREF-
CVRSRC VDD=or [(VREF+) - (VREF-)]
CVREF = (CVRSRC/32) X (8 + CVR<3:0>) + VREF-
Note: VREF- is 0 when CVRSS = 0
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PIC18F2XK20/4XK20
21.2 FVR Reference Module
The FVR reference is a stable Fixed Voltage
Reference, independent of VDD, with a nominal output
voltage of 1.2V. This reference can be enabled by
setting the FVREN bit of the CVRCON2 register to ‘1’.
The FVR defaults to on when any one or more of the
HFINTOSC, HLVD, BOR or ADC input channel
selection functions are enabled. The FVR voltage
reference can be routed to the com pa rator s or an ADC
input channel.
21.2.1 FVR STABILIZATION PERIOD
When the Fixed Voltage Reference module is enabled, it
will r equire some time for t he r eferenc e and its amplif ier
circuits to stabilize. The user program must include a
small delay routine to allow the module to settle. The
FVRST stable bit of the CVRCON2 register also indicates
that the FV R ref eren c e has been op er ati ng lo ng en ough
to be stable. See Section 26.0 “Electrical
Specifications” for the minimum delay requirement.
FIGURE 21-1: VOLTAGE REFERENCE BLOCK DIAGRAM
16-to-1 MUX
CVR<3:0>
8R
R
CVREN
CVRSS = 0
VDD
VREF+CVRSS = 1
8R
CVRSS = 0
VREF-CVRSS = 1
R
R
R
R
R
R
16 Steps
CVRR
CVREF
1.2 Volt Fixed
Reference
EN FVRST
FVR
FVREN
From HVLD, BOR circuits
and ADC channel selection
(CHS<3:0> = 1111)
PIC18F2XK20/4XK20
DS40001303H-page 274 2010-2015 Microchip Technology Inc.
FIGURE 21-2: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE
REGISTER 21-1: CVRCON: COMPARATOR VO LTAGE REFERENCE CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CVREN CVROE(1) CVRR CVRSS CVR3 CVR2 CVR1 CVR0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 CVREN: Comparator Voltage Reference Enable bit
1 =CV
REF circuit powered on
0 =CV
REF circuit powered down
bit 6 CVROE: Comparator VREF Output Enable bit(1)
1 =CVREF voltage level is also output on the CVREF pin
0 =CV
REF voltage is disconnected from the CVREF pin
bit 5 CVRR: Comparator VREF Range Selection bit
1 = 0 to 0.667 CVRSRC, with CVRSRC/24 step size (low range)
0 =0.25 CV
RSRC to 0.75 CVRSRC, with CVRSRC/32 step size (high range)
bit 4 CVRSS: Comparator VREF Source Selection bit
1 = Comparator reference source, CVRSRC = (VREF+) – (VREF-)
0 = Comparator reference source, CVRSRC = VDD – VSS
bit 3-0 CVR<3:0>: Comparator VREF Value Selection bits (0 (CVR<3:0>) 15)
When CVRR = 1:
CVREF = ((CVR<3:0>)/24) (CVRSRC) + VREF-
When CVRR = 0:
CVREF = (C VRSRC/4) + ((CVR<3:0>)/32) (CVRSRC) + VREF-
Note 1: CVROE overrides the TRISA<2> bit setting.
Buffered C VREF Outp u t
+
–
CVREF
Module
Voltage
Reference
Output
Impedance
R(1)
CVREF
Note 1: R is dependent upon the voltage ref erence Configuration bits, CVR<3:0> and CVRR.
PIC18F2XK20/4XK20
2010-2015 Microchip Technology Inc. DS40001303H-page 275
PIC18F2XK20/4XK20
TABLE 21-1: REGISTERS ASSOCIATED WITH COMPARATOR VOLTAGE REFERENCE
REGISTER 21-2: CVRCON2: COMPARATOR VOLTAGE REFERENCE CONTROL 2 REGISTER
R/W-0 R-0 U-0 U-0 U-0 U-0 U-0 U-0
FVREN FVRST — — — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 FVREN: Fixed Voltage Reference Enable bit
1 = FVR circuit powered on
0 = FVR circuit not enabled by FVREN. Other peripherals may enable FVR.
bit 6 FVRST: Fixed Voltage Stable Status bit
1 = FVR is stable and can be used.
0 = FVR is not stable and should not be used.
bit 5-0 Unimplemented: Read as ‘0’.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset
Values
on page
CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 59
CVRCON2 FVREN FVRST ——————58
CM1CON0 C1ON C1OUT C1OE C1POL C1SP C1R C1CH1 C1CH0 59
CM2CON0 C2ON C2OUT C2OE C2POL C2SP C2R C2CH1 C2CH0 59
CM2CON1 MC1OUT MC2OUT C1RSEL C2RSEL ————60
TRISA TRISA7(1) TRISA6(1) PORTA Data Direction Control Register 59
Legend: Shaded cells are not used with the comparator voltage reference.
Note 1: PORTA pins are enabled based on oscillator configuration.
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22.0 HIGH/LOW-VOLTAGE
DETECT (HLVD)
PIC18F2XK20/4XK20 devices have a High/Low-V oltage
Detect module (HLVD). This is a programmable circuit
that allows the user to specify both a device voltage trip
point and the direction of change from that point. If the
device experiences an excursion past the trip point in
that direction, an interrupt flag is set. If the interrupt is
enabled, the program execution will branch to the inter-
rupt vector address and the software can then respond
to the interrupt.
The High/Low-Voltage Detect Control register
(Register 22-1) complete ly controls the operation of the
HLVD module. This allows the circuitry to be “turned
off” by the user under software control, which
minimizes the current consumption for the device.
The block diagram for the HLVD module is shown in
Figure 22-1.
The module is enabled by setting the HLVDEN bit.
Each time that the HLVD module is enabled, the cir-
cuitry requires some time to stabilize. The IRVST bit is
a read-only bit and is used to indicate when the circuit
is stable. The module can only generate an interrupt
after the circuit is stable and IRVST is set.
The VDIRMAG bit determines the overall operation of
the module. When VDIRMAG is cleared, the module
monitors for drops in VDD below a predetermined set
point. Wh en the bit is set, the mo dule moni tors for rise s
in VDD above the set point.
REGISTER 22-1: HLVDCON: HIGH/LOW-VOLTAGE DETECT CONTROL REGISTER
R/W-0 U-0 R-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-1
VDIRMAG — IRVST HLVDEN HLVDL3(1) HLVDL2(1) HLVDL1(1) HLVDL0(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented C = Clearable only bit
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 VDIRMAG: Voltage Direction Magnitude Select bit
1 = Event occurs when voltage equals or exceeds trip point (HLVDL<3:0>)
0 = Event occurs when voltage equals or falls below trip point (HLVDL<3:0>)
bit 6 Unimplemented: Read as ‘0’
bit 5 IRVST: Internal Reference Voltage Stable Flag bit
1 = Indicates that the vol tage detec t logic w ill generate t he interrupt fl ag at the spe cified volt age range
0 = Indicates that the voltage detect logic will not generate the interrupt flag at the specified voltage
range and the HLVD interrupt should not be enabled
bit 4 HLVDEN: High/Low-Voltage Detect Power Enable bit
1 = HLVD enabled
0 = HLVD dis abl ed
bit 3-0 HLVDL<3:0>: Voltage Detection Limit bits(1)
1111 = External analog input is used (input comes from the HLVD IN pin)
1110 = Maximum setting
.
.
.
0000 = Minimum setting
Note 1: See Table 26-4 for specific ati ons .
2010-2015 Microchip Technology Inc. DS40001303H-page 277
PIC18F2XK20/4XK20
22.1 Operation
When the HLVD module is enab led, a co mparat or uses
an internally generated reference voltage as the set
point. The set point is compared with the trip point,
where each node in the resistor divider represents a
trip point voltage. The “trip point” voltage is the voltage
level at which the device detects a high or low-voltage
event, depending on the configuration of the module.
When the supply voltage is equal to the trip point, the
voltage tapped off of the resistor array is equal to the
internal reference voltage generated by the voltage
reference module. The comparator then generates an
interrupt signal by setting the HLVDIF bit.
The trip poi nt voltage is software programma ble to an y
one of 16 values. The trip point is selected by
programming the HLVDL<3:0> bits of the HLVDCON
register.
The HLVD mo dule has a n additio nal f eature tha t allow s
the user to supply the trip voltage to the module from a n
external source. This mode is enabled when bits
HLVDL<3:0> are set to ‘1111’. In this state, the
comparator input is multiplexed from the external input
pin, HLVDIN. This gives users flexibility because it
allows them to configure the High/Low-Voltage Detect
interrupt to occur at any voltage in the valid operating
range.
FIGURE 22-1: HLVD MODULE BLOC K DIAGRAM (WITH EXTERNA L INPUT)
Set
VDD
16-to-1 MUX
HLVDEN
HLVDCON
HLVDIN
HLVDL<3:0> Register
HLVDIN
VDD
Externally Generated
Trip Point
HLVDIF
HLVDEN
BOREN Intern al Voltage
Reference
VDIRMAG
PIC18F2XK20/4XK20
DS40001303H-page 278 2010-2015 Microchip Technology Inc.
22.2 HLVD Setup
The following steps are needed to set up the HLVD
module:
1. Write the value to the HLVDL<3:0> bits that
selects the desired HLVD trip point.
2. Set the VDIRMAG bit to detect high voltage
(VDIRMAG = 1) or low voltage (VDIRMAG = 0).
3. Enable the HLVD module by setting the
HLVDEN bit.
4. Clear the HLVD interrupt flag bit of the PIR2
register, which may have been set from a
previous interrupt.
5. Enable the HLVD interrupt if interrupts are
desired by setting the HLVDIE bit of the PIE2
register, and the GIE and PEIE bits of the
INTCON register. An interrupt will not be gener-
ated unt il the IR VST bit is se t.
22.3 Current Consumption
When the module is enabled, the HLVD comparator
and volt age divider are enabled and will consume st atic
current. The total current consumption, when enabled,
is specified in electrical specification pa rameter D024B.
Depending on the application, the HLVD module does
not need to be operating constantly. To decrease the
current requirements, the HLVD circuitry may only
need to be en abled for short pe riod s where the volt age
is checked. After doing the check, the HLVD module
may be disabled.
22.4 HLVD Start-up Time
The internal reference voltage of the HLVD module,
specified in electrical specification parameter D420,
may be used by other internal circuitry, such as the
Programmable Brown-out Reset. If the HLVD or other
circuits using the voltage reference are disabled to
lower the device’s current consumption, the reference
volt age cir cuit will requ ire time to be come stable before
a low or high-voltage condition can be reliably
detected. This start-up time, TIRVST, is an interval that
is independent of device clock speed. It is specified in
electrical specification parameter 36.
The HLVD interrupt flag is not enabled until TIRVST has
expired and a stable reference voltage is reached. For
this reason, brief excursions beyond the set point may
not be detected during this interval. Refer to Figure 22-2
or Figu re 22-3.
FIGURE 22-2: LOW-VOLT AGE DETECT OPERATION (VDIRMAG = 0)
VHLVD
VDD
HLVDIF
VHLVD
VDD
Enable HLVD
TIVRST
HLVDIF may not be set
Enable HLVD
HLVDIF
HLVDIF cleared by software
HLVDIF cleared by software
HLVDIF cleared by software,
CASE 1:
CASE 2:
HLVDIF remains set since HLVD condition still exists
TIVRST
Internal Reference is stable
Internal Reference is stable
IRVST
IRVST
2010-2015 Microchip Technology Inc. DS40001303H-page 279
PIC18F2XK20/4XK20
FIGURE 22-3: HIGH-VOLTAGE DETECT OPERATION (VDIRMAG = 1)
VHLVD
VDD
HLVDIF
VHLVD
VDD
Enable HLVD
TIVRST
HLVDIF may not be set
Enable HLVD
HLVDIF
HLVDIF cleared by software
HLVDIF cleared by software
HLVDIF cleared by software,
CASE 1:
CASE 2:
HLVDIF remains set since HLVD condition still exists
TIVRST
IRVST
Internal Reference is stable
Internal Reference is stable
IRVST
PIC18F2XK20/4XK20
DS40001303H-page 280 2010-2015 Microchip Technology Inc.
22.5 Applications
In many a ppl ications , the abi lit y to dete ct a drop below,
or rise above, a particular threshold is desirable. For
example, the HLVD module could be periodically
enabled to de tec t U nivers al Seria l Bus (USB) attach or
det ach. This a ssumes the dev ice is powered by a lower
voltage source than the USB when detached. An attach
would indicate a h igh-volt a ge dete ct from, fo r exam ple,
3.3V to 5V (the voltage on USB) and vice versa for a
detach. This feature could save a design a few extra
components and an attach signal (input pin).
For general battery applications, Figure 22-4 shows a
possible voltage curve. Over time, the device voltage
decreases. When the device voltage reaches voltage
VA, the HLVD logic generates an interrupt at time TA.
The interrupt could cause the execution of an ISR,
which would allow the application to perform
“housekeeping tasks” and perform a controlled
shutdown before the device voltage exits the valid
operating range at TB. The HLVD, thus, would gi ve the
application a time window, represented by the
diffe rence between TA and TB, to safely exit.
FIGURE 22-4: TYPICAL LOW-VOLTAGE
DETECT APPLICATION
TABLE 22-1: REGISTERS ASSOCIATED WITH HIGH/LOW-VOLTAGE DETECT MODULE
Time
Voltage
VA
VB
TATB
VA = HLVD trip point
VB = Minimum valid device
operating voltage
Legend:
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset
Values
on Page
HLVDCON VDIRMAG — IRVST HLVDEN HLVDL3 HLVDL2 HLVDL1 HLVDL0 57
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 56
PIR2 OSCFIF C1IF C2IF EEIF BCLIF HLVDIF TMR3IF CCP2IF 59
PIE2 OSCFIE C1IE C2IE EEIE BCLIE HLVDIE TMR3IE CCP2IE 59
IPR2 OSCFIP C1IP C2IP EEIP BCLIP HLVDIP TMR3IP CCP2IP 59
Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the HLVD module.
2010-2015 Microchip Technology Inc. DS40001303H-page 281
PIC18F2XK20/4XK20
23.0 SPECIAL FEATURES OF
THE CPU
PIC18F2XK20/4XK20 devices include several features
intended to maximize reliability and minimize cost through
elimination of external components. These are:
• Oscillator Selection
• Resets:
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
• Interrupts
• Watchdog Timer (WDT)
• Code Protection
• ID Locations
• In-Circuit Serial Programming™
The oscillator can be configured for the application
dependi ng on frequ ency, power, accuracy and c ost. All
of the options are discussed in detail in Section 2.0
“Oscillator M odule (W ith Fai l-Safe Clock Monitor)” .
A complete discussion of device Resets and interrupts
is available in previous sectio ns of this data sheet.
In addition to their Power-up and Oscillator Start-up
Timers provided for Resets, PIC18F2XK20/4XK20
devices have a Watchdog Timer, which is either
permanently enabled via the Configuration bits or
software co ntrolled (if configured a s disabl ed).
The inclu si on of an in tern al R C osc ill ato r also prov ide s
the additional benefits of a Fail-Safe Clock Monitor
(FSCM) and Two-Speed Start-up. FSCM provides for
background monitoring of the peripheral clock and
automatic switchover in the event of its failure. Two-
Speed Start-up enables code to be executed almost
immed iately on s tart-up, while t he primary c lock sourc e
completes its start-up delays.
All of these features are enabled and configured by
setting the appropriate Configuration register bits.
PIC18F2XK20/4XK20
DS40001303H-page 282 2010-2015 Microchip Technology Inc.
23.1 Configuration Bits
The Configuration bits can be programmed (read as
‘0’) or l eft unprog ramme d (read as ‘1’) to selec t various
dev ice conf igurati ons. Th ese bits ar e mappe d starting
at program memory location 300000h.
The user will note that address 300000h is beyond the
user program memory space. In fact, it belongs to the
configuration memory space (300000h-3FFFFFh), which
can only be accessed using table reads and table writes.
Programming the Configuration registers is done in a
manner si milar to programmin g the Flash memory. The
WR bit in th e EECON 1 regis ter st art s a se lf-timed w rite
to the Configuration register. In Normal Operation
mode, a TBLWT instruc tion with the TBLP TR pointing to
the Configuration register sets up the address and the
data for the Configuration register write. Setting the WR
bit starts a long write to the Configuration register. The
Configuration registers are written a byte at a time. To
write or erase a configuration cell, a TBLWT inst ruct ion
can writ e a ‘1’ or a ‘0’ into th e cell. For add itional det ails
on Flash programming, refer to Section 6.5 “Writing
to Flash Program Memory”.
TABLE 23-1: CONFIGURATION BITS AND DEVICE IDs
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Default/
Unprogramme
d
Value
300001h CON-
FIG1H IESO FCMEN —— FOSC3 FOSC2 FOSC1 FOSC0 00-- 0111
300002h CONFIG2L — — — BORV1 BORV0 BOREN1 BOREN0 PWRTEN ---1 1111
300003h CON-
FIG2H — — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDTEN ---1 1111
300005h CON-
FIG3H MCLRE — — —HFOFSTLPT1OS
CPBADEN CCP2MX 1--- 1011
300006h CONFIG4L DEBUG XINST — — —LVP—STVREN10-- -1-1
300008h CONFIG5L — — — —CP3
(1) CP2(1) CP1 CP0 ---- 1111
300009h CON-
FIG5H CPD CPB — — — — — — 11-- ----
30000Ah CONFIG6L — — — —WRT3
(1) WRT2(1) WRT1 WRT0 ---- 1111
30000Bh CON-
FIG6H WRTD WRTB WRTC — — — — — 111- ----
30000Ch CONFIG7L — — — —EBTR3
(1) EBTR2(1) EBTR1 EBTR0 ---- 1111
30000Dh CON-
FIG7H —EBTRB— — — — — — -1-- ----
3FFFFEh DEVID1(2) DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 qqqq qqqq(2)
3FFFFFh DEVID2(2) DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 0000 1100
Legend: x = unknown, u = unchanged, – = unimplemented, q = value depends on condition.
Shaded cells are unimplemented, read as ‘0’.
Note 1: Implemented but not used in PIC18FX3K20 and PIC18FX4K20 devices; maintain this bit set.
2: See Register 23-12 for DEVID1 values. DEVID registers are read-only and cannot be programmed by the user.
2010-2015 Microchip Technology Inc. DS40001303H-page 283
PIC18F2XK20/4XK20
REGISTER 23-1: CONFIG1H: CONFIGURATION REGISTER 1 HIGH
R/P-0 R/P-0 U-0 U-0 R/P-0 R/P-1 R/P-1 R/P-1
IESO FCMEN —— FOSC3 FOSC2 FOSC1 FOSC0
bit 7 bit 0
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed x = Bit is unknown
bit 7 IESO: Internal/Ex tern al Os ci lla tor Switc hov er bit
1 = Oscill ator Switchover mode enabled
0 = Oscillator Switchover mode disabled
bit 6 FCMEN: Fail-Safe Clock Monitor Enable bit
1 = Fail-Safe Cloc k Mo nito r enabl ed
0 = Fail-Safe Cloc k Mo nito r disa bled
bit 5-4 Unimplemented: Read as ‘0’
bit 3-0 FOSC<3:0>: Oscillator Selection bits
11xx = External RC oscillator, CLKOUT function on RA6
101x = External RC oscillator, CLKOUT function on RA6
1001 = Internal oscillator block, CLKOUT function on RA6, port function on RA7
1000 = Internal oscillator block, port function on RA6 and RA7
0111 = Ex tern al RC osc il lat or, port functi on on RA6
0110 = HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1)
0101 = EC oscillator, port function on RA6
0100 = EC oscillator, CLKOUT function on RA 6
0011 = External RC oscillator, CLKOUT function on RA6
0010 = HS oscillat or
0001 = XT oscillator
0000 = LP oscillator
PIC18F2XK20/4XK20
DS40001303H-page 284 2010-2015 Microchip Technology Inc.
REGISTER 23-2: CONFIG2L: CONFIGURATION REGISTER 2 LOW
U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1
— — —BORV1
(1) BORV0(1) BOREN1(2) BOREN0(2) PWRTEN(2)
bit 7 bit 0
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed x = Bit is unknown
bit 7-5 Unimplemented: Read as ‘0’
bit 4-3 BORV<1:0>: Brown-out Reset Voltage bits(1)
11 = VBOR set to 1.8V nominal
10 = VBOR set to 2.2V nominal
01 = VBOR set to 2.7V nominal
00 = VBOR set to 3.0V nominal
bit 2-1 BOREN<1:0>: Brown-out Reset Enable bits (2)
11 = Brown-out Reset enabled in hardware only (SBOREN is disabled)
10 = Brown-out Reset enabled in hardware only and disabled in Sleep mode
(SBOREN is disabled)
01 = Brown-out Reset enabled and controlled by software (SBOREN is enabled)
00 = Brown-out Reset disabled in hardware and software
bit 0 PWRTEN: Power-up Timer Enable bit(2)
1 = PWRT disabled
0 = PWRT enabled
Note 1: See Section 26.1 “DC Characteristics: Supply Voltage” for specifications.
2: The Power-up Timer is decoupled from Brown-out Reset, allowing these features to be independently controlled.
REGISTER 23-3: CONFIG2H: CONFIGURATION REGISTER 2 HIGH
U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1
— — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDTEN
bit 7 bit 0
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed x = Bit is unknown
bit 7-5 Unimplemented: Read as ‘0’
bit 4-1 WDTPS<3:0>: Watchdog Timer Postscale Select bits
1111 = 1:32,768
1110 = 1:16,384
1101 = 1:8,192
1100 = 1:4,096
1011 = 1:2,048
1010 = 1:1,024
1001 = 1:512
1000 = 1:256
0111 = 1:128
0110 = 1:64
0101 = 1:32
0100 = 1:16
0011 = 1:8
0010 = 1:4
0001 = 1:2
0000 = 1:1
bit 0 WDTEN: Watchdog Timer Enable bit
1 = WDT is always enabled. SWDTEN bit has no effect
0 = WDT is controlled by SWDTEN bit of the WDTCON register
2010-2015 Microchip Technology Inc. DS40001303H-page 285
PIC18F2XK20/4XK20
REGISTER 23-4: CONFIG3H: CONFIGURATION REGISTER 3 HIGH
R/P-1 U-0 U-0 U-0 R/P-1 R/P-0 R/P-1 R/P-1
MCLRE — — — HFOFST LPT1OSC PBADEN CCP2MX
bit 7 bit 0
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed x = Bit is unknown
bit 7 MCLRE: MCLR Pin Enable bit
1 = MCLR pin enabled; RE3 input pin disabled
0 = RE3 input pin enable d; MCLR dis ab led
bit 6-4 Unimplemented: Read as ‘0’
bit 3 HFOFST: HFINTOSC Fast Start-up
1 = HFINTOSC starts clocking the CPU without waiting for the oscillator to stabilize.
0 = The system clock is held off until the HFINTOSC is stable.
bit 2 LPT1OSC: Low-Power Timer1 Oscillator Enable bit
1 = Timer1 configured for low-power operation
0 = Timer1 configured for higher power operation
bit 1 PBADEN: PORTB A/D Enable bit
(Affects ANSELH Reset state. ANSELH controls PORTB<4:0> pin configuration.)
1 = PORTB<4:0> pins are configured as analog input channels on Reset
0 = PORTB<4:0> pins are configured as digita l I/O on Reset
bit 0 CCP2MX: CCP2 MUX bit
1 = CCP2 inpu t/output is multiplexed with RC1
0 = CCP2 inpu t/output is multiplexed with RB3
REGISTER 23-5: CONFIG4L: CONFIGURATION REGISTER 4 LOW
R/P-1 R/P-0 U-0 U-0 U-0 R/P-1 U-0 R/P-1
DEBUG XINST — — —LVP
(1) —STVREN
bit 7 bit 0
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed x = Bit is unknown
bit 7 DEBUG: Background Debugger Enable bit
1 = Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins
0 = Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug
bit 6 XINST: Extended Instruction Set Enable bit
1 = Instruction set extension and Indexed Addressing mode enabled
0 = Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
bit 5-3 Unimplemented: Read as ‘0’
bit 2 LVP: Single-Supply ICSP Enable bit
1 = Single-Supply ICSP enabled
0 = Single-Supply ICSP disabled
bit 1 Unimplemented: Read as ‘0’
bit 0 STVREN: Stack Full/Underflow Reset Enable bit
1 = Stack full/underflow will cause Reset
0 = Stack full/underflow will not cause Reset
Note 1: Can only be changed by a program mer in High-Volt age Programming mode.
PIC18F2XK20/4XK20
DS40001303H-page 286 2010-2015 Microchip Technology Inc.
REGISTER 23-6: CONFIG5L: CONFIGURATION REGISTER 5 LOW
U-0 U-0 U-0 U-0 R/C-1 R/C-1 R/C-1 R/C-1
— — — —CP3
(1) CP2(1) CP1 CP0
bit 7 bit 0
Legend:
R = Readable bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed C = Clearable only bit
bit 7-4 Unimplemented: Read as ‘0’
bit 3 CP3: Code Protection bit(1)
1 = Block 3 not code-protected
0 = Block 3 code-protected
bit 2 CP2: Code Protection bit(1)
1 = Block 2 not code-protected
0 = Block 2 code-protected
bit 1 CP1: Code Protection bit
1 = Block 1 not code-protected
0 = Block 1 code-protected
bit 0 CP0: Code Protection bit
1 = Block 0 not code-protected
0 = Block 0 code-protected
Note 1: Implemented, but not used in PIC18FX3K20 and PIC18FX4K20 devices.
REGISTER 23-7: CONFIG5H: CONFIGURATION REGISTER 5 HIGH
R/C-1 R/C-1 U-0 U-0 U-0 U-0 U-0 U-0
CPD CPB — — — — — —
bit 7 bit 0
Legend:
R = Readable bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed C = Clearable only bit
bit 7 CPD: Data EEPROM Code Protection bit
1 = Data EEPROM not code-protected
0 = Data EEPROM code-protected
bit 6 CPB: Boot Block Code Protection bit
1 = Boot Block not code-protected
0 = Boot Block code-protected
bit 5-0 Unimplemented: Read as ‘0’
2010-2015 Microchip Technology Inc. DS40001303H-page 287
PIC18F2XK20/4XK20
REGISTER 23-8: CONFIG6L: CONFIGURATION REGISTER 6 LOW
U-0 U-0 U-0 U-0 R/C-1 R/C-1 R/C-1 R/C-1
— — — —WRT3
(1) WRT2(1) WRT1 WRT0
bit 7 bit 0
Legend:
R = Readable bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed C = Clearable only bit
bit 7-4 Unimplemented: Read as ‘0’
bit 3 WRT3: Write Protect ion bit(1)
1 = Block 3 not write-protected
0 = Block 3 write-protected
bit 2 WRT2: Write Protect ion bit(1)
1 = Block 2 not write-protected
0 = Block 2 write-protected
bit 1 WRT1: Write Protect ion bit
1 = Block 1 not write-protected
0 = Block 1 write-protected
bit 0 WRT0: Write Protect ion bit
1 = Block 0 not write-protected
0 = Block 0 write-protected
Note 1: Implemented, but not used in PIC18FX3K20 and PIC18FX4K20 devices.
REGISTER 23-9: CONFIG6H: CONFIGURATION REGISTER 6 HIGH
R/C-1 R/C-1 R-1 U-0 U-0 U-0 U-0 U-0
WRTD WRTB WRTC(1) — — — — —
bit 7 bit 0
Legend:
R = Readable bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed C = Clearable only bit
bit 7 WRTD: Data EEPROM Write Protection bit
1 = Data EEPROM not write-protected
0 = Data EEPROM write-protected
bit 6 WRTB: Boot Block Write Protection bit
1 = Boot Block not write -pro tected
0 = Boot Block write-protected
bit 5 WRTC: Configuration Register Write Protection bit(1)
1 = Configuration registers not write-protected
0 = Conf igur ation registe rs write-protected
bit 4-0 Unimplemented: Read as ‘0’
Note 1: This bi t i s rea d-o nl y in No rm al Ex ec ut io n m o de ; i t c an b e w rit ten only in Progra m m od e.
PIC18F2XK20/4XK20
DS40001303H-page 288 2010-2015 Microchip Technology Inc.
REGISTER 23-10: CONFIG7L: CONFIGURATION REGISTER 7 LOW
U-0 U-0 U-0 U-0 R/C-1 R/C-1 R/C-1 R/C-1
— — — — EBTR3(1) EBTR2(1) EBTR1 EBTR0
bit 7 bit 0
Legend:
R = Readable bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed C = Clearable only bit
bit 7-4 Unimplemented: Read as ‘0’
bit 3 EBTR3: Table Read Protection bit(1)
1 = Block 3 not protected from table reads executed in other blocks
0 = Block 3 protected from table reads executed in other blocks
bit 2 EBTR2: Table Read Protection bit(1)
1 = Block 2 not protected from table reads executed in other blocks
0 = Block 2 protected from table reads executed in other blocks
bit 1 EBTR1: Table Read Protection bit
1 = Block 1 not protected from table reads executed in other blocks
0 = Block 1 protected from table reads executed in other blocks
bit 0 EBTR0: Table Read Protection bit
1 = Block 0 not protected from table reads executed in other blocks
0 = Block 0 protected from table reads executed in other blocks
Note 1: Implemented, but not used in PIC18FX3K20 and PIC18FX4K20 devices.
REGISTER 23-11: CONFIG7H: CONFIGURATION REGISTER 7 HIGH
U-0 R/C-1 U-0 U-0 U-0 U-0 U-0 U-0
— EBTRB — — — — — —
bit 7 bit 0
Legend:
R = Readable bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed C = Clearable only bit
bit 7 Unimplemented: Read as ‘0’
bit 6 EBTRB: Boot Block Table Read Protection bit
1 = Boot Block not protected from table reads executed in other blocks
0 = Boot Block protected from table reads executed in other blocks
bit 5-0 Unimplemented: Read as ‘0’
2010-2015 Microchip Technology Inc. DS40001303H-page 289
PIC18F2XK20/4XK20
REGISTER 23-12: DEVID1: DEVICE ID REGISTER 1 FOR PIC18F2XK20/4XK20
RRRRRRRR
DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0
bit 7 bit 0
Legend:
R = Readable bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed C = Clearable only bit
bit 7-5 DEV<2:0>: Device ID bits
000 = PIC18F46K20
001 = PIC18F26K20
010 = PIC18F45K20
011 = PIC18F25K20
100 = PIC18F44K20
101 = PIC18F24K20
110 = PIC18F43K20
111 = PIC18F23K20
bit 4-0 REV<4:0>: Revision ID bits
These bits are used to indicate the device revision.
REGISTER 23-13: DEVID2: DEVICE ID REGISTER 2 FOR PIC18F2XK20/4XK20
RRRRRRRR
DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3
bit 7 bit 0
Legend:
R = Readable bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed C = Clearable only bit
bit 7-0 DEV<10:3>: Device ID bits
These bits are used with the DEV<2:0> bits in the Device ID Register 1 to identify the
part num be r.
0010 0000 = PIC18F2XK20/4XK20 devices
Note 1: These values for DEV<10:3> may be shared with other devices. The specific device is always identified
by using the entire DEV<10:0> bit sequence.
PIC18F2XK20/4XK20
DS40001303H-page 290 2010-2015 Microchip Technology Inc.
23.2 Watchdog Timer (WDT)
For PIC18F2XK20/4XK20 devices, the WDT is driven
by the LFIN TOSC sour ce. W hen the W DT is enabl ed,
the clock source is also enabled. The nominal WDT
period is 4 ms and has the same stability as the
LFIN TO SC oscillator.
The 4 ms period of the WDT is multiplied by a 16-bit
postscaler. Any output of the WDT postscaler is
selected by a multiplexer , controlled by bits in Configu-
ration Register 2H. Available periods range from 4 ms
to 131.072 seconds (2.18 minutes). The WDT and
post scaler are cleare d when any of the following events
occur: a SLEEP or CLRWDT instruction is executed, the
IRCF bits of the OSCCON register are changed or a
clock failure has oc curred.
FIGURE 23-1: WDT BLOCK DIAGRAM
Note 1: The CLRWDT and SLEEP instructions
clear the WDT and postscaler counts
when execute d.
2: Changing the setting of the IRCF bits of
the OSCCON register clears the WDT
and postscaler counts.
3: When a CLRWDT instruction is executed,
the postscaler count will be cleared.
LFINTOSC Source
WDT
Wake-up
Reset
WDT Counter
Progra mmable P ostscaler
1:1 to 1:32,768
Enable WDT
WDTPS<3:0>
SWDTEN
WDTEN
CLRWDT
4
from Power
Reset
All Device Resets
Sleep
128
Change on IRCF bits Managed Modes
2010-2015 Microchip Technology Inc. DS40001303H-page 291
PIC18F2XK20/4XK20
23.2.1 CONTROL REGISTER
Register 23-14 shows the WDTCON register. This is a
readable and writable regis te r whic h co nt ains a control
bit that allows software to override the WDT enable
Configuration bit, but only if the Configuration bit has
disabled the WDT.
REGISTER 23-14: WDTCON: WATCHDOG TIMER CONTROL REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0
— — — — — — —SWDTEN
(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-1 Unimplemented: Read as ‘0’
bit 0 SWDTEN: Software Enable or Disable the Watchdog Timer bit(1)
1 = WDT is turned on
0 = WDT is turned off (Reset value)
Note 1: This bit has no effect if the Configuration bit, WDTEN, is enabled.
TABLE 23-2: SUMMARY OF WATCHDOG TIMER REGISTERS
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset
Values
on page
RCON IPEN SBOREN —RI TO PD POR BOR 55
WDTCON ———————SWDTEN57
CONFIG2H WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDTEN 284
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Watchdog Timer.
PIC18F2XK20/4XK20
DS40001303H-page 292 2010-2015 Microchip Technology Inc.
23.3 Program Verification and
Code Protection
The overall structure of the code protection on the
PIC18 Flash devices differs significantly from other
PIC® microcontroller device s.
The user program memory is divided into three or five
blocks, depending on the device. One of these is a
Boot Block of 0.5K or 2K bytes, depending on the
device. The remainder of the memory is divided into
individual blocks on binary boundaries.
Each of the blocks has three code protection bits
associated with them. They are:
• Code-Protect bit (CPn)
• Write-Protect bit (WRTn)
• External Block Table Read bit (EBTRn)
Figure 23-2 shows the program memory organization
for 8, 16 and 32-Kbyte devices and the specific code
protection bit associated with each block. The actual
locations of the bits are summarized in Table .
FIGURE 23-2: CODE-PROTECTED PROGRAM MEMORY FOR PIC18F2XK20/4XK20
TABLE 23-3: SUMMARY OF CODE PROTECTION REGISTERS
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
300008h CONFIG5L — — — —CP3
(1) CP2(1) CP1 CP0
300009h CONFIG5H CPD CPB — — — — — —
30000Ah CONFIG6L — — — —WRT3
(1) WRT2(1) WRT1 WRT0
30000Bh CONFIG6H WRTD WRTB WRTC — — — — —
30000Ch CONFIG7L — — — — EBTR3(1) EBTR2(1) EBTR1 EBTR0
30000Dh CONFIG7H — EBTRB — — — — — —
Legend: Shaded cells are unimplem en ted.
Note 1: Implemented, but not used in PIC18FX3K20 and PIC18FX4K20 devices.
MEMORY SIZE/DEVICE Block Code P rotection
Controlled By:
8Kbytes
(PIC18FX3K20) 16 Kbytes
(PIC18FX4K20) 32 Kbytes
(PIC18FX5K20) 64 Kbytes
(PIC18FX6K20)
Boot Block
(000h-1FFh) Boot Bloc k
(000h-7FFh) Boot Bloc k
(000h-7FFh) Boot Block
(000h-7FFh) CPB, WRTB, EBTRB
Block 0
(200h-FFFh) Block 0
(800h-1FFFh) Block 0
(800h-1FFFh) Block 0
(800h-3FFFh) CP0, WRT0, EBTR0
Block 1
(1000h-1FFFh) Block 1
(2000h-3FFFh) Block 1
(2000h-3FFFh) Block 1
(4000h-7FFFh) CP1, WRT1, EBTR1
Unimplemented
Read ‘0’s
(2000h-1FFFFFh)
Unimplemented
Read ‘0’s
(4000h-1FFFFFh)
Block 2
(4000h-5FFFh) Block 2
(8000h-BFFFh) CP2, WRT2, EBTR2
Block 3
(6000h-7FFFh) Block 3
(C000h-FFFFh) CP3, WRT3, EBTR3
Unimplemented
Read ‘0’s
(8000h-1FFFFFh)
Unimplemented
Read ‘0’s
(10000h-1FFFFFh)
(Unimplemented
Memory Space)
2010-2015 Microchip Technology Inc. DS40001303H-page 293
PIC18F2XK20/4XK20
23.3.1 PROGRAM MEMORY
CODE PROTECTION
The program memory may be read to or written from
any location using the table read and table write
instructions. The device ID may be read with table
reads. The Configuration registers may be read and
written with the table read and table write instructions.
In normal execution mode, the CPn bits have no direct
ef fect. CPn bits inhi bit external reads and writes. A block
of user memory may be protected fro m table writes if the
WRTn Configuration bit is ‘0’. The EBTRn bits control
table reads. Fo r a block of u ser memory with the EBTRn
bit cleared to ‘0’, a table READ instruction that executes
from within that block is allowed to read. A table read
instruction that executes from a location outside of that
block is not allowed to read and will res ult in reading ‘0’s.
Figures 23-3 through 23-5 illustrate tab le write and table
read protection.
FIGURE 23-3: TABLE WRITE (WRTn) DISALLOWED
Note: Code protection bits may only be written
to a ‘0’ from a ‘1’ s tate . It is not p ossib le to
write a ‘1’ to a bit in the ‘0’ state. Code pro-
tection b its are only set to ‘1’ b y a full chip
erase or block erase function. The full chip
erase and block erase functions can only
be initiated via ICSP or an external
programmer.
000000h
0007FFh
000800h
001FFFh
002000h
003FFFh
004000h
005FFFh
006000h
007FFFh
WRTB, EBTRB = 11
WRT0, EBTR0 = 01
WRT1, EBTR1 = 11
WRT2, EBTR2 = 11
WRT3, EBTR3 = 11
TBLWT*
TBLPTR = 0008FFh
PC = 001FFEh
TBLWT*
PC = 005FFEh
Register Va lues Program Memory Configuration Bit Settings
Results: All table writes disabled to Blockn whenever WRTn = 0.
PIC18F2XK20/4XK20
DS40001303H-page 294 2010-2015 Microchip Technology Inc.
FIGURE 23-4: EXTERN AL BLOCK TABLE READ (EBTRn) DISALLOWED
FIGURE 23-5: EXTERN AL BLOCK TABLE READ (EBTRn) ALLOWED
WRTB, EBTRB = 11
WRT0, EBTR0 = 10
WRT1, EBTR1 = 11
WRT2, EBTR2 = 11
WRT3, EBTR3 = 11
TBLRD*
TBLPTR = 0008FFh
PC = 003FFEh
Results: All table reads from external blocks to Blockn are disabled whenever EBTRn = 0.
TABLAT register returns a value of ‘0’.
Register Values Program Memory Configuration Bit Settings
000000h
0007FFh
000800h
001FFFh
002000h
003FFFh
004000h
005FFFh
006000h
007FFFh
WR TB, EBTRB = 11
WRT0, EBTR0 = 10
WRT1, EBTR1 = 11
WRT2, EBTR2 = 11
WRT3, EBTR3 = 11
TBLRD*
TBLPTR = 0008FFh
PC = 001FFEh
Register Values Program Memory Configuration Bit Settings
Results: Table reads permitted withi n Bloc kn, even when EBTRBn = 0.
TABLAT register returns the value of the data at the location TBLPTR.
000000h
0007FFh
000800h
001FFFh
002000h
003FFFh
004000h
005FFFh
006000h
007FFFh
2010-2015 Microchip Technology Inc. DS40001303H-page 295
PIC18F2XK20/4XK20
23.3.2 DATA EEPROM
CODE PROTECTION
The entire data EEPROM is protected from external
reads and writes by two bits: CPD and WRTD. CPD
inhibits external reads and writes of data EEPROM.
WRTD inhibits internal and external writes to data
EEPROM. The CPU can always read data EEPROM
under n ormal op eration, re gardless o f the prot ection bit
settings.
23.3.3 CONFIGURATION REGISTER
PROTECTION
The Configuration registers can be write-protected.
The WRTC bit controls protection of the Configuration
registers. In Normal Execution mode, the WRTC bit is
readable only. WRTC can only be written via ICSP or
an external programmer.
23.4 ID Locations
Eight memory locations (200000h-200007h) are
designated as ID locations, where the user can store
checksum or other code identification numbers. These
locatio ns are b oth read abl e and writable d urin g normal
execution through the TBLRD and TBLWT instructions
or du r ing p r ogr am / ver if y. Th e I D lo ca tio n s c a n b e re ad
when the device is code-protected.
23.5 In-Circuit Serial Programming
PIC18F2XK20/4XK20 devices can be serially
progra mmed w hile in t he en d app licati on c ircuit. This is
simply done with tw o lines for cl ock and dat a and thre e
other lines for power, ground and the programming
voltage. This allows customers to manufacture boards
with unprogrammed devices and then program the
microcontroller just before shipping the product. This
also allows the most recent firmware or a custom
firmware to be programmed.
23.6 In-Circui t Debugger
When the DEBUG Configuration bit is programmed to
a ‘0’, the In-Circuit Debugger functionality is enabled.
This funct ion al lows s imple debug ging f unct ions wh en
use d wi t h M PLA B® IDE. When the microcontroller has
this featu r e ena ble d, so me reso urc es are not avail abl e
for gene ral us e. Table 23-4 shows which resources are
required by the background debugger.
TABLE 23-4: DEBUGGER RESOURCES
To use the In-Circuit Debugger function of the micro-
controller, the design must implement In-Circuit Serial
Programming connections to the following pins:
•MCLR
/VPP/RE3
•V
DD
•VSS
•RB7
•RB6
This will interface to the In-Circuit Debugger module
availa ble from M icrochip or one of the third p arty deve l-
opment tool comp an ies .
23.7 Single-Supply ICSP Programming
The LVP Configuration bit enables Single-Supply ICSP
Programming (formerly known as Low-Voltage ICSP
Programming or LVP). When Single-Supply Program-
ming is enabled, the microcontroller can be programmed
without requiring high voltage being applied to the
MCLR/VPP/RE3 pin, but the RB5/KBI1/PGM pin is then
dedicated to controlling Pr ogram mode entry and is not
available as a general purpos e I/O pin.
While programming, using Single-Supply Programming
mode, VDD is applied to the MCLR/VPP/RE3 pin as in
normal execution mode. To enter Programming mode,
VDD is applied to the PGM pin.
If Single-Supply ICSP Programming mode will not be
used, the LV P bit c an b e cl ear ed. R B5 / KBI1/ PGM the n
become s a vaila ble as the dig ita l I/O p in, RB 5. The LVP
bit may be set or cleared only when using standard
high-voltage programming (VIHH applied to the MCLR/
VPP/RE3 pin). Once LVP has been disabled, only the
standard high-voltage programming is available and
must be used to program the device.
Memory tha t is not code -protected ca n be erased usin g
either a b lock erase, or erased ro w by row, th en wr itten
at any s pecified VDD. If co de-protected m emory is to be
erased, a block erase is required.
I/O pins: RB6 , RB7
Stack: 2 levels
Program Memory: 512 bytes
Data Memory: 10 bytes
Note 1: High-voltage programming is always
available, regardless of the state of the
LVP bit or the PGM pi n, by ap ply in g V IHH
to the MCLR pin.
2: By default, Single-Supply ICSP is
enabled in unprogrammed devices (as
supplied from Microchip) and erased
devices.
3: When Single-Supply Programming is
enabled, the RB5 pin can no longer be
used as a general purpose I/O pin.
4: When LVP is enabled, ex ternally pull the
PGM pin to VSS to allow normal program
execution.
PIC18F2XK20/4XK20
DS40001303G-page 296 2010-2015 Microchip Technology Inc.
24.0 INSTRUCTION SET SUMMARY
PIC18F2XK20/4XK20 devices incorporate the standard
set of 75 PIC18 core instructions, as well as an extended
set of eight new instructions, for the optimiz ation of code
that is recursive or that utilizes a software stack. The
extended set is discu ssed la te r in this sec tion.
24.1 Standard Instruction Set
The standard PIC18 instruction set adds many
enhancements to the previous PIC® MCU instruction
sets, while maintaining an easy migration from these
PIC® MCU instruction sets. Most instructions are a
single program memory word (16 bits), but there are
four instructions that require two program memory
locations.
Each single-word instruction is a 16-bit word divided
into an o pcode, whi ch specifies the instructi on type an d
one or more operands, which further specify the
operation of the inst ruction.
The instruction set is highly orthogonal and is grouped
into four basic categories:
•Byte-oriented operations
•Bit-oriented operations
•Literal operati ons
•Control operations
The PI C18 instr uction s et summ ary in Table 24-2 lists
byte-oriented, bit-oriented, literal and control
operations. Table sho ws the o pcode fiel d des cripti ons.
Most byte-oriented in str uct ions have three operands:
1. The file register (specified by ‘f’)
2. The destination of the result (specified by ‘d’)
3. The access ed memo ry (s pecified by ‘a’)
The file register designator ‘f’ specifies which file
register is to be use d by the instruc tion. The des tination
designator ‘d’ specifies where the result of the opera-
tion is to be pl aced. If ‘d’ is zero, the result is placed in
the WREG register. If ‘d’ is one, the result is placed in
the file register specified in the instruction.
All bit-oriented instructions have three operands:
1. The file register (specified by ‘f’)
2. The bit in the file register (specified by ‘b’)
3. The access ed memo ry (s pecified by ‘a’)
The bit field des ignato r ‘b’ sele cts the nu mber of the bit
affected by the operation, while the file register
designa tor ‘f’ repr esent s the numbe r of the fil e in whic h
the bit is located.
The literal ins truc tions m ay use so me of the follo wing
operands:
• A literal value to be loaded into a file register
(specified by ‘k’)
• The desired FSR register to load the literal value
into (specif ied by ‘f’)
• No operand requir ed
(specified by ‘—’)
The control ins tructions may use so me of the f ollowing
operands:
• A program memory address (specified by ‘n’)
• The mode of th e CALL or RETURN instructions
(specified by ‘s’)
• The mode of the table read and table write
ins tructions (spe cified by ‘m’)
• No operand requir ed
(specified by ‘—’)
All instructions are a single word, except for four
double-word instructions. These instructions were
made double-word to contain the required information
in 32 bits. In the second word, the 4 MSbs are ‘1’s. If
this second word is executed as an instruction (by
it se lf), it will exe cu te as a NOP.
All single-word instructions are executed in a single
inst ruct ion c yc le , un le ss a conditional test is true or th e
program counter is changed as a result of the instruc-
tion. In th ese cases, the execution takes two i nstruction
cycle s, with the addit ional in struction cycle(s) ex ecuted
as a NOP.
The double-word instructions execute in two instruction
cycles.
One in struction cycle consist s of f our oscil lator p eriods.
Thus, for an oscillator frequency of 4 MHz, the normal
inst ruction ex ecution ti me is 1 s. If a cond itional tes t is
true, or the program counter is changed as a result of
an instruction, the instruction execution time is 2 s.
Two-word branch instructions (if true) would take 3 s.
Figure shows the genera l form at s that the in stru cti on s
can have. All examples use the conve ntion ‘nnh’ to rep-
resent a hexadecimal number.
TABLE 24-1: OPCODE FIELD DESCRIPTIONS
Field Description
aRAM access bit
a = 0: RAM location in Access RAM (BSR register is ignored)
a = 1: RAM bank is specified by BSR register
bbb Bit address within an 8-bit file register (0 to 7).
BSR Bank Select Register. Used to select the current RAM bank.
C, DC, Z, OV, N ALU Status bits: Carry, Digit Carry, Zero, Overflow, Negative.
2010-2015 Microchip Technology Inc. DS40001303G-page 297
PIC18F2XK20/4XK20
dDestination select bit
d = 0: store result in WREG
d = 1: store result in file register f
dest Destination: either the WREG register or the specified register file location.
f8-bit Register file address (00h to FFh) or 2-bit FSR designator (0h to 3h).
fs12-bit Register file address (000h to FFFh). This is the source address.
fd12-bit Register file address (000h to FFFh). This is the destination address.
GIE Global Interrupt Enable bit.
kLiteral field, constant data or lab el (may be either an 8-bit, 12-bit or a 20-bit value).
label Label name.
mm The mode of the TBLPTR register for the table read and table write instructions.
Only used with table read and table write instructions:
*No change to register (such as TBLPTR with table reads and writes)
*+ Post-Increment register (suc h as TBLPTR with table reads and writes)
*- Post-Decremen t register (such as TBLPT R with table reads and writes)
+* Pre-Increment register (such as TBLPTR with table reads and writes)
nThe relative address (2’s complement number) for relative branch instructions or the direct address for
CALL/BRANCH and RETURN instructions.
PC Program Counter.
PCL Program Counter Low Byte.
PCH Program Counter High Byte.
PCLATH Program Counter High Byte Latch.
PCLATU Program Counter Upper Byte Latch.
PD Power-down bit.
PRODH Product of Multiply High Byte.
PRODL Product of Multiply Low Byte.
sFast Call/Return mode select bit
s = 0: do not update into/from shadow registers
s = 1: certain registers loaded into/from shadow registers (Fast mode)
TBLPTR 21-bit Table Pointer (points to a Program Memory location).
TABLAT 8-bit Table Latch.
TO Time-out bit.
TOS Top-of-Stack.
uUnused or unchanged.
WDT Watchdog Timer.
WREG Working register (accumulator).
xDon’t care (‘0’ or ‘1’). The assembler will generate code with x = 0. It is the recommended form of use for
compatibility with all Microchip software tools.
zs7-bit offset value for indirect addressing of register files (source).
zd7-bit offset value for indirect addressing of register files (destination).
{ } Optional argument.
[text] Indicates an indexed address.
(text) The contents of text.
[expr]<n> Spec ifies bit n of the register indicated by the pointer expr.
Assigned to.
< > Register bit field.
In the set of.
italics User defined term (font is Courier).
TABLE 24-1: OPCODE FIELD DESCRIPTIONS (CONTINUED)
Field Description
PIC18F2XK20/4XK20
DS40001303G-page 298 2010-2015 Microchip Technology Inc.
FIGURE 24-1: GENERAL FORMAT FOR INSTRUCTIONS
Byte-oriented file register operations
15 10 9 8 7 0
d = 0 for result destination to be WREG register
OPCODE d a f (FILE #)
d = 1 for result destination to be file register (f)
a = 0 to force Access Bank
Bit-oriented file register operations
15 12 11 9 8 7 0
OPCODE b (BIT #) a f (FILE #)
b = 3-bit position of bit in file register (f)
Literal operations
15 8 7 0
OPCODE k (literal)
k = 8-bit immediate value
Byte to Byte move operations (2-word)
15 12 11 0
OPCODE f (Source FILE #)
CALL, GOTO and Branch operations
15 8 7 0
OPCODE n<7:0> (literal)
n = 20-bit immediate value
a = 1 for BSR to select bank
f = 8-bit file register address
a = 0 to force Acc ess Bank
a = 1 for BSR to select bank
f = 8-bit file register address
15 12 11 0
1111 n<19:8> (literal)
15 12 11 0
1111 f (Desti n a tion FILE #)
f = 12-bit file register address
Control operations
Example Instruction
ADDWF MYREG, W, B
MOVFF MYREG1, MYREG2
BSF MYREG, bit, B
MOVLW 7Fh
GOTO Label
15 8 7 0
OPCODE n<7:0> (literal)
15 12 11 0
1111 n<19:8> (literal)
CALL MYFUNC
15 11 10 0
OPCOD E n<10:0 > ( litera l )
S = Fast bit
BRA MYFUNC
15 8 7 0
OPCODE n<7:0> (literal) BC MYFUNC
S
2010-2015 Microchip Technology Inc. DS40001303G-page 299
PIC18F2XK20/4XK20
TABLE 24-2: PIC18FXXXX INSTRU CTION SET
Mnemonic,
Operands Description Cycles 16-Bit Instruction Word Status
Affected Notes
MSb LSb
BYTE-ORIENTED OPERATIONS
ADDWF
ADDWFC
ANDWF
CLRF
COMF
CPFSEQ
CPFSGT
CPFSLT
DECF
DECFSZ
DCFSNZ
INCF
INCFSZ
INFSNZ
IORWF
MOVF
MOVFF
MOVWF
MULWF
NEGF
RLCF
RLNCF
RRCF
RRNCF
SETF
SUBFWB
SUBWF
SUBWFB
SWAPF
TSTFSZ
XORWF
f, d, a
f, d, a
f, d, a
f, a
f, d, a
f, a
f, a
f, a
f, d, a
f, d, a
f, d, a
f, d, a
f, d, a
f, d, a
f, d, a
f, d, a
fs, fd
f, a
f, a
f, a
f, d, a
f, d, a
f, d, a
f, d, a
f, a
f, d, a
f, d, a
f, d, a
f, d, a
f, a
f, d, a
Add WREG and f
Add WREG and CARRY bit to f
AND WREG with f
Clear f
Complement f
Compare f with WREG, skip =
Compare f with WREG, skip >
Compare f with WREG, skip <
Decrement f
Decrement f, Skip if 0
Decrement f, Skip if Not 0
Increment f
Increment f, Skip if 0
Increment f, Skip if Not 0
Inclusive OR WREG with f
Move f
Move fs (source) to 1st word
fd (destination) 2nd word
Move WRE G to f
Multiply WREG with f
Negate f
Rotate Left f through Carry
Rot ate Left f (No Carry)
Rotate Right f through Carry
Rotate Right f (No Carry)
Set f
Subtract f from WREG with
borrow
Subtract WREG from f
Subtract WREG from f with
borrow
Swap nibbles in f
Test f, skip if 0
Exclusive OR WREG with f
1
1
1
1
1
1 (2 or 3)
1 (2 or 3)
1 (2 or 3)
1
1 (2 or 3)
1 (2 or 3)
1
1 (2 or 3)
1 (2 or 3)
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1 (2 or 3)
1
0010
0010
0001
0110
0001
0110
0110
0110
0000
0010
0100
0010
0011
0100
0001
0101
1100
1111
0110
0000
0110
0011
0100
0011
0100
0110
0101
0101
0101
0011
0110
0001
01da
00da
01da
101a
11da
001a
010a
000a
01da
11da
11da
10da
11da
10da
00da
00da
ffff
ffff
111a
001a
110a
01da
01da
00da
00da
100a
01da
11da
10da
10da
011a
10da
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
C, DC, Z, OV, N
C, DC, Z, OV, N
Z, N
Z
Z, N
None
None
None
C, DC, Z, OV, N
None
None
C, DC, Z, OV, N
None
None
Z, N
Z, N
None
None
None
C, DC, Z, OV, N
C, Z, N
Z, N
C, Z, N
Z, N
None
C, DC, Z, OV, N
C, DC, Z, OV, N
C, DC, Z, OV, N
None
None
Z, N
1, 2
1, 2
1,2
2
1, 2
4
4
1, 2
1, 2, 3, 4
1, 2, 3, 4
1, 2
1, 2, 3, 4
4
1, 2
1, 2
1
1, 2
1, 2
1, 2
1, 2
4
1, 2
Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value
present on the pins themselves. For example, if the data lat ch is ‘1’ for a pin configured as input and is driven low by an
external device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and where applicable, ‘d’ = 1), the prescaler will be cleared if
assigned.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless
the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program mem-
ory locations have a valid instruction.
PIC18F2XK20/4XK20
DS40001303G-page 300 2010-2015 Microchip Technology Inc.
BIT-ORIENTED OPERATIONS
BCF
BSF
BTFSC
BTFSS
BTG
f, b, a
f, b, a
f, b, a
f, b, a
f, d, a
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
Bit Toggle f
1
1
1 (2 or 3)
1 (2 or 3)
1
1001
1000
1011
1010
0111
bbba
bbba
bbba
bbba
bbba
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
None
None
None
None
None
1, 2
1, 2
3, 4
3, 4
1, 2
CONTROL OPERATIONS
BC
BN
BNC
BNN
BNOV
BNZ
BOV
BRA
BZ
CALL
CLRWDT
DAW
GOTO
NOP
NOP
POP
PUSH
RCALL
RESET
RETFIE
RETLW
RETURN
SLEEP
n
n
n
n
n
n
n
n
n
n, s
—
—
n
—
—
—
—
n
s
k
s
—
Branch if Carry
Branch if Negative
Branch if Not Carry
Branch if Not Negative
Branch if Not Overflow
Branch if Not Zero
Branch if Overflow
Branch Unconditionally
Branch if Zero
Call subroutine 1st word
2nd word
Clear Wat chdog Timer
Decimal Adjust WREG
Go to address 1st word
2nd word
No Operation
No Operation
Pop top of return stack (TOS)
Push top of return stack (TOS)
Relative Call
Software device Reset
Return from interrupt enable
Return with literal in WREG
Return from Subroutine
Go into Standby mode
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
2
1 (2)
2
1
1
2
1
1
1
1
2
1
2
2
2
1
1110
1110
1110
1110
1110
1110
1110
1101
1110
1110
1111
0000
0000
1110
1111
0000
1111
0000
0000
1101
0000
0000
0000
0000
0000
0010
0110
0011
0111
0101
0001
0100
0nnn
0000
110s
kkkk
0000
0000
1111
kkkk
0000
xxxx
0000
0000
1nnn
0000
0000
1100
0000
0000
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
kkkk
kkkk
0000
0000
kkkk
kkkk
0000
xxxx
0000
0000
nnnn
1111
0001
kkkk
0001
0000
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
kkkk
kkkk
0100
0111
kkkk
kkkk
0000
xxxx
0110
0101
nnnn
1111
000s
kkkk
001s
0011
None
None
None
None
None
None
None
None
None
None
TO, PD
C
None
None
None
None
None
None
All
GIE/GIEH,
PEIE/GIEL
None
None
TO, PD
4
TABLE 24-2: PIC18FXXXX INSTRUCTION SET (CONTINUED)
Mnemonic,
Operands Description Cycles 16-Bit Instruction Word Status
Affected Notes
MSb LSb
Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value
present on the pins themselves. For example, if the data lat ch is ‘1’ for a pin configured as input and is driven low by an
external device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and where applicable, ‘d’ = 1), the prescaler will be cleared if
assigned.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless
the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program mem-
ory locations have a valid instruction.
2010-2015 Microchip Technology Inc. DS40001303G-page 301
PIC18F2XK20/4XK20
LITERAL OPERATIONS
ADDLW
ANDLW
IORLW
LFSR
MOVLB
MOVLW
MULLW
RETLW
SUBLW
XORLW
k
k
k
f, k
k
k
k
k
k
k
Add literal and WREG
AND literal with WREG
Inclusive OR literal with WREG
Move literal (12-bit) 2nd word
to FSR(f) 1st word
Move literal to BSR<3:0>
Move literal to WREG
Multiply literal with WREG
Return with literal in WREG
Subtract WREG from literal
Exclusive OR literal with WREG
1
1
1
2
1
1
1
2
1
1
0000
0000
0000
1110
1111
0000
0000
0000
0000
0000
0000
1111
1011
1001
1110
0000
0001
1110
1101
1100
1000
1010
kkkk
kkkk
kkkk
00ff
kkkk
0000
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
C, DC, Z, OV, N
Z, N
Z, N
None
None
None
None
None
C, DC, Z, OV, N
Z, N
DATA MEMORY PROGRAM MEMORY OPERATIONS
TBLRD*
TBLRD*+
TBLRD*-
TBLRD+*
TBLWT*
TBLWT*+
TBLWT*-
TBLWT+*
Table Read
Table Read with post-increment
Table Read with post-decrement
Table Read with pre-increment
Table Write
Table Write with post-increment
Table Write with post-decrement
Table Write with pre-increment
2
2
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
1000
1001
1010
1011
1100
1101
1110
1111
None
None
None
None
None
None
None
None
TA BLE 24-2: PIC18FXXXX INSTRUCTION SET (CONTINUED)
Mnemonic,
Operands Description Cycles 16-Bit Instruction Word Status
Affected Notes
MSb LSb
Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value
present on the pins themselves. For example, if the data lat ch is ‘1’ for a pin configured as input and is driven low by an
external device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and where applicable, ‘d’ = 1), the prescaler will be cleared if
assigned.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless
the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program mem-
ory locations have a valid instruction.
PIC18F2XK20/4XK20
DS40001303G-page 302 2010-2015 Microchip Technology Inc.
24.1.1 STANDARD INSTRUCTION SET
ADDLW ADD literal to W
Syntax: ADDLW k
Operands: 0 k 255
Operation: (W) + k W
Status Affected: N, OV, C, DC, Z
Encoding: 0000 1111 kkkk kkkk
Description: The contents of W are added to the
8-bit literal ‘k’ and the result is placed in
W.
Words: 1
Cycles: 1
Q Cycle Activity :
Q1 Q2 Q3 Q4
Decode Read
literal ‘k’ Process
Data Wri te to W
Example:ADDLW 15h
Before Instruction
W = 10h
After Instruction
W = 25h
ADDWF ADD W to f
Syntax: ADDWF f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (W) + (f) dest
Status Affected: N, OV, C, DC, Z
Encoding: 0010 01da ffff ffff
Description: Add W to register ‘f’. If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’, the
result is stored back in register ‘f’
(default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR i s used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Ins tructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity :
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data Write to
destination
Example:ADDWF REG, 0, 0
Before Instruction
W = 17h
REG = 0C2h
After Instruction
W = 0D9h
REG = 0C2h
Note: All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in
symbolic addressing. If a label is used, the instruction fo rmat then becomes: {label} in struction argument(s).
2010-2015 Microchip Technology Inc. DS40001303G-page 303
PIC18F2XK20/4XK20
ADDWFC ADD W and CARRY bit to f
Syntax: ADDWFC f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (W) + (f) + (C) dest
Status Affected: N,OV, C, DC, Z
Encoding: 0010 00da ffff ffff
Description: Add W, the CARRY flag and data mem-
ory location ‘f’. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed in data memory location ‘f’.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this i nstruction operates
in In d e x e d L it e ra l Offset Ad d r e ssin g
mode whenever f 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity :
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data Write to
destination
Example:ADDWFC REG, 0, 1
Before Instruction
CARRY bit = 1
REG = 02h
W=4Dh
After Instruction
CARRY bit = 0
REG = 02h
W = 50h
ANDLW AND literal with W
Syntax: ANDLW k
Operands: 0 k 255
Operation: (W) .AND. k W
Status Affected: N, Z
Encoding: 0000 1011 kkkk kkkk
Description: The contents of W are AND’ed with the
8-bit literal ‘k’. The result is placed in W.
Words: 1
Cycles: 1
Q Cycle Activity :
Q1 Q2 Q3 Q4
Decode Read literal
‘k’ Proces s
Data Write to W
Example:ANDLW 05Fh
Before Instruction
W=A3h
After Instruction
W = 03h
PIC18F2XK20/4XK20
DS40001303G-page 304 2010-2015 Microchip Technology Inc.
ANDWF AND W with f
Syntax: ANDWF f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (W) .AND. (f) dest
Status Affected: N, Z
Encoding: 0001 01da ffff ffff
Description: The contents of W are AND’ed with
register ‘f’. If ‘d’ is ‘0’, the result is stored
in W. If ‘d’ is ‘1’, the result is stored back
in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR i s used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in In d e x e d L it e ra l Offset Ad d r e ssin g
mode whenever f 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity :
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data Write to
destination
Example:ANDWF REG, 0, 0
Before Instruction
W = 17h
REG = C2h
After Instruction
W = 02h
REG = C2h
BC Branch if Carry
Syntax: BC n
Operands: -128 n 127
Operation: if CARRY bit is ‘1’
(PC) + 2 + 2n PC
Status Affected: None
Encoding: 1110 0010 nnnn nnnn
Description: If the CARRY bit is ‘1’, then the program
will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruct ion.
Words: 1
Cycles: 1(2)
Q Cycle Activity :
If Jump: Q1 Q2 Q3 Q4
Decode Read literal
‘n’ Process
Data Write to PC
No
operation No
operation No
operation No
operation
If No Jump:
Q1 Q2 Q3 Q4
Decode Read literal
‘n’ Process
Data No
operation
Example:HERE BC 5
Before Instruction
PC = address (HERE)
After Instruction
If CARRY = 1;
PC = address (HERE + 12)
If CARRY = 0;
PC = address (HERE + 2)
2010-2015 Microchip Technology Inc. DS40001303G-page 305
PIC18F2XK20/4XK20
BCF Bit Clear f
Syntax: BCF f, b {,a}
Operands: 0 f 255
0 b 7
a [0,1]
Operation: 0 f<b>
Status Affected: None
Encoding: 1001 bbba ffff ffff
Description: Bit ‘b’ in register ‘f’ is cleared.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR i s used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in In d e x e d L it e ra l Offset Ad d r e ssin g
mode whenever f 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity :
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data Write
register ‘f’
Example:BCF FLAG_REG, 7, 0
Before Instruction
FLAG_REG = C 7h
After Instruction
FLAG_REG = 47h
BN Branch if Negative
Syntax: BN n
Operands: -128 n 127
Operation: if NEGATIVE bit is ‘1’
(PC) + 2 + 2n PC
Status Affected: None
Encoding: 1110 0110 nnnn nnnn
Description: If the NEGATIVE bit is ‘1’, then the
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruct ion.
Words: 1
Cycles: 1(2)
Q Cycle Activity :
If Jump: Q1 Q2 Q3 Q4
Decode Read literal
‘n’ Process
Data Write to PC
No
operation No
operation No
operation No
operation
If No Jump:
Q1 Q2 Q3 Q4
Decode Read literal
‘n’ Process
Data No
operation
Example:HERE BN Jump
Before Instruction
PC = address (HERE)
After Instruction
If NEGATIVE = 1;
PC = address (Jump)
If NEGATIVE = 0;
PC = address (HERE + 2)
PIC18F2XK20/4XK20
DS40001303G-page 306 2010-2015 Microchip Technology Inc.
BNC Branch if Not Carry
Syntax: BNC n
Operands: -128 n 127
Operation: if CARRY bit is ‘ 0’
(PC) + 2 + 2n PC
Status Affected: None
Encoding: 1110 0011 nnnn nnnn
Description: If the CARRY bit is ‘0’, then the program
will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
2-cycle instruction.
Words: 1
Cycles: 1(2)
Q Cycle Activity :
If Jump: Q1 Q2 Q3 Q4
Decode Read literal
‘n’ Process
Data Write to PC
No
operation No
operation No
operation No
operation
If No Jump:
Q1 Q2 Q3 Q4
Decode Read literal
‘n’ Process
Data No
operation
Example:HERE BNC Jump
Before Instruction
PC = address (HERE)
After Instruction
If CARRY = 0;
PC = address (Jump)
If CARRY = 1;
PC = address (HERE + 2)
BNN Branch if Not Negative
Syntax: BNN n
Operands: -128 n 127
Operation: if NEGATIVE bit is ‘0’
(PC) + 2 + 2n PC
Status Affected: None
Encoding: 1110 0111 nnnn nnnn
Description: If the NEGATIVE bit is ‘0’, then the
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
2-cycle instruction.
Words: 1
Cycles: 1(2)
Q Cycle Activity :
If Jump: Q1 Q2 Q3 Q4
Decode Read literal
‘n’ Process
Data Write to PC
No
operation No
operation No
operation No
operation
If No Jump:
Q1 Q2 Q3 Q4
Decode Read literal
‘n’ Process
Data No
operation
Example:HERE BNN Jump
Before Instruction
PC = address (HERE)
After Instruction
If NEGATIVE = 0;
PC = address (Jump)
If NEGATIVE = 1;
PC = address (HERE + 2)
2010-2015 Microchip Technology Inc. DS40001303G-page 307
PIC18F2XK20/4XK20
BNOV Branch if Not Overflow
Syntax: BNOV n
Operands: -128 n 127
Operation: if OVERFLOW bit is ‘0’
(PC) + 2 + 2n PC
Status Affected: None
Encoding: 1110 0101 nnnn nnnn
Description: If the OVERFLOW bit is ‘0’, then the
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
2-cycle instruction.
Words: 1
Cycles: 1(2)
Q Cycle Activity :
If Jump: Q1 Q2 Q3 Q4
Decode Read literal
‘n’ Process
Data Write to PC
No
operation No
operation No
operation No
operation
If No Jump:
Q1 Q2 Q3 Q4
Decode Read literal
‘n’ Process
Data No
operation
Example:HERE BNOV Jump
Before Instruction
PC = address (HERE)
After Instruction
If OVERFL OW= 0;
PC = address (Jump)
If OVERFL OW= 1;
PC = address (HERE + 2)
BNZ Branch if Not Zero
Syntax: BNZ n
Operands: -128 n 127
Operation: if ZERO bit is ‘0’
(PC) + 2 + 2n PC
Status Affected: None
Encoding: 1110 0001 nnnn nnnn
Description: If the ZERO bit is ‘0’, then the program
will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
2-cycle instruction.
Words: 1
Cycles: 1(2)
Q Cycle Activity :
If Jump: Q1 Q2 Q3 Q4
Decode Read literal
‘n’ Process
Data Write to PC
No
operation No
operation No
operation No
operation
If No Jump:
Q1 Q2 Q3 Q4
Decode Read literal
‘n’ Process
Data No
operation
Example:HERE BNZ Jump
Before Instruction
PC = address (HERE)
After Instruction
If ZERO = 0;
PC = address (Jump)
If ZERO = 1;
PC = address (HERE + 2)
PIC18F2XK20/4XK20
DS40001303G-page 308 2010-2015 Microchip Technology Inc.
BRA Unconditional Branch
Syntax: BRA n
Operands: -1024 n 1023
Operation: (PC) + 2 + 2n PC
Status Affected: None
Encoding: 1101 0nnn nnnn nnnn
Description: Add the 2’s complement number ‘2n’ to
the PC. Since the PC will have incre-
mented to fetch the next instruction, the
new address will be PC + 2 + 2n. This
instruction is a 2-cycle instruction.
Words: 1
Cycles: 2
Q Cycle Activity :
Q1 Q2 Q3 Q4
Decode Read literal
‘n’ Process
Data Write to PC
No
operation No
operation No
operation No
operation
Example:HERE BRA Jump
Before Instruction
PC = address (HERE)
After Instruction
PC = address (Jump)
BSF Bit Set f
Syntax: BSF f, b {,a}
Operands: 0 f 255
0 b 7
a [0,1]
Operation: 1 f<b>
Status Affected: None
Encoding: 1000 bbba ffff ffff
Description: Bit ‘b’ in register ‘f’ is set.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR i s used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Ins tructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity :
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data Write
register ‘f’
Example:BSF FLAG_REG, 7, 1
Before Instruction
FLAG_REG = 0Ah
After Instruction
FLAG_REG = 8Ah
2010-2015 Microchip Technology Inc. DS40001303G-page 309
PIC18F2XK20/4XK20
BTFSC Bit Test File, Skip if Clear
Syntax: BTFSC f, b {,a}
Operands: 0 f 255
0 b 7
a [0,1]
Operation: skip if (f<b>) = 0
Status Affected: None
Encoding: 1011 bbba ffff ffff
Description: If bit ‘b’ in register ‘f’ is ‘0’, then the next
instruction is skipped. If bit ‘b’ is ‘0’, then
the next instruction fetched during the
current instruction execution is discarded
and a NOP is executed instead, making
this a 2-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected. If
‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates in
Indexed Literal Offset Addressing
mode whenever f 95 (5Fh).
See Section 24.2.3 “Byte-Orien ted and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity :
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data No
operation
If skip: Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
No
operation No
operation No
operation No
operation
Example:HERE
FALSE
TRUE
BTFSC
:
:
FLAG, 1, 0
Before Instruction
PC = address (HERE)
After Instruction
If FLAG<1> = 0;
PC = address (TRUE)
If FLAG<1> = 1;
PC = address (FALSE)
BTFSS Bit Test File, Skip if Set
Syntax: BTFSS f, b {,a}
Operands: 0 f 255
0 b < 7
a [0,1]
Operation: skip if (f<b>) = 1
Status Affected: None
Encoding: 1010 bbba ffff ffff
Description: If bit ‘b’ in register ‘f’ is ‘1’, then the next
instruction is skipped. If bit ‘b’ is ‘1’, then
the next instruction fetched during the
current instruction execution is discarded
and a NOP is executed instead, making
this a 2-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is s elec ted. If
‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh).
See Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructio ns in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity :
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data No
operation
If skip: Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
No
operation No
operation No
operation No
operation
Example:HERE
FALSE
TRUE
BTFSS
:
:
FLAG, 1, 0
Before Instruction
PC = address (HERE)
After Instruction
If FLAG<1> = 0;
PC = address (FALSE)
If FLAG<1> = 1;
PC = address (TRUE)
PIC18F2XK20/4XK20
DS40001303G-page 310 2010-2015 Microchip Technology Inc.
BTG Bit Toggle f
Syntax: BTG f, b {,a}
Operands: 0 f 255
0 b < 7
a [0,1]
Operation: (f<b>) f<b>
Status Affected: None
Encoding: 0111 bbba ffff ffff
Description: Bit ‘b’ in data mem ory location ‘f’ is
inverted.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity :
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data Write
register ‘f’
Example:BTG PORTC, 4, 0
Before Instruction:
PORTC = 0111 0101 [75h]
After Instruction:
PORTC = 0110 0101 [65h]
BOV Branch if Overflow
Syntax: BOV n
Operands: -128 n 127
Operation: if OVERFLOW bit is ‘1’
(PC) + 2 + 2n PC
Status Affected: None
Encoding: 1110 0100 nnnn nnnn
Description: If the OVERFLOW bit is ‘1’, then the
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
2-cycle instruction.
Words: 1
Cycles: 1(2)
Q Cycle Activity :
If Jump: Q1 Q2 Q3 Q4
Decode Read literal
‘n’ Process
Data Write to PC
No
operation No
operation No
operation No
operation
If No Jump:
Q1 Q2 Q3 Q4
Decode Read literal
‘n’ Process
Data No
operation
Example:HERE BOV Jump
Before Instruction
PC = address (HERE)
After Instruction
If OVERFL OW= 1;
PC = address (Jump)
If OVERFL OW= 0;
PC = address (HERE + 2)
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PIC18F2XK20/4XK20
BZ Branch if Zero
Syntax: BZ n
Operands: -128 n 127
Operation: if ZERO bit is ‘1’
(PC) + 2 + 2n PC
Status Affected: None
Encoding: 1110 0000 nnnn nnnn
Description: If the ZERO bit is ‘1’, then the program
will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
2-cycle instruction.
Words: 1
Cycles: 1(2)
Q Cycle Activity :
If Jump: Q1 Q2 Q3 Q4
Decode Read literal
‘n’ Process
Data Write to PC
No
operation No
operation No
operation No
operation
If No Jump:
Q1 Q2 Q3 Q4
Decode Read literal
‘n’ Process
Data No
operation
Example:HERE BZ Jump
Before Instruction
PC = address (HERE)
After Instruction
If ZERO = 1;
PC = address (Jump)
If ZERO = 0;
PC = address (HERE + 2)
CALL Subroutine Call
Syntax: CALL k {,s}
Operands: 0 k 1048575
s [0,1]
Operation: (PC) + 4 TOS,
k PC<20:1>,
if s = 1
(W) WS,
(S tatus) STAT USS,
(BSR) BSRS
Status Affected: None
Encoding:
1st word (k<7:0>)
2nd word(k<19:8>) 1110
1111 110s
k19kkk k7kkk
kkkk kkkk0
kkkk8
Description: Subroutine call of entire 2-Mbyte
memory range. First, return address
(PC + 4) is pushed onto the return
stack. If ‘s’ = 1, the W, Status and BSR
registers are also pushed into their
respective shadow registers, WS,
STATUSS and BSRS. If ‘s’ = 0, no
update occurs (default). Then, the
20-bit value ‘k’ is loaded into PC<20:1>.
CALL is a 2-cycle instruction.
Words: 2
Cycles: 2
Q Cycle Activity :
Q1 Q2 Q3 Q4
Decode Read literal
‘k’<7:0>, PUSH PC to
stack Read literal
‘k’<19:8>,
Write to PC
No
operation No
operation No
operation No
operation
Example:HERE CALL THERE, 1
Before Instruction
PC = address (HERE)
After Instruction
PC = address (THERE)
TOS = address (HERE + 4)
WS = W
BSRS = BSR
STATUSS= Status
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CLRF Clear f
Syntax: CLRF f {,a}
Operands: 0 f 255
a [0,1]
Operation: 000h f
1 Z
Status Affected: Z
Encoding: 0110 101a ffff ffff
Description: Clears the contents of the specified
register.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR i s used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in In d e x e d L it e ra l Offset Ad d r e ssin g
mode whenever f 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity :
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data Write
register ‘f’
Example:CLRF FLAG_REG, 1
Before Instruction
FLAG_REG = 5Ah
After Instruction
FLAG_REG = 00h
CLRWDT Clear Watchdog Timer
Syntax: CLRWDT
Operands: None
Operation: 000h WDT,
000h WDT postscaler,
1 TO,
1 PD
Status Affected: T O, PD
Encoding: 0000 0000 0000 0100
Description: CLRWDT instruction resets the
Watchdog Timer. It also resets the post-
scaler of the WDT. Status bits, TO and
PD, are set.
Words: 1
Cycles: 1
Q Cycle Activity :
Q1 Q2 Q3 Q4
Decode No
operation Process
Data No
operation
Example:CLRWDT
Before Instruction
WDT Counter = ?
After Instruction
WDT Counter = 00h
WDT Postscaler = 0
TO =1
PD =1
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PIC18F2XK20/4XK20
COMF Complement f
Syntax: COMF f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f) dest
Status Affected: N, Z
Encoding: 0001 11da ffff ffff
Description: The contents of register ‘f’ are
complemented. If ‘d’ is ‘0’, the result is
stored in W. If ‘d’ is ‘1’, the result is
stored back in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR i s used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in In d e x e d L it e ra l Offset Ad d r e ssin g
mode whenever f 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity :
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data Write to
destination
Example:COMF REG, 0, 0
Before Instruction
REG = 13h
After Instruction
REG = 13h
W=ECh
CPFSEQ Compare f with W, skip if f = W
Syntax: CPFSEQ f {,a}
Operands: 0 f 255
a [0,1]
Operation: (f) – (W),
skip if (f) = (W)
(unsigned comparison)
Status Affected: None
Encoding: 0110 001a ffff ffff
Description: Compares the contents of data memory
location ‘f’ to the contents of W by
performing an unsigned subtraction.
If ‘f’ = W, then the fetched instruction is
discarded and a NOP is execut ed
instead, making this a 2-cycle
instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR i s used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Ins tructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity :
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data No
operation
If skip: Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
No
operation No
operation No
operation No
operation
Example:HERE CPFSEQ REG, 0
NEQUAL :
EQUAL :
Before Instruction
PC Address = HERE
W=?
REG = ?
After Instruction
If REG = W;
PC = Address (EQUAL)
If REG W;
PC = Address (NEQUAL)
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CPFSGT Compare f with W, skip if f > W
Syntax: CPFSGT f {,a}
Operands: 0 f 255
a [0,1]
Operation: (f) –W),
skip if (f) > (W)
(unsigned comparison)
Status Affected: None
Encoding: 0110 010a ffff ffff
Description: Compares the contents of data memory
location ‘f’ to the contents of the W by
performing an unsigned subtraction.
If the contents of ‘f’ are greater than the
contents of WREG, then the fetched
instruction is discarded and a NOP is
executed instead, making this a
2-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR i s used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in In d e x e d L it e ra l Offset Ad d r e ssin g
mode whenever f 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity :
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data No
operation
If skip: Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
No
operation No
operation No
operation No
operation
Example:HERE CPFSGT REG, 0
NGREATER :
GREATER :
Before Instruction
PC = Address (HERE)
W= ?
After Instruction
If REG W;
PC = Address (GREATER)
If REG W;
PC = Address (NGREATER)
CPFSLT Compare f with W, skip if f < W
Syntax: CPFSLT f {,a}
Operands: 0 f 255
a [0,1]
Operation: (f) –W),
skip if (f) < (W)
(unsigned comparison)
Status Affected: None
Encoding: 0110 000a ffff ffff
Description: Compares the contents of data memory
location ‘f’ to the contents of W by
performing an unsigned subtraction.
If the contents of ‘f’ are less than the
contents of W, then the fetched
instruction is discarded and a NOP is
executed instead, making this a
2-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR i s used to select the
GPR bank.
Words: 1
Cycles: 1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity :
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data No
operation
If skip: Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
No
operation No
operation No
operation No
operation
Example:HERE CPFSLT REG, 1
NLESS :
LESS :
Before Instruction
PC = Address (HERE)
W= ?
After Instruction
If REG < W;
PC = Address (LESS)
If REG W;
PC = Address (NLESS)
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PIC18F2XK20/4XK20
DAW Decimal Adjust W Register
Syntax: DAW
Operands: None
Operation: If [W<3:0> > 9] or [DC = 1] then
(W<3:0>) + 6 W<3:0>;
else
(W<3:0>) W<3:0>;
If [W<7:4> + DC > 9] or [C = 1] then
(W<7:4>) + 6 + DC W<7:4>;
else
(W<7:4>) + DC W<7:4>
Status Affected: C
Encoding: 0000 0000 0000 0111
Description: DAW adjusts the 8-bit value in W, result-
ing from the earlier addition of two vari-
ables (each in packed BCD format) and
produces a correct packed BCD result.
Words: 1
Cycles: 1
Q Cycle Activity :
Q1 Q2 Q3 Q4
Decode Read
register W Process
Data Write
W
Example1:
DAW
Before Instruction
W=A5h
C=0
DC = 0
After Instruction
W = 05h
C=1
DC = 0
Example 2:
Before Instruction
W=CEh
C=0
DC = 0
After Instruction
W = 34h
C=1
DC = 0
DECF Decrement f
Syntax: DECF f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f) – 1 dest
Status Affected: C, DC, N, OV, Z
Encoding: 0000 01da ffff ffff
Description: Decrement register ‘f ’. If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’, the
result is stored back in register ‘f’
(default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR i s used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Ins tructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity :
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data Write to
destination
Example:DECF CNT, 1, 0
Before Instruction
CNT = 01h
Z=0
After Instruction
CNT = 00h
Z=1
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DECFSZ Decrement f, skip if 0
Syntax: DECF SZ f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f) – 1 dest,
skip if result = 0
Status Affected: None
Encoding: 0010 11da ffff ffff
Description: The contents of register ‘f’ are
decremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
If the result is ‘0’, the next instruction,
which is already fetched, is discarded
and a NOP is executed instead, making
it a 2-cycle instruction.
If ‘a’ is ‘0’ , the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in In d e x e d L it e ra l Offset Ad d r e ssin g
mode whenever f 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity :
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data Write to
destination
If skip: Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
No
operation No
operation No
operation No
operation
Example:HERE DECFSZ CNT, 1, 1
GOTO LOOP
CONTINUE
Before Instruction
PC = Address (HERE)
After Instruction
CNT = CNT - 1
If CNT = 0;
PC = Address (CONTINUE)
If CNT 0;
PC = Address (HERE + 2)
DCFSNZ Decrement f, skip if not 0
Syntax: DCFSNZ f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f) – 1 dest,
skip if result 0
Status Affected: None
Encoding: 0100 11da ffff ffff
Description: The contents of register ‘f’ are
decremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
If the result is not ‘0’, the next
instruction, which is already fetched, is
discarded and a NOP is executed
instead, making it a 2-cycle
instruction.
If ‘a’ is ‘0’ , the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Ins tructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity :
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data Write to
destination
If skip: Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
No
operation No
operation No
operation No
operation
Example:HERE DCFSNZ TEMP, 1, 0
ZERO :
NZERO :
Before Instruction
TEMP = ?
After Instruction
TEMP = TEM P – 1,
If TEMP = 0;
PC = Address (ZERO)
If TEMP 0;
PC = Address (NZERO)
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PIC18F2XK20/4XK20
GOTO Unconditional Branch
Syntax: GOTO k
Operands: 0 k 1048575
Operation: k PC<20:1>
Status Affected: None
Encoding:
1st word (k<7:0>)
2nd word(k<19:8>) 1110
1111 1111
k19kkk k7kkk
kkkk kkkk0
kkkk8
Description: GOTO allows an unconditional branch
anywhere within entire
2-Mbyte memory range. The 20-bit
value ‘k’ is loaded into PC<20:1>.
GOTO is always a 2-cycle
instruction.
Words: 2
Cycles: 2
Q Cycle Activity :
Q1 Q2 Q3 Q4
Decode Read literal
‘k’<7:0>, No
operation Read literal
‘k’<19:8>,
Write to PC
No
operation No
operation No
operation No
operation
Example:GOTO THERE
After Instruction
PC = Address (THERE)
INCF Increm ent f
Syntax: INCF f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f) + 1 dest
Status Affected: C, DC, N, OV, Z
Encoding: 0010 10da ffff ffff
Description: The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR i s used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Ins tructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity :
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data Write to
destination
Example:INCF CNT, 1, 0
Before Instruction
CNT = FFh
Z=0
C=?
DC = ?
After Instruction
CNT = 00h
Z=1
C=1
DC = 1
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INCFSZ Increment f, skip if 0
Syntax: INCFSZ f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f) + 1 dest,
skip if result = 0
Status Affected: None
Encoding: 0011 11da ffff ffff
Description: The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
If the result is ‘0’, the next instruction,
which is already fetched, is discarded
and a NOP is executed instead, making
it a 2-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR i s used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in In d e x e d L it e ra l Offset Ad d r e ssin g
mode whenever f 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity :
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data Write to
destination
If skip: Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
No
operation No
operation No
operation No
operation
Example:HERE INCFSZ CNT, 1, 0
NZERO :
ZERO :
Before Instruction
PC = Address (HERE)
After Instruction
CNT = CNT + 1
If CNT = 0;
PC = Address (ZERO)
If CNT 0;
PC = Address (NZERO)
INFSNZ Increment f, skip if not 0
Syntax: INFSNZ f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f) + 1 dest,
skip if result 0
Status Affected: None
Encoding: 0100 10da ffff ffff
Description: The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
If the result is not ‘0’, the next
instruction, which is already fetched, is
discarded and a NOP is executed
instead, making it a 2-cycle
instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR i s used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Ins tructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity :
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data Write to
destination
If skip: Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
No
operation No
operation No
operation No
operation
Example:HERE INFSNZ REG, 1, 0
ZERO
NZERO
Before Instruction
PC = Address (HERE)
After Instruction
REG = REG + 1
If REG 0;
PC = Address (NZERO)
If REG = 0;
PC = Address (ZERO)
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IORLW Inclusive OR literal with W
Syntax: IORLW k
Operands: 0 k 255
Operation: (W) .OR. k W
Status Affected: N, Z
Encoding: 0000 1001 kkkk kkkk
Description: The contents of W are ORed with the
8-bit literal ‘k’. The result is placed in W.
Words: 1
Cycles: 1
Q Cycle Activity :
Q1 Q2 Q3 Q4
Decode Read
literal ‘k’ Process
Data Write to W
Example:IORLW 35h
Before Instruction
W=9Ah
After Instruction
W=BFh
IORWF Inclusive OR W with f
Syntax: IORWF f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (W) .OR. (f) dest
Status Affected: N, Z
Encoding: 0001 00da ffff ffff
Description: Inclusive OR W with register ‘f’. If ‘d’ is
‘0’, the result is placed in W. If ‘d’ is ‘1’,
the result is placed back in register ‘f ’
(default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR i s used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Ins tructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity :
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data Write to
destination
Example:IORWF RESULT, 0, 1
Before Instruction
RESULT = 13h
W = 91h
After Instruction
RESULT = 13h
W = 93h
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LFSR Load FSR
Syntax: LFSR f, k
Operands: 0 f 2
0 k 4095
Operation: k FSRf
Status Affected: None
Encoding: 1110
1111 1110
0000 00ff
k7kkk k11kkk
kkkk
Description: The 12-bit literal ‘k’ is loaded into the
File Select Register pointed to by ‘f’.
Words: 2
Cycles: 2
Q Cycle Activity :
Q1 Q2 Q3 Q4
Decode Read literal
‘k’ MSB Process
Data Write
literal ‘k’
MSB to
FSRfH
Decode Read literal
‘k’ L S B Process
Data Write literal
‘k’ to FSRfL
Example:LFSR 2, 3ABh
After Instruction
FSR2H = 03h
FSR2L = ABh
MOVF Move f
Syntax: MOVF f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: f dest
Status Affected: N, Z
Encoding: 0101 00da ffff ffff
Description: The contents of register ‘f’ are moved to
a destination dependent upon the
status of ‘d’. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
Location ‘f’ can be anywhere in the
256-byte bank.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR i s used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Ins tructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity :
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data Write W
Example:MOVF REG, 0, 0
Before Instruction
REG = 22h
W=FFh
After Instruction
REG = 22h
W = 22h
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PIC18F2XK20/4XK20
MOVFF Move f to f
Syntax: MOVFF fs,fd
Operands: 0 fs 4095
0 fd 4095
Operation: (fs) fd
Status Affected: None
Encoding:
1st word (source)
2nd word (destin.) 1100
1111 ffff
ffff ffff
ffff ffffs
ffffd
Description: The contents of source register ‘fs’ are
moved to destination register ‘fd’.
Location of source ‘f s’ can be anywhere
in the 4096-byte data space (000h to
FFFh) and location of destination ‘fd’
can also be anywhere from 000h to
FFFh.
Either source or destination can be W
(a useful special situation).
MOVFF is particularly useful for
transferring a data memory location t o a
peripheral register (such as the transmit
buffer or an I/O port).
The MOVFF instruction cannot use the
PCL, TOSU, TOSH or TOSL as the
destination register.
Words: 2
Cycles: 2 (3)
Q Cycle Activity :
Q1 Q2 Q3 Q4
Decode Read
register ‘f’
(src)
Process
Data No
operation
Decode No
operation
No dummy
read
No
operation Write
register ‘f’
(dest)
Example:MOVFF REG1, REG2
Before Instruction
REG1 = 33h
REG2 = 11h
After Instruction
REG1 = 33h
REG2 = 33h
MOVLB Move litera l to low nibbl e in BSR
Syntax: MOVLW k
Operands: 0 k 255
Operation: k BSR
Status Affected: None
Encoding: 0000 0001 kkkk kkkk
Description: The 8-bit literal ‘k’ is loaded into the
Bank Select Register (BSR). The value
of BSR<7:4> always remains ‘0’,
regardless of the value of k7:k4.
Words: 1
Cycles: 1
Q Cycle Activity :
Q1 Q2 Q3 Q4
Decode Read
literal ‘k’ Process
Data W rite literal
‘k’ to BSR
Example:MOVLB 5
Before Instruction
BSR Register = 02h
After Instruction
BSR Register = 05h
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MOVLW Move literal to W
Syntax: MOVLW k
Operands: 0 k 255
Operation: k W
Status Affected: None
Encoding: 0000 1110 kkkk kkkk
Description: The 8-bit literal ‘k’ is loaded into W.
Words: 1
Cycles: 1
Q Cycle Activity :
Q1 Q2 Q3 Q4
Decode Read
literal ‘k’ Process
Data Write to W
Example:MOVLW 5Ah
After Instruction
W=5Ah
MOVWF Move W to f
Syntax: MOVWF f {,a}
Operands: 0 f 255
a [0,1 ]
Operation: (W) f
Status Affected: None
Encoding: 0110 111a ffff ffff
Description: Move data from W to register ‘f’.
Location ‘f’ can be anywhere in the
256-byte bank.
If ‘a’ is ‘0’, the Access Bank is selec ted.
If ‘a’ is ‘1’, t he BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Index ed
Literal Offset Mod e” for details.
Words: 1
Cycles: 1
Q Cycle Activity :
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data Write
register ‘f’
Example:MOVWF REG, 0
Before Instruction
W=4Fh
REG = FFh
After Instruction
W=4Fh
REG = 4Fh
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PIC18F2XK20/4XK20
MULLW Multiply literal with W
Syntax: MULLW k
Operands: 0 k 255
Operation: (W ) x k PRO D H : PRODL
Status Affected: None
Encoding: 0000 1101 kkkk kkkk
Description: An unsigned multiplication is carried
out between the contents of W and the
8-bit literal ‘k’. The 16-bit result is
placed in the PRODH:PRODL register
pair. PRODH contains the high byte.
W is unchanged.
None of the Status flags are affected.
Note that neither overflow nor carry is
possible in this operation. A zero result
is possible but not detected.
Words: 1
Cycles: 1
Q Cycle Activity :
Q1 Q2 Q3 Q4
Decode Read
literal ‘k’ Process
Data Write
registers
PRODH:
PRODL
Example:MULLW 0C4h
Before Instruction
W=E2h
PRODH = ?
PRODL = ?
After Instruction
W=E2h
PRODH = ADh
PRODL = 08h
MULWF Multiply W with f
Syntax : MULWF f {,a}
Operands: 0 f 255
a [0,1]
Operation: (W) x (f) PRODH:PRODL
Status Affected: None
Encoding: 0000 001a ffff ffff
Description: An unsigned multiplication is carried
out between the contents of W and the
register file location ‘f’. The 16-bit
result is stored in the PRODH:PRODL
register pair. PRODH contains the
high byte. Both W and ‘f’ are
unchanged.
None of the Status flags are affected.
Note that neither overflow nor carry is
possible in this operation. A zero
result is possible but not detected.
If ‘a’ is ‘0’, the Access Bank is
selected. If ‘a’ is ‘1’, the BSR is used
to select the GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction
operates in Indexed Literal Offset
Addressing mode whenever
f 95 (5Fh). See Section 24.2.3
“Byte-Oriented and Bit-Oriented
Instructions in Indexed Literal Offset
Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity :
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data Write
registers
PRODH:
PRODL
Example:MULWF REG, 1
Before Instruction
W=C4h
REG = B5h
PRODH = ?
PRODL = ?
After Instruction
W=C4h
REG = B5h
PRODH = 8Ah
PRODL = 94h
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NEGF Negate f
Syntax: NEG F f {,a}
Operands: 0 f 255
a [0,1]
Operation: ( f ) + 1 f
Status Affected: N, OV, C, DC, Z
Encoding: 0110 110a ffff ffff
Description: Location ‘f’ is negated using two’s
complement. The result is placed in the
data memory location ‘f’.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Liter a l Offset Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity :
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data Write
register ‘f’
Example:NEGF REG, 1
Before Instruction
REG = 0011 1010 [3Ah]
After Instruction
REG = 1100 0110 [C6h]
NOP No Operation
Syntax: NOP
Operands: None
Operation: No operation
Status Affected: None
Encoding: 0000
1111 0000
xxxx 0000
xxxx 0000
xxxx
Description: No operation.
Words: 1
Cycles: 1
Q Cycle Activity :
Q1 Q2 Q3 Q4
Decode No
operation No
operation No
operation
Example:
None.
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PIC18F2XK20/4XK20
POP Pop Top of Return Stack
Syntax: POP
Operands: None
Operation: (TOS) bit bucket
Status Affected: None
Encoding: 0000 0000 0000 0110
Description: The TOS value is pulled off the return
stack and is discarded. The TOS value
then becomes the previous value that
was pushed onto the return stack.
This instruction is provided to enable
the user to properly manage the return
stack to incorporate a software stack.
Words: 1
Cycles: 1
Q Cycle Activity :
Q1 Q2 Q3 Q4
Decode No
operation POP TOS
value No
operation
Example:POP
GOTO NEW
Before Instruction
TOS = 0031A2h
Stack (1 level down) = 014332h
After Instruction
TOS = 014332h
PC = NEW
PUSH Push Top of Return Stack
Syntax: PUSH
Operands: None
Operation: (PC + 2) TOS
Status Affected: None
Encoding: 0000 0000 0000 0101
Description: The PC + 2 is pushed onto the top of
the return stack. The previous TOS
value is pushed down on the stack.
This instruction allows implementing a
software stack by modifying TOS and
then pushing it onto the return stack.
Words: 1
Cycles: 1
Q Cycle Activity :
Q1 Q2 Q3 Q4
Decode PUSH
PC + 2 onto
return stack
No
operation No
operation
Example:PUSH
Before Instruction
TOS = 345Ah
PC = 0124h
After Instruction
PC = 0126h
TOS = 0126h
Stack (1 level down) = 345Ah
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RCALL Relative Call
Syntax: RCALL n
Operands: -1024 n 1023
Operation: (PC) + 2 TOS,
(PC) + 2 + 2n PC
Status Affected: None
Encoding: 1101 1nnn nnnn nnnn
Description: Subroutine call with a jump up to 1K
from the current location. First, return
address (PC + 2) is pushed onto the
stack. Then, add the 2’s complement
number ‘2n’ to the PC. S ince the PC will
have incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is a
2-cycle instruction.
Words: 1
Cycles: 2
Q Cycle Activity :
Q1 Q2 Q3 Q4
Decode Read literal
‘n’
PUSH PC to
stack
Process
Data Write to PC
No
operation No
operation No
operation No
operation
Example:HERE RCALL Jump
Before Instruction
PC = Address (HERE)
After Instruction
PC = Address (Jump)
TOS = Address (HERE + 2)
RESET Reset
Syntax: RESET
Operands: None
Operation: Reset all registers and flags that are
affected by a MCLR Reset.
Status Affected: All
Encoding: 0000 0000 1111 1111
Description: This instruction provides a way to
execute a MCLR Rese t b y so ftw a re.
Words: 1
Cycles: 1
Q Cycle Activity :
Q1 Q2 Q3 Q4
Decode Start
Reset No
operation No
operation
Example:RESET
After Instruction
Registers = Reset Value
Flags* = Reset Value
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PIC18F2XK20/4XK20
RETFIE Return from Interrupt
Syntax: RETFIE {s}
Operands: s [0,1]
Operation: (TOS) PC,
1 GIE/GI EH o r PEIE/GIEL,
if s = 1
(WS) W,
(STATUSS) Status,
(BSRS) BSR,
PCLATU, PCLATH are unchanged.
Status Affected: GIE/GIEH, PEIE/GIEL.
Encoding: 0000 0000 0001 000s
Description: Return from interrupt. Stack is popped
and Top-of-Stac k (TOS) is loaded into
the PC. Interrupts are enabled by
setting either the high or low priority
global interrupt enable bit. If ‘s’ = 1, the
contents of the shadow registers, WS,
STATUSS and BSRS, are loaded into
their corresponding registers, W,
Status and BSR. If ‘s’ = 0, no update of
these registers occurs (default).
Words: 1
Cycles: 2
Q Cycle Activity :
Q1 Q2 Q3 Q4
Decode No
operation No
operation POP PC
from stack
Set GIEH or
GIEL
No
operation No
operation No
operation No
operation
Example:RETFIE 1
After Interrupt
PC = TOS
W=WS
BSR = BSRS
Status = STATUSS
GIE/ GIEH, PEIE/GIEL = 1
RETLW Return literal to W
Syntax: RETLW k
Operands: 0 k 255
Operation: k W,
(TOS) PC,
PCLATU, PCLATH are unchanged
Status Affected: None
Encoding: 0000 1100 kkkk kkkk
Description: W is loaded with the 8-bit literal ‘k’. The
program counter is loaded from the top
of the stack (the return address). The
high address latch (PCLATH) remains
unchanged.
Words: 1
Cycles: 2
Q Cycle Activity :
Q1 Q2 Q3 Q4
Decode Read
literal ‘k’ Process
Data POP PC
from stack,
Write to W
No
operation No
operation No
operation No
operation
Example:
CALL TABLE ; W contains table
; offset value
; W now has
; table value
:
TABLE
ADDWF PCL ; W = offset
RETLW k0 ; Begin table
RETLW k1 ;
:
:RETLW kn ; End of table
Before Instruction
W = 07h
After Instruction
W = value of kn
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RETURN Return from Subroutine
Syntax: RETURN {s}
Operands: s [0,1]
Operation: (TOS) PC,
if s = 1
(WS) W,
(STAT USS) Status,
(BSRS) BSR ,
PCLATU, PCLATH are unchanged
Status Affected: None
Encoding: 0000 0000 0001 001s
Description: Return from subroutine. The stack is
popped and the top of the stack (TOS)
is loaded into the program counter. If
‘s’= 1, the contents of the shadow
registers, WS, STATUS S and BSRS,
are loaded into their corresponding
registers, W, Status and BSR. If
‘s’ = 0, no update of these registers
occurs (default).
Words: 1
Cycles: 2
Q Cycle Activity :
Q1 Q2 Q3 Q4
Decode No
operation Process
Data POP PC
from stack
No
operation No
operation No
operation No
operation
Example:RETURN
After Instruction:
PC = TOS
RLCF Rotate Left f through Carry
Syntax: RLCF f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f<n>) dest<n + 1>,
(f<7>) C,
(C) dest<0>
Status Affected: C, N, Z
Encoding: 0011 01da ffff ffff
Description: The contents of register ‘f’ are rotated
one bit to the left through the CARRY
flag. If ‘d’ is ‘0’, the result is placed in
W. If ‘d’ is ‘1’, the result is stored back
in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is
selected. If ‘a’ is ‘1’, the BSR is used to
select the GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction
operates in Indexed Literal Offset
Addressing mode whenever
f 95 (5F h). See Section 24.2.3
“Byte-Oriented and Bit-Oriented
Instructions in Indexed Literal Offset
Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity :
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data Write to
destination
Example:RLCF REG, 0, 0
Before Instruction
REG = 1110 0110
C=0
After Instruction
REG = 1110 0110
W=1100 1100
C=1
Cregister f
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PIC18F2XK20/4XK20
RLNCF Rotate Left f (No Carry)
Syntax: RLNCF f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f<n>) dest<n + 1>,
(f<7>) dest<0>
Status Affected: N, Z
Encoding: 0100 01da ffff ffff
Description: The contents of register ‘f’ are rotated
one bit to the left. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result is
stored back in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5F h). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructi ons in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity :
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data Write to
destination
Example:RLNCF REG, 1, 0
Before Instruction
REG = 1010 1011
After Instruction
REG = 0101 0111
register f
RRCF Rotate Right f through Carry
Syntax: RRCF f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f<n>) dest<n – 1>,
(f<0>) C,
(C) dest<7>
Status Affected: C, N, Z
Encoding: 0011 00da ffff ffff
Description: The contents of register ‘f’ are rotated
one bit to the right through the CARRY
flag. If ‘d’ is ‘0’, the result is placed in W.
If ‘d’ is ‘1’, the result is placed back in
register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR i s used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Ins tructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity :
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data Write to
destination
Example:RRCF REG, 0, 0
Before Instruction
REG = 1110 0110
C=0
After Instruction
REG = 1110 0110
W=0111 0011
C=0
Cregister f
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RRNCF Rotate Right f (No Carry)
Syntax: RRNCF f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f<n>) dest<n – 1>,
(f<0>) dest<7>
Status Affected: N, Z
Encoding: 0100 00da ffff ffff
Description: The contents of register ‘f’ are rotated
one bit to the right. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank will be
selected (default), overriding the BSR
value. If ‘a’ is ‘1’, then the bank will be
selected as per the BSR value.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in In d e x e d L it e ra l Offset Ad d r e ssin g
mode whenever f 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity :
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data Write to
destination
Example 1:RRNCF REG, 1, 0
Before Instruction
REG = 1101 0111
After Instruction
REG = 1110 1011
Example 2:RRNCF REG, 0, 0
Before Instruction
W=?
REG = 1101 0111
After Instruction
W=1110 1011
REG = 1101 0111
register f
SETF Set f
Syntax: SETF f {,a}
Operands: 0 f 255
a [0,1]
Operation: FFh f
Status Affected: None
Encoding: 0110 100a ffff ffff
Description: The contents of the specified register
are set to FFh.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR i s used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Ins tructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity :
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data Write
register ‘f’
Example:SETF REG, 1
Before Instruction
REG = 5Ah
After Instruction
REG = FFh
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PIC18F2XK20/4XK20
SLEEP Enter Sleep mode
Syntax: SLEEP
Operands: None
Operation: 00h WDT,
0 WDT postscaler,
1 TO ,
0 PD
Status Affected: TO, PD
Encoding: 0000 0000 0000 0011
Description: The Power-down Status bit (PD) is
cleared. The Time-out Status bit (TO )
is set. Watchdog Timer and its
postscaler are cleared.
The processor is put into Sleep mode
with the oscillator stopped.
Words: 1
Cycles: 1
Q Cycle Activity :
Q1 Q2 Q3 Q4
Decode No
operation Process
Data Go to
Sleep
Example:SLEEP
Before Instruction
TO =?
PD =?
After Instruction
TO =1 †
PD =0
† If WDT causes wake-up, this bit is cleared.
SUBFWB Subtract f from W with borrow
Syntax: SUBFWB f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (W ) – (f) – (C) dest
Status Affected: N, OV, C, DC, Z
Encoding: 0101 01da ffff ffff
Description: Subtract register ‘f’ and CARRY flag
(borrow) from W (2’s complement
method). If ‘d’ is ‘0’, the result is stored
in W. If ‘d’ is ‘1’, the result is stored in
register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is
selected. If ‘a’ is ‘1’, the BSR is used
to select the GPR bank.
If ‘a’ is ‘0’ and t he extended instruction
set is enabled, this instruction
operates in Indexed Literal Offset
Addressing mode whenever
f 95 (5Fh). See Section 24.2.3
“Byte-Oriented and Bit-Oriented
Instructions in Indexed Literal Offset
Mode” f or details.
Words: 1
Cycles: 1
Q Cycle Activity :
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data Write to
destination
Example 1:SUBFWB REG, 1, 0
Before Instruction
REG = 3
W=2
C=1
After Instruction
REG = FF
W=2
C=0
Z=0
N = 1 ; result is negative
Example 2:SUBFWB REG, 0, 0
Before Instruction
REG = 2
W=5
C=1
After Instruction
REG = 2
W=3
C=1
Z=0
N = 0 ; result is positive
Example 3:SUBFWB REG, 1, 0
Before Instruction
REG = 1
W=2
C=0
After Instruction
REG = 0
W=2
C=1
Z = 1 ; result is zero
N=0
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SUBLW Subtract W from literal
Syntax: SUBLW k
Operands: 0 k 255
Operation: k – (W) W
Status Affected: N, OV, C, DC, Z
Encoding: 0000 1000 kkkk kkkk
Description W is subtracted from the 8-bit
literal ‘k’. The result is placed in W.
Words: 1
Cycles: 1
Q Cycle Activity :
Q1 Q2 Q3 Q4
Decode Read
literal ‘k’ Process
Data Write to W
Example 1: SUBLW 02h
Before Instruction
W = 01h
C=?
After Instruction
W = 01h
C = 1 ; result is positiv e
Z=0
N=0
Example 2:SUBLW 02h
Before Instruction
W = 02h
C=?
After Instruction
W = 00h
C = 1 ; result is ze ro
Z=1
N=0
Example 3:SUBLW 02h
Before Instruction
W = 03h
C=?
After Instruction
W = FFh ; (2 ’s comp leme nt)
C = 0 ; result is negative
Z=0
N=1
SUBWF Subtract W from f
Syntax: SUBWF f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f) – (W) dest
Status Affected: N, OV, C, DC, Z
Encoding: 0101 11da ffff ffff
Description: Subtract W fr om register ‘f ’ (2’s
complement method). If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’, the
result is stored back in register ‘f’
(default).
If ‘a’ is ‘0’, the Access Bank is
selected. If ‘a’ is ‘1’, the BSR is used
to select the GPR bank.
If ‘a’ is ‘0’ and t he extended instruction
set is enabled, this instruction
operates in Indexed Literal Offset
Addressing mode whenever
f 95 (5Fh). See Section 24.2.3
“Byte-Oriented and Bit-Oriented
Instructions in Indexed Literal Offset
Mode” f or details.
Words: 1
Cycles: 1
Q Cycle Activity :
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data Write to
destination
Example 1:SUBWF REG, 1, 0
Before Instruction
REG = 3
W=2
C=?
After Instruction
REG = 1
W=2
C = 1 ; result is positive
Z=0
N=0
Example 2:SUBWF REG, 0, 0
Before Instruction
REG = 2
W=2
C=?
After Instruction
REG = 2
W=0
C = 1 ; result is zero
Z=1
N=0
Example 3:SUBWF REG, 1, 0
Before Instruction
REG = 1
W=2
C=?
After Instruction
REG = FFh ;(2’s complement)
W=2
C = 0 ; result is negative
Z=0
N=1
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PIC18F2XK20/4XK20
SUBWFB Subtract W from f with Borrow
Syntax: SUBWFB f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f) – (W) – (C) dest
Status Affected: N, OV, C, DC, Z
Encoding: 0101 10da ffff ffff
Description: Subt ract W and the CARRY flag
(borrow) from register ‘f’ (2’s comple-
ment method). If ‘d’ is ‘0’, the result is
stored in W. If ‘d’ is ‘1’, the result is
stored back in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offs et Addressing
mode whenever f 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity :
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data Write to
destination
Example 1:SUBWFB REG, 1, 0
Before Instruction
REG = 19h (0001 1001)
W=0Dh (0000 1101)
C=1
After Instruction
REG = 0Ch (0000 1100)
W=0Dh (0000 1101)
C=1
Z=0
N = 0 ; result is positive
Example 2: SUBWFB REG, 0, 0
Before Instruction
REG = 1Bh (0001 1011)
W=1Ah (0001 1010)
C=0
After Instruction
REG = 1Bh (0001 1011)
W = 00h
C=1
Z = 1 ; res u l t is z e ro
N=0
Example 3: SUBWFB REG, 1, 0
Before Instruction
REG = 03h (0000 0011)
W=0Eh (0000 1110)
C=1
After Instruction
REG = F5h (1111 0101)
; [2’s co mp]
W=0Eh (0000 1110)
C=0
Z=0
N = 1 ; result is negative
SWAPF Swap f
Syntax: SWAPF f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f<3:0>) dest<7:4>,
(f<7:4>) dest<3:0>
Status Affected: None
Encoding: 0011 10da ffff ffff
Description: The upper and lower nibbles of register
‘f’ are exchanged. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result is
placed in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR i s used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Ins tructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity :
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data Write to
destination
Example:SWAPF REG, 1, 0
Before Instruction
REG = 53h
After Instruction
REG = 35h
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TBLRD Table Read
Syntax: TBLRD ( *; *+; *-; +*)
Operands: None
Operation: if TBLRD *,
(Prog Mem (TBLPTR)) TABLAT;
TBLPTR – No Change;
if TBLRD *+,
(Prog Mem (TBLPTR)) TABLAT;
(TBLPTR) + 1 TBLPT R ;
if TBLRD *-,
(Prog Mem (TBLPTR)) TABLAT;
(TBLPTR) – 1 TBLPTR;
if TBLRD +*,
(TBLPTR) + 1 TBLPT R ;
(Prog Mem (TBLPTR)) TABLAT;
S t at us Af fected : None
Encoding: 0000 0000 0000 10nn
nn=0 *
=1 *+
=2 *-
=3 +*
Description: This instruction is used to read the contents
of Program Memory (P.M.). To address the
program memory, a pointer called Table
Pointer (TBLPT R ) is used.
The TBLPTR (a 21-bit pointer) points to
each byte in the program memory. TBLPTR
has a 2-Mbyte address range.
TBLPTR[0] = 0: Least Significant Byte
of Program Memor y
Word
TBLPTR[0] = 1: Most Signif icant Byte
of Program Memor y
Word
The TBLRD instruction can modify the value
of TBLPTR as follows:
• no change
• post-increment
• post-decrement
• pre-increment
Words: 1
Cycles: 2
Q Cycle Activity :
Q1 Q2 Q3 Q4
Decode No
operation No
operation No
operation
No
operation No operatio n
(Read Program
Memory)
No
operation No operation
(Write TABLAT)
TBLRD Table Read (Continued)
Example1:TBLRD *+ ;
Before Instruction
TABLAT = 55h
TBLPTR = 00A356h
MEMORY (00A356h) = 34h
After Instruction
TABLAT = 34h
TBLPTR = 00A357h
Example2:TBLRD +* ;
Before Instruction
TABLAT = AAh
TBLPTR = 01A357h
MEMORY (01A357h) = 12h
MEMORY (01A358h) = 34h
After Instruction
TABLAT = 34h
TBLPTR = 01A358h
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PIC18F2XK20/4XK20
TBLWT Table Write
Syntax: TBLWT ( *; *+; *-; +*)
Operands: None
Operation: if TBLWT*,
(TABLAT) Holding Register;
TBLPTR – No Change;
if TBLWT*+,
(TABLAT) Holding Register;
(TBLPT R) + 1 TBLPTR;
if TBLWT*-,
(TABLAT) Holding Register;
(TBLPTR) – 1 TBLPTR;
if TBLWT+*,
(TBLPT R) + 1 TBLPTR;
(TABLAT) Holding Register;
Status Affected: None
Encoding: 0000 0000 0000 11nn
nn=0 *
=1 *+
=2 *-
=3 +*
Description: This instruction uses the 3 LSBs of
TBLPTR to determine which of the
8 holding registers the TABLAT is written
to. The holding registers are used to
program the contents of Program
Memory (P.M .). (Refer to Section 6.0
“Flash Program Memory” for additional
details on programming Flash memory.)
The TBLPTR (a 21-bit pointer) points to
each byte in the program memory.
TBLPTR has a 2-MByte address range.
The LSb of the TBLPTR selects which
byte of the program memory location to
access.
TBLPTR[0 ] = 0: Least Significant
Byte of Program
Memory Word
TBLPTR[0 ] = 1: Most Significant
Byte of Program
Memory Word
The TBLWT instruction can modify the
value of TBLPTR as follows:
• no change
• post-increment
• post-decrement
• pre-increment
Words: 1
Cycles: 2
Q Cycle Activity : Q1 Q2 Q3 Q4
Decode No
operation No
operation No
operation
No
operation No
operation
(Read
TABLAT)
No
operation No
operation
(Write to
Holding
Register )
TBLWT Table Write (Continued)
Example1:TBLWT *+;
Before Instruction
TABLAT = 55h
TBLPTR = 00A356h
HOLDING REGISTER
(00A356h) = FFh
After Instructions (table write completion)
TABLAT = 55h
TBLPTR = 00A357h
HOLDING REGISTER
(00A356h) = 55h
Example 2:TBLWT +*;
Before Instruction
TABLAT = 34h
TBLPTR = 01389Ah
HOLDING REGISTER
(01389Ah) = FFh
HOLDING REGISTER
(01389Bh) = FFh
After Instruction (table write completion)
TABLAT = 34h
TBLPTR = 01389Bh
HOLDING REGISTER
(01389Ah) = FFh
HOLDING REGISTER
(01389Bh) = 34h
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TSTFSZ Test f, skip if 0
Syntax: TSTFS Z f {,a}
Operands: 0 f 255
a [0,1]
Operation: skip if f = 0
Status Affected: None
Encoding: 0110 011a ffff ffff
Description: If ‘f’ = 0, the next instruction fetched
during the current instruction execution
is discarded and a NOP is executed,
making this a 2-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in In d e x e d L it e ra l Offset Ad d r e ssin g
mode whenever f 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity :
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data No
operation
If skip: Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
No
operation No
operation No
operation No
operation
Example:HERE TSTFSZ CNT, 1
NZERO :
ZERO :
Before Instruction
PC = Address (HERE)
After Instruction
If CNT = 00h,
PC = Address (ZERO)
If CNT 00h,
PC = Address (NZERO)
XORLW Exclusive OR literal with W
Syntax: XORLW k
Operands: 0 k 255
Operation: (W ) .X OR . k W
Status Affected: N, Z
Encoding: 0000 1010 kkkk kkkk
Description: The contents of W are XORed with
the 8-bit literal ‘k’. The result is placed
in W.
Words: 1
Cycles: 1
Q Cycle Activity :
Q1 Q2 Q3 Q4
Decode Read
literal ‘k’ Process
Data Write to W
Example:XORLW 0AFh
Before Instruction
W=B5h
After Instruction
W=1Ah
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PIC18F2XK20/4XK20
XORWF Exclusive OR W with f
Syntax: XORWF f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (W) .XOR. (f) dest
Status Affected: N, Z
Encoding: 0001 10da ffff ffff
Description: Exclusive OR the contents of W with
register ‘f’. If ‘d’ is ‘0’, the result is stored
in W. If ‘d’ is ‘1’, the result is stored back
in the register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR i s used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in In d e x e d L it e ra l Offset Ad d r e ssin g
mode whenever f 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity :
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data Write to
destination
Example:XORWF REG, 1, 0
Before Instruction
REG = AFh
W=B5h
After Instruction
REG = 1Ah
W=B5h
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DS40001303G-page 338 2010-2015 Microchip Technology Inc.
24.2 Extended Instruct ion Set
In additi on to the st an dard 75 i nst ruc tions of the PI C18
instruction set, PIC18F2XK20/4XK20 devices also
provide an optional extension to the core CPU
functionality. The added features include eight
additional instructions that augment indirect and
indexe d addressing o perations and th e implement ation
of Indexed Literal Offset Addressing mode for many of
the standard PIC18 instructions.
The additional features of the extended instruction set
are d isabled by d efault. To enabl e them, user s must set
the XINST Configuration bit.
The instructions in the extended set can all be
class ified as lit eral operat ions, whic h either man ipula te
the File Select Registers, or use them for indexed
addressing. Two of the instructions, ADDFSR and
SUBFSR, each have an additional special instantiation
for using FSR2. These versions (ADDULNK and
SUBULNK) allow for automatic return after execution.
The exte nded instr uctions are s pecifically im plemented
to optimize re-entrant program code (that is, code that
is recursive or that uses a software stack) written in
high-level languages, particularly C. Among other
things, they allow users working in high-level
languages to perform certain operations on data
structures more efficiently. These include:
• dynamic allocation and deallocation of software
stack space when entering and leaving
subroutines
• function pointer invoca tion
• software Stack Pointer manipulation
• manipulation of variables located in a software
stack
A summary of the instructions in the extended instruc-
tion set is provide d in Table 24-3. Deta iled des cripti ons
are pro vided in Section 24.2.2 “Extended Instruction
Set”. The opcode field descriptions in Table apply to
both the st andard and exte nded PIC18 instru ction sets .
24.2.1 EXT EN DED INSTRU CTION SYNTAX
Most of the extended instructions use indexed
arguments, using one of the File Select Registers and
some offset to specify a source or destination register.
When an argument for an instruction serves as part of
indexed addressing, it is enclosed in square brackets
(“[ ]”). This is done to in dicate that the argument is used
as an index or of f se t. MPASM™ Assembler wil l flag an
error if it de termines that an ind ex or o f fs et va lu e is not
bracketed.
When the ex tended ins truction s et is enabled, bra cket s
are also used to indicate index arguments in byte-
oriented and bit-oriented instr uctions. This is in addition
to other changes in their syntax. For more details, see
Section 24.2.3.1 “Extended Instruction Syntax with
Standard PIC18 Commands”.
TABLE 24-3: EXTENSIONS TO THE PIC18 INSTRUCTION SET
Note: The instruction set extension and the
Indexed Literal Offset Addressing mode
were designed for optimizing applications
written in C; the user m ay l ike ly ne ve r us e
these instructions directly in assembler.
The syntax for these commands is pro-
vided as a reference for users who may be
reviewing code that has been generated
by a compiler.
Note: In the past, square brackets have been
used to denote optional arguments in the
PIC18 and earlier instruction sets. In this
text and going forward, optional
arguments are denoted by braces (“{ }”).
Mnemonic,
Operands Description Cycles 16-Bit Instruction Word Status
Affected
MSb LSb
ADDFSR
ADDULNK
CALLW
MOVSF
MOVSS
PUSHL
SUBFSR
SUBULNK
f, k
k
zs, fd
zs, zd
k
f, k
k
Add literal to FSR
Add literal to FSR2 and return
Call subrou tine using WREG
Move zs (source) to 1st word
fd (destination) 2nd word
Move zs (source) to 1st word
zd (destination) 2nd word
Store literal at FSR2,
decrement FSR2
Subtract literal from FSR
Subtract literal from FSR2 and
return
1
2
2
2
2
1
1
2
1110
1110
0000
1110
1111
1110
1111
1110
1110
1110
1000
1000
0000
1011
ffff
1011
xxxx
1010
1001
1001
ffkk
11kk
0001
0zzz
ffff
1zzz
xzzz
kkkk
ffkk
11kk
kkkk
kkkk
0100
zzzz
ffff
zzzz
zzzz
kkkk
kkkk
kkkk
None
None
None
None
None
None
None
None
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PIC18F2XK20/4XK20
24.2.2 EXTENDED INSTRUCTION SET
ADDFSR Add Literal to FSR
Syntax: ADDF SR f, k
Operands: 0 k 63
f [ 0, 1, 2 ]
Operation: FSR(f) + k FSR(f)
Status Affected: None
Encoding: 1110 1000 ffkk kkkk
Description: The 6-bit literal ‘k’ is added to the
contents of the FSR specified by ‘f’.
Words: 1
Cycles: 1
Q Cycle Activity :
Q1 Q2 Q3 Q4
Decode Read
literal ‘k’ Process
Data Write to
FSR
Example: ADDFSR 2, 23h
Before Instruction
FSR2 = 03FFh
After Instruction
FSR2 = 0422h
ADDULNK Add L i t eral t o FSR2 and Re turn
Syntax: ADDULNK k
Operands: 0 k 63
Operation: FSR2 + k FSR2,
(TOS) PC
Status Affected: None
Encoding: 1110 1000 11kk kkkk
Description: The 6-bit literal ‘k’ is added to the
contents of FSR2. A RETURN is then
executed by loading the PC with the
TOS.
The instruction takes two cycles to
execute; a NOP is performed during
the second cycle.
This may be thought of as a special
case of the ADDFSR instr uction,
where f = 3 (binary ‘11’); it operates
only on FSR2.
Words: 1
Cycles: 2
Q Cycle Activity :
Q1 Q2 Q3 Q4
Decode Read
literal ‘k’ Process
Data Write to
FSR
No
Operation No
Operation No
Operation No
Operation
Example: ADDULNK 23h
Before Instruction
FSR2 = 03FFh
PC = 0100h
After Instruction
FSR2 = 0422h
PC = (TOS)
Note: All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in
symbolic addressing. If a label is used, the instruction syntax then becomes: {label} instruction argument(s).
PIC18F2XK20/4XK20
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CALLW Subroutine Call Using WREG
Syntax: CALLW
Operands: None
Operation: (PC + 2) TOS,
(W) PCL,
(PCLATH) PCH,
(PCLATU) PCU
Status Affected: None
Encoding: 0000 0000 0001 0100
Description First, the return address (PC + 2) is
pushed onto the return stack. Next, the
contents of W are written to PCL; the
existing value is discarded. Then, the
contents of PCLATH and PCLATU are
latched into PCH and PCU,
respectively. The second cycle is
executed as a NOP instruction while the
new next instruction is fetched.
Unlike CALL, there is no option to
update W, Status or BSR.
Words: 1
Cycles: 2
Q Cycle Activity :
Q1 Q2 Q3 Q4
Decode Read
WREG PUSH PC to
stack No
operation
No
operation No
operation No
operation No
operation
Example:HERE CALLW
Before Instruction
PC = address (HERE)
PCLATH = 10h
PCLATU = 00h
W = 06h
After Instruction
PC = 001006h
TOS = address (HERE + 2)
PCLATH = 10h
PCLATU = 00h
W = 06h
MOVSF Move Indexed to f
Syntax: MOVSF [zs], fd
Operands: 0 zs 127
0 fd 4095
Operation: ((FSR2) + zs) fd
Status Affected: None
Encoding:
1st word (source)
2nd word (destin.) 1110
1111 1011
ffff 0zzz
ffff zzzzs
ffffd
Description: The contents of the source register are
moved to destination register ‘fd’. The
actual address of the source register is
determined by adding the 7-bit literal
offset ‘zs’ in the first word to the value of
FSR2. The address of the destination
register is specified by the 12-bit literal
‘fd’ in the second word. Both addresses
can be anywhere in the 4096-byte data
space (000h to FFFh).
The MOVSF instruction cannot use the
PCL, TOSU, TOSH or TOSL as the
destination register.
If the resultant source address points to
an indirect addressing register, the
value returned will be 00h.
Words: 2
Cycles: 2
Q Cycle Activity :
Q1 Q2 Q3 Q4
Decode Determine
source addr Determine
source addr Read
source reg
Decode No
operation
No dummy
read
No
operation Write
register ‘f’
(dest)
Example:MOVSF [05h], REG2
Before Instruction
FSR2 = 80h
Contents
of 85h = 33h
REG2 = 11h
After Instruction
FSR2 = 80h
Contents
of 85h = 33h
REG2 = 33h
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PIC18F2XK20/4XK20
MOVSS Move Indexed to Indexed
Syntax: MOVS S [zs], [zd]
Operands: 0 zs 127
0 zd 127
Operation: ((FSR2) + zs) ((FSR2) + zd)
Status Affected: None
Encoding:
1st word (source)
2nd word (dest.) 1110
1111 1011
xxxx 1zzz
xzzz zzzzs
zzzzd
Description The contents of the source register are
moved to the destination register . The
addresses of the source and destination
registers are determined by adding the
7-bit literal offset s ‘zs’ or ‘zd’,
respectively, to the value of FSR2. Both
registers can be located anywhere in
the 4096-byte data memory space
(000h to FFFh).
The MOVSS instruction cannot use the
PCL, TOSU, TOSH or TOSL as the
destination register.
If the resultant source address points to
an indirect addressing register, the
value returned will be 00h. If the
resultant destination address points to
an indirect addressing register, the
instruction will execute as a NOP.
Words: 2
Cycles: 2
Q Cycle Activity :
Q1 Q2 Q3 Q4
Decode Determine
source addr Determine
source addr Read
source reg
Decode Determine
dest addr Determine
dest addr Write
to dest reg
Example:MOVSS [05h], [06h]
Before Instruction
FSR2 = 80h
Contents
of 85h = 33h
Contents
of 86h = 11h
After Instruction
FSR2 = 80h
Contents
of 85h = 33h
Contents
of 86h = 33h
PUSHL
Store Literal at FSR2, Decrement FSR2
Syntax: PUSHL k
Operands: 0k 255
Operation: k (FSR2),
FSR2 – 1 FSR2
S t at us Af fected : None
Encoding: 1111 1010 kkkk kkkk
Description: The 8-bit literal ‘k’ is written to the data
memory address specified by FSR2. FSR2
is decremented by 1 after the operation.
This instruction allows users to push values
onto a software stack.
Words: 1
Cycles: 1
Q Cycle Activity :
Q1 Q2 Q3 Q4
Decode Read ‘k’ Process
data Write to
destination
Example:PUSHL 08h
Before Instruction
FSR2H:FSR2L = 01ECh
Memory (01ECh) = 00h
After Instruction
FSR2H:FSR2L = 01EBh
Memory (01ECh) = 08h
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SUBFSR Subtract Literal from FSR
Syntax: SUBFSR f, k
Operands: 0 k 63
f [ 0, 1, 2 ]
Operation: FSR(f) – k FSRf
Status Affected: None
Encoding: 1110 1001 ffkk kkkk
Description: The 6-bit literal ‘k’ is subtracted from
the contents of the FSR specified by
‘f’.
Words: 1
Cycles: 1
Q Cycle Activity :
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data Write to
destination
Example:SUBFSR 2, 23h
Before Instruction
FSR2 = 03FFh
After Instruction
FSR2 = 03DCh
SUBULNK
Subtract Literal from FSR2 and Return
Syntax: SUBULNK k
Operands: 0 k 63
Operation: FSR2 – k FSR2
(TOS) PC
S t at us Af fected : None
Encoding: 1110 1001 11kk kkkk
Description: The 6-bit literal ‘k’ is subtracted from the
contents of the FSR2. A RETURN is then
executed by loading the PC with the TOS.
The instruction takes two cycles to
execute; a NOP is performed during the
second cycle.
This may be thought of as a special case of
the SUBFSR instruction, where f = 3 (binary
‘11’); it operates only on FSR2.
Words: 1
Cycles: 2
Q Cycle Activity :
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data Write to
destination
No
Operation No
Operation No
Operation No
Operation
Example:SUBULNK 23h
Before Instruction
FSR2 = 03FFh
PC = 0100h
After Instruction
FSR2 = 03DCh
PC = (TOS)
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PIC18F2XK20/4XK20
24.2.3 BY TE- ORIE NT ED AND
BIT-ORIENTED INSTR UCTIONS IN
INDEXED LITERAL OFFSET MODE
In additio n to eight new comm ands in the extende d set,
enabling the extended instruction set also enables
Indexed Literal Offset Addre ssing mode (Section 5.5.1
“Indexed Addressing with Literal Offset”). This has
a sign ificant im pact on the way t hat many com mands of
the standard PIC18 instruction set are interpreted.
When the extended set is disabled, addresses
embedded in opcodes are treated as literal memory
locatio ns : ei the r as a lo ca tio n in the Acc es s Ba nk (‘a’ =
0), or in a GPR bank designated by the BSR (‘a’ = 1).
When the extended instruction set is enabled and ‘a’ =
0, however, a file register argument of 5Fh or less is
interpreted as an offset from the point er val ue in FSR2
and not as a literal address. For practical pu rposes, this
means that all i nstructio ns that us e the Acc ess RAM b it
as an argument – that is, all byte-oriented and bit-
oriented instructions, or almost half of the core PIC18
instructions – may behave differently when the
extended instruction set is enabled.
When the content of FSR2 is 00h, the b oundaries of the
Access RAM are essentially remapped to their original
values. This may be useful in creating backward
compatible code. If this technique is used, it may be
necessary to save the value of FSR2 and restore it
when moving back and forth between C and as sembly
routines in order to preserve the Stack Pointer. Users
must also keep in mind the syntax requirements of the
extended instruction set (see Section 24.2.3.1
“Extended Instruction Syntax with Standard PIC18
Commands”).
Although the Indexed Literal Offset Addressing mode
can be very useful for dynamic stack and pointer
manipulation, it can also be very annoying if a simple
arithmetic operation is carried out on the wrong
register. Users who are accustomed to the PIC18
programming must keep in mind that, when the
extende d inst ruct ion se t is ena bled, re giste r add resses
of 5Fh or less are used for Indexed Literal Offset
Addressing.
Representative examples of typical byte-oriented and
bit-oriented instructions in the Indexed Literal Offset
Addressi ng mode ar e provided on the f ollowing p age to
show how execution is affected. The operand condi-
tions shown in the examples are applicable to all
instructions of these types.
24.2.3.1 Extended Instruction Syntax with
Standard PIC18 Commands
When the extended instruction set is enabled, the file
register arg ument, ‘f’, in the sta ndard byte-oriented an d
bit-or iented command s is replaced with the li teral of fset
value, ‘k ’. As al rea dy no ted, this occurs only when ‘f’ is
less t han or eq ual to 5Fh. When an of fset val ue is use d,
it mu st be i ndica ted by square bracke ts (“[ ] ”). As with
the exte nded ins tructions , the us e of brac kets indicate s
to the com pil er th at the val ue is to be in terp rete d as an
index or an offset. Omitting the brackets, or using a
value greater than 5Fh within brackets, will generate an
error in the MPASM Assembler.
If the ind ex argu me nt is pr operly bracketed for Inde xed
Literal O ffset Addre ssing, the Acc ess RAM argument i s
never specified; it will automatically be assumed to be
‘0’. This is in contrast to standard operation (extended
instruction set disabled) when ‘a’ is set on the basis of
the target address. Declaring the Access RAM bit in
this mode will also generate an error in the MPASM
Assembler.
The destination argument, ‘d’, functions as before.
In the latest versions of the MPASM™ assembler,
languag e s upp ort for the extended i ns truc tio n s et m ust
be explicitly invoked. This is done with either the
command line option, /y, or the PE directive in the
source lis tin g.
24.2.4 CONSIDERATIONS WHEN
ENABLING THE EXTENDED
INSTRUCTION SET
It is i mport ant to note that the ex tensions to th e ins truc-
tion set may not be beneficial to all users. In particular,
users who are not writing code that uses a software
stack may not benefit from using the extensions to the
instruction set.
Additionally, the Indexed Literal Offset Addressing
mode may create issues with legacy applications
written to the PIC18 assembler. This is because
instruc t ion s i n th e le gac y cod e m ay atte mp t to a ddress
registers in the Access Bank below 5Fh. Since these
addresses are interpreted as literal offsets to FSR2
when the instruction set extension is enabled, the
application may read or write to the wrong data
addresses.
When porting an application to the PIC18F2XK20/
4XK20, i t is very im portant to co nsider the type of code.
A large, re-entrant application that is written in ‘C’ and
would benefit from efficient compilation will do well
when using the instruction set extensions. Legacy
applic ations tha t heavily use the Ac cess Ban k will mos t
likely not benefit from using the extended instruction
set.
Note: Enabling the PIC18 instruction set
extension may cause legacy applications
to behave erratically or fail entirely.
PIC18F2XK20/4XK20
DS40001303G-page 344 2010-2015 Microchip Technology Inc.
ADDWF ADD W to Indexed
(Indexed Literal Offset mode)
Syntax: ADDWF [k] {,d}
Operands: 0 k 95
d [0,1]
Operation: (W) + ((FSR2) + k) dest
Status Affected: N, OV, C, DC, Z
Encoding: 0010 01d0 kkkk kkkk
Description: The contents of W are added to the
contents of the register indicated by
FSR2, offset by the value ‘k’.
If ‘d’ is ‘0’, the result is stored in W. If ‘d’
is ‘1’, the result is stored back in
register ‘f’ (default).
Words: 1
Cycles: 1
Q Cycle Activity :
Q1 Q2 Q3 Q4
Decode Read ‘k’ Process
Data Write to
destination
Example:ADDWF [OFST] , 0
Before Instruction
W = 17h
OFST = 2Ch
FSR2 = 0A00h
Contents
of 0A2Ch = 20h
After Instruction
W = 37h
Contents
of 0A2Ch = 20h
BSF Bit Set Indexe d
(Indexed Literal Offset mode)
Syntax : BSF [k], b
Operands: 0 f 95
0 b 7
Operation: 1 ((FSR2) + k)<b>
Status Affected: None
Encoding: 1000 bbb0 kkkk kkkk
Description: Bit ‘b’ of the register indicated by FSR2,
offset by the value ‘k’, is set.
Words: 1
Cycles: 1
Q Cycle Activity :
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data Write to
destination
Example:BSF [FLAG_OFST], 7
Before Instruction
FLAG_OFST = 0Ah
FSR2 = 0A00h
Contents
of 0A0Ah = 55h
After Instruction
Contents
of 0A0Ah = D5h
SETF Set Indexed
(Indexed Literal Offset mode)
Syntax: SETF [k]
Operands: 0 k 95
Operation: FFh ((FSR 2) + k)
Status Affected: None
Encoding: 0110 1000 kkkk kkkk
Description: The contents of the register indicated by
FSR2, offset by ‘k’, are set to FFh.
Words: 1
Cycles: 1
Q Cycle Activity :
Q1 Q2 Q3 Q4
Decode Read ‘k’ Process
Data Write
register
Example:SETF [OFST]
Before Instruction
OFST = 2Ch
FSR2 = 0A00h
Contents
of 0A2Ch = 00h
After Instruction
Contents
of 0A2Ch = FFh
2010-2015 Microchip Technology Inc. DS40001303G-page 345
PIC18F2XK20/4XK20
24.2.5 SPECIAL CONSIDERATIONS WITH
MICROCHIP MPL AB ® IDE TOOLS
The la test ver sions of Microc hip’s softwa re tools h ave
been de signe d t o full y sup port th e exte nded i nstruc tion
set of the PIC18 F2XK20/4 XK20 fami ly of dev ices . This
includes the MPLAB C18 C compiler, MPASM
assembly language and MPLAB Integrated
Development Environment (IDE).
When selecting a target device for software
development, MPLAB IDE will automatically set default
Configuration bits for th at device. The default setting for
the XINST Configuration bit is ‘0’, disabling the
extended instruction set and Indexed Literal Offset
Addressi ng m ode. For pr oper e xecut ion o f app licat ions
developed to take advantage of the extended
instruction set, XINST must be set during
programming.
To develop software for the extended instruction set,
the user must enable support for the instructions and
the Index ed Address ing mode i n their lang uage tool(s).
Depending on the environment being used, this may be
done in several ways:
• A menu option, or dialog box within the
environment, that allows the user to configure the
language tool and its settings for the project
• A command line option
• A directive in the sour ce code
These options vary between different compilers,
assemblers and development environments. Users are
encouraged to re view the documentation acc ompanying
their development systems for the appropriate
information.
PIC18F2XK20/4XK20
DS40001303H-page 346 2010-2015 Microchip Technology Inc.
25.0 DEVELOPMENT SUPPORT
The PIC® microcontrollers (MCU) and dsPIC® digital
signal controllers (DSC) are supported with a ful l range
of software and hardware development tools:
• Integrated Development Environment
- MPLAB® X IDE Software
• Compilers/Assemblers/Linkers
- MPLAB XC Compiler
-MPASM
TM Assembler
-MPLINK
TM Object Linker/
MPLIBTM Object Librarian
- MPLAB Assembler/Linker/Librarian for
Various Device Families
• Simulators
- MPLAB X SIM Software Simulator
•Emulators
- MPLAB REAL ICE™ In-Circuit Emulator
• In-Circuit Debuggers/Programmers
- MPLAB ICD 3
- PICkit™ 3
• Device Progra mmers
- MPLAB PM3 Device Programmer
• Low-C ost D emonstration/Development Boards,
Evaluation Kits and Starter Kits
• Third-party development tools
25.1 MPLAB X Integrated Development
Environment Software
The MPLAB X IDE is a single, unified graphical user
interface for Microchip and third-party software, and
hardware development tool that runs on Windows®,
Linux and Mac OS® X. Based on the NetBeans IDE,
MPLAB X IDE is an entirely new IDE with a host of free
software components and plug-ins for high-
performance application development and debugging.
Moving between tools and upgrading from software
simulators to hardware debugging and programming
tools is simple with the seamless user interface.
With com plete projec t managem ent, visual cal l graphs,
a configurable watch window and a feature-rich editor
that includes code completion and context menus,
MPLAB X IDE is flexible and friendly enough for new
users. With the ability to support multiple tools on
multipl e project s with simu ltane ous debugging, MPLAB
X IDE is also suitable for the needs of experienced
users.
Feature-Rich Editor:
• Color syntax highlighting
• Smart code completion makes suggestions and
provides hin ts as you type
• Automati c c od e f orm atti ng bas ed on us er-d efi ned
rules
• Live parsing
User-Friendly, Customizabl e Interfa ce :
• Fully customizable interface: toolbars, toolbar
buttons, windows, window placement, etc.
• Call graph window
Project -Based Workspaces:
• Multiple projects
• Multiple tools
• Multiple configurations
• Simu lt aneous debuggin g sess io ns
File History and Bug Tracking:
• Local file history feature
• Built-in support for Bugzilla issue tracker
2010-2015 Microchip Technology Inc. DS40001303H-page 347
PIC18F2XK20/4XK20
25.2 MPLAB XC Compilers
The MPLAB XC Compilers are complete ANSI C
compilers for all of Microchip’s 8, 16, and 32-bit MCU
and DSC devices. These compilers provide powerful
integration capabilities, superior code optimization and
ease of use. MPLAB XC Compilers run on Windows,
Linux or MAC OS X.
For easy source level debugging, the compilers provide
debug information that is optimized to the MPLAB X
IDE.
The free MPLAB XC Compiler editions support all
devices and commands, with no time or memory
restrictions, and offer sufficient code optimization for
most applications.
MPLAB XC Co mpilers inc lude an asse mbler , li nker and
utilities. The assembler generates relocatable object
files that can then be archived o r l inked wi th ot her relo-
catable object files and archives to create an execut-
able file. MPLAB XC Compiler uses the assembler to
produce its object file. Notable features of the assem-
bler inclu de:
• Support for the entire device instruction set
• Support for fixed-point and floating-point data
• Command-line interface
• Rich dire cti ve set
• Flexible macro language
• MPLAB X IDE compatibility
25.3 MPASM Assembler
The MPASM Assembler is a full-featured, universal
macro assembler for PIC10/12/16/18 MCUs.
The MPASM Assembler generates relocatable object
files fo r the MPLINK Ob ject Linker , Int el® standa rd HEX
files, MAP files to detail memory usage and symbol
reference, absolute LST files that contain source lines
and generated machine code, and COFF files for
debugging.
The MPASM Assembler features include:
• Integration into MPLAB X IDE projects
• User-defined macros to streamline
assembly co de
• Conditional assembly for multipurpose
sour ce fil es
• Directives that allow complete control over the
assembly proces s
25.4 MPLINK Object Linker/
MPLIB Object Librarian
The MPLINK Object Linker combines relocatable
objects created by the MPASM Assembler. It can link
relocatable objects from precompiled libraries, using
directives from a linker script.
The MPLI B Obje ct Libra rian man ages th e creati on and
modification of library files of precompiled code. When
a rout in e from a l ibra ry is called fro m a so urc e f ile, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, re placement, de letion and ex traction
25.5 MPLAB Assembler, Linker and
Librarian for Various Device
Families
MPLAB Assembler produces relocatable machine
code from symbolic assembly language for PIC24,
PIC32 and dsPIC DSC devices. MPLAB XC Compiler
uses the assembler to produce its object file. The
assembler generates relocatable object files that can
then be archi ved or link ed with other rel ocat ab le objec t
files and archives to create an executable file. Notable
features of the assembler include:
• Support for the entire device instruction set
• Support for fixed-point and floating-point data
• Command-line interface
• Rich dire cti ve set
• Flexible macro language
• MPLAB X IDE compatibility
PIC18F2XK20/4XK20
DS40001303H-page 348 2010-2015 Microchip Technology Inc.
25.6 MPLAB X SIM Software Simulator
The MPLAB X SIM Software Simulator allows code
development in a PC-hosted environment by simulat-
ing the PIC MCUs and dsPIC DSCs on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a comprehensive stimulus controller. Registers can be
logged to files for further run-time analysis. The trace
buffer and logic analyzer display extend the power of
the simulator to record and track program execution,
actions on I/O, most periph erals and i nternal regi sters.
The MPLAB X SIM Software Simulator fully supports
symbolic debugging using the MPLAB XC Compilers,
and the MPASM and MPLAB Assemblers. The soft-
ware simulator offers the flexibility to develop and
debug code outside of the hardware laboratory envi-
ronment, making it an excellent, economical software
developm ent too l.
25.7 MPLAB REAL ICE In-Circuit
Emulator System
The MPLAB REAL ICE In-Circuit Emulator System is
Microchip’s next generation high-speed emulator for
Microchip Flash DSC and MCU devices. It debugs and
programs all 8, 16 and 32-bit MCU, and DSC devices
with the easy-to-use, powerful graphical user interface of
the MPLAB X IDE.
The emulator is connected to the design engineer’s
PC using a high-speed USB 2.0 interface and is
connected to the target with either a connector
compatible with in-circuit debugger systems (RJ-11)
or with the new high-speed, noise tolerant, Low-
Voltage Differential Signal (LVDS) interconnection
(CAT5).
The emulator is field upgrad able through future firmware
downloads in MPLAB X IDE. MPLAB REAL ICE offers
significant advantages over competitive emulators
including full-speed emulation, run-time variable
watches, trace analysis, complex breakpoints, logic
probes, a ruggedized probe interface and long (up to
three meters) interconnection cable s.
25.8 MPLAB ICD 3 In-Circuit Debugger
System
The MPLAB ICD 3 In-Circuit Debugger System is
Microchip’s most cost-effective, high-speed hardware
debugger/programmer for Microchip Flash DSC and
MCU devices. It debugs and programs PIC Flash
microcontrollers and dsPIC DSCs with the powerful,
yet easy-to-use graphical user interface of the MPLAB
IDE.
The MPLAB ICD 3 In-Circuit Debugger probe is
connected to the design engineer’s PC using a high-
speed USB 2.0 int erface and is connected to t he target
with a connector compatible with the MPLAB ICD 2 or
MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3
supports all MPLAB ICD 2 headers.
25.9 PICkit 3 In-Circuit Debugger/
Programmer
The MPLAB PICkit 3 allows debugging and program-
ming of P IC and dsPIC Flash microcontrollers at a most
af fordable pr ice point us ing the powerfu l graphica l user
interface of the MPLAB IDE. The MPLAB PICkit 3 is
connected to the design engineer’s PC using a full-
speed USB interface and can be connected to the tar-
get via a Microchip debug (RJ-11) connector (compati-
ble with MPLAB ICD 3 and MPLAB REAL ICE). The
connector uses two device I/O pins and the Reset line
to implement in-circuit debugging and In-Circuit Serial
Programming™ (ICSP™).
25.10 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal,
CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
maximum reliability. It features a large LCD display
(128 x 64) for menus and error messages, and a mod-
ular, detachable socket assembly to support various
package types. The ICSP cable assembly is included
as a standard item. In Stand-Alone mode, the MPLAB
PM3 Devic e Programmer ca n read, verif y and program
PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 h as high-spe ed co mmunicat ions an d
optimized algorithms for quick programming of large
memory devices, and incorporates an MMC card for file
storage and data applications.
2010-2015 Microchip Technology Inc. DS40001303H-page 349
PIC18F2XK20/4XK20
25.11 Demonstration/Development
Boards, Evaluation Kits, and
Starter Kits
A wide variety of demonstration, development and
evaluation boards for various PIC MCUs and dsPIC
DSCs allows quick application development on fully
functional systems. Most boards include prototyping
areas for adding custom circuitry and provide applica-
tion firmware and source code for examination and
modification.
The boards support a variety of features, including LEDs,
temperature sensors, switches, speakers, RS-232
interfaces , LCD displays, potentiometers and additional
EEPROM memory.
The demonstration and development boards can be
use d in teac hing environments, for prot otyping custom
circuits and for learning about various microcontroller
applications.
In addition to the PICDEM™ and dsPICDEM™
demonstration/development board series of circuits,
Microchip has a l ine of evaluation k its an d demonstra-
tion software for analog fil ter desig n, KEELOQ® security
ICs, CAN, IrDA®, PowerSmart battery management,
SEEVAL® evaluation system, Sigma-Delta ADC, flow
rate sensing, plus many more.
Also available are starter kits that contain everything
needed to experience t he specified d evice. This usually
includes a single application and debug capability, all
on one board.
Check the Microchip web page (www.microchip.com)
for the complete list of demonstration, development
and evaluati on kits.
25.12 Third-Party Development Tools
Microchip also offers a great collection of tools from
third-party vendors. Thes e tools are carefully selected
to offer good value and unique functionality.
• Device Programmers and Gang Programmers
from companies, such as SoftLog and CCS
• Software Tools from companies, such as Gimpel
and Trace S ystems
• Protoc ol A nal yz ers from com p a nies, such as
Saleae and Total Phase
• Demonstration Boards from companies, such as
MikroElektronika, Digilent® and Olimex
• Embedded Ethernet Solutions from companies,
such as EZ Web Lynx, WIZnet and IPLogika®
PIC18F2XK20/4XK20
DS40001303H-page 350 2010-2015 Microchip Technology Inc.
26.0 ELECTRICAL SP ECIFICATIONS
26.1 Absolute Maximum Ratings (†)
Ambient temperature under bias............................................................................................................ .-40°C to +125°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on pins with respect to VSS (excep t VDD, and MCLR)........................................................-0.3V to (VDD + 0.3V)
on VDD pin .............................................................................................................................. -0.3V to +4.5V
on MCLR(2)................................................................................................................................. 0V to +11.0V
Total power dissipation(1) ..........................................................................................................................................1.0W
Maximum current
PIC18F2XK20/4XK20
out of VSS pin, -40°C to +85°C for industrial...................................................................................... 350 mA
out of VSS pin, +85°C to +125°C for extended................................................................................... 120 mA
PIC18F4XK20
into VDD pin, -40°C to +85°C for industrial......................................................................................... 350mA
into VDD pin, +85°C to +125°C for extended.......................................................................................120 mA
PIC18F2XK20
into VDD pin, -40°C to +85°C for industrial......................................................................................... 250mA
into VDD pin, +85°C to +125°C for extended.........................................................................................85 mA
Input clamp current, IIK (VI < 0 or VI > VDD)20 mA
Maximum output current
sunk by any I/O pin ...............................................................................................................................50 mA
sourced by any I/O pin..........................................................................................................................50 mA
Note 1: Po wer dissip ation is calculated as follows: PDIS = VDD x {IDD – IOH} + {(VDD – VOH) x IOH} + (VOL x IOL).
2: Voltage spikes below VSS at the MCLR/VPP/RE3 pin, inducing currents greater than 80 mA, may cause
latch-up. Thus, a series resistor of 50-100 should be used when applying a “low” level to the
MCLR/VPP/RE3 pin, rather than pulling this pin directly to VSS.
3: Maximum current rating requires even load distribution across I/O pins. Maximum current rating may be
limited by the device package power dissipation characterizations. See Table 26-15 to calculate device
specifications.
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device . This is a stre ss rating onl y and functi onal operati on of the devi ce at those or an y other condi tions abov e those
indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for
extended periods may affect device reliability.
2010-2015 Microchip Technology Inc. DS40001303H-page 351
PIC18F2XK20/4XK20
26.2 Standard Operating Conditions
The standard operating conditions for any device are defined as:
Operati ng Voltage: VDDMIN VDD VDDMAX
Operati ng Tempe rature: TA_MIN TA TA_MAX
VDD — Operating Supply Voltage(1)
PIC18F2XK20/4XK20
VDDMIN (Fosc < = 16 MHz)...................................................................................................... +1.8V
VDDMIN (Fosc < = 20 MHz)...................................................................................................... +2.0V
VDDMIN (Fosc < = 48 MHz, Extended Temperature)................................................................ +3.0V
VDDMIN (Fosc < = 64 MHz, Industrial Temperature) ................................................................ +3.0V
VDDMAX .................................................................................................................................... +3.6V
TA — Operating Ambient Temperature Range
Industrial Temperature
TA_MIN...................................................................................................................................... -40°C
TA_MAX.................................................................................................................................... +85°C
Extended Temperature
TA_MIN...................................................................................................................................... -40°C
TA_MAX.................................................................................................................................. +125°C
Note 1: See Parameter D001 in DC Characteristics: Supply Voltage.
PIC18F2XK20/4XK20
DS40001303H-page 352 2010-2015 Microchip Technology Inc.
FIGURE 26-1: PIC18F2XK20/4X K20 VOLTAGE-FREQUE NCY GR APH (EXTENDE D)
FIGURE 26-2: PIC18F2XK20/4X K20 VOLTAGE-FREQUE NCY GR APH (INDUSTRI AL)
Frequency (MHz)
Voltage
3.5V
1.8V
64
3.0V
2.7V
2.0V
10 20 6030 40 5032 48
Note: Maximum Frequency 16 MHz, 1.8V to 2.0V, -40°C to +125°C
Maximum Frequency 20 MHz, 2.0V to 3.0V, -40°C to +125°C
Maximum Frequency 48 MHz, 3.0V to 3.6V, -40°C to +125°C
16
Frequency (MHz)
Voltage
3.5V
1.8V
64
3.0V
2.7V
2.0V
10 20 6030 40 5032
Note: Maximum Frequency 16 MHz, 1.8V to 2.0V, -40°C to +85°C
Maximum Frequency 20 MHz, 2.0V to 3.0V, -40°C to +85°C
Maximum Frequency 64 MHz, 3.0V to 3.6V, -40°C to +85°C
16
2010-2015 Microchip Technology Inc. DS40001303H-page 353
PIC18F2XK20/4XK20
26.3 DC Characteristi cs
TABLE 26-1: SUPPLY VOLTAGE, PIC18F2XK20/4XK20
PIC18F2XK20/4XK20 Standard Operating Conditions (unless other w is e stated)
Param.
No. Symbol Characteristic Min. Typ. Max. Units Conditions
D001 VDD Supply Voltage 1.8 — 3.6 V
D002 VDR RAM Data Retention
Voltage(1) 1.5 — — V
D003 VPOR VDD Start Voltage
to ensure internal
Power-on Reset signal
— — 0.7 V See section on Power-on Reset for
details
D004 SVDD VDD Rise Rate
to ensure internal
Power-on Reset signal
0.05 — — V/ms See section on Power-on Reset for
details
D005 VBOR Brown-out Reset Voltage
BORV<1:0> = 11(2) 1.72 1.82 1.95 V
BORV<1:0> = 10 2.15 2.27 2.40 V
BORV<1:0> = 01 2.65 2.75 2.90 V
BORV<1:0> = 00(3) 2.98 3.08 3.25 V
Note 1: This is the li mi t to whi ch V DD can be lowered in Slee p m od e, or during a devi ce Res et, without losi ng R AM
data.
2: With BOR enabled, operation is supported until a BOR occurs. This is valid although VDD may be below
the minimum rated sup ply volt ag e.
3: With BOR enabled, full -speed operation (FOSC = 64 MHZ) is supported until a BOR occurs. This is valid
although VDD may be below the minimum voltage for this frequency.
TABLE 26-2: POWER-DOWN CURRENT, PIC18F2XK20/4XK20
PIC18F2XK20/4XK20 Standard Operating Conditions (unless otherwise stated)
Param.
No. Device Characteristics Typ. Max. Units Conditions
D006 Power-down Cu rrent (IPD)(1) 0.05 1.0 A -40°C
VDD = 1.8V, (Sleep mode)
0.05 1.0 A+25°C
0.6 3.0 A+85°C
420A +125°C
D007 0.1 1.0 A -40°C
VDD = 3.0V, (Sleep mode)
0.1 1.0 A+25°C
0.7 3.0 A+85°C
520A +125°C
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is
measure d with the part in Sl eep mo de, with all I/ O pins in high-impe dance state a nd tied to V DD or VSS and
all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
PIC18F2XK20/4XK20
DS40001303H-page 354 2010-2015 Microchip Technology Inc.
TABLE 26-3: RC RUN SUPPLY CURRENT, PIC18F2XK20/4XK20
PIC18F2XK20/4XK20 Standard Operating Cond itions (unless otherwise stated)
Param .
No. Device Characteristics Typ. Max. Units Conditions
D008 Supply Current (IDD)(1, 2) 5.5 9 A-40°C
VDD = 1.8V
FOSC = 31 kHz
(RC_RUN mode,
LFINTOSC source)
6.0 10 A+25°C
6.5 14 A+85°C
9.0 30 A +125°C
D008A 10.0 15 A-40°C
VDD = 3.0V
10.5 16 A+25°C
11.0 20 A+85°C
14.0 40 A +125°C
D009 0.40 0.50 mA -40°C TO +125°C VDD = 1.8V FOSC = 1 MHz
(RC_RUN mode,
HF-INTOSC source)
D009A 0.60 0.80 mA -40°C TO +125°C VDD = 3.0V
D010 2.2 3.0 mA -40°C TO +125°C VDD = 1.8V FOSC = 16 MHz
(RC_RUN mode,
HF-INTOSC source)
D010A 3.8 4.4 mA -40°C TO +125°C VDD = 3.0V
Note 1: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as
I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and
temperature, also have an impact on the current consumption.
2: The test conditions for all IDD measurements in active operation mode are:
All I/O pins set as outputs driven to Vss;
MCLR = VDD;
OSC1 = external square wave, from rail-to-rail (PRI_RUN and PRI_IDLE only).
2010-2015 Microchip Technology Inc. DS40001303H-page 355
PIC18F2XK20/4XK20
TABLE 26-4: RC IDLE SUPPLY CURRENT, PIC18F2XK20/4XK20
PIC18F2XK20/4XK20 St an dard Ope ratin g Conditions (unless otherwise stated)
Param .
No. Device Characteristics Typ. Max. Units Conditions
D011 Supply Current (IDD)(1, 2) 2.0 5 A -40°C
VDD = 1.8V
FOSC = 31 kHz
(RC_IDLE mode,
LFINTOSC source)
2.0 5 A+25°C
2.5 9 A+85°C
5.0 25 A +125°C
D011A 3.5 8 A -40°C
VDD = 3.0V
3.5 8 A+25°C
4.0 12 A+85°C
7.0 30 A +125°C
D012 0.30 0.40 mA -40°C to +125°C VDD = 1.8V FOSC = 1 MHz
(RC_IDLE mode,
HF-INTOSC source)
D012A 0.40 0.60 mA -40°C to +125°C VDD = 3.0V
D013 1.0 1.2 mA -40°C to +125°C VDD = 1.8V FOSC = 16 MHz
(RC_IDLE mode,
HF-INTOSC source)
D013A 1.6 2.0 mA -40°C to +125°C VDD = 3. 0V
Note 1: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as
I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and
temperature, also have an impact on the current consumption.
2: The test conditions for all IDD measurements in active operation mode are:
All I/O pins set as outputs driven to Vss;
MCLR = VDD;
OSC1 = external square wave, from rail-to-rail (PRI_RUN and PRI_IDLE only).
PIC18F2XK20/4XK20
DS40001303H-page 356 2010-2015 Microchip Technology Inc.
TABLE 26-5: PRIMARY RUN SUPPLY CURRENT, PIC18F2XK20/4XK20
PIC18F2XK20/4XK20 St an dard Ope ratin g Conditions (unless otherwise stated)
Param .
No. Device Characteristics Typ. Max. Units Conditions
D014 Supply Current (IDD)(1, 2) 0.25 0. 45 mA -40° C to +125°C VDD = 1.8V FOSC = 1 MHz
(PRI_RUN,
EC oscillator )
D014A 0.50 0.75 mA -40°C to +125° C VDD = 3.0V
D015 2.7 3.2 mA -40°C to +125°C VDD = 2V FOSC = 20 MHz
(PRI_RUN,
EC oscillator )
D015A 4.3 5.0 mA -40°C to +125°C VDD = 3.0V
D016 12.2 14.0 mA -40°C to +85°C VDD = 3. 0V FOSC = 64 MHz
(PRI_RUN,
EC oscillator )
D017 2.1 2.9 mA -40°C to +125°C VDD = 1.8V FOSC = 4 MHz
16 MHz Internal
(PRI_RUN HS+PLL)
D017A 4.2 5.0 mA -40°C to +125°C VDD = 3.0V
D018 12.2 15.0 mA -40°C to +85°C VDD = 3. 0V FOSC = 16 MHz
64 MHz Internal
(PRI_RUN HS+PLL)
Note 1: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as
I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and
temperature, also have an impact on the current consumption.
2: The test conditions for all IDD measurements in active operation mode are:
All I/O pins set as outputs driven to Vss;
MCLR = VDD;
OSC1 = external square wave, from rail-to-rail (PRI_RUN and PRI_IDLE only).
TABLE 26-6: PRIMARY IDLE SUPPLY CURRENT, PIC18F2XK20/4XK20
PIC18F2XK20/4XK20 St an dard Ope ratin g Conditions (unless otherwise stated)
Param .
No. Device Characteristics Typ. Max. Units Conditions
D019 Supply Current (IDD)(1, 2) 0.05 0.07 mA -4 0°C to +125°C VDD = 1.8V FOSC = 1 MHz
(PRI_IDLE mode,
EC oscillator )
D019A 0.09 0.15 mA -40°C to +125°C VDD = 3.0V
D020 1.2 1.6 mA -40°C to +125°C VDD = 2.0V FOSC = 20 MHz
(PRI_IDLEmode,
EC oscillator )
D020A 1.8 2.5 mA -40°C to +125 °C VDD = 3.0V
D021 5.6 7.0 mA -40°C to +85°C VDD = 3.0V FOSC = 64 MHz
(PRI_IDLEmode,
EC oscillator )
Note 1: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as
I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and
temperature, also have an impact on the current consumption.
2: The test conditions for all IDD measurements in active operation mode are:
All I/O pins set as outputs driven to Vss;
MCLR = VDD;
OSC1 = external square wave, from rail-to-rail (PRI_RUN and PRI_IDLE only).
2010-2015 Microchip Technology Inc. DS40001303H-page 357
PIC18F2XK20/4XK20
TABLE 26-7: SECONDARY OSCILLATOR SUPPLY CURRENT, PIC18F2XK20/4XK20
PIC18F2XK20/4XK20 St an dard Ope ratin g Conditions (unless otherwise stated)
Param .
No. Device Characteristics Typ. Max. Units Conditions
D022 Supply Current (IDD)(1, 2) 5.5 9 A -40°C VDD = 1.8V FOSC = 32 kHz(3)
(SEC_RUN mode,
Time r1 as clock)
5.5 10 A+25°C
6.5 14 A+85°C
D022A 10.0 15 A -40°C VDD = 3.0V10.0 16 A+25°C
11.0 20 A+85°C
D023 2.0 5 A -40°C VDD = 1.8V FOSC = 32 kHz(3)
(SEC_IDLE mode,
Time r1 as clock)
2.0 5 A+25°C
2.5 9 A+85°C
D023A 3.5 8 A -40°C VDD = 3.0V3.5 8 A+25°C
4.0 12 A+85°C
Note 1: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as
I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and
temperature, also have an impact on the current consumption.
2: The test conditions for all IDD measurements in active operation mode are:
All I/O pins set as outputs driven to Vss;
MCLR = VDD;
OSC1 = external square wave, from rail-to-rail (PRI_RUN and PRI_IDLE only).
3: Low-Power mode on T1 osc. Low -Power mode is limited to 85°C.
PIC18F2XK20/4XK20
DS40001303H-page 358 2010-2015 Microchip Technology Inc.
TABLE 26-8: PERIPHERAL SUPPLY CURRENT, PIC18F2XK20/4XK20
PIC18F2XK20/4XK20 Standard Operating Conditions (unless otherwise stated)
Param.
No. Device Characteristics Typ. Max. Units Conditions
Modu l e D i fferential Cu rrents
D024
(IWDT)Watchdog Timer 0.7 2.0 A -40°C to +125°C VDD = 1. 8V
1.1 3.0 A -40°C to +125°C VDD = 3.0V
D024A
(IBOR)Br own-out Res et(2) 21 50 A-40C to +125CVDD = 2.0V
25 60 A-40C to +125CV
DD = 3.3V
0—A-40C to +125CV
DD = 3.3V Sleep mode,
BOREN<1:0> = 10
D024B
(IHLVD)High/Low-Voltage Detect(2) 13 30 A-40C to +125CVDD = 1.8-3.0V
D025
(IOSCB)
LP
Timer1 Oscillator 0.5 2.0 A-40CVDD = 1.8V 3 2 kHz on Timer1(1)
0.5 2.0 A+25C
0.7 2.0 A+85C
0.7 3.0 A-40CVDD = 3. 0V 32 kHz on Timer1(1)
0.7 3.0 A+25C
0.9 3.0 A+85C
D025A
(IOSCB)
HP
Timer1 Oscillator 11 30 A-40CVDD = 1. 8V 32 kHz on Timer1(3)
13 33 A+25C
15 35 A+85C
14 33 A-40CVDD = 3.0V 32 kHz on Timer1(3)
17 37 A+25C
19 40 A+85C
D026
(IAD)A/D Converter(4) 200 360 A-40C to +125CVDD = 1.8V A/D on, not convert ing
260 500 A-40C to +125CV
DD = 3.0V
IFRC 25A-40C to +125CVDD = 1.8V Adder for FRC
11 18 A-40C to +125CV
DD = 3.0V
Note 1: Low-Power mode on T1 osc. Low-Power m ode is limited t o 85°C.
2: BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be
less than t he sum of bot h specificat i ons.
3: High-Power mode in T1 osc.
4: A/D converter differential currents apply only in Run mode. In Sleep or Idle mode both the ADC and the FRC turn
off as soon as conversion (if an y) is complete.
2010-2015 Microchip Technology Inc. DS40001303H-page 359
PIC18F2XK20/4XK20
TABLE 26-9: INPUT/OUTPUT CHARACTERISTICS, PIC18F2XK20/4XK20
DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)
Param.
No. Symbol Characteristic Min. Typ.† Max. Units Conditions
VIL Input Low Voltage
I/O ports:
D030 with TTL buf fer VSS —0.15 VDD V
D031 with Schmitt T ri gge r VSS —0.2 VDD V
D032 MCLR VSS —0.2 VDD V
D033 OSC1 VSS —0.3 VDD V HS, HSPLL m ode s
D033A
D033B
D034
OSC1
OSC1
T13CKI
VSS
VSS
VSS
—
—
—
0.2 VDD
0.3 VDD
0.3 VDD
V
V
V
RC, EC modes(1)
XT, LP modes
VIH Input High Voltage
I/O ports:
D040 with TTL buf fer 0. 2 5 VDD +
0.8V —VDD V
D041 VIH with Schmitt Trigger: 0.8 VDD
0.9 VDD —
—VDD
VDD V
V2.4V < VDD < 3.6V
VDD < 2.4V
D042 VIH MCLR 0.8 VDD
0.9 VDD —
—VDD
VDD V
V2.4V < VDD < 3.6V
VDD < 2.4V
D043 OSC1 0.7 VDD —VDD V HS, HSPLL m odes
D043A
D043B
D043C
D044
OSC1
OSC1
OSC1
T13CKI
0.8 VDD
0.9 VDD
1.6
1.6
—
—
—
—
VDD
VDD
VDD
VDD
V
V
V
V
EC mode
RC mode(1)
XT, LP modes
IIL Input Leakage I/O and
MCLR(2,3) VSS VPIN VDD,
Pin at
high-impedance
D060
D061
D062
IIL
IIL
I/O ports
Input Leakage RA2
Input Leakage RA3
—
—
—
—
—
—
—
—
—
—
—
—
5
10
30
100
10
35
200
400
10
25
70
300
50
100
200
1000
100
250
750
2000
80
200
500
1500
nA
nA
nA
nA
nA
nA
nA
nA
nA
nA
nA
nA
+25°C
+60°C
+85°C
+125°C
+25°C
+60°C
+85°C
+125°C
+25°C
+60°C
+85°C
+125°C
IPU Weak Pull-up Current
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that
the PIC® device be driven with an external clock while in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
3: Negative current is defined as current sourced by the pin.
4: Paramete r is chara cteriz ed but not tes ted .
PIC18F2XK20/4XK20
DS40001303H-page 360 2010-2015 Microchip Technology Inc.
D070 IPURB PORTB w eak pull-up
current 50 90 400 AVDD = 3.0V , VPIN =
VSS
TABLE 26-9: INPUT/OUTPUT CHARACTERISTICS, PIC18F2XK20/4XK20 (CONTINUED)
DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)
Param.
No. Symbol Characteristic Min. Typ.† Max. Units Conditions
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that
the PIC® device be driven with an external clock while in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
3: Negative current is defined as current sourced by the pin.
4: Paramete r is chara cteriz ed but not tes ted .
2010-2015 Microchip Technology Inc. DS40001303H-page 361
PIC18F2XK20/4XK20
VOL Output Low Voltage
D080 I/O ports — — 0.6 V IOL = 8.5 mA, VDD
= 3.0V,
-40C to +85C
D083 OSC2/CLKOUT
(RC, RCIO, EC, ECIO
modes)
——0.6VIOL = 1.6 mA, VDD
= 3.0V,
-40C to +85C
VOH Output High Voltage(3)
D090 I/O ports VDD – 0.7 — — V IOH = -3.0 mA, VDD
= 3.0V,
-40C to +85C
D092 OSC2/CLKOUT
(RC, RCIO, EC, ECIO
modes)
VDD – 0.7 — — V IOH = -1.3 mA, VDD
= 3.0V,
-40C to +85C
Capacitive Loading
Specs
on Output Pi ns
D100(4) COSC2 OSC2 pin —— 15 pF In XT, HS and LP
modes w hen
exte rnal clock is
used to dr ive
OSC1
D101 CIO All I/O pins and OSC2
(in RC mode) — — 50 pF To meet the AC
Timing
Specifications
D102 CBSCL, SDA — — 400 pF I2C™ Specification
TABLE 26-9: INPUT/OUTPUT CHARACTERISTICS, PIC18F2XK20/4XK20 (CONTINUED)
DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)
Param.
No. Symbol Characteristic Min. Typ.† Max. Units Conditions
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that
the PIC® device be driven with an external clock while in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
3: Negative current is defined as current sourced by the pin.
4: Paramete r is chara cteriz ed but not tes ted .
PIC18F2XK20/4XK20
DS40001303H-page 362 2010-2015 Microchip Technology Inc.
TABLE 26-10: MEMORY PROGRAMMING REQUIREMENTS
DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)
Param.
No. Sym. Characteristic Min. Typ.† Max. Units Conditions
Internal Program Memory
Programming Specifications(1)
D110 VPP Voltage on MCLR /VPP/RE3 pin VDD + 8 — 9 V (Note 3, Note 4)
D113 IDDP Supply Current during
Programming ——10mA
Data EEPROM Memory
D120 EDByte Endurance 100K — — E/W -40C to +85C
D121 VDRW VDD for Read/Write 1.8 — 3.6 V Using EECON to
read/write
D122 TDEW Erase/Write Cycle Time — 4 — ms
D123 TRETD Characteristic Retention 40 — — Year Provided no other
specifications are violated
D124 TREF Number of Total Erase/Write
Cycles before Refresh(2) 1M 10M — E/W -40°C to +85°C
Program Flash Memory
D130 EPCell Endurance 10K — — E/W -40C to +85C (Note 5)
D131 VPR VDD for Read 1.8 — 3.6 V
D132 VIW VDD for Row Erase or Write 2.2 — 3.6 V
D133 TIW Self-timed Write Cycle Time — 2 — ms
D134 TRETD Characteristic Retention 40 — — Year Provided no other
specifications are violated
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: These specifications are for programming the on-chip program memory through the use of table write
instructions.
2: Refer to Section 7.8 “Using the Data EEPROM” for a more detailed discussion on data EEPROM
endurance.
3: Require d on ly if sing le -su pp ly pro gr am m ing is disa ble d.
4: The MPLAB ICD 2 does not support variable VPP output. Circuitry to limit the ICD 2 VPP voltage must be
placed between the ICD 2 and target system when programming or debugging with the ICD 2.
5: Self-write and Block Erase.
2010-2015 Microchip Technology Inc. DS40001303H-page 363
PIC18F2XK20/4XK20
26.4 Analog Characteristics
TABLE 26-11: COMPARATOR SPECIFICATIONS
Operating Condit ions : 1.8V < VDD < 3.6V, -40°C < TA < +125°C (unless otherwise stated).
Param.
No. Sym. Characteristics Min. Typ. Max. Units Comments
CM01 VIOFF Input Offset Voltage — 10 50 mV VREF = VDD/2,
High-Power mo de
—1280mVV
REF = VDD/2,
Low-Power mode
CM02 VICM Input Common-mode V ol t age VSS —VDD V
CM04 TRESP Response Time — 200 400 ns H igh-Power mode
— 300 600 ns Low-Power mode
CM05 TMC2OV Compa rato r Mode Chan ge to
Output Valid* ——10s
* These parameters are characterized but not tested.
Note 1: Response time measured with one comparator input at VDD/2, while the other input transitions
from VSS to VDD.
TABLE 26-12: CVREF VOLTAGE REFERENCE SPECIFICATIONS
Operating Condit ions : 1.8V < VDD < 3.6V, -40°C < TA < +125°C (unless otherwise stated).
Param.
No. Sym. Characteristics Min. Typ. Max. Units Comments
CV01* CLSB Step Size(2) —
—VDD/24
VDD/32 —
—V
VLow Range (VRR = 1)
High Range (VRR = 0)
CV02* CACC Abso lute A ccuracy — — 1/2 LSb
CV03* CRUnit Resistor Value (R) — 3k —
CV04* CST Settling Time(1) —7.510s
* These parameters are characterized but not tested.
Note 1: Settling time measured while CVRR = 1 and CVR3:CVR0 transitions from ‘0000’ to ‘1111’.
2: See Section 21.1 “Comparator Voltage Reference” for more information.
TABLE 26-13: FIXED VOLTAGE REFERENCE (FVR) SPECIFICATIONS
Operating Condit ions : 1.8V < VDD < 3.6V, -40°C < TA < +125°C (unless otherwise stated).
VR Voltage Reference Specifications Standard Operating Conditions (unless otherwise stated)
Param.
No. Sym. Characteristics Min. Typ. Max. Units Comments
VR01 VROUT VR voltage output 1.15 1.20 1.25 V -40°C to +85°C
1.10 1.20 1.30 V +85°C to +125 °C
VR02* TCVOUT Voltage drift temperature
coefficient — <50 — ppm/C -40°C to +40°C (See
Figure 27-34)
VR03* VROUT/
VDD Voltage d rift with respect to
VDD regulat ion — <2000 — V/V 25°C, 2.0 to 3.3V (See
Figure 27-33)
VR04* TSTABLE Settling Time — 25 100 s 0 to 125°C
* These parameters are characterized but not tested.
PIC18F2XK20/4XK20
DS40001303H-page 364 2010-2015 Microchip Technology Inc.
FIGURE 26-3: HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS
TABLE 26-14: HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Param.
No. Symbol Characteristic Min. Typ.† Max. Units Conditions
D420 HLVD Voltage on
VDD Transition
High-to-Low
HLVDL<3:0> = 0000 1.70 1.85 2.00 V
HLVDL<3:0> = 0001 1.80 1.95 2.10 V
HLVDL<3:0> = 0010 1.91 2.06 2.21 V
HLVDL<3:0> = 0011 2.02 2.17 2.32 V
HLVDL<3:0> = 0100 2.15 2.30 2.45 V
HLVDL<3:0> = 0101 2.22 2.37 2.52 V
HLVDL<3:0> = 0110 2.38 2.53 2.68 V
HLVDL<3:0> = 0111 2.46 2.61 2.76 V
HLVDL<3:0> = 1000 2.55 2.70 2.85 V
HLVDL<3:0> = 1001 2.65 2.80 2.95 V
HLVDL<3:0> = 1010 2.75 2.90 3.05 V
HLVDL<3:0> = 1011 2.87 3.02 3.17 V
HLVDL<3:0> = 1100 2.98 3.13 3.28 V
HLVDL<3:0> = 1101 3.26 3.41 3.56 V
HLVDL<3:0> = 1110 3.42 3.57 3.72 V
† Production tested at TAMB = 25°C. Specifications over temperature limits ensured by characterization.
VHLVD
HLVDIF
VDD
(HLVDIF set by hardware)
(HLVDIF can be
cleared by sof tware)
2010-2015 Microchip Technology Inc. DS40001303H-page 365
PIC18F2XK20/4XK20
TABLE 26-15: THERMAL CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Param.
No. Sym. Characteristic Typ. Units Conditions
TH01 JA Thermal Resistance Junction to
Ambient 60.0 C/W 28-pin SPDIP package
80.3 C/W 28-pin SOIC pa ckage
90.0 C/W 28-pin SSOP package
36.0 C/W 28-pin QFN 6x6 mm package
48.0 C/W 28-pin UQFN 4x4 mm package
47.2 C/W 40-pin PDIP package
46.0 C/W 44-pin TQFP package
24.4 C/W 44-pin QFN package
41.0 C/W 40-pin UQFN 5x5 mm package
TH02 JC Ther mal Resistance Junction to
Case 31.4 C/W 28-pin SPDIP package
24.0 C/W 28-pin SOIC pa ckage
24.0 C/W 28-pin SSOP package
6.0 C/W 28-pin QFN 6x6 mm package
12.0 C/W 28-pin UQFN 4x4 mm package
24.7 C/W 40-pin PDIP package
14.5 C/W 44-pin TQFP package
20.0 C/W 44-pin QFN package
50.5 C/W 40-pin UQFN 5x5 mm package
TH03 TJMAX Maximum Junction Temperature 150 C—
TH04 PD Power Dissipation — W PD = PINTERNAL + PI/O
TH05 PINTERNAL Internal Power Dissipation — W PINTERNAL = IDD X VDD(1)
TH06 PI/O I/O Power Dissipation — W PI/O =(IOL * VOL) + (IOH * (VDD - VOH))
TH07 PDER Derated Power — W PDER = PDMAX (TJ - TA)/JA(2)
Note 1: IDD is current to run the chip alone without driving any load on the output pins.
2: TA = Ambient Temperature, TJ = Junction Temperature
PIC18F2XK20/4XK20
DS40001303H-page 366 2010-2015 Microchip Technology Inc.
26.5 AC (Timing) Characteristics
26.5.1 TIMING PARAMETER SYMBOLOGY
The timing parameter symbols have been created
using one of the following formats:
1. TppS2ppS 3. TCC:ST (I2C™ spec ifications only)
2. TppS 4. Ts (I2C specifications only)
TF Frequency T Time
Lowercase letters (pp) and thei r meanings:
pp cc CCP1 osc OSC1
ck CLKOUT rd RD
cs CS rw RD or WR
di SDI sc SCK
do SDO ss SS
dt Data in t0 T0CKI
io I/O port t1 T13CKI
mc MCLR wr WR
Uppercase letters and their meanings:
SF Fall P Period
HHigh RRise
I Inv alid (High-impedance) V Valid
L Low Z High-impedance
I2C only
AA outpu t access High High
BUF Bus free Low Lo w
TCC:ST (I2C specif ic ati on s only )
CC HD Hold SU Setup
ST DAT DATA input hold STO Stop condition
STA Start condition
2010-2015 Microchip Technology Inc. DS40001303H-page 367
PIC18F2XK20/4XK20
26.5.2 TIMING CONDITIONS
The temperature and vo lt a ges s pec ifi ed in Table 26-16
apply to all timing specifications unless otherwise
noted. Figure 26-4 specifies the load conditions for the
timing specification s.
FIGURE 26-4: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
26.5.3 TIMING DIAGRAMS AND SPECIFICATIONS
FIGURE 26-5: EXTER NAL CLOCK TIMING (ALL MODES EXCEPT PLL)
TABLE 26-16: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC
AC CHARACTERISTICS Standard Operating Conditions (unle ss other wis e stated)
Operating voltage VDD range as described in DC spec Section 26-1 and
Section 26-9.
VDD/2
CL
RL
Pin
Pin
VSS
VSS
CL
RL=464
CL= 50 pF for all pi ns except OSC2/C LKOUT
and including D and E outputs as ports
Load Condition 1 Load Condition 2
OSC1
CLKOUT
Q4 Q1 Q2 Q3 Q4 Q1
1
23344
PIC18F2XK20/4XK20
DS40001303H-page 368 2010-2015 Microchip Technology Inc.
TABLE 26-17: EXTERNAL CLOCK TIMING REQUIREMENTS
Param.
No. Symbol Characteristic Min. Max. Units Conditions
1A FOSC External CLKIN
Frequency(1) DC 48 MHz EC, ECIO Oscillator mode,
(Extended Range Devices)
DC 64 MHz EC, ECIO Oscillator mode,
(Industrial Range Devices)
Oscillator Frequency(1) DC 4 MHz RC Oscillator mode
0.1 4 MHz XT Oscillator mode
4 25 MHz HS Oscillator mode
4 16 MHz HS + PLL Oscillator mode,
(Industrial Range Devices)
4 12 MHz HS + PLL Oscillator mode,
(Extended Range Devices)
5 200 kHz LP Oscillator mode
1T
OSC External CLKIN Period(1) 20 .8 — ns EC, ECIO, Oscillator mo de
(Extended Range Devices)
15.6 — ns EC, ECIO, Oscilla tor mo de,
(Industrial Range Devices)
Oscillator Period(1) 250 — ns RC Oscillator mode
250 10,000 ns XT Oscillator mode
40
62.5
83.3
250
250
250
ns
ns
ns
HS Oscillator mode
HS + PLL Oscillator mode,
(Industrial range devices)
HS + PLL Oscillator mode,
(Extended Range Devices)
5200s LP Oscillator mo de
2T
CY Instruction Cycle Time(1) 62.5 — ns TCY = 4/FOSC
3TOSL,
TOSHExternal Cloc k in (OS C1)
High or Low Time 30 — ns XT Oscillator mode
2.5 — s LP Oscilla tor mo de
10 — ns HS Oscillator mode
4TOSR,
TOSFExternal Cloc k in (OS C1)
Rise or Fall Time — 20 ns XT Oscillator mode
— 50 ns LP Oscillator mo de
— 7.5 ns HS Oscillator mode
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period for all configurations
except PLL. All specified values are based on characterization data for that particular oscillator type under
standard operatin g c ond iti ons with the device executin g c od e. Ex c eed ing th ese specified li mits may res ult
in an u nst able oscil lator o peration a nd/or high er than ex pected c urrent cons umption . All devi ces ar e tested
to oper ate a t “min .” va lue s wit h an ex ternal clock applied to the OSC1/CLKIN pin. Whe n an exte rna l cl ock
input is used, the “max.” cycle time limit is “DC” (no clock) for all devices.
2010-2015 Microchip Technology Inc. DS40001303H-page 369
PIC18F2XK20/4XK20
TABLE 26-18: PLL CLOCK TIMING SP ECIFICATIONS (VDD = 1.8V TO 3.6V)
Param.
No. Sym. Characteristic Min. Typ.† Max. Units Conditions
F10 FOSC Oscillator Frequency Range 4 — 4 MHz VDD = 1.8-2.0V
4—5MHzVDD = 2.0-3.0V
4—16MHzV
DD = 3.0-3.6V,
Industrial Range Devices
4—12MHz
VDD = 3.0-3.6V,
Extended Range Devices
F11 FSYS On-Chi p VCO System Frequency 16 — 16 MHz VDD = 1.8-2.0V
16 — 20 MHz VDD = 2.0-3.0V
16 — 64 MHz VDD = 3.0-3.6V,
Industrial Range Devices
16 — 48 MHz VDD = 3.0-3.6V,
Extended Range Devices
F12 trc PLL Start-up Time (Lock Time) — — 2 ms
F13 CLK CLKOUT Stabil ity (Jitter) -2 — +2 %
TABLE 26-19: INTERNAL OSCILLATORS ACCURACY, PIC18F2XK20/4XK20
PIC18F2XK20/4XK20 Standard Operating Conditions (unless otherwise stated)
Param.
No. Characteristic Min. Typ. Max. Units Conditions
OA1 HFINTOSC Accuracy @ Freq = 16 MHz, 8 MHz, 4 MHz, 2 MHz, 1 MHz, 500 kHz, 250 kHz(1)
-2 0 +2 % +0°C to +70°C VDD = 1.8-3.6 V
-3 — +2 % +70°C to +85°C VDD = 1.8-3.6V
-5 — +5 % -40°C to 0°C and
+85°C to 125°C VDD = 1.8-3.6V
OA2 LFINTOSC Accura cy @ Freq = 31.25 kHz
-15 — +15 % -40°C to +125°C VDD = 1.8-3.6V
Note 1: Frequency calibrated at 25°C. OSCTUNE register can be used to compensate for temperature drift.
PIC18F2XK20/4XK20
DS40001303H-page 370 2010-2015 Microchip Technology Inc.
FIGURE 26-6: CLKOUT AND I/O TIMING
TABLE 26-20: CLKOUT AND I/O TIMING REQUIREMENTS
Param.
No. Symbol Characteristic Min. Typ. Max. Unit
sCondition
s
10 TosH2ckL OSC1 to CLKOUT — 75 200 ns (Note 1)
11 TosH2ck
HOSC1 to CLKOUT — 75 200 ns (Note 1)
12 TckR CLKOUT Rise Time — 35 100 ns (Note 1)
13 TckF CLKOUT Fall Time — 35 100 ns (Note 1)
14 TckL2ioV CLKOUT to Port Out Valid — — 0.5 TCY +
20 ns (Note 1)
15 TioV2ckH Port In Valid before CLKOUT 0.25 TCY +
25 ——ns (Note 1)
16 TckH2ioI Port In Hold after CLKOUT 0——ns(Note 1)
17 TosH2ioV OSC1 (Q1 cycle) to Port Out Valid — 50 150 ns
18 TosH2ioI OSC1 (Q2 cycle) to Port Input Invalid
(I/O in hold time) 100 — — ns
19 TioV2osH Port Input V alid to OSC1 (I/O in setup
time) 0——ns
20 TioR Port Output Rise Time — 10 25 ns
21 TioF Port Ou tput Fall Time — 10 25 ns
22† TINP INTx pin High or Low Time 20 — — ns
23† TRBP RB<7:4> Change KBIx High or Low Time TCY ——ns
† These parameters are asynchronous events not related to any internal clock edges.
Note 1: Measurements are taken in RC mode, where CLKOUT output is 4 x TOSC.
Note: Refer to Figure 26-4 for load conditions.
OSC1
CLKOUT
I/O pin
(Input)
I/O pin
(Output)
Q4 Q1 Q2 Q3
10
13 14
17
20, 21
19 18
15
11
12
16
Old Value New Value
2010-2015 Microchip Technology Inc. DS40001303H-page 371
PIC18F2XK20/4XK20
FIGURE 26-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND
POWER-UP TIMER TIMING
FIGURE 26-8: BROWN-OUT RESET TIMING
VDD
MCLR
Internal
POR
PWRT
Time-out
OSC
Time-out
Internal
Reset
Watchdog
Timer
Reset
33
32
30
31
34
I/O pins
34
Note: Refer to Figure 26-4 for load conditions.
VDD BVDD
35 VBGAP = 1.2V
VIVRST
Enable Internal
Internal Reference 36
Reference V olt age
Voltage Stable
PIC18F2XK20/4XK20
DS40001303H-page 372 2010-2015 Microchip Technology Inc.
FIGURE 26-9: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
TABLE 26-21: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET REQUIREMENTS
Param.
No. Symbol Characteristic Min. Typ. Max. Units Conditions
30 TmcL MCLR Pulse W idth (low) 2 — — s
31 TWDT Watchdog Timer Time-out Period
(no postscaler) 3.5 4.1 4.7 ms 1:1 prescale r
32 TOST Oscillation Start-up Timer Period 1024 TOSC — 1024 TOSC —TOSC = OSC1 peri od
33 TPWRT Power-up Timer Period 54.8 64.4 74.1 ms
34 TIOZ I/O High-Impedance from MCLR
Low or Watchdog Timer Reset —2—s
35 TBOR Brown-out Reset Puls e Width 200 — — sVDD BVDD (see
D005)
36 TIVRST Internal Reference Voltage Stable — 25 35 s
37 THLVD High /L ow- Vol t a ge De t ec t Pu ls e
Width 200 — — sVDD VHLVD
38 TCSD CPU Start-up Time 5 — 10 s
39 TIOBST Time for HF-INTOSC to Stabilize — 0.25 1 ms
Note: Refer to Figure 26-4 for load conditions.
46
47
45
48
41
42
40
T0CKI
T1OSO/T13CKI
TMR0 or
TMR1
2010-2015 Microchip Technology Inc. DS40001303H-page 373
PIC18F2XK20/4XK20
FIGURE 26-10: CAPTURE/COMPARE/PWM TIMINGS (ALL CCP MODULES)
TABLE 26-22: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Param
.
No. Symbol Characteristic Min. Max. Units Conditions
40 Tt0H T0CKI High Pulse Width No prescaler 0.5 TCY + 20 — ns
With prescaler 1 0 — ns
41 Tt0L T0CKI Low Pulse Width No prescaler 0.5 TCY + 20 — ns
With prescaler 1 0 — ns
42 Tt0P T0CKI Period No prescaler TCY + 10 — ns
With prescaler Gr eater of:
20 ns or
(TCY + 40)/N
— ns N = prescale
value
(1, 2, 4,..., 256)
45 Tt1H T13CKI
High Time Synchronous, no prescaler 0.5 TCY + 20 — ns
Synchronous,
with prescaler 10 — ns
Asynchronous 30 — ns
46 Tt1L T13CKI
Low Time Synchronous, no prescaler 0.5 TCY + 5 — ns
Synchronous,
with prescaler 10 — ns
Asynchronous 30 — ns
47 Tt1P T13CKI
Input Period Synchronous Greater of:
20 ns or
(TCY + 40)/N
— ns N = prescale
value (1, 2, 4, 8)
Asynchronous 60 — ns
Ft1 T13CKI Clock Input Frequency Range DC 50 kHz
48 Tcke2tmrI Delay from External T13CKI Clock Edge to
Timer Increment 2 TOSC 7 TOSC —
Note: Refer to Figure 26-4 for load conditions.
CCPx
(Capture Mode)
50 51
52
CCPx
53 54
(Compare or PWM Mode)
PIC18F2XK20/4XK20
DS40001303H-page 374 2010-2015 Microchip Technology Inc.
FIGURE 26-11: PARALLEL SLAVE PORT TIMING (PIC18F4XK20)
TABLE 26-23: CAPTURE/COMPARE/PWM REQUIREMENTS (ALL CCP MODULES)
Param.
No. Symbol Characteristic Min. Max. Units Conditions
50 T ccL CCPx Input Low
Time No prescaler 0.5 TCY + 20 — ns
With
prescaler 10 — ns
51 TccH CCPx Input
High Time No prescaler 0.5 TCY + 20 — ns
With
prescaler 10 — ns
52 Tc cP CCPx Input Period 3 TCY + 40
N— ns N = prescale
value (1, 4 or
16)
53 TccR CCPx Output Fal l Time — 25 ns
54 TccF CCPx Output Fall Time — 25 ns
TABLE 26-24: PARALLEL SLAVE PORT REQUIREMENTS (PIC18F4XK20)
Param.
No. Symbol Characteristic Min. Max. Units Conditions
62 TdtV2wrH Data In Valid before WR or CS
(setup time) 20 — ns
63 TwrH2dtI WR or CS to Data–In Invalid (hold time) 20 — ns
64 TrdL2dtV RD and CS to Data–Out Valid — 80 ns
65 TrdH2dtI RD or CS to Data–Out Invalid 10 3 0 ns
66 TibfINH Inhibit of the IBF Flag bit being cleared from
WR or CS —3 T
CY
Note: Refer to Figure 26-4 for load conditions.
RE2/CS
RE0/RD
RE1/WR
RD7:RD0
62
63
64
65
2010-2015 Microchip Technology Inc. DS40001303H-page 375
PIC18F2XK20/4XK20
FIGURE 26-12 : EX AMP L E SPI MASTER MODE TIMING (CKE = 0)
TABLE 26-25: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0)
Param.
No. Symbol Characteristic Min. Max. Units Conditions
70 TssL2scH,
TssL2scL SS to SCK or SCK Input TCY —ns
71 TscH SCK Input High Time
(Slave mode) Continuous 1.25 TCY + 30 — ns
71A Single Byte 40 — ns (Note 1)
72 TscL SCK Input Low Time
(Slave mode) Continuous 1.25 TCY + 30 — ns
72A Single Byte 40 — ns (Note 1)
73 TdiV2scH,
TdiV2scL Setup Time of SDI Data Input to SCK Edge 100 — ns
73A Tb2b Last Cl ock Edge o f Byte 1 to t he 1st Clock Edg e
of Byte 2 1.5 TCY + 40 — ns (Note 2)
74 TscH2diL,
TscL2diL Hold Time of SDI Data Input to SCK Edge 100 — ns
75 TdoR SDO Data Output Rise Time — 25 ns
76 TdoF SDO Data Output Fall Time — 25 ns
78 TscR SCK Output Rise Time
(Master mo de) —25ns
79 TscF SCK Output Fall Time (Master mode) — 25 ns
80 TscH2doV,
TscL2doV SDO Data Output Valid after SCK Edge — 50 ns
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
70
71 72
73 74
75, 76
78
79
80
79
78
MSb LSb
bit 6 - - - - - -1
MSb In LSb In
bit 6 - - - -1
Note: Refer to Figure 26-4 for load conditions.
PIC18F2XK20/4XK20
DS40001303H-page 376 2010-2015 Microchip Technology Inc.
FIGURE 26-13 : EX AMP L E SPI MASTER MODE TIMING (CKE = 1)
TABLE 26-26: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1)
Param.
No. Symbol Characteristic Min. Max. Units Conditions
71 TscH SCK Input High Time
(Slave mode) Continuous 1.25 TCY + 30 — ns
71A Single Byte 40 — ns (Note 1)
72 TscL SCK Input Low Time
(Slave mode) Continuous 1.25 TCY + 30 — ns
72A Single Byte 40 — ns (Note 1)
73 TdiV2scH,
TdiV2scL Setup Time of SDI Data Input to SCK Edge 100 — ns
73A Tb2b Last Clock Edge of Byte 1 to the 1st Clock Edge
of Byte 2 1.5 TCY + 40 — ns (N ote 2)
74 TscH2diL,
TscL2diL Hold Time of SDI Data Input to SCK Edge 100 — ns
75 TdoR SDO Data Output Rise Time — 25 ns
76 TdoF SDO Data Output Fall Time — 25 ns
78 TscR SCK Output Rise Time
(Master mode) —25ns
79 TscF SCK Output Fall Time (Master mode) — 25 ns
80 TscH2doV,
TscL2doV SDO Data Output Valid after SCK Edge — 50 ns
81 TdoV2scH,
TdoV2scL SDO Data Output Setup to SCK Edge TCY —ns
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
81
71 72
74
75, 76
78
80
MSb
79
73
MSb In
bit 6 - - - - - -1
LSb In
bit 6 - - - -1
LSb
Note: Refer to Figure 26-4 for load conditions.
2010-2015 Microchip Technology Inc. DS40001303H-page 377
PIC18F2XK20/4XK20
FIGURE 26-14 : EX AMP L E SPI SLAVE MODE TIMING (CKE = 0)
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
70
71 72
73 74
75, 76 77
78
79
80
79
78
SDI
MSb LSb
bit 6 - - - - - -1
MSb In bit 6 - - - -1 LSb In
83
Note: Refer to Figure 26-4 for load conditions.
TABLE 26-27: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING, CKE = 0)
Param.
No. Symbol Characteristic Min. Max. Units Conditions
70 TssL2scH,
TssL2scL SS to SCK or SCK Input TCY —ns
71 TscH SCK Input High Time
(Slave mode) Continuo us 1.25 TCY + 30 — ns
71A Single Byte 40 — ns (Note 1)
72 TscL SCK In put Low Time
(Slave mode) Continuo us 1.25 TCY + 30 — ns
72A Single Byte 40 — ns (Note 1)
73 TdiV2scH,
TdiV2scL Setup Time of SDI Data Input to SCK Edge 100 — ns
73A Tb2b Last Clock Edge of Byte 1 to the First Clock Edge of
Byte 2 1.5 TCY + 40 — ns (Note 2)
74 TscH2diL,
TscL2diL Hold Time of SDI Data Input to SCK Edge 100 — ns
75 TdoR SDO Data Output Rise Time — 25 ns
76 TdoF SDO Data Output Fall Time — 25 ns
77 TssH2doZ SS to SDO Output High-Impedance 10 50 ns
78 TscR SCK Out put Rise Time (Ma ster mode) — 25 ns
79 TscF SCK Output Fall Time (Maste r mode ) — 25 ns
80 TscH2doV,
TscL2doV SDO Data Output Valid after SCK Edge — 50 ns
83 TscH2ssH,
TscL2ssH SS after SCK edge 1.5 TCY + 40 — ns
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.
PIC18F2XK20/4XK20
DS40001303H-page 378 2010-2015 Microchip Technology Inc.
FIGURE 26-15 : EX AMP L E SPI SLAVE MODE TIMING (CKE = 1)
TABLE 26-28: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1)
Param.
No. Symbol Characteristic Min. Max. Units Conditions
70 TssL2scH,
TssL2scL SS to SCK or SCK Input TCY —ns
71 TscH SCK Input High Time
(Slave mode) Continuous 1.25 TCY +
30 —ns
71A Single Byte 40 — ns (Note 1)
72 TscL SCK Input Low Time
(Slave mode) Continuous 1.25 TCY +
30 —ns
72A Single Byte 40 — ns (Note 1)
73A Tb2b Last Clock Edge of Byte 1 to the First Clock Edge of
Byte 2 1.5 TCY + 40 — ns (Note 2)
74 TscH2diL,
TscL2diL Hold Time of SDI Data Input to SCK Edge 100 — ns
75 TdoR SDO Data Output Rise Time — 25 ns
76 TdoF SDO Data Output Fall Time — 25 ns
77 TssH2doZ SS to SDO Output High-Im pedance 10 50 ns
78 TscR SCK Output Rise Time
(Master mo de) —25ns
79 TscF SCK Output Fall Time (Master mode) — 25 ns
80 TscH2doV,
TscL2doV SDO Data Output Valid after SCK Edge — 50 ns
82 TssL2doV SDO Data Output Valid after SS Edge — 50 ns
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
70
71 72
82
SDI
74
75, 76
MSb bit 6 - - - - - -1 LSb
77
MSb In bit 6 - - - -1 LSb In
80
83
Note: Re fe r to Figure 26-4 for load conditions.
2010-2015 Microchip Technology Inc. DS40001303H-page 379
PIC18F2XK20/4XK20
FIGURE 26-16 : I2C™ BUS START/STOP BITS T I MING
83 TscH2ssH,
TscL2ssH SS after SCK Edge 1.5 TCY + 40 — ns
TABLE 26-29: I2C™ BUS START/STOP BITS REQUIREMENTS (SLAVE MODE)
Param.
No. Symbol Characteristic Min. Max. Units Conditions
90 TSU:STA Start Condition 100 kHz mode 4700 — ns Only relevant for Repeated
Start condition
Setup Time 400 kHz mode 600 —
91 THD:STA Start Condition 100 kHz mode 4000 — ns After this period, the first
clock pulse is generated
Hold Time 400 kHz mode 600 —
92 TSU:STO Stop Conditio n 100 kHz mode 4700 — ns
Setup Time 400 kHz mode 600 —
93 THD:STO Stop Cond ition 100 kHz mode 4000 — ns
Hold Time 400 kHz mode 600 —
TABLE 26-28: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1) (CONTINUED)
Param.
No. Symbol Characteristic Min. Max. Units Conditions
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.
Note: Refer to Figure 26-4 for load conditions.
91
92
93
SCL
SDA
Start
Condition Stop
Condition
90
2010-2015 Microchip Technology Inc. DS40001303H-page 381
PIC18F2XK20/4XK20
TABLE 26-30: I2C™ BUS DATA REQUIREMENTS (SLAVE MODE)
Param.
No. Symbol Characteristic Min. Max. Units Conditions
100 THIGH Clock High Time 100 kHz mode 4.0 — s PIC18FXXXX must
operate at a minimum of
1.5 MHz
400 kHz mode 0.6 — s PIC18FXXXX must
operate at a minim um of 10
MHz
SSP Module 1.5 TCY —
101 TLOW Clock Low Time 100 kHz mode 4.7 — s PIC18FXXXX must
operate at a minimum of
1.5 MHz
400 kHz mode 1.3 — s PIC18FXXXX must
operate at a minim um of 10
MHz
SSP Module 1.5 TCY —
102 TRSDA and SCL Rise
Time 100 kHz mode — 1000 ns
400 kHz mode 20 + 0.1 CB300 ns CB is specified to be from
10 to 400 pF
103 TFSDA and SCL Fall
Time 100 kHz mode — 300 ns
400 kHz mode 20 + 0.1 CB300 ns CB is specified to be from
10 to 400 pF
90 TSU:STA Start Condition
Setup Time 100 kHz mode 4.7 — s Only r ele vant f or Re peated
Start condition
400 kHz mode 0.6 — s
91 THD:STA Start Condition
Hold Time 100 kHz mode 4.0 — s After this period, the first
clock pulse is generated
400 kHz mode 0.6 — s
106 THD:DAT Data Input Hold
Time 100 kHz mode 0 — ns
400 kHz mode 0 0.9 s
107 TSU:DAT Data Input Setup
Time 100 kHz mode 250 — ns (Note 2)
400 kHz mode 100 — ns
92 TSU:STO Stop Condition
Setup Time 100 kHz mode 4.7 — s
400 kHz mode 0.6 — s
109 TAA Output Valid from
Clock 100 kHz mode — 3500 ns (Note 1)
400 kHz mode — — ns
110 TBUF Bus Free Time 100 kHz mode 4.7 — s Time the bus must be free
before a new tr ansmission
can start
400 kHz mode 1.3 — s
D102 CBBus Capacitive Loading — 400 pF
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
2: A fast mode I2C bus device can be used in a standard mode I2C bus syste m but the requ ire me nt,
TSU:DAT 250 ns, must then be met. This will automatically be the case if the device does not stretch the
LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must
output the next data bit to the SDA line, TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the
standard mode I2C bus specification), before the SCL line is released.
PIC18F2XK20/4XK20
DS40001303H-page 382 2010-2015 Microchip Technology Inc.
FIGURE 26-18: MASTER SS P I2C™ BUS START/STOP BITS TIMING WAVEFORMS
FIGURE 26-19: MASTER SS P I2C™ BUS DATA TIMING
TABLE 26-31: MASTER SSP I2C™ BUS START/STOP BITS REQUIREMENTS
Param.
No. Symbol Characteristic Min. Max. Units Conditions
90 TSU:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns Only relevant for
Repeat ed Star t
condition
Setup Time 400 kHz mode 2(TOSC)(BRG + 1) —
1 MHz mode(1) 2(TOSC)(BRG + 1) —
91 THD:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns After this period, the
first clock pulse is
generated
Hold Time 400 kHz mode 2(TOSC)(BRG + 1) —
1 MHz mode(1) 2(TOSC)(BRG + 1) —
92 TSU:STO Stop Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns
Setup Time 400 kHz mode 2(TOSC)(BRG + 1) —
1 MHz mode(1) 2(TOSC)(BRG + 1) —
93 THD:STO Stop Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns
Hold Time 400 kHz mode 2(TOSC)(BRG + 1) —
1 MHz mode(1) 2(TOSC)(BRG + 1) —
Note 1: Maximum pin capacitance = 10 pF for all I2C pins.
Note: Refer to Figure 26-4 for load conditions.
91 93
SCL
SDA
Start
Condition Stop
Condition
90 92
Note: Refer to Figure 26-4 for load conditions.
90 91 92
100 101
103
106 107
109 109 110
102
SCL
SDA
In
SDA
Out
2010-2015 Microchip Technology Inc. DS40001303H-page 383
PIC18F2XK20/4XK20
TABLE 26-32: MASTER SSP I2C™ BUS DATA REQUIREMENTS
Param.
No. Symbol Characteristic Min. Max. Units Conditions
100 THIGH Clock High Time 100 kHz mode 2(TOSC)(BRG + 1) — ms
400 kHz mode 2(TOSC)(BRG + 1) — ms
1 MHz mode(1) 2(TOSC)(BRG + 1) — ms
101 TLOW Clock Low Time 100 kHz mode 2(TOSC)(BRG + 1) — ms
400 kHz mode 2(TOSC)(BRG + 1) — ms
1 MHz mode(1) 2(TOSC)(BRG + 1) — ms
102 TRSDA and SCL
Rise Time 100 kHz mode — 1000 ns CB is specified to be
from 10 to 400 pF
400 kHz mode 20 + 0.1 CB300 ns
1 MHz mode(1) — 300 ns
103 TFSDA and SCL
Fall Time 100 kHz mode — 300 ns CB is specified t o be
from 10 to 400 pF
400 kHz mode 20 + 0.1 CB 300 ns
1 MHz mode(1) — 100 ns
90 TSU:STA Start Condition
Setup Time 100 kHz mode 2(TOSC)(BRG + 1) — ms Only relevant for
Repeated Start
condition
400 kHz mode 2(TOSC)(BRG + 1) — ms
1 MHz mode(1) 2(TOSC)(BRG + 1) — ms
91 THD:STA Start C ond iti on
Hold Time 100 kHz mode 2(TOSC)(BRG + 1) — ms After this period, the firs t
clock pulse is generated
400 kHz mode 2(TOSC)(BRG + 1) — ms
1 MHz mode(1) 2(TOSC)(BRG + 1) — ms
106 THD:DAT Data Input
Hold Time 100 kHz mode 0 — ns
400 kHz mode 0 0.9 ms
107 TSU:DAT Data Input
Setup Time 100 kHz mode 250 — ns (Note 2)
400 kHz mode 100 — ns
92 TSU:STO S top C ond iti on
Setup Time 100 kHz mode 2(TOSC)(BRG + 1) — ms
400 kHz mode 2(TOSC)(BRG + 1) — ms
1 MHz mode(1) 2(TOSC)(BRG + 1) — ms
109 TAA Output Valid
from Clock 100 kHz mode — 3500 ns
400 kHz mode — 1000 ns
1 MHz mode(1) ——ns
110 TBUF Bus Free Time 100 kHz mode 4.7 — ms Time the bus must be
free before a new
transmission can start
400 kHz mode 1.3 — ms
D102 CBBus Capacitive Loading — 400 pF
Note 1: Maximum pin capacitance = 10 pF for all I2C pins.
2: A fast mode I2C bus device can be used in a standard mode I2C bus system, but parameter 107 250 ns
must then be met. This will automatically be the case if the device does not stretch the LOW period of the
SCL si gnal. If suc h a d evic e does s tret ch the L OW pe riod o f th e SCL s ignal, it mu st ou tput the n ext da ta bit
to the SDA line, parameter 102 + parameter 107 = 1000 + 250 = 1250 ns (for 100 kHz mode), befo re the
SCL line is released.
PIC18F2XK20/4XK20
DS40001303H-page 384 2010-2015 Microchip Technology Inc.
FIGURE 26-20: EUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
FIGURE 26-21: EUSART SYNCHRO NOUS RECEIVE (MASTER/SLAVE) TIMING
121 121
120 122
RC6/TX/CK
RC7/RX/DT
pin
pin
Note: Refer to Figure 26-4 for load conditions.
TABLE 26-33: EUSART SYNCHRONOUS TRANSMISSION REQUIREM ENTS
Param.
No. Symbol Characteristic Min. Max. Units Conditions
120 TckH2dtV SYNC XMIT (MASTER & SLAVE)
Clock High to Data Out Valid — 40 ns
121 Tckrf Clock Out Rise Time and Fall Time
(Master mode) —20ns
122 Tdtrf Data Out Rise Time and Fall Time — 20 ns
125
126
RC6/TX/CK
RC7/RX/DT
pin
pin
Note: Refer to Figure 26-4 for load conditions.
TABLE 26-34: EUSART SYNCHRONOUS RECEIVE REQUIRE MENTS
Param.
No. Symbol Characteristic Min. Max. Units Conditions
125 TdtV2ckl SYNC RCV (MASTER & SLAVE)
Data Setup before CK (DT setup time) 10 — ns
126 TckL2dtl Data Hold after CK (DT hold time) 15 — ns
2010-2015 Microchip Technology Inc. DS40001303H-page 385
PIC18F2XK20/4XK20
TABLE 26-35: A/D CONVERTER CHARACTERISTICS:PIC18F2XK20/4XK20
Param.
No. Symbol Characteristic Min. Typ. Max. Units Conditions
A01 NRResolut ion — — 10 bits -40°C to +85°C ,
VREF 2.0 V
A03 EIL Integral Linear ity Error — ±0.5 ±1 LSb -40°C to +85°C,
VREF 2.0 V
A04 EDL Differential Linearity Error — ±0.4 ±1 LSb -40°C to +85°C,
VREF 2.0 V
A06 EOFF Offset Error — 0.4 ±2 LSb -40°C to +85°C,
VREF 2.0 V
A07 EGN Gain Error — 0.3 ±2 LSb -40°C to +85°C,
VREF 2.0 V
A08 ETOTL Total Error — 1 ±3 LSb -40°C to +85°C,
VREF 2.0 V
A20 VREF Reference Volt age Ran ge
(VREFH – V REFL)1.8
2.0 —
——
—V
VABsolute Minimum
Minimum for 1LSb
Accuracy
A21 VREFH Reference Volt age High VDD/2 — VDD + 0.3 V
A22 VREFL Reference Volt age Low VSS – 0.3V — VDD/2 V
A25 VAIN Analog Input Voltage VREFL —VREFH V
A30 ZAIN Recom me nde d I mpe da nce of
Analog Voltage Source —— 3k-40°C to +85°C
Note 1: The A/D conversion result never decreases with an increase in the input voltage and has no missing
codes.
2: VREFH current is from RA3/AN3/VREF+ pin or VDD, whichever is selected as the VREFH source.
VREFL current is from RA2/AN2/VREF-/CVREF pin or VSS, whichever is se lec ted as the VREFL source.
PIC18F2XK20/4XK20
DS40001303H-page 386 2010-2015 Microchip Technology Inc.
FIGURE 26-22: A/D CONVERSION TIMING
TABLE 26-36: A/D CONVERSION REQUIREMENTS
Param.
No. Symbol Characteristic Min. Max. Units Conditions
130 TAD A/D Clock Period 0.7 25.0(1) sTOSC based,
-40C to +85C
0.7 4.0(1) sTOSC based,
+85C to +125C
1.0 4.0 s FRC mode, VDD2.0V
131 TCNV Conversion Time
(not including acquisition time) (Note 2) 12 12 TAD
132 TACQ Acquisition Time (Note 3) 1.4 — sVDD = 3V, Rs = 50
135 TSWC Switching Time from Convert Sample — (Note 4)
136 TDIS Di scharge Time 2 2 TAD
Legend: TBD = To Be Determined
Note 1: The time of the A/D clock period is dependent on the device frequency and the TAD clock divider.
2: ADRES register may be read on the following TCY cycle.
3: The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale
after the co nve rsi on ( VDD to VSS or VSS to VDD).
The source impedan ce (Rs) on the input channels is 50
4: On the following cycle of the device clock.
131
130
132
BSF ADCON0, GO
Q4
A/D CLK
A/D DATA
ADRES
ADIF
GO
SAMPLE
OLD_DATA
SAMPLING STOPPED
DONE
NEW_DATA
(Note 2)
987 21 0
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts.
This allows the SLEEP instruction to be executed.
2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
.. . . . .
TCY
2010-2015 Microchip Technology Inc. DS40001303H-page 387
PIC18F2XK20/4XK20
27.0 DC AND AC CHARACTERIS TICS GRAPHS AND TABLES
FIGURE 27-1: PIC18F4XK20/PIC18F2XK20 TYPICAL BASE IPD
FIGURE 27-2: PIC184XK20/PIC18F2XK20 MAXIMUM BASE IPD
Limited Accuracy
-40°C
25°C
40°C
85°C
125°C
0.01
0.1
1
10
1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
VDD (V)
IPD (uA)
25°C
40°C
85°C
125°C
1
10
100
1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
VDD (V)
IPD (uA)
PIC18F2XK20/4XK20
DS40001303H-page 388 2010-2015 Microchip Technology Inc.
FIGURE 27-3: PIC18F4X K20 /PI C18F 2XK20 TYPICAL RC_RUN 31 kHz IDD
FIGURE 27-4: PIC18F4X K20/PIC18F2XK20 MAXIMUM RC_RUN 31 kHz IDD
-40°C
25°C
85°C
125°C
4
6
8
10
12
14
16
1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
VDD (V)
IDD (uA)
-40°C
25°C
85°C
125°C
5
10
15
20
25
30
35
40
45
1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
VDD (V)
IDD (uA)
2010-2015 Microchip Technology Inc. DS40001303H-page 389
PIC18F2XK20/4XK20
FIGURE 27-5: PIC18F4X K20 /PI C 18F2XK20 TYPICAL RC_RUN IDD
FIGURE 27-6: PIC18F4X K20 /PI C 18F2XK20 MAXIMUM RC_RUN IDD
1 MHz
4 M Hz
8 MHz
16 MHz
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
VDD (V)
IDD (mA)
1 MHz
4 MHz
8 MHz
16 MHz
0
1
2
3
4
5
6
1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
VDD (V)
IDD (mA)
PIC18F2XK20/4XK20
DS40001303H-page 390 2010-2015 Microchip Technology Inc.
FIGURE 27-7: PIC18F4XK20/PIC18F2XK20 TYPICAL RC_IDLE 31 kHz IDD
FIGURE 27-8: PIC18F4XK20/PIC18F2XK20 MAXIMUM RC_IDLE 31 kHz IDD
-40°C
25°C
85°C
125°C
1
2
3
4
5
6
7
1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
VDD (V)
IDD (uA)
-40°C
25°C
85°C
125
°
C
0
5
10
15
20
25
30
35
1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
VDD (V)
IDD (uA)
2010-2015 Microchip Technology Inc. DS40001303H-page 391
PIC18F2XK20/4XK20
FIGURE 27-9: PIC18F4XK20/PIC18F2XK20 TYPICAL RC_IDLE IDD
FIGURE 27-10: PIC18F4XK20/PIC18F2XK20 MAXIMUM RC_IDLE IDD
1 MHz
4 MHz
8 MHz
16 MHz
0.0
0.5
1.0
1.5
2.0
2.5
1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
VDD (V)
IDD (mA)
1 MHz
4 MHz
8 MHz
16 MHz
0.0
0.5
1.0
1.5
2.0
2.5
3.0
1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
VDD (V)
IDD (mA)
PIC18F2XK20/4XK20
DS40001303H-page 392 2010-2015 Microchip Technology Inc.
FIGURE 27-11: PI C18F4X K20/PIC18F2XK20 TYPICAL PRI_RUN IDD (EC)
FIGURE 27-12: PIC18F4XK20/PIC18F2XK20 MAXIMUM PRI_RUN IDD (EC)
4 MHz
10 MHz
16 MHz
20 MHz
40 MHz
64 MHz
0
2
4
6
8
10
12
14
16
1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
VDD (V)
IDD (mA)
4 MHz
10 MHz
16 MHz
20 MHz
40 MHz
64 MHz
0
2
4
6
8
10
12
14
16
18
1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
VDD (V)
IDD (mA)
2010-2015 Microchip Technology Inc. DS40001303H-page 393
PIC18F2XK20/4XK20
FIGURE 27-13: PIC18F4X K20 /PI C18F2 XK20 TYPICAL PRI_RUN IDD (HS + PLL)
FIGURE 27-14: PIC18F4XK20/PIC18F2XK20 MAXIMUM PRI_RUN IDD (HS + PLL)
16 MHz
(4 MHz Input)
40 MHz
(10 MHz Input)
64 MHz
(16 MHz Input)
0
2
4
6
8
10
12
14
16
1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
VDD (V)
IDD (mA)
16 MHz
(4 MHz Input)
40 MHz
(10 MHz Input)
64 MHz
(16 MHz Input)
0
2
4
6
8
10
12
14
16
18
20
1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
VDD (V)
IDD (mA)
PIC18F2XK20/4XK20
DS40001303H-page 394 2010-2015 Microchip Technology Inc.
FIGURE 27-15 : PI C18F 4X K20 /PI C18F 2 XK20 TYPICAL PRI_IDLE IDD (EC)
FIGURE 27-16: PIC18F4XK20/PIC18F2XK20 MAXIMUM PRI_IDLE IDD (EC)
4 MHz
10 MHz
16 MHz
20 MHz
40 MHz
64 MHz
0
1
2
3
4
5
6
7
1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
VDD (V)
IDD (mA)
4 MHz
10 MHz
16 MHz
20 MHz
40 MHz
64 MHz
0
1
2
3
4
5
6
7
8
9
1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
VDD (V)
IDD (mA)
2010-2015 Microchip Technology Inc. DS40001303H-page 395
PIC18F2XK20/4XK20
FIGURE 27-17 : PI C18F 4X K20 /PI C18F2 XK2 0 IWDT – Delta IPD for Watchdog Timer, -40°C to
+125°C
FIGURE 27-18 : PI C18F 4X K20 /PI C18F2 XK2 0 IBOR and IHLVD – Delt a IPD for Brown-out Reset
and High/Low Voltage Detect, -40°C to +125°C
Typ.
Max.
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
VDD (V)
IPD (uA )
Typ. BOR
Max. BOR
Typ. HLVD
Max. HLVD
0
10
20
30
40
50
60
70
1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
VDD (V)
IPD (uA)
PIC18F2XK20/4XK20
DS40001303H-page 396 2010-2015 Microchip Technology Inc.
FIGURE 27-19 : PI C18F 4X K20 /PI C18F2 XK2 0 IOCSB – Delta IPD for Low-Power Timer1 Oscillator
FIGURE 27-20 : PI C18F 4X K20 /PI C18F2 XK2 0 IOCSB – Typical Delta IPD for High-Power Timer1
Oscillator
Typ. 25°C
Typ. 85°C
Max.
-40°C to +85°C
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
VDD (V)
IPD (uA )
-40°C
25°C
85°C
10
12
14
16
18
20
1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
VDD (V)
IPD (uA)
2010-2015 Microchip Technology Inc. DS40001303H-page 397
PIC18F2XK20/4XK20
FIGURE 27-21 : PI C18F 4X K20 /PI C18F2 XK2 0 IOCSB – Maximum Delta IPD for High-Power Timer1
Oscillator
FIGURE 27-22 : PI C18F 4X K20 /PI C18F2 XK2 0 ICVREF – Delta IPD for Comparator Voltage
Reference, -40°C to +125°C
-40°C
25°C
85°C
28
30
32
34
36
38
40
42
1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
VDD (V)
IPD (uA)
Typ.
Max.
0
10
20
30
40
50
60
70
80
1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
VDD (V)
IPD (uA)
PIC18F2XK20/4XK20
DS40001303H-page 398 2010-2015 Microchip Technology Inc.
FIGURE 27-23 : PI C18F 4X K20 /PI C18F2 XK2 0 IAD – Typical Delta IDD for ADC, 25°C to +125°C
(Run Mode, ADC on, but not converting)
FIGURE 27-24 : PI C18F 4X K20 /PI C18F2 XK2 0 IAD – Maximum Delta IDD for ADC, 25°C to +125°C
(Run Mode, ADC on, but not converting)
25°C
85°C
125°C
180
200
220
240
260
280
300
320
340
1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
VDD (V)
IDD (uA)
25°C
85°C
125°C
220
240
260
280
300
320
340
360
380
400
420
440
1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
VDD (V)
IDD (uA)
2010-2015 Microchip Technology Inc. DS40001303H-page 399
PIC18F2XK20/4XK20
FIGURE 27-25 : P I C18F 4X K20 /PI C18F2XK20 ICOMP – Typical Delta IPD for Comparator in Low-
Power Mode, -40°C to +125°C
FIGURE 27-26 : PI C18F 4X K20 /PI C18F2 XK2 0 ICOMP – Maximum Delta IPD for Comparator in
Low-Power Mode, -40°C to +125°C
-40°C
25°C
85°C
125°C
3.5
4.0
4.5
5.0
5.5
6.0
6.5
7.0
1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
VDD (V)
IPD (uA)
-40°C
25°C
85°C
125°C
10
11
12
13
14
15
16
1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
VDD (V)
IPD (uA)
PIC18F2XK20/4XK20
DS40001303H-page 400 2010-2015 Microchip Technology Inc.
FIGURE 27-27 : PI C18F 4X K20 /PI C18F2 XK2 0 ICOMP – Typical Delta IPD for Comparator in High-
Power Mode, -40°C to +125°C
FIGURE 27-28 : PI C18F 4X K20 /PI C18F2 XK2 0 ICOMP – Maximum Delta IPD for Comparator in
High-Power Mode, -40° C to +125°C
-40°C
25°C
85°C
125°C
30
35
40
45
50
55
1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
VDD (V)
IPD (uA)
-40°C
25°C
85°C
125°C
60
65
70
75
80
85
90
95
1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
VDD (V)
IPD (uA)
2010-2015 Microchip Technology Inc. DS40001303H-page 401
PIC18F2XK20/4XK20
FIGURE 27-29: PIC18F4X K20 /PI C18F2 XK20 COMPARATOR OFFSET (LOW POWER, VDD = 1.8V)
FIGURE 27-30: PIC18F4X K20 /PI C18F2 XK20 COMPARATOR OFFSET (LOW POWER, VDD = 3.6V)
0
10
20
30
40
50
60
70
0.00.20.40.60.81.01.21.41.61.8
VREF (V)
Abs. Offset (mV)
Typical
125°C 3 sigma
85°C 3 sigma
25°C 3 sigma
-40°C 3 sigma
0
10
20
30
40
50
60
70
0.00.40.81.21.62.02.42.83.23.6
VREF (V)
Abs. Offset (mV)
Typical
125°C 3 sigma
85°C 3 sigma
25°C 3 sigma
-40°C 3 sigma
PIC18F2XK20/4XK20
DS40001303H-page 402 2010-2015 Microchip Technology Inc.
FIGURE 27-31 : PI C18F 4X K20 /PI C18F2 XK2 0 COMP ARATOR OFFSET (HIGH POWER, VDD = 1.8V)
FIGURE 27-32 : PI C18F 4X K20 /PI C18F2 XK2 0 COMP ARATOR OFFSET (HIGH POWER, VDD = 3.6V)
0
5
10
15
20
25
30
35
40
45
0.00.20.40.60.81.01.21.41.61.8
VREF (V)
Abs. Offset (mV)
Typical
125°C 3 sigma
85°C 3 sigma
25°C 3 sigma
-40°C 3 sigma
0
5
10
15
20
25
30
35
40
45
0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6
VREF (V)
Abs. Offset (mV)
Typical
125°C 3 sigma
85°C 3 sigma
-40°C 3 sigma
25°C 3 sigma
2010-2015 Microchip Technology Inc. DS40001303H-page 403
PIC18F2XK20/4XK20
FIGURE 27-33 : PI C18F 4X K20 /PI C18F2 XK2 0 TYPICAL FIXED VOLTAGE REFERENCE
FIGURE 27-34 : PI C18F 4X K20 /PI C18F2 XK2 0 TYPICAL FIXED V OLT AGE REFERENCE (MAX./MIN.
= 1.2V +/- 50MV FROM -40°C TO +85°C)
-40°C
25°C
85°C
125°C
1.175
1.180
1.185
1.190
1.195
1.200
1.205
1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
VDD (V)
FVR (V)
1.8V
2.0V
3.6V
1.175
1.180
1.185
1.190
1.195
1.200
1.205
-40 -20 0 20 40 60 80 100 120
Temp. (°C)
FVR (V)
PIC18F2XK20/4XK20
DS40001303H-page 404 2010-2015 Microchip Technology Inc.
FIGURE 27-35: PIC18F4XK20/PIC18F2XK20 TTL BUFFER VIH
FIGURE 27-36: PIC18F4XK20/PIC18F2XK20 SCHMITT TRIGGER BUFFER VIH
-40°C
25°C
85°C
125°C
Min.
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
VDD (V)
VIH (V)
-40°C
25°C
85°C125°C
Min.
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
VDD (V)
VIH (V)
2010-2015 Microchip Technology Inc. DS40001303H-page 405
PIC18F2XK20/4XK20
FIGURE 27-37: PIC18F4XK20/PIC18F2XK20 TTL BUFFER VIL
FIGURE 27-38: PIC18F4XK20/PIC18F2XK20 SCHMITT TRIGGER BUFFER VIL
-40°C
25°C
85°C
125°C
Max.
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
VDD (V)
VIL (V)
-40°C25°C
85°C125°C
Max.
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
VDD (V)
VIL (V)
PIC18F2XK20/4XK20
DS40001303H-page 406 2010-2015 Microchip Technology Inc.
FIGURE 27-39 : PI C18F 4X K20 /PI C18F2 XK2 0 VOH VS. IOH (-40°C TO +125°C)
FIGURE 27-40 : PI C18F 4X K20 /PI C18F2 XK2 0 VOL VS. IOL (-40°C TO +125°C)
Min. 1.8V
Typ. 1.8V
Typ. 3.0V
Min. 3.0V
Typ. 3.6V
Min. 3.6V
0
0.6
1.2
1.8
2.4
3
3.6
0 5 10 15 20 25
IOH (mA)
VOH (V)
1.8V
Max. 1.8V
3.0V
Max. 3.0V
3.6V
Max. 3.6V
0
0.3
0.6
0.9
1.2
1.5
1.8
0 5 10 15 20 25
IOL (mA )
VOL (V)
2010-2015 Microchip Technology Inc. DS40001303H-page 407
PIC18F2XK20/4XK20
FIGURE 27-41: PIC18F4X K20 /PIC18F2XK20 PIN INPUT LEAKAGE
I/O Ports Typ.
I/O Ports Max.
RA2 Typ.
RA2 Max.
RA3 Typ.
RA3 Max.
1
10
100
1000
25 30 35 40 45 50 55 60 65 70 75 80 85
Temp. (°C)
Input Leakage (nA)
PIC18F2XK20/4XK20
DS40001303H-page 408 2010-2015 Microchip Technology Inc.
FIGURE 27-42 : PI C18F 4X K20 /PI C18F 2 XK20 TYPICAL HF-INTOSC FREQUENCY
FIGURE 27-43 : PI C18F 4X K20 /PI C18F 2 XK20 TYPICAL HF-INTOSC FREQUENCY
-40°C
25°C
85°C
125°C
15.68
15.76
15.84
15.92
16.00
16.08
1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
VDD (V)
Frequency (MHz)
3.0V
Min
Max
15.20
15.36
15.52
15.68
15.84
16.00
16.16
16.32
16.48
16.64
16.80
-40 -20 0 20 40 60 80 100 120
Temp. (°C)
Frequency (MHz)
2010-2015 Microchip Technology Inc. DS40001303H-page 409
PIC18F2XK20/4XK20
FIGURE 27-44 : PI C 18F4X K20 /PI C18F 2 XK2 0 TYPICAL LF-INTOSC FREQUENCY (MAX./MIN. =
31.25 kHz +/- 15 %)
FIGURE 27-45 : PI C 18F4X K20 /PI C18F 2 XK20 TY PICAL LF-INTOSC FREQUENCY (MAX./MIN. =
31.25 kHz +/- 15 %)
-40°C
25°C
85°C
125°C
28.25
29.25
30.25
31.25
32.25
33.25
1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
VDD (V)
Frequency (kHz)
1.8V
2.5V
3.0V
3.6V
28.25
29.25
30.25
31.25
32.25
33.25
-40 -20 0 20 40 60 80 100 120
Temp. (°C)
Frequency (kH z)
PIC18F2XK20/4XK20
DS40001303H-page 410 2010-2015 Microchip Technology Inc.
28.0 PACKAGING INFORMATION
28.1 Package Marking Information
28-Lead SPDIP (.300”) Example
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC® designator ( )
can be found on the outer packaging for this package.
Note: In the event the full Micr ochip p art number cann ot be mark ed on on e line, it will
be carried over to the next line, thus limiting the number of available
characte rs for customer-specific informati on.
3
e
3
e
PIC18F25K20
-E/SP
1519017
28-Lead SOIC (7.50 mm) Example
YYWWNNN
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
PIC18F25K20
-E/SO
1519017
28-Lead SSOP (5.30 mm) Example
PIC18F25K20
-E/SS
1519017
3
e
3
e
3
e
2010-2015 Microchip Technology Inc. DS40001303H-page 411
PIC18F2XK20/4XK20
Package Marking Information (Continued)
28-Lead QFN (6x6 mm) Example
XXXXXXXX
XXXXXXXX
YYWWNNN
PIN 1 PIN 1
18F24K20
-E/ML
1519017
28-Lead UQFN (4x4x0.5 mm) Example
PIN 1 PIN 1
PIC18
F23K20
-E/MV
519017
3
e
3
e
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC® designator ( )
can be found on the outer packaging for this package.
Note: In the event the ful l Micro chip p art nu mber ca nnot be m arked on one line , it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
40-Lead PDIP (600 mil) Example
XXXXXXXXXXXXXXXXXX
YYWWNNN
XXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXX
PIC18F45K20
-E/P
1519017
3
e
PIC18F2XK20/4XK20
DS40001303H-page 412 2010-2015 Microchip Technology Inc.
Package Marking Information (Continued)
40-Lead UQFN (5x5x0.5 mm) Example
PIN 1 PIN 1
PIC18F
45K20
-I/MV
3
e
1519017
44-Lead QFN (8x8x0.9 mm) Example
XXXXXXXXXXX
XXXXXXXXXXX
YYWWNNN
XXXXXXXXXXX
PIN 1 PIN 1
44-Lead TQFP (10x10x1 mm) Example
XXXXXXXXXX
YYWWNNN
XXXXXXXXXX
XXXXXXXXXX
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
*This package is P b-f ree. The Pb-free JEDEC® designator ( )
can be found on the outer packaging for this package.
Note: In the event th e full Mi crochi p pa rt numbe r cannot be marke d on o ne line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
PIC18F45K20
-E/ML
1519017
PIC18F44K20
-E/PT
1519017
2010-2015 Microchip Technology Inc. DS40001303H-page 413
PIC18F2XK20/4XK20
28.2 Package Details
The foll owing sections give the technical details of the packages.
!"
!"
NOTE 1
N
12
D
E1
eB
c
E
L
A2
eb
b1
A1
A
3
PIC18F2XK20/4XK20
DS40001303H-page 414 2010-2015 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2010-2015 Microchip Technology Inc. DS40001303H-page 415
PIC18F2XK20/4XK20
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
PIC18F2XK20/4XK20
DS40001303H-page 416 2010-2015 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2010-2015 Microchip Technology Inc. DS40001303H-page 417
PIC18F2XK20/4XK20
#$%&'%
!"
!"
L
L1
c
A2
A1
A
E
E1
D
N
12
NOTE 1 b
e
φ
PIC18F2XK20/4XK20
DS40001303H-page 418 2010-2015 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2010-2015 Microchip Technology Inc. DS40001303H-page 419
PIC18F2XK20/4XK20
PIC18F2XK20/4XK20
DS40001303H-page 420 2010-2015 Microchip Technology Inc.
2010-2015 Microchip Technology Inc. DS40001303H-page 421
PIC18F2XK20/4XK20
()*!+,-.-()!
/#'&&0+#
!"
PIC18F2XK20/4XK20
DS40001303H-page 422 2010-2015 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2010-2015 Microchip Technology Inc. DS40001303H-page 423
PIC18F2XK20/4XK20
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
PIC18F2XK20/4XK20
DS40001303H-page 424 2010-2015 Microchip Technology Inc.
2010-2015 Microchip Technology Inc. DS40001303H-page 425
PIC18F2XK20/4XK20
1-
!"
!"
N
NOTE 1
E1
D
123
A
A1 b1
be
c
eB
E
L
A2
PIC18F2XK20/4XK20
DS40001303H-page 426 2010-2015 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2010-2015 Microchip Technology Inc. DS40001303H-page 427
PIC18F2XK20/4XK20
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
PIC18F2XK20/4XK20
DS40001303H-page 428 2010-2015 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2010-2015 Microchip Technology Inc. DS40001303H-page 429
PIC18F2XK20/4XK20
PIC18F2XK20/4XK20
DS40001303H-page 430 2010-2015 Microchip Technology Inc.
2010-2015 Microchip Technology Inc. DS40001303H-page 431
PIC18F2XK20/4XK20
PIC18F2XK20/4XK20
DS40001303H-page 432 2010-2015 Microchip Technology Inc.
B
A
0.20 H A B
0.20 H A B
44 X b
0.20 C A B
(DATUM B)
(DATUM A)
C
SEATING PLANE
2X
TOP VIEW
SIDE VIEW
BOTTOM VIEW
Microchip Technology Drawing C04-076C Sheet 1 of 2
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
e
NOTE 1
12
N
D
D1
EE1
2X
A2
A1
A
0.10 C
3
N
AA
0.20 C A B
4X 11 TIPS
123
44-Lead Plastic Thin Quad Flatpack (PT) - 10x10x1.0 mm Body [TQFP]
NOTE 1
NOTE 2
2010-2015 Microchip Technology Inc. DS40001303H-page 433
PIC18F2XK20/4XK20
Microchip Technology Drawing C04-076C Sheet 2 of 2
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
L
(L1)
c
θ
SECTION A-A
H
Number of Leads
Overall Height
Lead Width
Overall Width
Overall Length
Lead Length
Molded Package Width
Molded Package Length
Molded Package Thickness
Lead Pitch
Standoff
Units
Dimension Limits
A1
A
b
D
E1
D1
A2
e
L
E
N
0.80 BSC
0.45
0.30
-
0.05
0.37
12.00 BSC
0.60
10.00 BSC
10.00 BSC
-
-
12.00 BSC
MILLIMETERS
MIN NOM
44
0.75
0.45
1.20
0.15
MAX
0.95 1.00 1.05
REF: Reference Dimension, usually without tolerance, for information purposes only.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
1.
2.
3.
Notes:
Pin 1 visual index feature may vary, but must be located within the hatched area.
Exact shape of each corner is optional.
Dimensioning and tolerancing per ASME Y14.5M
Footprint L1 1.00 REF
θ3.5°0° 7°Foot Angle
Lead Thickness c0.09 - 0.20
44-Lead Plastic Thin Quad Flatpack (PT) - 10x10x1.0 mm Body [TQFP]
PIC18F2XK20/4XK20
DS40001303H-page 434 2010-2015 Microchip Technology Inc.
RECOMMENDED LAND PATTERN
44-Lead Plastic Thin Quad Flatpack (PT) - 10X10X1 mm Body, 2.00 mm Footprint [TQFP]
SILK SCREEN
1
2
44
C1
E
G
Y1
X1
C2
Contact Pad Width (X44)
0.25
Contact Pad Length (X44)
Distance Between Pads
X1
Y1
G
1.50
Contact Pad Spacing
Contact Pitch
C1
E
Units
Dimension Limits
11.40
0.55
0.80 BSC
MILLIMETERS
MAXMIN NOM
11.40C2Contact Pad Spacing
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
1. Dimensioning and tolerancing per ASME Y14.5M
Notes:
Microchip Technology Drawing No. C04-2076B
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
2010-2015 Microchip Technology Inc. DS40001303H-page 435
PIC18F2XK20/4XK20
APPENDIX A: REVISION HISTORY
Revision A (07/2006)
Original data sheet for PIC18F2XK20/4XK20 de vices.
Revision B (03/2007)
Added part numbers PIC18F26K20 and
PIC18F46K20; Replaced Development Support
Section; Replaced Package Drawings .
Revision C (10/2007)
Revised Table 1, DIL Pins 34 and 35; Table 2, Pins 22
and 24; Table 1-2, Pins RB1 and RB3; Table 1-3, Pins
RB1 and RB3; Revised Sections 4.3, 4.4, 4.4.1, 4.4.2,
4.4.4; Revised Table 4-3, Note 2; Revised Table 6-1;
Revise Section 7.8: Revised Section 9.2; Revised
Examples 10-1 and 10-2; Revised Table 10-3, Pins
RB1 and RB3; Revised Sections 12.2 through 12.5;
Revised Register 16-1, bit 3-0; Revised Sections 16.1,
16.2, 16.4.4; Revised Register 16-2, bit 6-4; Revised
Table 16-2, Note 2; Revised Register 17-1, bit 6;
Revised Register 17-3; Revised Table 17-4; Revised
Register 19-1, added Note 2; Revised Register 20-3,
bits 5 and 4; Revised Register 23-4, bit 1; Revised
Regis ter 23 -12, bit 7-5; R evis ed Sec tio n 23.3; Revised
Section 24.1.1, instruction set descriptions; Revised
Section 26.0, voltage on MCLR; Revised DC
Characteristics 26.2, 26.3, 26.4 26.5, 26.6, 26.7, 26.8
and 26.10; Revised Tables 26-1, 26-6, 26-7, 26-9, 26-
23.
Revision D (08/2008)
Update to Peripheral Highlights (EUSART module);
Deleted Section 2.2.6 (Oscillator Transitions); Revised
Sections 2.5.3, 2.9; Added Section 2.9.3 (Clock Switch
Timing); Deleted Section 2.10.4 (Clock Switching
Timing); Replaced BAUDCTL with BAUDCON
throughout; Revised Table 5-2 (PLUSW0, PLUSW1,
PLUSW2); Add Note 1 to Table 7-1 (EEADRH);
Revised Section 6.4.4 and Register 16-2 (FLT0 pin);
Revised Registers 17-2 and 17-5 (SSPEN); Revised
Register 17-6 (SEN); Added new paragraph after
Figure 18-2; Revised Note, Section 18.1.1; Deleted
Note, Section 18.1.2; Added new Note 2, Sections
18.1.2.9 and 18.1.2.10; Revised Note 1, Section
18.3.1; Added Section 18.3.2; Revised Section 18.3.5;
Added new Note 2, Sections 18.4.1.5, 18.4.1.10,
18.4.2.2, 18.4.2.4; Revised Register 21-1 (CVR);
Revised Note 1, Registers 23-6, 23.8, 23-10, Table 23-
3; Added new Figure 26-1; Revised 26.2, 26.6, 26.7
(Note 3), 26.8, 26.9, 26.10; Revised Tables 26-1, 26-2,
26-3, 26-6, 26-7, 26-8, 26-25; Updated Package
Drawings.
Revision E (04/2009)
Revised data sheet title; Revised Power-Managed
Modes, Peripheral Highlights, and Analog Features;
Revised 26.2, DC Char. table.
Revision F (09/2009)
Changed the values in the “Extreme Low-Power
Management with XLP” section; Added new Note 2 to
Pin Diagrams; Updated Electrical Characteristics
section; Added charts to the DS Characteristics
section; Removed Preliminary label; Added UQFN to
Pin Diagrams; Added the 28-pin UQFN to Table 3-1;
Updated MSSP section (Register 17-3; changing
SSPADD<6:0> to SSPADD<7:0>); Updated the
Development Support section deleting section 25.7;
Added the 28-Lead UQFN package marking diagrams
and the 28 -Lead Plastic Ultra Th in Quad Flat, No Lead
Package (MV) - 4X4X0.5 mm Body (UQFN) p ackage to
Packaging Information section; Other minor
corrections.
Revision G (01/2010)
Updated Figure 9-1; Reviewed Section 26 (Electrical
Characteristics); Added Figures 27-29, 27-30, 27-31
and 27-32 to Section 27 (DC and AC Characteristics
Graphs and Tables); Reviewed Product Identification
Syste m se cti on.
Revision H (06/2015)
Updated Figures 1 to 6 to new pin diagrams format;
Added pin diagram for 40-Pin UQFN; Updated pin
allocation Table 2 for 40-Pin UQFN; Revised pin
allocation tables; Updated Table 1-1 for 40-Pin UQFN;
Updated Table 1-3 for 40-Pin UQFN; Updated chapter
26.0 Electrical Specifications to new format; Updated
Table 26-18 in Electrical Specifications; Updated
Section 21.2, FVR Reference Module; Updated Figure
21-1; Updated Table B-1 in Appendix B for 40-Pin
UQFN; Updated Packaging Information chapter;
Revised Product Identification System section.
PIC18F2XK20/4XK20
DS40001303H-page 436 2010-2015 Microchip Technology Inc.
APPENDIX B: DEVICE
DIFFERENCES
The differences between the devices listed in this data
sheet are shown in Table B-1.
TABLE B-1: DEVICE DIFFERENCES
Features PIC18F23K20 PIC18F24K20 PIC18F25K20 PIC18F26K20 PIC18F43K20 PIC18F44K20 PIC18F45K20 PIC18F46K20
Pro gr am Me mo ry
(Bytes) 8192 16384 32768 65536 8192 16384 32768 65536
Pro gr am Me mo ry
(Instructions) 4096 8192 16384 32768 4096 8192 16384 32768
Interrupt Sources 19 19 19 19 20 20 20 20
I/O Ports Ports A, B, C,
(E) Ports A, B, C,
(E) Por ts A, B, C,
(E) Ports A, B, C,
(E) Ports A, B , C,
D, E Ports A, B, C,
D, E Ports A, B, C,
D, E Ports A, B, C,
D, E
Capture/
Compare/PWM
Modules
11111111
Enhanced
Capture/
Compare/PWM
Modules
11111111
Parallel
Communications
(PSP)
No No No No Yes Yes Yes Yes
10-bit An alo g-t o-
Digital Module 11 input
channels 11 input
channels 11 input
channels 11 input
channels 14 input
channels 14 input
channels 14 input
channels 14 input
channels
Packages 28-pin PDIP
28-pin SOIC
28-pin SSOP
28-pin QFN
28-pin UQFN
28-pin PDIP
28-pin SOIC
28-pin SSOP
28-pin QFN
28-pin PDIP
28-pin SOIC
28-pin SSOP
28-pin QFN
28-pin PDIP
28-pin SOIC
28-pin SSO P
28-pin QFN
40-pin PDIP
44-pin TQFP
44-pin QFN
40-pin UQF N
40-pin PDIP
44-pin TQFP
44-pin QFN
40-pin UQFN
40-pin PDIP
44-pin TQF P
44-pin QFN
40-pin UQFN
40-pin PDIP
44-pin TQFP
44-pin QFN
40-pin UQFN
2010-2015 Microchip Technology Inc. DS40001303H-page 437
PIC18F2XK20/4XK20
THE MICROCHIP WEB SITE
Microchip provides online support via our web site at
www.microchip.com. This web si te i s us ed as a m ean s
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:
•Product Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
•General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online dis cu ss io n gr oups, Microchip con sultant
program member listing
•Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of sem inars and events, lis tings of
Microchip sales offices, distributors and factory
representatives
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specif ied produ ct family or develo pment tool of interes t.
To register, access the Microchip web site at
www.microchip.com. Under “Support”, click on
“Customer Change Notification” and follow the
registration instructions.
CUSTOMER SUPP ORT
Users of Microchip products can receive assistance
through several channels:
• Distributor or Representative
• Local Sales Office
• Field Application Engi neer (FAE)
• Technical Support
Customers should contact their distributor,
representative or Field Application Engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
Technic al suppo rt is a vailable throug h the web site
at: http://www.microchip.com/support
PIC18F2XK20/4XK20
DS40001303H-page 438 2010-2015 Microchip Technology Inc.
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. X/XX XXX
PatternPackageTemperature
Range
Device
Device: PIC18F23K20; PIC18F24K20; PIC18F25K20; PIC18F26K20;
PIC18F43K20; PIC18F44K20; PIC18F45K20; PIC18F46K20.
Tape and Reel
Option: Blank = Standard packaging (tube or tray)
T = Tape and Reel(1)
Temperature
Range: I= -40C to +125C (Industrial)
E= -65C to +150C (Extended)
Package: PT = TQFP (Thin Quad Flatpack)
SS = SSOP
SO = SOIC
SP = SPDIP (Skinny Plastic DIP)
P=PDIP
ML = QFN
MV = UQFN
Pattern: QTP, SQTP, Code or Special Requirements
(blank otherwise)
Examples:
a) PIC18F45K20 - E/P 301 = Industrial temp.,
PDIP package, QTP pattern #301.
b) PIC18F23K20 - I/SO = Industrial temp., SOIC
package.
c) PIC18F44K20 - E/P = Exte nd ed temp., PDIP
package.
d) PIC18F4 6K20 - I/PT = Indu strial temp., TQFP
package, tape and reel.
Note 1: Tape and Reel identifier only appears in the
catalog part number description. This
identifier is used for ordering purposes and
is not printed on the device package. Check
with your Microchip Sales Office for package
availability with the Tape and Reel option.
[X](1)
Tape and Ree l
Option
2010-2015 Microchip Technology Inc. DS40001303H-page 439
Information contained in this publication regarding device
applications a nd the lik e is pro vid ed only for your c on ve nience
and may be supers eded by u pdates. It is y our res po ns i bil it y to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer ,
LANCheck, MediaLB, MOST, MOST logo, MPLAB,
OptoL yzer , PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC,
SST, SST Logo, SuperFlash and UNI/O are registered
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
The Embedded Control Solutions Company and mTouch are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo,
CodeGuard, dsPICDEM, dsP ICDEM. net, ECA N, In-Circuit
Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet,
KleerNet logo, MiWi, MPASM, MPF, MPLAB Certified logo,
MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code
Generation, PICDEM, PICDEM.net, PICkit, PICtail,
RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Tot al
Endurance, TSHARC, USBCheck, VariSense, ViewS pan,
WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip T echnology Incorporated
in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchi p
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2010-2015, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
ISBN: 978-1-63277-505-4
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that i t s family of products is one of the most secure families of it s kind on the market today, when used i n the
intended manner and under normal conditions.
• The re are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is c onstantly evolving. We a t Microc hip are co m mitted to continuously improving the code prot ect ion featur es of our
products. Attempts to break Microchip’ s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperiph erals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
QUALITY MANAGEMENT S
YSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
DS40001303H-page 440 2010-2015 Microchip Technology Inc.
AMERICAS
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Techn ic al Support:
http://www.microchip.com/
support
Web Address:
www.microchip.com
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
Austin, TX
Tel: 512-257-3370
Boston
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Chicago
Itasc a , IL
Tel: 630-285-0071
Fax: 630-285-0075
Cleveland
Independence, OH
Tel: 216-447-0464
Fax: 216-447-0643
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
Detroit
Novi, MI
Tel: 248-848-4000
Houston, TX
Tel: 281-894-5983
Indianapolis
Noblesville, IN
Tel: 317-773-8323
Fax: 317-773-5453
Los A n ge les
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
New York, NY
Tel: 631-435-6000
San Jose, CA
Tel: 408-735-9110
Canada - Toronto
Tel: 905-673-0699
Fax: 905-673-6509
ASIA/PACIFIC
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
Hong Kong
Tel: 852-2943-5100
Fax: 852-2401-3431
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
China - Beijing
Tel: 86-10-8569-7000
Fax: 86-10-8528-2104
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
China - Chongqing
Tel: 86-23-8980-9588
Fax: 86-23-8980-9500
China - Dongguan
Tel: 86-769-8702-9880
China - Hangzhou
Tel: 86-571-8792-8115
Fax: 86-571-8792-8116
China - Hong Kong SAR
Tel: 852-2943-5100
Fax: 852-2401-3431
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
China - Shenzhen
Tel: 86-755-8864-2200
Fax: 86-755-8203-1760
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
ASIA/PACIFIC
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4123
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
India - Pune
Tel: 91-20-3019-1500
Japan - Osaka
Tel: 81-6-6152-7160
Fax: 81-6-6152-9310
Japan - Tokyo
Tel: 81-3-6880- 3770
Fax: 81-3-6880-3771
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
Taiwan - Hsin Chu
Tel: 886-3-5778-366
Fax: 886-3-5770-955
Taiwan - Ka ohs iung
Tel: 886-7-213-7828
Taiwan - Taipei
Tel: 886-2-2508-8600
Fax: 886-2-2508-0102
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
EUROPE
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Cop e nha gen
Tel: 45-4450-2828
Fax: 45-4485-2829
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Germany - Dusseldorf
Tel: 49-2129-3766400
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-14 4-44
Germany - Pforzheim
Tel: 49-7231-424750
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Italy - Venice
Tel: 39-049-7625286
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Poland - Warsaw
Tel: 48-22-3325737
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08 -91
Sweden - Stockholm
Tel: 46-8-5090-4654
UK - Wokingham
Tel: 44-118-921-5800
Fax: 44-118-921-5820
Worldwide Sales and Service
01/27/15
