PIC18F6525/6621/8525/8621
DS39612C-page 392 2003-2013 Microchip Technology Inc.
Timer0...............................................................................131
16-Bit Mode Timer Reads and Writes.......................133
Associ a te d Re g i sters ......................... .......................133
Clock Source Edge Select (T0SE Bit).......................133
Clock Sou rc e Se le ct (T0CS Bit)...... ..........................133
Operation ..................................................................133
Overflow Inte rrupt ................. .......... ........... ...............133
Prescaler. See Prescaler, Time r0.
Timer1...............................................................................135
16-Bit Read/Wr ite Mod e...... ............................. .........137
Associ a te d Re gisters........................................... .....13 9
Operation ..................................................................136
Oscillator...........................................................135, 137
Overflow Interrupt .............................................135, 137
Special Event Trigger (ECCP) ..........................137, 160
TMR1H Register .......................................................135
TMR1L Register........................................................135
Use as a Real-Time Clock........................................138
Timer2...............................................................................141
Associ a te d Re gisters........................................... .....14 2
MSSP Clock Shift..............................................141, 142
Operation ..................................................................141
Postscaler. See Postscaler, Timer2.
PR2 Register.............................................141, 154, 160
Prescaler. See Prescaler, Time r2.
TMR2 Register..........................................................141
TMR2 to PR2 Match Interrupt...........141, 142, 154, 160
Timer3...............................................................................143
Associ a te d Re gisters........................................... .....14 5
Operation ..................................................................144
Oscillator...........................................................143, 145
Overflow Interrupt .............................................143, 145
Special Event Trigger (ECCP)..................................145
TMR3H Register .......................................................143
TMR3L Register........................................................143
Timer4...............................................................................147
Associ a te d Re gisters........................................... .....14 8
MSSP Clock Shift............................ ..........................148
Operation ..................................................................147
Postscaler. See Postscaler, Timer4.
PR4 Register.............................................................147
Prescaler. See Prescaler, Time r4.
TMR4 Register..........................................................147
TMR4 to PR4 Match Interrupt...........................147, 148
Timing Diagrams
A/D Conversion.... ........... .......... ........... .......... ...........355
Acknowledge Sequence ...........................................206
Asynchronous Reception..........................................224
Asynchronous Transmission.....................................222
Asynchronous Transmission
(Back to Back)...................................................222
Automatic Baud Rate Calculation .............................220
Auto-Wake-up Bit (WUE) During
Normal Operatio n ..............................................225
Auto-Wake-up Bit (WUE) During Sleep ....................225
Baud Rate Generator with Clock Arbitration.............200
BRG Reset Due to SDA Arbitration
During Start Condition.......................................209
Brown-out Reset (BOR)............................................341
Bus Collision During a Repeated Start
Condition (Case 1)............................................210
Bus Collision During a Repeated Start
Condition (Case 2)............................................210
Bus Collision During a Start
Condition (SCL = 0)..........................................209
Bus Collision During a Stop
Condition (Case 1)............................................ 211
Bus Collision During a Stop
Condition (Case 2)............................................ 211
Bus Collision During Start
Condition (SDA Only)....................................... 208
Bus Collision for Transmit and
Acknowledge.................................................... 207
Capture/Compare/PWM
(All ECCP/CCP Modules)................................. 343
CLKO and I/O........................................................... 338
Cloc k Synch ro n i zatio n. .. ...... .. ..... .. ...... .. ...... ..... .. ...... . 19 3
Cloc k/In structi o n C ycle.. .. ...... .. ..... ...... .. ...... ..... .. ...... ... 44
EUSART Synchronous
Receive (Master/Slave) .................................... 353
EUSART Synchronous
Transmis sion (Master/Slave)............................ 353
Example SPI Master Mode (CK E = 0)...................... 345
Example SPI Master Mode (CK E = 1)...................... 346
Example SPI Slave Mode (CKE = 0)........................ 347
Example SPI Slave Mode (CKE = 1)........................ 348
External Clock (All Modes Except PLL).................... 337
External Memory Bus Timing for Sleep
(Microprocessor Mode)....................................... 77
External Memory Bus Timing for TBLRD
(Extended Microcontroller Mode) ....................... 76
External Memory Bus Timing for TBLRD
(Microprocessor Mode)....................................... 76
Full-Bridge PWM Output........................................... 165
Half-Bridge Output. ................................................... 163
I2C Bus Data ............................................................. 349
I2C Bus Start/Stop Bits............................................. 349
I2C Master Mode
(7 or 10 -Bit Tr a n smissi o n ) .. .. ...... .. ...... ..... .. ...... . 20 4
I2C Master Mode (7-Bit Reception)........................... 205
I2C Master Mode First Start Bit Timing..................... 201
I2C Slave Mode (10-Bit Reception, SEN = 0)........... 190
I2C Slave Mode (10-Bit Reception, SEN = 1)........... 195
I2C Slave Mode (10-Bit Transmission) ..................... 191
I2C Slave Mode (7-Bit Reception, SEN = 0)............. 188
I2C Slave Mode (7-Bit Reception, SEN = 1)............. 194
I2C Slave Mode (7-Bit Transmission) ....................... 189
Low-Voltage Detect .................................................. 256
Master SSP I 2C Bus Data........ ................................. 351
Master SSP I 2C Bus Start/Stop Bits......................... 351
Parallel Slave Port (PSP).......................................... 344
Para ll e l Sl a ve Po rt (PS P) R e a d.. ...... .. ...... .. ..... .. ...... . 13 0
Parallel Slave Port (PSP) Write................................ 129
Program Memory Read............................................ 339
Program Memory Write............................................. 340
PWM Auto-Shutdown (PRSEN = 0,
Auto-R e start Disabled)............ ......................... 170
PWM Auto-Shutdown (PRSEN = 1,
Auto-Restart Enabled)...................................... 170
PWM Direction Change................... .... .... .... ......... .... 167
PWM Direction Change at Near
100% Duty Cycle.............................................. 167
PWM Output............... .......... ........... ......................... 154
Repeated Start Condition ........................ .. .. ....... .. .. .. 202
Reset, Watchdog Timer (WDT),
Oscillator Start-up Timer (OST)
and Power-up Timer (PWRT)........................... 341
Send Break Character Sequenc e............................. 226
Slave Mode General Call Address Sequence
(7 or 10-Bit Address Mode) .............................. 196