Standard Products UT9Q512K32 16Megabit SRAM MCM Advanced Data Sheet January 15, 2001 FEATURES q 35ns maximum (5 volt supply) address access time q Asynchronous operation for compatible with industry standard 512K x 8 SRAMs q TTL compatible inputs and output levels, three-state bidirectional data bus q Typical radiation performance - Total dose - Solution #1: Up to 30krads - Solution #2: Up to 300krads INTRODUCTION The UT9Q512K32 is a high-performance 2M byte (16Mbit) CMOS static RAM multi-chip module (MCM), organized as four individual 524,288 x 8 bit SRAMs with a common output enable. Memory expansion is provided by an active LOW chip enable (En), an active LOW output enable (G), and three-state drivers. This device has a power-down feature that reduces power consumption by more than 90% when deselected. 2 - SEL Immune >100 MeV-cm /mg - LETTH(0.25) = 40 MeV-cm2/mg - Saturated Cross Section (cm2) per bit, 1.0E-9 - 3.8E-11 errors/bit-day, Adams 90% geosynchronous heavy ion - Inherent Neutron Hardness: 1.0E14n/cm2 - Dose Rate - Upset 1.0E9 rad(Si)/sec - Latchup >1.0E11 rad(Si)/sec q Packaging options: - 68-lead dual cavity ceramic quad flatpack (CQFP) q Standard Microcircuit Drawing pending - QML T and Q compliant part E3 W3 E2 Writing to each memory is accomplished by taking chip enable (En) input LOW and write enable (Wn) inputs LOW. Data on the eight I/O pins (DQ 0 through DQ7) is then written into the location specified on the address pins (A0 through A18). Reading from the device is accomplished by taking chip enable (En) and output enable (G) LOW while forcing write enable (Wn) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins (DQ0 through DQ7) are placed in a high impedance state when the device is deselected ( En HIGH), the outputs are disabled (G HIGH), or during a write operation (En LOW and Wn LOW). Perform 8, 16, 24 or 32 bit accesses by making Wn along with G a common input to any combination of the discrete memory die. W2 E1 W1 W0 E0 A(18:0) G 512K x 8 512K x 8 DQ(31:24) or DQ3(7:0) DQ(23:16) or DQ2(7:0) 512K x 8 DQ(15:8) or DQ1(7:0) Figure 1. UT9Q512K32 SRAM Block Diagram 512K x 8 DQ(7:0) or DQ0(7:0) NC A0 A1 A2 A3 A4 A5 E2 VSS E3 W1 A6 A7 A8 A9 A10 VDD DEVICE OPERATION 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Top View 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 The UT9Q512 has three control inputs called Enable 1 (En), Write Enable (Wn), and Output Enable (G); 19 address inputs, A(18:0); and eight bidirectional data lines, DQ(7:0). En Device Enable controls device selection, active, and standby modes. Asserting En enables the device, causes I DD to rise to its active value, and decodes the 19 address inputs to select one of 524,288 words in the memory. Wn controls read and write operations. During a read cycle, G must be asserted to enable the outputs. DQ0(2) DQ1(2) DQ2(2) DQ3(2) DQ4(2) DQ5(2) DQ6(2) DQ7(2) VSS DQ0(3) DQ1(3) DQ2(3) DQ3(3) DQ4(3) DQ5(3) DQ6(3) DQ7(3) Table 1. Device Operation Truth Table VDD A11 A12 A13 A14 A15 A16 E0 G E1 A17 W2 W3 W4 A18 NC NC DQ0(0) DQ1(0) DQ2(0) DQ3(0) DQ4(0) DQ5(0) DQ6(0) DQ7(0) VSS DQ0(1) DQ1(1) DQ2(1) DQ3(1) DQ4(1) DQ5(1) DQ6(1) DQ7(1) Figure 2. 25ns SRAM Pinout (68) DQn(7:0) En Address Data Input/Output Enable Wn En I/O Mode Mode X1 X 1 3-state Standby X 0 0 Data in Write 1 1 0 3-state Read2 0 1 0 Data out Read Notes: 1. "X" is defined as a "don't care" condition. 2. Device active; outputs disabled. PIN NAMES A(18:0) G Wn Write Enable READ CYCLE G Output Enable A combination of Wn greater than VIH (min) and En less than VIL (max) defines a read cycle. Read access time is measured from the latter of Device Enable, Output Enable, or valid address to valid data output. VDD Power VSS Ground SRAM Read Cycle 1, the Address Access in figure 3a, is initiated by a change in address inputs while the chip is enabled with G asserted and Wn deasserted. Valid data appears on data outputs DQ(7:0) after the specified t AVQV is satisfied. Outputs remain active throughout the entire cycle. As long as Device Enable and Output Enable are active, the address inputs may change at a rate equal to the minimum read cycle time (tAVAV). SRAM read Cycle 2, the Chip Enable - Controlled Access in figure 3b, is initiated by En going active while G remains asserted, Wn remains deasserted, and the addresses remain stable for the entire cycle. After the specified t ETQV is satisfied, the eight-bit word addressed by A(18:0) is accessed and appears at the data outputs DQ(7:0). SRAM read Cycle 3, the Output Enable - Controlled Access in figure 3c, is initiated by G going active while En is asserted, Wn is deasserted, and the addresses are stable. Read access time is tGLQV unless tAVQV or tETQV have not been satisfied. 2 WRITE CYCLE TYPICAL RADIATION HARDNESS A combination of Wn less than VIL(max) and En less than VIL(max) defines a write cycle. The state of G is a "don't care" for a write cycle. The outputs are placed in the high-impedance state when either G is greater than V IH(min), or when Wn is less than VIL(max). The UT9Q512K32 SRAM incorporates features which allows operation in a limited radiation environment. Table 2. Radiation Hardness Design Specifications1 Write Cycle 1, the Write Enable-controlled Access is defined by a write terminated by Wn going high, with En still active. The write pulse width is defined by t WLWH when the write is initiated by Wn, and by t ETWH when the write is initiated by En. Unless the outputs have been previously placed in the highimpedance state by G, the user must wait t WLQZ before applying data to the nine bidirectional pins DQ(7:0) to avoid bus contention. Total Dose 30 krad(Si) Heavy Ion Error Rate2 1.0E-11 Errors/Bit-Day Notes: 1. The SRAM will not latchup during radiation exposure under recommended operating conditions. 2. 90% worst case particle environment, Geosynchronous orbit, 100 mils of Aluminum. Write Cycle 2, the Chip Enable-controlled Access is defined by a write terminated by the latter of En going inactive. The write pulse width is defined by t WLEF when the write is initiated by Wn, and by tETEF when the write is initiated by the En going active. For the Wn initiated write, unless the outputs have been previously placed in the high-impedance state by G, the user must wait tWLQZ before applying data to the eight bidirectional pins DQ(7:0) to avoid bus contention. 3 ABSOLUTE MAXIMUM RATINGS 1 (Referenced to V SS) SYMBOL PARAMETER LIMITS VDD DC supply voltage -0.5 to 7.0V VI/O Voltage on any pin -0.5 to 7.0V TSTG Storage temperature -65 to +150C PD Maximum power dissipation 1.0W (per byte) TJ Maximum junction temperature2 +150C Thermal resistance, junction-to-case 3 10C/W DC input current 10 mA JC II Notes: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability and performance. 2. Maximum junction temperature may be increased to +175C during burn-in and steady-static life. 3. Test per MIL-STD-883, Method 1012. RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER LIMITS VDD Positive supply voltage 4.5 to 5.5V TC Case temperature range -55 to +125C VIN DC input voltage 0V to VDD 4 DC ELECTRICAL CHARACTERISTICS (Pre/Post-Radiation)* (-55C to +125C) (V DD = 5.0V + 10%) SYMBOL PARAMETER VIH High-level input voltage VIL Low-level input voltage VOL1 Low-level output voltage VOL2 CONDITION MIN MAX 2.0 UNIT V 0.8 V IOL = 8mA, V DD =4.5V 0.4 V Low-level output voltage IOL = 200A,VDD =4.5V 0.05 V VOH1 High-level output voltage IOH = -4mA,VDD =4.5V 2.4 V VOH2 High-level output voltage IOH = 200A,VDD =4.5V 3.2 V CIN1 Input capacitance = 1MHz @ 0V 10 pF CIO1 Bidirectional I/O capacitance = 1MHz @ 0V 12 pF IIN Input leakage current VIN = VDD and VSS, VDD = V DD (max) -2 2 A IOZ Three-state output leakage current VO = VDD and VSS -2 2 A -90 90 mA 125 mA 180 mA -55C and 25C 6 mA 125C 12 mA VDD = VDD (max) G = VDD (max) IOS2, 3 Short-circuit output current VDD = VDD (max), VO = V DD VDD = VDD (max), VO = 0V IDD(OP) Supply current operating @ 1MHz (per byte) Inputs: VIL = 0.8V, VIH = 2.0V IOUT = 0mA VDD = VDD (max) IDD1(OP) Supply current operating @40MHz (per byte) Inputs: VIL = 0.8V, VIH = 2.0V IOUT = 0mA VDD = VDD (max) IDD2(SB) Supply current standby @0MHz 25 C 5.5V pre-radiation (per byte) Inputs: VIL = V SS IOUT = 0mA E1 = VDD - 0.5, VDD = VDD (max) VIH = VDD - 0.5V Notes: * Post-radiation performance guaranteed at 25C per MIL-STD-883 Method 1019. 1. Measured only for initial qualification and after process or design changes that could affect input/output capacitance. 2. Supplied as a design limit but not guaranteed or tested. 3. Not more than one output may be shorted at a time for maximum duration of one second. 5 AC CHARACTERISTICS READ CYCLE (Pre/Post-Radiation)* (-55C to +125C) (V DD = 5.0V + 10%) SYMBOL PARAMETER 9Q512-25 5.0V MIN MAX tAVAV1 Read cycle time tAVQV Read access time tAXQX2 Output hold time 3 ns tGLQX2 G-controlled Output Enable time 3 ns tGLQV G-controlled Output Enable time (Read Cycle 3) 10 ns tGHQZ2 G-controlled output three-state time 10 ns tETQX2,3 En-controlled Output Enable time tETQV3 En-controlled access time 25 ns En-controlled output three-state time 10 ns tEFQZ1,2,4 35 UNIT ns 35 3 ns Notes: * Post-radiation performance guaranteed at 25C per MIL-STD-883 Method 1019. 1. Functional test. 2. Three-state is defined as a 500mV change from steady-state output voltage. 3. The ET (enable true) notation refers to the falling edge of En. SEU immunity does not affect the read parameters. 4. The EF (enable false) notation refers to the rising edge of En. SEU immunity does not affect the read parameters. High Z to Active Levels Active to High Z Levels VH - 500mV V LOAD + 500mV } VLOAD { { } VLOAD - 500mV VL + 500mV Figure 3. 5-Volt SRAM Loading 6 ns tAVAV A(18:0) DQn(7:0) Previous Valid Data Valid Data tAVQV Assumptions: 1. En and G < VIL (max) and Wn > VIH (min) tAXQX Figure 4a. SRAM Read Cycle 1: Address Access A(18:0) En tETQV tETQX tEFQZ DQn(7:0) DATA VALID Assumptions: 1. G < VIL (max) and Wn > V IH (min) Figure 4b. SRAM Read Cycle 2: Chip Enable-Controlled Access tAVQV A(18:0) G tGHQZ tGLQX DATA VALID DQn(7:0) tGLQV Assumptions: 1. En < V IL (max) and Wn > VIH (min) Figure 4c. SRAM Read Cycle 3: Output Enable-Controlled Access 7 AC CHARACTERISTICS WRITE CYCLE (Pre/Post-Radiation)* (-55C to +125C) (V DD = 5.0V + 10%) SYMBOL PARAMETER 9Q512-25 5.0V MIN MAX UNIT tAVAV1 Write cycle time 35 ns tETWH Device Enable to end of write 20 ns tAVET Address setup time for write (En - controlled) 0 ns tAVWL Address setup time for write (Wn - controlled) 0 ns tWLWH Write pulse width 20 ns tWHAX Address hold time for write (Wn - controlled) 0 ns tEFAX Address hold time for Device Enable (En - controlled) 0 ns tWLQZ2 Wn - controlled three-state time tWHQX2 Wn - controlled Output Enable time 5 ns tETEF Device Enable pulse width (En - controlled) 20 ns tDVWH Data setup time 15 ns tWHDX Data hold time 0 ns tWLEF Device Enable controlled write pulse width 20 ns tDVEF Data setup time 15 ns tEFDX Data hold time 0 ns tAVWH Address valid to end of write 20 ns tWHWL1 Write disable time 5 ns 10 Notes: * Post-radiation performance guaranteed at 25C per MIL-STD-883 Method 1019. 1. Functional test performed with outputs disabled (G high). 2. Three-state is defined as 500mV change from steady-state output voltage. 8 ns A(18:0) tAVAV2 En tAVWH tETWH tWHWL Wn tAVWL tWLWH tWHAX Qn(7:0) tWLQZ Dn(7:0) tWHQX APPLIED DATA Assumptions: 1. G < VIL (max). If G > VIH (min) then Qn(7:0) will be in three-state for the entire cycle. 2. G high for tAVAV cycle. tDVWH tWHDX Figure 5a. SRAM Write Cycle 1: Write Enable - Controlled Access 9 tAVAV3 A(18:0) tETEF tAVET tEFAX En or tAVET En tETEF tEFAX tWLEF Wn Dn(7:0) APPLIED DATA tWLQZ tDVEF Qn(7:0) tEFDX Assumptions & Notes: 1. G < VIL (max). If G > V IH (min) then Qn(7:0) will be in three-state for the entire cycle. 2. Either En scenario above can occur. 3. G high for t AVAV cycle. Figure 5b. SRAM Write Cycle 2: Chip Enable - Controlled Access CMOS 90% VDD-0.05V 680 ohms VLOAD = 1.55V 10% 0.5V 10% < 5ns 50pF < 5ns Input Pulses Notes: 1. 50pF including scope probe and test socket capacitance. 2. Measurement of data output occurs at the low to high or high to low transition mid-point (i.e., CMOS input = V DD/2). Figure 6. AC Test Loads and Input Waveforms 10 DATA RETENTION MODE VDR > 2.5V VDD 4.5V 4.5V tR tEFR E1 VDD = V DR Figure 7. Low VDD Data Retention Waveform DATA RETENTION CHARACTERISTICS (Pre/Post-Irradiation) (1 Second Data retention Test) SYMBOL PARAMETER MINIMUM MAXIMUM UNIT VDD for data retention 2.5 -- V IDDR 1,2 Data retention current (per byte) -- 5.0 mA tEFR1,3 Chip deselect to data retention time 0 ns tAVAV Ns VDR tR1,3 Operation recovery time Notes: 1. En = VDD - .2V, all other inputs = VDR or VSS. 2. Data retention current (IDDR) Tc = 25oC. 3. Not guaranteed or tested. DATA RETENTION CHARACTERISTICS (Pre/Post-Irradiation) (10 Second Data Retention Test) SYMBOL PARAMETER VDD1 tEFR2, 3 tR2, 3 VDD for data retention Chip select to data retention time Operation recovery time Notes: 1. Performed at V DD (min) and VDD (max). 2. En = VSS, all other inputs = VDR or VSS. 3. Not guaranteed or tested. 11 MINIMUM MAXIMUM UNIT 4.5 5.5 V 0 ns tAVAV ns PACKAGING Notes: 1. Package shipped with non-conductive strip (NCS). Leads are not trimmed. Figure 8. 68-pin Ceramic FLATPACK 12 ORDERING INFORMATION 512K32 16Megabit SRAM MCM: UT ***** -* * * Lead Finish: (A) = Hot solder dipped (C) = Gold (X) = Factory option (gold or solder) Screening: (C) = Military Temperature Range flow (P) = Prototype flow Package Type: (S) = 68-lead dual cavity CQFP Device Type: (9Q512K32) = 16Megabit SRAM Notes: 1. Lead finish (A,C, or X) must be specified. 2. If an "X" is specified when ordering, then the part marking will match the lead finish and will be either "A" (solder) or "C" (gold). 3. Prototype flow per UTMC Manufacturing Flows Document. Tested at 25 C only. Lead finish is GOLD ONLY. Radiation neither tested nor guaranteed. 4. Military Temperature Range flow per UTMC Manufacturing Flows Document. Devices are tested at -55 C, room temp, and 125 C. Radiation neither tested nor guaranteed. 13 512K32 16Megabit SRAM MCM: SMD 5962 - **TBD** ** * * * Lead Finish: (A) = Hot solder dipped (C) = Gold (X) = Factory Option (gold or solder Case Outline: (X) = 68-lead dual cavity CQFP Class Designator: (T) = QML Class T (Q) = QML Class Q Device Type 01 = 25 ns access time, 5.0V operation Drawing Number: TBD Total Dose (D) = 1E4 (10krad(Si)) (P) = 3E4 (30krad(Si)) (contact factory) Federal Stock Class Designator: No Options Notes: 1. Lead finish (A,C, or X) must be specified. 2. If an "X" is specified when ordering, part marking will match the lead finish and will be either "A" (solder) or "C" (gold). 3. Total dose radiation must be specified when ordering. QML Q and QML T not available without radiation hardening. 14