FEATURES
q35ns maximum (5 volt supply) address access time
qAsynchronous operation for compatible with industry
standard 512K x 8 SRAMs
qTTL compatible inputs and output levels, three-state
bidirectional data bus
qTypical radiation performance
- Total dose
- Solution #1: Up to 30krads
- Solution #2: Up to 300krads
- SEL Immune >100 MeV-cm2/mg
- LETTH(0.25) = 40 MeV-cm2/mg
- Saturated Cross Section (cm2) per bit, 1.0E-9
- 3.8E-11 errors/bit-day, Adams 90% geosynchronous
heavy ion
- Inherent Neutron Hardness: 1.0E14n/cm2
- Dose Rate
- Upset 1.0E9 rad(Si)/sec
- Latchup >1.0E11 rad(Si)/sec
qPackaging options:
- 68-lead dual cavity ceramic quad flatpack (CQFP)
qStandard Microcircuit Drawing pending
- QML T and Q compliant part
INTRODUCTION
The UT9Q512K32 is a high-performance 2M byte (16Mbit)
CMOS static RAM multi-chip module (MCM), organized
as four individual 524,288 x 8 bit SRAMs with a common
output enable. Memory expansion is provided by an active
LOW chip enable (En), an active LOW output enable (G),
and three-state drivers. This device has a power-down
feature that reduces power consumption by more than 90%
when deselected.
Writing to each memory is accomplished by taking chip
enable (En) input LOW and write enable (Wn) inputs LOW.
Data on the eight I/O pins (DQ0 through DQ7) is then written
into the location specified on the address pins (A0 through
A18). Reading from the device is accomplished by taking
chip enable (En) and output enable (G) LOW while forcing
write enable (Wn) HIGH. Under these conditions, the
contents of the memory location specified by the address
pins will appear on the I/O pins.
The eight input/output pins (DQ0 through DQ7) are placed
in a high impedance state when the device is deselected (En
HIGH), the outputs are disabled (G HIGH), or during a write
operation (En LOW and Wn LOW). Perform 8, 16, 24 or
32 bit accesses by making Wn along with G a common input
to any combination of the discrete memory die.
Figure 1. UT9Q512K32 SRAM Block Diagram
512K x 8 512K x 8 512K x 8 512K x 8
DQ(31:24)
or
DQ3(7:0)
DQ(23:16)
or
DQ2(7:0)
DQ(15:8)
or
DQ1(7:0)
DQ(7:0)
or
DQ0(7:0)
G
A(18:0)
W3
E3E2E1E0
W2W1W0
Standard Products
UT9Q512K32 16Megabit SRAM MCM
Advanced Data Sheet January 15, 2001