FDS8880 N-Channel PowerTrench® MOSFET
©2007 Semiconductor Components Industries, LLC.
October-2017, Rev. 2
Publication Order Number:
FDS8880/D
1
FDS8880
N-Channel PowerTrench® MOSFET
30V, 11.6A, 10mΩ
Features
rDS(on) = 10mΩ, VGS = 10V, ID = 11.6A
rDS(on) = 12mΩ, VGS = 4.5V, ID = 10.7A
High performance trench technology for extremely low
rDS(on)
Low gate charge
High power and current handling capability
RoHS Compliant
General Description
This N-Channel MOSFET has been designed specifically to
improve the overall efficiency of DC/DC converters using
either synchronous or conventional switching PWM
controllers. It has been optimized for low gate charge, low
rDS(on) and fast switching speed.
Applications
DC/DC converters
SO-8
Branding Dash
1
5
2
3
4
4
3
2
1
5
6
7
8
FDS8880 N-Channel PowerTrench® MOSFET
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2
MOSFET Maximum Ratings TA = 25°C unless otherwise noted
Symbol Parameter Ratings Units
VDSS Drain to Source Voltage 30 V
VGS Gate to Source Voltage ±20 V
ID
Drain Current
11.6 A
Continuous (TA = 25oC, VGS = 10V, RθJA = 50oC/W)
Continuous (TA = 25oC, VGS = 4.5V, RθJA = 50oC/W) 10.7 A
Pulsed 83 A
EAS Single Pulse Avalanche Energy (Note 1) 82 mJ
PD
Power dissipation 2.5 W
Derate above 25oC20 mW/oC
TJ, TSTG Operating and Storage Temperature -55 to 150 oC
Thermal Characteristics
RθJC Thermal Resistance, Junction to Case (Note 2) 25 oC/W
RθJA Thermal Resistance, Junction to Ambient (Note 2a) 50 oC/W
RθJA Thermal Resistance, Junction to Ambient (Note 2b) 125 oC/W
Package Marking and Ordering Information
Device Marking Device Package Reel Size Tape Width Quantity
FDS8880 FDS8880 SO-8 330mm 12mm 2500 units
Electrical Characteristics TJ = 25°C unless otherwise noted
Symbol Parameter Test Conditions Min Typ Max Units
Off Characteristics
BVDSS Drain to Source Breakdown Voltage ID = 250µA, VGS = 0V 30 - - V
IDSS Zero Gate Voltage Drain Current VDS = 24V - - 1 µA
VGS = 0V TJ = 150oC - - 250
IGSS Gate to Source Leakage Current VGS = ±20V - - ±100 nA
On Characteristics
VGS(TH) Gate to Source Threshold Voltage VGS = VDS, ID = 250µA1.2 -2.5 V
rDS(on) Drain to Source On Resistance
ID = 11.6A, VGS = 10V -7.9 10.0
mΩ
ID = 10.7A, VGS = 4.5V -9.6 12.0
ID = 11.6A, VGS = 10V,
TJ = 150oC-12.5 16.3
Dynamic Characteristics
CISS Input Capacitance VDS = 15V, VGS = 0V,
f = 1MHz
-1235 -pF
COSS Output Capacitance -260 -pF
CRSS Reverse Transfer Capacitance -150 -pF
RGGate Resistance VGS = 0.5V, f = 1MHz 0.6 2.5 4.3 Ω
Qg(TOT) Total Gate Charge at 10V VGS = 0V to 10V
VDD = 15V
ID = 11.6A
Ig = 1.0mA
-23 30 nC
Qg(5) Total Gate Charge at 5V VGS = 0V to 5V -12 16 nC
Qg(TH) Threshold Gate Charge VGS = 0V to 1V -1.3 1.6 nC
Qgs Gate to Source Gate Charge -3.3 -nC
Qgs2 Gate Charge Threshold to Plateau -2.0 -nC
Qgd Gate to Drain “Miller” Charge -4.2 -nC
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Switching Characteristics (VGS = 10V)
tON Turn-On Time
VDD = 15V, ID = 11.6A
VGS = 10V, RGS = 11Ω
- - 51 ns
td(ON) Turn-On Delay Time - 7 - ns
trRise Time -27 -ns
td(OFF) Turn-Off Delay Time -38 -ns
tfFall Time -15 -ns
tOFF Turn-Off Time - - 80 ns
Drain-Source Diode Characteristics
VSD Source to Drain Diode Voltage ISD = 11.6A - - 1.25 V
ISD = 2.1A - - 1.0 V
trr Reverse Recovery Time ISD = 11.6A, dISD/dt = 100A/µs - - 30 ns
QRR Reverse Recovered Charge ISD = 11.6A, dISD/dt = 100A/µs - - 20 nC
Notes:
1: Starting TJ = 25°C, L = 1mH, IAS = 12.8A, VDD = 30V, VGS = 10V.
2: RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the
drain pins. RθJC is guaranteed by design while RθJA is determined by the user’s board design.
a) 50°C/W when mounted on a 1in2 pad of 2 oz copper.
b) 125°C/W when mounted on a minimum pad.
FDS8880 N-Channel PowerTrench® MOSFET
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4
Typical Characteristics TJ = 25°C unless otherwise noted
Figure 1.
TA, AMBIENT TEMPERATURE (oC)
POWER DISSIPATION MULTIPLIER
0
0 25 50 75 100 150
0.2
0.4
0.6
0.8
1.0
1.2
125
Normalized Power Dissipation vs
Ambient Temperature
Figure 2.
0
2
4
6
8
10
12
25 50 75 100 125 150
ID, DRAIN CURRENT (A)
TA, AMBIENT TEMPERATURE (oC)
RθJA=50oC/W
VGS = 10V
VGS = 4.5V
Maximum Continuous Drain Current vs
Ambient Temperature
Figure 3.
10-4 10-3 10-2 10-1 100101102103
0.001
0.01
0.1
1
SINGLE PULSE
RθJA = 125oC/W
0.0005
DUTY CYCLE-DESCENDING ORDER
NORMALIZED THERMAL
IMPEDANCE, ZθJA
t, RECTANGULAR PULSE DURATION (s)
D = 0.5
0.2
0.1
0.05
0.02
0.01
2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJA x RθJA + TA
PDM
t1
t2
Normalized Maximum Transient Thermal Impedance
Figure 4.
10-4 10-3 10-2 10-1 100101102103
1
10
100
1000
P(PK), PEAK TRANSIENT POWER (W)
VGS = 10V
SINGLE PULSE
RθJA = 125oC/W
TA = 25oC
t, PULSE WIDTH (s)
2000
0.5
Single Pulse Maximum Power Dissipation
FDS8880 N-Channel PowerTrench® MOSFET
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Figure 5.
1
10
100
0.01 0.1 1 10 100
IAS, AVALANCHE CURRENT (A)
tAV, TIME IN AVALANCHE (ms)
NOTE: Refer to ON Semiconductor Application Notes AN7514 and AN7515
STARTING TJ = 25oC
STARTING TJ = 150oC
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
If R = 0
If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
Unclamped Inductive Switching
Capability
Figure 6.
0
10
20
30
40
50
1.5 2.0 2.5 3.0 3.5
ID, DRAIN CURRENT (A)
VGS, GATE TO SOURCE VOLTAGE (V)
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD = 15V
TJ = 150oC
TJ = 25oC
TJ = -55oC
Transfer Characteristics
Figure 7. Saturation Characteristics
0
10
20
30
40
50
0 0.2 0.4 0.6 0.8
ID, DRAIN CURRENT (A)
VDS, DRAIN TO SOURCE VOLTAGE (V)
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VGS = 3V
VGS = 10V
TA = 25oC
VGS = 4V
VGS = 5V
Figure 8.
0
10
20
30
40
50
246810
VGS, GATE TO SOURCE VOLTAGE (V)
ID = 11.6A
rDS(ON), DRAIN TO SOURCE
ON RESISTANCE (mW)
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
ID = 1A
Drain to Source On Resistance vs Gate
Voltage and Drain Current
Figure 9.
0.6
0.8
1.0
1.2
1.4
1.6
-80 -40 0 40 80 120 160
NORMALIZED DRAIN TO SOURCE
TJ, JUNCTION TEMPERATURE (oC)
ON RESISTANCE
VGS = 10V, ID = 11.6A
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
Normalized Drain to Source On
Resistance vs Junction Temperature
Figure 10.
0.6
0.8
1.0
1.2
-80 -40 0 40 80 120 160
NORMALIZED GATE
TJ, JUNCTION TEMPERATURE (oC)
VGS = VDS, ID = 250µA
THRESHOLD VOLTAGE
Normalized Gate Threshold Voltage vs
Junction Temperature
Typical Characteristics TJ = 25°C unless otherwise noted
FDS8880 N-Channel PowerTrench® MOSFET
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6
Figure 11.
0.90
0.95
1.00
1.05
1.10
-80 -40 0 40 80 120 160
TJ, JUNCTION TEMPERATURE (oC)
NORMALIZED DRAIN TO SOURCE
ID = 250µA
BREAKDOWN VOLTAGE
Normalized Drain to Source
Breakdown Voltage vs Junction Temperature
Figure 12.
100
1000
0.1 1 10
2000
30
C, CAPACITANCE (pF)
VGS = 0V, f = 1MHz
CISS = CGS + CGD
COSS ≅ CDS + CGD
CRSS = CGD
VDS, DRAIN TO SOURCE VOLTAGE (V)
Capacitance vs Drain to Source
Voltage
Figure 13.
0
2
4
6
8
10
0 5 10 15 20 25
VGS, GATE TO SOURCE VOLTAGE (V)
Qg, GATE CHARGE (nC)
VDD = 15V
ID = 11.6A
ID = 1A
WAVEFORMS IN
DESCENDING ORDER:
Gate Charge Waveforms for Constant
Gate Currents
Figure 14. Forward Bias Safe Operating Area
0.01 0.1 1 10 100
0.01
0.1
1
10
100
DC
10s
1s
100ms
10ms
1ms
100us
ID, DRAIN CURRENT (A)
VDS, DRAIN to SOURCE VOLTAGE (V)
THIS AREA IS
LIMITED BY rDS(on)
SINGLE PULSE
TJ = MAX RATED
RθJA = 125oC/W
TA = 25oC
Typical Characteristics TJ = 25°C unless otherwise noted
Test Circuits and Waveforms
Figure 15.
tP
VGS
0.01Ω
L
IAS
+
-
VDS
VDD
RG
DUT
VARY tP TO OBTAIN
REQUIRED PEAK IAS
0V
Unclamped Energy Test Circuit Figure 16.
VDD
VDS
BVDSS
tP
IAS
tAV
0
Unclamped Energy Waveforms
Figure 17.
VGS +
-
VDS
VDD
DUT
Ig(REF)
L
Gate Charge Test Circuit Figure 18.
VDD
Qg(TH)
VGS = 1V
Qgs2
Qg(TOT)
VGS = 10V
VDS VGS
Ig(REF)
0
0
Qgs Qgd
Qg(5)
VGS = 5V
Gate Charge Waveforms
Figure 19.
VGS
RL
RGS
DUT
+
-
VDD
VDS
VGS
Switching Time Test Circuit Figure 20.
tON
td(ON)
tr
90%
10%
VDS
90%
10%
tf
td(OFF)
tOFF
90%
50%
50%
10% PULSE WIDTH
VGS
0
0
Switching Time Waveforms
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FDS8880 N-Channel PowerTrench® MOSFET
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Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, TJM, and the
thermal resistance of the heat dissipating path determines
the maximum allowable device power dissipation, PDM, in an
application. Therefore the application’s ambient
temperature, TA (oC), and thermal resistance RθJA (oC/W)
must be reviewed to ensure that TJM is never exceeded.
Equation 1 mathematically represents the relationship and
serves as the basis for establishing the rating of the part.
(EQ. 1)
PDM
TJM TA
–()
RθJA
-------------------------------=
In using surface mount devices such as the SO8 package,
the environment in which it is applied will have a significant
influence on the part’s current and maximum power
dissipation ratings. Precise determination of PDM is complex
and influenced by many factors:
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.
2. The number of copper layers and the thickness of the
board.
3. The use of external heat sinks.
4. The use of thermal vias.
5. Air flow and board orientation.
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
ON Semiconductor provides thermal information to assist
the designer’s preliminary application evaluation. Figure 21
defines the RθJA for the device as a function of the top
copper (compo-nent side) area. This is for a horizontally
positioned FR-4 board with 1oz copper after 1000 seconds
of steady state power with no air flow. This graph provides
the necessary in-formation for calculation of the steady
state junction temper-ature or power dissipation. Pulse
applications can be evaluated using the ON
Semiconductor device Spice thermal model or manually
utilizing the normalized maximum transient
thermal impedance curve.
Thermal resistances corresponding to other copper areas
can be obtained from Figure 21 or by calculation using
Equation 2. The area, in square inches is the top copper
area including the gate and source pads.
(EQ. 2)
RθJA 64 26
0.23 Area+
-------------------------------
+=
The transient thermal impedance (ZθJA) is also effected by
varied top copper board area. Figure 22 shows the effect of
copper pad area on single pulse transient thermal imped-
ance. Each trace represents a copper pad area in square
inches corresponding to the descending list in the graph.
Spice and SABER thermal models are provided for each of
the listed pad areas.
Copper pad area has no perceivable effect on transient
thermal impedance for pulse widths less than 100ms. For
pulse widths less than 100ms the transient thermal
impedance is determined by the die and package.
Therefore, CTHERM1 through CTHERM5 and RTHERM1
through RTHERM5 remain constant for each of the thermal
models. A listing of the model component values is available
in Table 1.
100
150
200
0.001 0.01 0.1 1 10
50
Figure 21. Thermal Resistance vs Mounting
Pad Area
RθJA = 64 + 26/(0.23+Area)
RθJA (oC/W)
AREA, TOP COPPER AREA (in2)
0
30
60
90
120
150
10-1 100101102103
Figure 22. Thermal Impedance vs Mounting Pad Area
t, RECTANGULAR PULSE DURATION (s)
ZθJA, THERMAL
COPPER BOARD AREA - DESCENDING ORDER
0.04 in2
0.28 in2
0.52 in2
0.76 in2
1.00 in2
IMPEDANCE (oC/W)
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PSPICE Electrical Model
.SUBCKT FDS8880 2 1 3 ; rev August 2004
Ca 12 8 9.3e-10
Cb 15 14 9.3e-10
Cin 6 8 1.15e-9
Dbody 7 5 DbodyMOD
Dbreak 5 11 DbreakMOD
Dplcap 10 5 DplcapMOD
Ebreak 11 7 17 18 33.5
Eds 14 8 5 8 1
Egs 13 8 6 8 1
Esg 6 10 6 8 1
Evthres 6 21 19 8 1
Evtemp 20 6 18 22 1
It 8 17 1
Lgate 1 9 3.6e-9
Ldrain 2 5 1.0e-9
Lsource 3 7 1.2e-10
RLgate 1 9 36
RLdrain 2 5 10
RLsource 3 7 1.2
Mmed 16 6 8 8 MmedMOD
Mstro 16 6 8 8 MstroMOD
Mweak 16 21 8 8 MweakMOD
Rbreak 17 18 RbreakMOD 1
Rdrain 50 16 RdrainMOD 2.9e-3
Rgate 9 20 2.5
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
Rsource 8 7 RsourceMOD 5.4e-3
Rvthres 22 8 RvthresMOD 1
Rvtemp 18 19 RvtempMOD 1
S1a 6 12 13 8 S1AMOD
S1b 13 12 13 8 S1BMOD
S2a 6 15 14 13 S2AMOD
S2b 13 15 14 13 S2BMOD
Vbat 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*170),5))}
.MODEL DbodyMOD D (IS=2.6E-12 IKF=10 N=1.01 RS=5.6e-3 TRS1=8e-4 TRS2=2e-7
+ CJO=5e-10 M=0.55 TT=1e-11 XTI=2)
.MODEL DbreakMOD D (RS=0.2 TRS1=1e-3 TRS2=-8.9e-6)
.MODEL DplcapMOD D (CJO=4.27e-10 IS=1e-30 N=10 M=0.38)
.MODEL MmedMOD NMOS (VTO=1.8 KP=5 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=2.5)
.MODEL MstroMOD NMOS (VTO=2.21 KP=150 IS=1e-30 N=10 TOX=1 L=1u W=1u)
.MODEL MweakMOD NMOS (VTO=1.53 KP=0.05 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=25 RS=0.1)
.MODEL RbreakMOD RES (TC1=8.3e-4 TC2=-8e-7)
.MODEL RdrainMOD RES (TC1=5.5e-3 TC2=1.2e-5)
.MODEL RSLCMOD RES (TC1=1e-4 TC2=1e-6)
.MODEL RsourceMOD RES (TC1=1e-3 TC2=3e-6)
.MODEL RvthresMOD RES (TC1=-1.5e-3 TC2=-6e-6)
.MODEL RvtempMOD RES (TC1=-1.8e-3 TC2=2e-7)
.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-4 VOFF=-3.5)
.MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-3.5 VOFF=-4)
.MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-1.5 VOFF=-1.0)
.MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-1.0 VOFF=-1.5)
.ENDS
Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.
18
22
+-
6
8
+
-
5
51
+
-
19
8
+-
17
18
6
8
+
-
5
8+
-
RBREAK
RVTEMP
VBAT
RVTHRES
IT
17 18
19
22
12
13
15
S1A
S1B
S2A
S2B
CA CB
EGS EDS
14
8
13
8
14
13
MWEAK
EBREAK DBODY
RSOURCE
SOURCE
11
73
LSOURCE
RLSOURCE
CIN
RDRAIN
EVTHRES 16
21
8
MMED
MSTRO
DRAIN
2
LDRAIN
RLDRAIN
DBREAK
DPLCAP
ESLC
RSLC1
10
5
51
50
RSLC2
1
GATE RGATE
EVTEMP
9
ESG
LGATE
RLGATE
20
+
-
+
-
+
-
6
FDS8880 N-Channel PowerTrench® MOSFET
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10
SABER Electrical Model
REV August 2004
template FDS8880 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (isl=2.6e-12,ikf=10,nl=1.01,rs=5.6e-3,trs1=8e-4,trs2=2e-7,cjo=5e-10,m=0.55,tt=1e-11,xti=2)
dp..model dbreakmod = (rs=0.2,trs1=1e-3,trs2=-8.9e-6)
dp..model dplcapmod = (cjo=4.27e-10,isl=10e-30,nl=10,m=0.38)
m..model mmedmod = (type=_n,vto=1.8,kp=5,is=1e-30, tox=1)
m..model mstrongmod = (type=_n,vto=2.21,kp=150,is=1e-30, tox=1)
m..model mweakmod = (type=_n,vto=1.53,kp=0.05,is=1e-30, tox=1,rs=0.1)
sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-4,voff=-3.5)
sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-3.5,voff=-4)
sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-1.5,voff=-1.0)
sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=-1.0,voff=-1.5)
c.ca n12 n8 = 9.3e-10
c.cb n15 n14 = 9.3e-10
c.cin n6 n8 = 1.15e-9
dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod
spe.ebreak n11 n7 n17 n18 = 33.5
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evthres n6 n21 n19 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
i.it n8 n17 = 1
l.lgate n1 n9 = 3.6e-9
l.ldrain n2 n5 = 1.0e-9
l.lsource n3 n7 = 1.2e-10
res.rlgate n1 n9 = 36
res.rldrain n2 n5 = 10
res.rlsource n3 n7 = 1.2
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
res.rbreak n17 n18 = 1, tc1=8.3e-4,tc2=-8e-7
res.rdrain n50 n16 = 2.9e-3, tc1=5.5e-3,tc2=1.2e-5
res.rgate n9 n20 = 2.5
res.rslc1 n5 n51 = 1e-6, tc1=1e-4,tc2=1e-6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 5.4e-3, tc1=1e-3,tc2=3e-6
res.rvthres n22 n8 = 1, tc1=-1.5e-3,tc2=-6e-6
res.rvtemp n18 n19 = 1, tc1=-1.8e-3,tc2=2e-7
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/170))** 5))
}
}
18
22
+-
6
8
+
-
19
8
+-
17
18
6
8
+
-
5
8+
-
RBREAK
RVTEMP
VBAT
RVTHRES
IT
17 18
19
22
12
13
15
S1A
S1B
S2A
S2B
CA CB
EGS EDS
14
8
13
8
14
13
MWEAK
EBREAK
DBODY
RSOURCE
SOURCE
11
73
LSOURCE
RLSOURCE
CIN
RDRAIN
EVTHRES 16
21
8
MMED
MSTRO
DRAIN
2
LDRAIN
RLDRAIN
DBREAK
DPLCAP
ISCL
RSLC1
10
5
51
50
RSLC2
1
GATE RGATE
EVTEMP
9
ESG
LGATE
RLGATE
20
+
-
+
-
+
-
6
FDS8880 N-Channel PowerTrench® MOSFET
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11
SPICE Thermal Model
REV August 2004
FDS8880
Copper Area =1.0 in2
CTHERM1 TH 8 2.0e-3
CTHERM2 8 7 5.0e-3
CTHERM3 7 6 1.0e-2
CTHERM4 6 5 4.0e-2
CTHERM5 5 4 9.0e-2
CTHERM6 4 3 2e-1
CTHERM7 3 2 1
CTHERM8 2 TL 3
RTHERM1 TH 8 1e-1
RTHERM2 8 7 5e-1
RTHERM3 7 6 1
RTHERM4 6 5 5
RTHERM5 5 4 8
RTHERM6 4 3 12
RTHERM7 3 2 18
RTHERM8 2 TL 25
SABER Thermal Model
Copper Area = 1.0 in2
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 8 =2.0e-3
ctherm.ctherm2 8 7 =5.0e-3
ctherm.ctherm3 7 6 =1.0e-2
ctherm.ctherm4 6 5 =4.0e-2
ctherm.ctherm5 5 4 =9.0e-2
ctherm.ctherm6 4 3 =2e-1
ctherm.ctherm7 3 2 1
ctherm.ctherm8 2 tl 3
rtherm.rtherm1 th 8 =1e-1
rtherm.rtherm2 8 7 =5e-1
rtherm.rtherm3 7 6 =1
rtherm.rtherm4 6 5 =5
rtherm.rtherm5 5 4 =8
rtherm.rtherm6 4 3 =12
rtherm.rtherm7 3 2 =18
rtherm.rtherm8 2 tl =25
}
TABLE 1. THERMAL MODELS
COMPONANT 0.04 in20.28 in20.52 in20.76 in21.0 in2
CTHERM6 1.2e-1 1.5e-1 2.0e-1 2.0e-1 2.0e-1
CTHERM7 0.5 1.0 1.0 1.0 1.0
CTHERM8 1.3 2.8 3.0 3.0 3.0
RTHERM6 26 20 15 13 12
RTHERM7 39 24 21 19 18
RTHERM8 55 38.7 31.3 29.7 25
RTHERM6
RTHERM8
RTHERM7
RTHERM5
RTHERM4
RTHERM3
CTHERM4
CTHERM6
CTHERM5
CTHERM3
CTHERM2
CTHERM1
tl
2
3
4
5
6
7
JUNCTION
CASE
8
th
RTHERM2
RTHERM1
CTHERM7
CTHERM8
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