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FEATURES DESCRIPTION
APPLICATIONS
FUNCTIONAL DIAGRAM
8
2
3
4
7
6
VCC
A
B
VBB
Y
Z
2 Gbps
223 - 1 PRBS
VCC = 3.3 V
VID = 200 mV
VIC = 1.2 V
Horizontal Scale= 200 ps/div
Vert.Scale= 200 mV/div
EYE PATTERN
1 GHz
SN65LVDS100 and SN65LVDS101
2
3
7
6
A
B
Y
Z
110 Ω
SN65LVDT100 and SN65LVDT101
SN65LVDS100, SN65LVDT100SN65LVDS101, SN65LVDT101
SLLS516C – AUGUST 2002 – REVISED JUNE 2004
DIFFERENTIAL TRANSLATOR/REPEATER
•Designed for Signaling Rates
(1)
≥2 Gbps
The SN65LVDS100, SN65LVDT100, SN65LVDS101,and SN65LVDT101 are a high-speed differential re-•Total Jitter < 65 ps
ceiver and driver connected as a repeater. The•Low-Power Alternative for the MC100EP16
receiver accepts low-voltage differential signaling•Low 100 ps (Max) Part-To-Part Skew
(LVDS), positive-emitter-coupled logic (PECL), or cur-•25 mV of Receiver Input Threshold Hysteresis rent-mode logic (CML) input signals at rates up to 2Gbps and repeats it as either an LVDS or PECLOver 0-V to 4-V Common-Mode Range
output signal. The signal path through the device is•Inputs Electrically Compatible With LVPECL,
differential for low radiated emissions and minimalCML, and LVDS Signal Levels
added jitter.•3.3-V Supply Operation
The outputs of the SN65LVDS100 and•LVDT Integrates 110-ΩTerminating Resistor
SN65LVDT100 are LVDS levels as defined by•Offered in SOIC and MSOP
TIA/EIA-644-A. The outputs of the SN65LVDS101and SN65LVDT101 are compatible with 3.3-V PECLlevels. Both drive differential transmission lines withnominally 100-Ωcharacteristic impedance.•622 MHz Central Office Clock Distribution•High-Speed Network Routing
The SN65LVDT100 and SN65LVDT101 include a110-Ωdifferential line termination resistor for less•Wireless Basestations
board space, fewer components, and the shortest•Low Jitter Clock Repeater
stub length possible. They do not include the V
BB•Serdes LVPECL Output to FPGA LVDS
voltage reference found in the SN65LVDS100 andInput Translator
SN65LVDS101. V
BB
provides a voltage reference oftypically 1.35 V below V
CC
for use in receivingsingle-ended input signals and is particularly usefulwith single-ended 3.3-V PECL inputs. When not used,V
BB
should be unconnected or open.(1) The signaling rate of a line is the number of voltage
All devices are characterized for operation fromtransitions that are made per second expressed in the unitsbps (bits per second). –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains PRO-
Copyright © 2002–2004, Texas Instruments IncorporatedDUCTION DATA information current as of publication date. Prod-ucts conform to specifications per the terms of Texas Instrumentsstandard warranty. Production processing does not necessarilyinclude testing of all parameters.
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ABSOLUTE MAXIMUM RATINGS
(1)
POWER DISSIPATION RATINGS
SN65LVDS100, SN65LVDT100SN65LVDS101, SN65LVDT101
SLLS516C – AUGUST 2002 – REVISED JUNE 2004
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integratedcircuits be handled with appropriate precautions. Failure to observe proper handling and installationprocedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precisionintegrated circuits may be more susceptible to damage because very small parametric changes couldcause the device not to meet its published specifications.
ORDERING INFORMATION
OUTPUT TERMINATION RESISTOR V
BB
PART NUMBER
(1)
PART MARKING PACKAGE
LVDS No Yes SN65LVDS100D DL100 SOICLVDS No Yes SN65LVDS100DGK AZK MSOPLVDS Yes No SN65LVDT100D DE100 SOICLVDS Yes No SN65LVDT100DGK AZL MSOPLVPECL No Yes SN65LVDS101D DL101 SOICLVPECL No Yes SN65LVDS101DGK AZM MSOPLVPECL Yes No SN65LVDT101D DE101 SOICLVPECL Yes No SN65LVDT101DGK BAF MSOP
(1) Add the suffix R for taped and reeled carrier (i.e. SN65LVDS100DR).
over operating free-air temperature range unless otherwise noted
UNIT
V
CC
Supply voltage range
(2)
–0.5 V to 4 VI
BB
V
BB
Output current ±0.5 mAV
I
Voltage range, (A, B, Y, Z) 0 V to 4.3 VV
O
V
ID
Differential voltage, |V
A
– V
B
| ('LVDT100 and 'LVDT101 only) 1 VA, B, Y, Z, and GND ±5 kVHuman Body Model
(3)ESD All pins ±2 kVCharged-Device Model
(4)
All pins ±1500 VP
D
Continuous power dissipation See Dissipation Rating Table
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.(3) Tested in accordance with JEDEC Standard 22, Test Method A114-A.7.(4) Tested in accordance with JEDEC Standard 22, Test Method C101.
T
A
≤25°C DERATING FACTOR
(1)
T
A
= 85°CPACKAGE
POWER RATING ABOVE T
A
= 25°C POWER RATING
DGK 377 mW 3.8 mW/°C 151 mWD 481 mW 4.8 mW/°C 192 mW
(1) This is the inverse of the junction-to-ambient thermal resistance with no air flow installed on the JESD51-3 low effective thermalconductivity test board for leadless surface mount packages.
2
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RECOMMENDED OPERATING CONDITIONS
ELECTRICAL CHARACTERISTICS
SN65LVDS100, SN65LVDT100SN65LVDS101, SN65LVDT101
SLLS516C – AUGUST 2002 – REVISED JUNE 2004
MIN NOM MAX UNIT
Supply voltage, V
CC
3 3.3 3.6 V'LVDS100 or 'LVDS101 0.1 1Magnitude of differential input voltage |V
ID
| V'LVDT100 or 'LVDT101 0.1 0.8Input voltage (any combination of common-mode or input signals), V
I
0 4 VV
BB
output current, I
O(VBB)
–400
(1)
12 µAOperating free-air temperature, T
A
–40 85 °C
(1) The algebraic convention, in which the less positive (more negative) limit is designated minimum, is used in this data sheet.
over recommended operating conditions (unless otherwise specified)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
Supply current, 'LVDx100 No load or input 25 30I
CC
mASupply current, 'LVDx101 R
L
= 50 Ωto 1 V, No input 50 61Device power dissipation, 'LVDx100 R
L
= 100 Ω, No input 110P
D
mWY and Z to V
CC
- 2 V through 50 Ω,Device power dissipation, 'LVDx101 116 142No inputReference voltage output, 'LVDS100 orV
BB
I
O
= –400 µA or 12 µA V
CC
–1.4 V
CC
–1.35 V
CC
–1.3 mV'LVDS101
SN65LVDS100 and SN65LVDS101 INPUT CHARACTERISTICS (see Figure 1 )
Positive-going differential input voltageV
IT+
100threshold
See Figure 1 and Table 1 mVNegative-going differential input voltageV
IT-
–100threshold
V
I
= 0 V or 2.4 V,
–20 20 µASecond input at 1.2 VI
I
Input current
V
I
= 4 V, Second input at 1.2 V 33 µAV
CC
= 1.5 V, V
I
= 0 V or 2.4 V,
–20 20Second input at 1.2 VI
I(OFF)
Power off input current µAV
CC
= 1.5 V, V
I
= 4 V,
33Second input at 1.2 VI
IO
Input offset current (|I
IA
- I
IB
|) V
IA
= V
IB,
0≤V
IA
≤4 V –6 6 µAC
i
Small-signall input capacitance to GND V
I
= 1.2 V 0.6 pF
SN65LVDT100 and SN65LVDT101 INPUT CHARACTERISTICS (see Figure 1 )
Positive-going differential input voltageV
IT+
100threshold
See Figure 1 and Table 1 mVNegative-going differential input voltageV
IT-
–100threshold
V
I
= 0 V or 2.4 V, Other input open –40 40I
I
Input current µAV
I
= 4 V, Other input open 66V
CC
= 1.5 V, V
I
= 0 V or 2.4 V,
–40 40Other input openI
I(OFF)
Power off input current µAV
CC
= 1.5 V, V
I
= 4 V, Other input
66open
V
ID
= 300 mV or 500 mV, V
IC
= 0 V
90 110 132or 2.4 VR
(T)
Differential input resistance ΩV
CC
= 0 V, V
ID
= 300 mV or 500 mV,
90 110 132V
IC
= 0 V or 2.4 VC
i
Small-signall differential input capacitance V
I
= 1.2 V 0.6 pF
(1) Typical values are with a 3.3-V supply voltage and room temperature
3
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SWITCHING CHARACTERISTICS
SN65LVDS100, SN65LVDT100SN65LVDS101, SN65LVDT101
SLLS516C – AUGUST 2002 – REVISED JUNE 2004
ELECTRICAL CHARACTERISTICS (continued)over recommended operating conditions (unless otherwise specified)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
SN65LVDS100 and SN65LVDT100 OUTPUT CHARACTERISTICS (see Figure 1 )
|V
OD
| Differential output voltage magnitude 247 340 454See Figure 2 mVChange in differential output voltage magni-∆|V
OD
| –50 50tude between logic statesV
OC(SS)
Steady-state common-mode output voltage 1.125 1.375 VChange in steady-state common-mode output∆V
OC(SS)
See Figure 3 –50 50 mVvoltage between logic statesV
OC(PP)
Peak-to-peak common-mode output voltage 50 150 mVI
OS
Short-circuit output current V
O(Y)
or V
O(Z)
= 0 V –24 24 mAI
OS(D)
Differential short-circuit output current V
OD
= 0 V –12 12 mA
SN65LVDS101 and SN65LVDT101 OUTPUT CHARACTERISTICS (see Figure 1 )
50 Ωto V
CC
– 2 V, See Figure 4 V
CC
–1.25 V
CC
–1.02 V
CC
–0.9 VV
OH
High-level output voltage
V
CC
= 3.3 V, 50-Ωload to 2.3 V 2055 2280 2405 mV50 Ωto V
CC
- 2 V, See Figure 4 V
CC
–1.83 V
CC
–1.61 V
CC
–1.53 VV
OL
Low-level output voltage
V
CC
= 3.3 V, 50-Ωload to 2.3 V 1475 1690 1775 mV|V
OD
| Differential output voltage magnitude 50-Ωload to V
CC
– 2 V, SeeFigure 4 475 575 750 mV
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
'LVDx100 300 470 800Propagation delay time,t
PLH
pslow-to-high-level output
'LVDx101 400 630 900'LVDx100 300 470 800Propagation delay time,t
PHL
pshigh-to-low-level output
'LVDx100 See Figure 5 400 630 900t
r
Differential output signal rise time (20%–80%) 220 pst
f
Differential output signal fall time (20%–80%) 220 pst
sk(p)
Pulse skew (|t
PHL
– t
PLH
|)
(2)
5 50 pst
sk(pp)
Part-to-part skew
(3)
V
ID
= 0.2 V, See Figure 5 100 pst
jit(per)
RMS period jitter
(4)
1 3.7 ps1 GHz 50% duty cycle square wave input,V
ID
= 200 mV, V
IC
= 1.2 V, See Figure 6t
jit(cc)
Peak cycle-to-cycle jitter
(5)
6 23 ps2 GHz PRBS, 2
23
–1 run length, V
ID
= 200 mV,t
jit(pp)
Peak-to-peak jitter 28 65 psV
IC
= 1.2 V, See Figure 62 GHz PRBS, 2
7
–1 run length, V
ID
= 200 mV,t
jit(det)
Peak-to-peak deterministic jitter
(6)
17 48 psV
IC
= 1.2 V, See Figure 6
(1) All typical values are at 25°C and with a 3.3 V supply.(2) t
sk(p)
is the magnitude of the time difference between the t
PLH
and t
PHL
of any output of a single device.(3) t
sk(pp)
is the magnitude of the time difference in propagation delay time between any specified terminals of two devices when bothdevices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.(4) Period jitter is the deviation in cycle time of a signal with respect to the ideal period over a random sample of 1000,000 cycles.(5) Cycle-to-cycle jitter is the variation in cycle time of a signal between adjacent cycles, over a random sample of 1,000 adjacent cyclepairs. (6) Deterministic jitter is the sum of pattern-dependent jitter and pulse-width distortion.
4
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PARAMETER MEASUREMENT INFORMATION
Y
Z
A
B
VID VOD
VIB
VIA
VO(Z)
VO(Y)
IIB
IIA
VIA+VIB VIC
2VOC
IO
VBB
VBB
+
-
VOD 100 Ω
3.74 kΩ
3.74 kΩ
_
+0 V ≤ V(test) ≤ 2.4 V
Y
Z
VOC
49.9 Ω ±1%
Y
1 pF
VOC(PP) VOC(SS)
VOC
1.4 V
B
A
1.0 V
49.9 Ω ±1%
Z
A
VID
B
SN65LVDS100, SN65LVDT100SN65LVDS101, SN65LVDT101
SLLS516C – AUGUST 2002 – REVISED JUNE 2004
Figure 1. Voltage and Current Definitions
Table 1. Receiver Input Voltage Threshold Test
RESULTING DIFFERENTIAL RESULTING COMMON-APPLIED VOLTAGES OUTPUT
(1)INPUT VOLTAGE MODE INPUT VOLTAGE
V
IA
V
IB
V
ID
V
IC
1.25 V 1.15 V 100 mV 1.2 V H1.15 V 1.25 V –100 mV 1.2 V L4.0 V 3.9 V 100 mV 3.95 V H3.9 V 4. 0 V –100 mV 3.95 V L0.1 V 0.0 V 100 mV 0.05 V H0.0 V 0.1 V –100 mV 0.05 V L1.7 V 0.7 V 1000 mV 1.2 V H0.7 V 1.7 V –1000 mV 1.2 V L4.0 V 3.0 V 1000 mV 3.5 V H3.0 V 4.0 V –1000 mV 3.5 V L1.0 V 0.0 V 1000 mV 0.5 V H0.0 V 1.0 V –1000 mV 0.5 V L
(1) H = high level, L = low level
Figure 2. SN65LVDx100 Differential Output Voltage (V
OD
) Test Circuit
NOTE: All input pulses are supplied by a generator having the following characteristics: t
r
or t
f
≤0.25 ns, pulse repetition rate(PRR) = 0.5 Mpps, pulse width = 500 ±10 ns . C
L
includes instrumentation and fixture capacitance within 0,06 mm ofthe D.U.T. The measurement of V
OC(PP)
is made on test equipment with a –3 dB bandwidth of at least 300 MHz.
Figure 3. Test Circuit and Definitions for the SN65LVDx100 Driver Common-Mode Output Voltage
5
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50 Ω
VOY
VOZ
50 Ω
VOD
+
-
VCC - 2V
+
-
1.4 V
1 V
tPLH
0.4 V
0 V
VIA
VIB
VID
80% 100%
0%
tPHL
20%
tftr
VOD 0 V
Y
Z
A
B
VID 1 pF
VIB
VIA
VOD 100 Ω
-0.4 V
50 Ω
50 Ω
VCC - 2V
+
-
OR
VOD
0 V
CLOCK INPUT
1/fo
IDEAL OUTPUT 0 V
1/fo
ACTUAL OUTPUT
0 V
tc(n)
0 V
PRBS INPUT
0 V
ACTUAL OUTPUT
0 V
PRBS OUTPUT
Period Jitter Cycle to Cycle Jitter
tjit(per) = |tc(n) - 1/fo|
tc(n) tc(n+1)
tjit(cc) = |tc(n) - tc(n+1)|
tjit(pp)
SN65LVDS100, SN65LVDT100SN65LVDS101, SN65LVDT101
SLLS516C – AUGUST 2002 – REVISED JUNE 2004
Figure 4. Typical Termination for LVPECL Output Driver (65LVDx101)
NOTE: All input pulses are supplied by a generator having the following characteristics: t
r
or t
f
≤0.25 ns, pulse repetition rate(PRR) = 50 Mpps, pulse width = 10 ±0.2 ns. C
L
includes instrumentation and fixture capacitance within 0,06 mm ofthe D.U.T. Measurement equipment provides a bandwidth of 5 GHz minimum.
Figure 5. Timing Test Circuit and Waveforms
Figure 6. Driver Jitter Measurement Waveforms
6
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Pattern
Generator
Oscilloscope
EVM
Power Supply 1 +
-
Power Supply 2 +
-
VCC
EVM
GND
DUT
GND
1.22V
3.3V
Matched
Cables
SMA to SMA
Matched
Cables
SMA to SMA
J2
J7
J6
J5
J4
J3 J1
100
50 50
DUT
(Note A)
(Note B)
Tektronix
TDS6604
Agilent
E4862B
PIN ASSIGNMENTS
VCC
Y
Z
GND
8
7
6
5
1
2
3
4
NC
A
B
VBB
D AND DGK PACKAGE
(TOP VIEW)
VCC
Y
Z
GND
8
7
6
5
1
2
3
4
NC
A
B
NC
D AND DGK PACKAGE
(TOP VIEW)
NC = Not Connected
SN65LVDS100 and SN65LVDS101 SN65LVDT100 and SN65LVDT101
SN65LVDS100, SN65LVDT100SN65LVDS101, SN65LVDT101
SLLS516C – AUGUST 2002 – REVISED JUNE 2004
A. Source jitter is subtracted from the measured values.B. TDS JIT3 jitter analysis software installed
Figure 7. Jitter Setup Connections for SN65LVDS100 and SN65LVDS101
FUNCTION TABLE
DIFFERENTIAL INPUT OUTPUTS
(1)
V
ID
= V
A
– V
B
Y ZV
ID
≥100 mV H L–100 mV < V
ID
< 100 mV ? ?V
ID
≤– 100 mV L HOpen ? ?
(1) H = high level, L = low level, ? = indeterminate
7
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EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
VCC VCC
AB
INPUT
VCC
Y Z
OUTPUT
(SN65LVDS100 and SN65LVDT100)
7 V 7 V
7 V
7 V
R R
Y
Z
VCC
OUTPUT
(SN65LVDS101 and SN65LVDT101)
VCC 7 V
7 V
R R
VCC VCC
(SN65LVDT only)
215 A
110
350 A
215 A
350 A
SN65LVDS100, SN65LVDT100SN65LVDS101, SN65LVDT101
SLLS516C – AUGUST 2002 – REVISED JUNE 2004
8
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TYPICAL CHARACTERISTICS
15
25
35
45
55
0 200 400 600 800 1200
Frequency - MHz
- Supply Current - mA
ICC
1000
LVDS100
LVDS101= Loaded
VCC = 3.3 V
TA = 25°C
VIC = 1.2 V
VID = 200 mV
10
20
30
40
50
60
-40 -20 0 20 40 60 80 100
TA - Free-Air Temperature - °C
- Supply Current - mA
ICC
VCC = 3.3 V
VIC = 1.2 V
VID = 200 mV
f = 750 MHz
LVDS101 = Loaded
LVDS100
200
300
400
500
600
700
0 200 400 600 800 1000 1200
f - Frequency - MHz
- Differential Output Voltage - mVVOD
VCC = 3.3 V
TA = 25°C
VIC = 1.2 V
VID = 200 mV
LVDS101
LVDS100
300
350
400
450
500
550
600
012345
VIC - Common-Mode Input Voltage - V
- Propagation Delay Time - pst pd
tPLH
tPHL
VCC = 3.3 V
TA = 25°C
VID = 200 mV
f = 150 MHz
350
400
450
500
550
-40 -20 0 20 40 60 80 100
TA - Free-Air Temperature - °C
- Propagation Delay Time - pst pd
VCC = 3.3 V
VID = 200 mV
f = 150 MHz
tPHL
tPLH
450
500
550
600
650
700
750
0 1 2 3 4 5
VIC - Common-Mode Input Voltage - V
- Propagation Delay Time - pst pd
VCC = 3.3 V
TA = 25°C
VID = 200 mV
f = 150 MHz
tPLH
tPHL
450
500
550
600
650
700
750
-40 -20 0 20 40 60 80 100
TA - Free-Air Temperature - °C
- Propagation Delay Time - pst pd
VCC = 3.3 V
VID = 200 mV
f = 150 MHz
tPHL
tPLH
0
10
20
30
40
50
60
300 800 1300 1800
Data Rate - Mbps
Peak-To-Peak Jitter - ps
2300
VOC = 3.3 V
TA = 25°C
VIC = 400 mV
Input = PRBS 223-1
VID = 0.5 V
VID = 0.3 V
VID = 0.8 V
0
5
10
15
20
25
30
200 400 600 800 1000
f - Frequency - MHz
Peak-To-Peak Jitter - ps
VID = 0.8 V
VID = 0.5 V
VID = 0.3 V
VCC = 3.3 V
TA = 25°C
VIC = 400 mV
Input = Clock
SN65LVDS100, SN65LVDT100SN65LVDS101, SN65LVDT101
SLLS516C – AUGUST 2002 – REVISED JUNE 2004
SUPPLY CURRENT SUPPLY CURRENT DIFFERENTIAL OUTPUT VOLTAGEvs vs vsFREQUENCY FREE-AIR TEMPERATURE FREQUENCY
Figure 8. Figure 9. Figure 10.
SN65LVDS100 SN65LVDS101 SN65LVDS100PROPAGATION DELAY TIME PROPAGATION DELAY TIME PROPAGATION DELAY TIMEvs vs vsCOMMON-MODE INPUT VOLTAGE COMMON-MODE INPUT VOLTAGE FREE-AIR TEMPERATURE
Figure 11. Figure 12. Figure 13.
SN65LVDS101 SN65LVDS100 SN65LVDS100PROPAGATION DELAY TIME PEAK-TO-PEAK JITTER PEAK-TO-PEAK JITTERvs vs vsFREE-AIR TEMPERATURE FREQUENCY DATA RATE
Figure 14. Figure 15. Figure 16.
9
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0
5
10
15
20
25
30
200 400 600 800 1000
f - Frequency - MHz
Peak-To-Peak Jitter - ps
VCC = 3.3 V
TA = 25°C
VIC = 400 mV
Input = Clock
VID = 0.5 V
VID = 0.8 V
VID = 0.3 V
0
10
20
30
40
50
60
300 800 1300 1800
Data Rate - Mbps
Peak-To-Peak Jitter - ps
VCC = 3.3 V
TA = 25°C
VIC = 400 mV
Input = PRBS 223-1
2300
VID = 0.3 V
VID = 0.5 V
VID = 0.8 V
0
5
10
15
20
25
30
200 400 600 800 1000
f - Frequency - MHz
Peak-To-Peak Jitter - ps
VID = 0.5 V VID = 0.8 V
VID = 0.3 V
VCC = 3.3 V
TA = 25°C
VIC = 1.2 V
Input = Clock
0
10
20
30
40
50
60
300 800 1300 1800
Data Rate - Mbps
Peak-To-Peak Jitter - ps
VCC = 3.3 V
TA = 25°C
VIC= 1.2 V
Input = PRBS 223-1 VID = 0.3 V
VID = 0.8 V
2300
VID = 0.5 V
0
5
10
15
20
25
30
200 400 600 800 1000
f - Frequency - MHz
Peak-To-Peak Jitter - ps
VID = 0.3 V VID = 0.8 V
VID = 0.5 V
VCC = 3.3 V
TA = 25°C
VIC= 1.2 V
Input = Clock
0
10
20
30
40
50
60
300 800 1300 1800
Data Rate - Mbps
Peak-To-Peak Jitter - ps
VID = 0.5 V
VID = 0.8 V
2300
VCC = 3.3 V
TA = 25°C
VIC= 1.2 V
Input = PRBS 223-1
VID = 0.3 V
0
5
10
15
20
25
30
200 400 600 800 1000
f - Frequency - MHz
Peak-To-Peak Jitter - ps
VID = 0.3 V
VID = 0.8 V VID = 0.5 V
VCC = 3.3 V
TA = 25°C
VIC = 2.9 V
Input = Clock
0
5
10
15
20
25
30
200 400 600 800 1000
f - Frequency - MHz
Peak-To-Peak Jitter - ps
VID = 0.3 V
VID = 0.8 V VID = 0.5 V
VCC = 3.3 V
TA = 25°C
VIC = 2.9 V
Input = Clock
0
10
20
30
40
50
60
300 800 1300 1800
Data Rate - Mbps
Peak-To-Peak Jitter - ps
VID = 0.3 V
VID = 0.8 V
VID = 0.5 V
VCC = 3.3 V
TA = 25°C
VIC = 2.9 V
Input = PRBS 223-1
2300
SN65LVDS100, SN65LVDT100SN65LVDS101, SN65LVDT101
SLLS516C – AUGUST 2002 – REVISED JUNE 2004
TYPICAL CHARACTERISTICS (continued)
SN65LVDS101 SN65LVDS101 SN65LVDS100PEAK-TO-PEAK JITTER PEAK-TO-PEAK JITTER PEAK-TO-PEAK JITTERvs vs vsFREQUENCY DATA RATE FREQUENCY
Figure 17. Figure 18. Figure 19.
SN65LVDS100 SN65LVDS101 SN65LVDS101PEAK-TO-PEAK JITTER PEAK-TO-PEAK JITTER PEAK-TO-PEAK JITTERvs vs vsDATA RATE FREQUENCY DATA RATE
Figure 20. Figure 21. Figure 22.
SN65LVDS100 SN65LVDS100 SN65LVDS101PEAK-TO-PEAK JITTER PEAK-TO-PEAK JITTER PEAK-TO-PEAK JITTERvs vs vsFREQUENCY DATA RATE FREQUENCY
Figure 23. Figure 24. Figure 25.
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0
10
20
30
40
50
-40 -20 0 20 40 60 80 100
TA - Free-Air Temperature - °C
Peak-To-Peak Jitter - ps
VCC = 3.3 V
VIC = 1.2 V
VID = 200 mV
Input = 2 Gbps 223-1
LVDS100
LVDS101
0
50
100
150
200
250
300
350
400
0 500 1000 1500 2000 2500
0
10
20
30
40
50
60
70
80
f - Frequency - MHz
- Differential Output Voltage - mV
VOD
Period Jitter - ps
Added Random Jitter
VCC = 3.3 V,
VIC = 1.2 V,
|VID| = 200 mV,
TA = 25°C,
Input = Clock
0
10
20
30
40
50
60
300 800 1300 1800
Data Rate - Mbps
Peak-To-Peak Jitter - ps
VID = 0.3 V
VID = 0.8 V
VID = 0.5 V
VCC = 3.3 V
TA = 25°C
VIC = 2.9 V
Input = PRBS 223-1
2300
300
380
460
540
620
700
0 400 800 1200 1600 2000
0
10
20
30
40
50
f - Frequency - MHz
- Differential Output Voltage - mV
VOD
Period Jitter - ps
Added Random Jitter
VCC = 3.3 V,
VIC = 1.2 V,
|VID| = 200 mV,
TA = 25°C,
Input = Clock
0
20
40
60
80
100
0 1000 2000 3000 4000
Data Rate - Mbps
Peak-to-Peak Jitter - ps
VCC = 3.3 V,
VIC = 1.2 V,
|VID| = 200 mV,
TA = 25°C,
Input = PRBS 223-1
0
20
40
60
80
100
0 1000 2000 3000 4000 5000
Data Rate - Mbps
Peak-to-Peak Jitter - ps
VCC = 3.3 V,
VIC = 1.2 V,
|VID| = 200 mV,
TA = 25°C,
Input = PRBS 223-1
SN65LVDS100, SN65LVDT100SN65LVDS101, SN65LVDT101
SLLS516C – AUGUST 2002 – REVISED JUNE 2004
TYPICAL CHARACTERISTICS (continued)
SN65LVDS101 SN65LVDS100 SN65LVDS100PEAK-TO-PEAK JITTER PEAK-TO-PEAK JITTER DIFFERENTIAL OUTPUT VOLTAGEvs vs vsDATA RATE FREE-AIR TEMPERATURE FREQUENCY
Figure 26. Figure 27. Figure 28.
SN65LVDS100 SN65LVDS101 SN65LVDS101PEAK-TO-PEAK JITTER DIFFERENTIAL OUTPUT VOLTAGE PEAK-TO-PEAK JITTERvs vs vsDATA RATE FREQUENCY DATA RATE
Figure 29. Figure 30. Figure 31.
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LVPECL-to-LVDS
Horizontal Scale= 200 ps/div
LVPECL-to-LVDS
Horizontal Scale= 100 ps/div
LVDS-to-LVPECL
Horizontal Scale= 200 ps/div
LVDS-to-LVPECL
Horizontal Scale= 100 ps/div
SN65LVDS100, SN65LVDT100SN65LVDS101, SN65LVDT101
SLLS516C – AUGUST 2002 – REVISED JUNE 2004
TYPICAL CHARACTERISTICS (continued)
SN65LVDS100 SN65LVDS100622 Mbps, 2
23
– 1 PRBS 2 Gbps, 2
23
– 1 PRBS
Figure 32. Figure 33.
SN65LVDS101 SN65LVDS101622 Mbps, 2
23
– 1 PRBS 2 Gbps, 2
23
– 1 PRBS
Figure 34. Figure 35.
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0
-5
-15
-20 0 1 2 3 4 5
Input Voltage Threshold - mV
5
15
20
Common-Mode Input Voltage - V
10
-10
3 V, 85°C
3 V, 85°C
3.6 V, 85°C
3.6 V, 85°C
3.6 V, -40°C
3.6 V, -40°C
3 V, -40°C
3 V, -40°C
VIT+
VIT-
|VOD| = 250 mV,
RL = 100 Ω,
Nominal Process
SN65LVDS100, SN65LVDT100SN65LVDS101, SN65LVDT101
SLLS516C – AUGUST 2002 – REVISED JUNE 2004
TYPICAL CHARACTERISTICS (continued)
NOTE: V
IT
is a steady-state parameter. The switching time is influenced by the input overdrive above this steady-statethreshold up to a differential input voltage magnitude of 100 mV.
Figure 36. SN65LVDS100 Simulated Input Voltage Threshold vsCommon-Mode Input Voltage, Supply Voltage, and Temperature
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APPLICATION INFORMATION
VCC
VEE 50 50
VCC-2 V
SN65LVDS100
100
SN65LVDS100
ECL
LVDS
50 50
SN65LVDT101
LVDS 3.3 v
PECL
VEE 50 50
3 V
SN65LVDS101
50 50
ECL
5 V
3.3 v
PECL
50 50
VTT
SN65LVDS100 or
SN65LVDS101
CML
SN65LVDS100, SN65LVDT100SN65LVDS101, SN65LVDT101
SLLS516C – AUGUST 2002 – REVISED JUNE 2004
The SN65LVDS100, SN65LVDT100, SN65LVDS101, and SN65LVDT101 inputs will detect a 100-mV differencebetween any two signals between 0 V and 4 V, This range will allow receipt of many different single-ended anddifferential signals. Following are some of the more common connections.
Figure 37. PECL-to-LVDS Translation
Figure 38. LVDS-to-3.3 V PECL Translation
Figure 39. 5-V PECL to 3.3-V PECL Translation
Figure 40. CML-to-LVDS or 3.3-V PECL Translation
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LVDS
VEE
SN65LVDS100
50
ECL
3.3 V
VBB
22 k
0.01 F
Z0 = 50 100
* closest standard value
LVDS
100
CMOS
1 V < VDD < 4 V
VDD
SN65LVDS100
VDD/600 A*
VDD/600 A*
0.01 F
* closest standard
value
CMOS
1 V < VDD < 4 V
VDD
SN65LVDS101
VDD/600 A*
VDD/600 A*
0.01 F50 50
3.3 v
PECL
C
C
0.01 F
50
50
22 k
SN65LVDS100 or
SN65LVDS101
VBB
SN65LVDS100, SN65LVDT100SN65LVDS101, SN65LVDT101
SLLS516C – AUGUST 2002 – REVISED JUNE 2004
APPLICATION INFORMATION (continued)
Figure 41. Single-Ended 3.3-V PECL-to-LVDS Translation
Figure 42. Single-Ended CMOS-to-LVDS Translation
Figure 43. Single-Ended CMOS-to-3.3-V PECL Translation
Figure 44. Receipt of AC-Coupled Signals
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FAILSAFE CONSIDERATIONS
1.6 kΩ
1.6 kΩ
100 Ω
3.3 V
SN65LVDS100, SN65LVDT100SN65LVDS101, SN65LVDT101
SLLS516C – AUGUST 2002 – REVISED JUNE 2004
APPLICATION INFORMATION (continued)
Failsafe, in regard to a line receiver, usually means that the output goes to a defined logical state with no inputsignal. To keep added jitter to an absolute minimum, the SN65LVDS100 does not include this feature. It doesexhibit 25 mV of input voltage hysteresis to prevent oscillation and keep the output in the last state prior toinput-signal loss (assuming the differential noise in the system is less than the hysteresis).
Should failsafe be required, it may be added externally with a 1.6-kΩpull-up resistor to the 3.3-V supply and a1.6-kΩpull-down resistor to ground as shown in Figure 45 The default output state is determined by which line ispulled up or down and is the user's choice. The location of the 1.6-kΩresistors is not critical. However the 100-Ωresistor should be located at the end of the transmission line.
Figure 45. External Failsafe Circuit
Addition of this external failsafe will reduce the differential noise margin and add jitter to the output signal. Theroughly 100-mV steady-state voltage generated across the 100-Ωresistor adds (or subtracts) from the signalgenerated by the upstream line driver. If the line driver's differential output is symmetrical about zero volts, thenthe input at the receiver will appear asymmetrical with the external failsafe. Perhaps more important, is the extratime it takes for the input signal to overcome the added failsafe offset voltage.
In Figure 46 and using an external failsafe, the high-level differential voltage at the input of the SN65LVDS100reaches 340 mV and the low-level –400 mV indicating a 60-mV differential offset induced by the external failsafecircuitry. The figure also reveals that the lowest peak-to-peak time jitter does not occur at zero-volt differential(the nominal input threshold of the receiver) but at –60 mV, the failsafe offset.
The added jitter from external failsafe increases as the signal transition times are slowed by cable effects. Whena ten-meter CAT-5 UTP cable is introduced between the driver and receiver, the zero-crossing peak-to-peak jitterat the receiver output adds 250 ps when the external failsafe is added with this specific test set up. If externalfailsafe is used in conjunction with the SN65LVDS100, the noise margin and jitter effects should be budgeted.
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SN65LVDS100, SN65LVDT100SN65LVDS101, SN65LVDT101
SLLS516C – AUGUST 2002 – REVISED JUNE 2004
Figure 46. Receiver Input Eye Pattern With External Failsafe
17
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
SN65LVDS100D ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS100DG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS100DGK ACTIVE VSSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS100DGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS100DGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS100DGKRG4 ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS100DR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS100DRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS101D ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS101DG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS101DGK ACTIVE VSSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS101DGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS101DGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS101DGKRG4 ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS101DR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS101DRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDT100D ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM