PACKAGE DIMENSIONS
1/7/04
Page 1 of 13
© 2004 Fairchild Semiconductor Corporation
HIGH SPEED-10 MBit/s
LOGIC GATE OPTOCOUPLERS
HCPL-0600 HCPL-0601
DESCRIPTION
The HCPL-0600/0601 optocouplers consist of an AlGaAS LED, optically coupled to a very high speed integrated photo-detector
logic gate with a strobable output. The devices are housed in a compact small-outline package. This output features an open
collector, thereby permitting wired OR outputs. The coupled parameters are guaranteed over the temperature range of -40°C to
+85°C. A maximum input signal of 5 mA will provide a minimum output sink current of 13 mA (fan out of 8). An internal noise
shield provides superior common mode rejection of typically 10 kV/µs.
FEATURES
• Compact SO8 package
• Very high speed-10 MBit/s
• Superior CMR-10 kV/µs
• Fan-out of 8 over -40°C to +85°C
• Logic gate output
• Strobable output
• Wired OR-open collector
• U.L. recognized (File # E90700)
APPLICATIONS
• Ground loop elimination
• LSTTL to TTL, LSTTL or
5-volt CMOS
• Line receiver, data transmission
• Data multiplexing
• Switching power supplies
• Pulse transformer replacement
• Computer-peripheral interface
TRUTH T ABLE
(Positive Logic)
A 0.1 µF bypass capacitor must be connected between pins 8 and 5. (See note 1)
Input Enable Output
HHL
LHH
HLH
LLH
HNCL
LNCH
NOTE
All dimensions are in inches (millimeters)
Lead Coplanarity : 0.004 (0.10) MAX
0.202 (5.13)
Pin 1
0.019 (0.48)
0.182 (4.63)
0.021 (0.53)
0.011 (0.28) 0.050 (1.27)
TYP
0.244 (6.19)
0.224 (5.69)
0.143 (3.63)
0.123 (3.13)
0.008 (0.20)
0.003 (0.08)
0.010 (0.25)
0.006 (0.16)
SEATING PLANE
0.164 (4.16)
0.144 (3.66)
1
2
3
4 5
6
7
8
N/C
_
VCC
VE
VO
GND
+
N/C
VF
Single-channel
circuit drawing
HIGH SPEED-10 MBit/s
LOGIC GATE OPTOCOUPLERS
HCPL-0600 HCPL-0601
1/7/04
Page 2 of 13
© 2004 Fairchild Semiconductor Corporation
*6.3 mA is a guard banded value which allows for at least 20% CTR degr adation. Initial input current threshold v alue is 5.0 mA or
less
ABSOLUTE MAXIMUM RATINGS
(No derating required up to 85°C)
Parameter Symbol Value Units
Storage Temperature T
STG
-40 to +125 °C
Operating Temperature T
OPR
-40 to +85 °C
Lead Solder Temperature T
SOL
260 for 10 sec °C
EMITTER
DC/Average Forward Input Current I
F
50 mA
Enable Input Voltage
Not to exceed VCC by more than 500 mV V
E
5.5 V
Reverse Input Voltage V
R
5.0 V
Power Dissipation P
I
45 mW
DETECTOR
Supply Voltage V
CC
(1 minute max) 7.0 V
Output Current I
O
50 mA
Output Voltage V
O
7.0 V
Collector Output Power Dissipation P
O
85 mW
RECOMMENDED OPERATING CONDITIONS
Parameter Symbol Min Max Units
Input Current, Low Level I
FL
0 250 µA
Input Current, High Level I
FH
*6.3 15 mA
Supply Voltage, Output V
CC
4.5 5.5 V
Enable Voltage, Low Level V
EL
0 0.8 V
Enable Voltage, High Level V
EH
2.0 V
CC
V
Operating Temperature T
A
-40 +85 °C
Fan Out (TTL load) N 8
1/7/04
Page 3 of 13
© 2004 Fairchild Semiconductor Corporation
HIGH SPEED-10 MBit/s
LOGIC GATE OPTOCOUPLERS
HCPL-0600 HCPL-0601
ELECTRICAL CHARACTERISTICS
(T
A
= -40°C to +85°C Unless otherwise specified.)
INDIVIDUAL COMPONENT CHARACTERISTICS
Parameter Test Conditions Symbol Min Typ** Max Unit
EMITTER
(I
F
= 10 mA) V
F
1.8 V
Input Forward Voltage T
A
=25°C 1.75
Input Reverse Breakdown Voltage (I
R
= 10 µA) B
VR
5.0 V
Input Capacitance (V
F
= 0, f = 1 MHz) C
IN
60 pF
Input Diode Temperature Coefficient (I
F
= 10 mA)
∆
VF/
∆
TA -1.4 mV/°C
DETECTOR
High Level Supply Current (V
CC
= 5.5 V, I
F
= 0 mA)
(V
E
= 0.5 V) I
CCH
710mA
Low Level Supply Current (V
CC
= 5.5 V, I
F
= 10 mA)
(V
E
= 0.5 V) I
CCL
913mA
Low Level Enable Current (V
CC
= 5.5 V, V
E
= 0.5 V) I
EL
-0.8 -1.6 mA
High Level Enable Current (V
CC
= 5.5 V, V
E
= 2.0 V) I
EH
-0.6 -1.6 mA
High Level Enable Voltage (V
CC
= 5.5 V, I
F
= 10 mA) V
EH
2.0 V
Low Level Enable Voltage (V
CC
= 5.5 V, I
F
= 10 mA) (Note 2) V
EL
0.8 V
SWITCHING CHARA CTERISTICS
(T
A
= -40°C to +85°C, V
CC
= 5 V, I
F
= 7.5 mA Unless otherwise specified.)
AC Characteristics Test Conditions Device Symbol Min Typ Max Unit
Propagation Delay Time
to Output High Level (Note 3) (T
A
=25°C) All T
PLH
20 45 75 ns
(R
L
= 350
Ω
, C
L
= 15 pF) (Fig. 12) 100
Propagation Delay Time
to Output Low Level (Note 4) (T
A
=25°C) All T
PHL
25 45 75 ns
(R
L
= 350
Ω
, C
L
= 15 pF) (Fig. 12) 100
Pulse Width Distortion (R
L
= 350
Ω
, C
L
= 15 pF) (Fig. 12) All |T
PHL
-T
PLH
| 3 35 ns
Output Rise Time
(10-90%) (R
L
= 350
Ω
, C
L
= 15 pF)
(Note 5) (Fig. 12) All t
r
50 ns
Output Fall Time
(90-10%) (R
L
= 350
Ω
, C
L
= 15 pF)
(Note 6) (Fig. 12) All t
f
12 ns
Enable Propagation
Dela y Time
to Output High Level
(I
F
= 7.5 mA, V
EH
= 3.5 V)
(R
L
= 350
Ω
, C
L
= 15 pF)
(Note 7) (Fig. 13) All t
ELH
20 ns
Enable Propagation
Dela y Time
to Output Low Level
(I
F
= 7.5 mA, V
EH
= 3.5 V)
(R
L
= 350
Ω
, C
L
= 15 pF)
(Note 8) (Fig. 13) All t
EHL
20 ns
Common Mode
Transient Immunity
(at Output High Level)
(R
L
= 350
Ω
) (T
A
=25°C)
(I
F
= 0 mA, V
OH
(Min.) = 2.0 V)
(Note 9)(Fig. 14)
|V
CM
| = 10 V HCPL-0600 |CM
H
|10,000 V/µs
|VCM| = 50 V HCPL-0601 5000 10,000
Common Mode
Transient Immunity
(at Output Low Level)
(RL = 350Ω) (TA =25°C)
(IF = 7.5 mA, VOL (Max.) = 0.8 V)
(Note 10)(Fig. 14)
|VCM| = 10 V HCPL-0600 |CMH|10,000 V/µs
|VCM| = 50 V HCPL-0601 5000 10,000
HIGH SPEED-10 MBit/s
LOGIC GATE OPTOCOUPLERS
HCPL-0600 HCPL-0601
1/7/04
Page 4 of 13
© 2004 Fairchild Semiconductor Corporation
** All typical values are at VCC = 5 V, TA = 25°C
1. The VCC supply to each optoisolator must be bypassed by a 0.1µF capacitor or larger. This can be either a ceramic or solid
tantalum capacitor with good high frequency characteristic and should be connected as close as possible to the package VCC
and GND pins of each device.
2. Enable Input - No pull up resistor required as the device has an internal pull up resistor.
3. tPLH - Propagation delay is measured from the 3.75 mA level on the HIGH to LOW transition of the input current pulse to the
1.5V level on the LOW to HIGH transition of the output voltage pulse.
4. tPHL - Propagation delay is measured from the 3.75 mA level on the LOW to HIGH transition of the input current pulse to the
1.5V level on the HIGH to LOW transition of the output voltage pulse.
5. tr - Rise time is measured from the 90% to the 10% levels on the LOW to HIGH transition of the output pulse.
6. tf - Fall time is measured from the 10% to the 90% levels on the HIGH to LOW transition of the output pulse.
7. tELH - Enable input propagation dela y is measured from the 1.5V le v el on the HIGH to LO W transition of the input v oltage pulse
to the 1.5V level on the LOW to HIGH transition of the output voltage pulse.
8. tEHL - Enable input propagation dela y is measured from the 1.5V le v el on the LO W to HIGH transition of the input v oltage pulse
to the 1.5V level on the HIGH to LOW transition of the output voltage pulse.
9. CMH - The maximum tolerable rate of rise of the common mode voltage to ensure the output will remain in the high state (i.e.,
VOUT > 2.0 V). Measured in volts per microsecond (V/µs).
10. CML - The maximum tolerable rate of fall of the common mode voltage to ensure the output will remain in the low output state
(i.e., V OUT < 0.8 V). Measured in volts per microsecond (V/µs).
11. Device considered a two-terminal device: Pins 1,2,3 and 4 shorted together, and Pins 5,6,7 and 8 shorted together.
TRANSFER CHARACTERISTICS (TA = -40°C to +85°C Unless otherwise specified.)
DC Characteristics Test Conditions Symbol Min Typ** Max Unit
High Level Output Current (VCC = 5.5 V, VO = 5.5 V)
(IF = 250 µA, VE = 2.0 V) (Note 2) IOH 100 µA
Low Level Output Voltage (VCC = 5.5 V, IF = 5 mA)
(VE = 2.0 V, IOL = 13 mA) (Note 2) VOL .35 0.6 V
Input Threshold Current (VCC = 5.5 V, VO = 0.6 V,
VE = 2.0 V, IOL = 13 mA) IFT 35mA
ISOLATION CHARACTERISTICS (TA = -40°C to +85°C Unless otherwise specified.)
Characteristics Test Conditions Symbol Min Typ** Max Unit
Input-Output
Insulation Leakage Current
(Relative humidity = 45%)
(TA = 25°C, t = 5 s)
(VI-O = 3000 VDC)
(Note 11)
II-O 1.0* µA
Withstand Insulation Test V oltage (RH < 50%, TA = 25°C)
(Note 11) ( t = 1 min.) VISO 2500 VRMS
Resistance (Input to Output) (VI-O = 500 V) (Note 11) RI-O 1012 Ω
Capacitance (Input to Output) (f = 1 MHz) (Note 11) CI-O 0.6 pF
NOTES
1/7/04
Page 5 of 13
© 2004 Fairchild Semiconductor Corporation
HIGH SPEED-10 MBit/s
LOGIC GATE OPTOCOUPLERS
HCPL-0600 HCPL-0601
TYPICAL PERFORMANCE CURVES
Fig. 1 Forward Current vs. Input Forward Voltage
VF - FORWARD VOLTAGE (V)
IF - FORWARD CURRENT (mA)
Fig. 2 Output Voltage vs. Forward Current
IOH - HIGH LEVEL OUTPUT CURRENT (µA)
ITH - INPUT THRESHOLD CURRENT (mA)
Fig. 3 Input Threshold Current vs. Temperature
TA - TEMPERATURE (˚C) TA - TEMPERATURE (˚C)
Fig. 4 High Level Output Current vs. Temperature
IF - FORWARD INPUT CURRENT (mA)
Vo - OUTPUT VOLTAGE (V)
0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7
0.001
0.01
0.1
1
10
100
TA = 85°C
TA = 70°C
TA = 25°C
TA = 0°C
TA = -40°C
012345
0
1
2
3
4
5
6
TA = 25¡C
VCC = 5V
RL = 350Ω
RL = 1kΩ
-40-20 0 20406080100
0
1
2
3
4
5
VCC = 5V
VO = 0.6V
RL = 350Ω
RL = 1KΩ
-40-200 20406080100
0
2
4
6
8
10
12
14
16
VO = VCC = 5.5V
VE = 2V
IF = 250 A
HIGH SPEED-10 MBit/s
LOGIC GATE OPTOCOUPLERS
HCPL-0600 HCPL-0601
1/7/04
Page 6 of 13
© 2004 Fairchild Semiconductor Corporation
Fig. 5 Low Level Output Voltage vs. Temperature
TA - TEMPERATURE (˚C)
TA - TEMPERATURE (˚C)
TA - TEMPERATURE (˚C)
VOL - LOW LEVEL OUTPUT VOLTAGE (V)
TP - PROPAGATION DELAY (ns)
Fig. 6 Low Level Output Current vs. Temperature
IOL - LOW LEVEL OUTPUT CURRENT (mA)
TP - PROPAGATION DELAY (ns)
Fig. 7 Propagation Delay vs. Temperature Fig. 8 Propagation Delay vs. Pulse Input Current
IF - PULSE INPUT CURRENT (mA)
-40-200 20406080100
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8 VCC = 5.5V
VE = 2V
IF = 5mA
IO = 12.8mA
IO = 9.6mA
IO = 6.4mA
IO = 16mA
-40-200 20406080100
20
25
30
35
40
45
50
55
60 VCC = 5V
VE = 2V
VOL = 0.6V
IF = 10-15mA
IF = 5mA
-40-200 20406080100
20
30
40
50
60
70
80
90
100 VCC = 5V
IF = 7.5mA
tPLH
RL = 1kΩ
tPLH
RL = 350Ω
tPHL
RL = 350Ω & 1kΩ
5 7 9 11 13 15
20
30
40
50
60
70
80
90 VCC = 5V
TA = 25°C
tPLH
RL = 1kΩ
tPLH
RL = 350Ω
tPHL
RL = 350Ω & 1kΩ
1/7/04
Page 7 of 13
© 2004 Fairchild Semiconductor Corporation
HIGH SPEED-10 MBit/s
LOGIC GATE OPTOCOUPLERS
HCPL-0600 HCPL-0601
Fig. 9 Typical Enable Propagation Delay vs. Temparature
TA - TEMPERATURE (˚C) TA - TEMPERATURE (˚C)
TA - TEMPERATURE (˚C)
tE - ENABLE PROPAGATION DELAY (ns)
Fig. 10 Typical Rise and Fall Time vs. Temperature
tf - F ALL TIME (ns)
Fig. 11 Typical Pulse Width Distortion vs. Temperature
PWD - PULSE WIDTH DISTORTION (ns)
-40-200 20406080100
0
10
20
30
40
50
60
70
80
90 VCC = 5V
VEH = 3V
VEL = 0V
IF = 7.5mA tELH
RL = 1kΩ
tELH
RL = 350Ω
tEHL
RL = 350Ω & 1kΩ
-40-200 20406080100
0
40
80
120
160
200
240 VCC = 5V
IF = 7.5mA
tr
RL = 1kΩ
tr
RL = 350Ω
tf
RL = 350Ω & 1kΩ
-40-200 20406080100
0
5
10
15
20
25
30
35
40 VCC = 5V
IF = 7.5mA
RL = 1kΩ
RL = 350Ω
HIGH SPEED-10 MBit/s
LOGIC GATE OPTOCOUPLERS
HCPL-0600 HCPL-0601
1/7/04
Page 8 of 13
© 2004 Fairchild Semiconductor Corporation
47Ω
PHL
t
F
I = 7.5 mA
1.5 V
90%
10%
7.5 mA
+5V
1.5 V
3.0 V
1.5 V
3
2
1
4
8
7
6
5
4 5
Pulse
1
2
3
Generator
tr = 5ns
Z = 50Ω
O
8
7
6
+5V
GND
PLH
t
I = 3.75 mA
F
Output
O
(V )
Input
(I )
F
Output
(V )
O
f
t
r
t
CC
V
Output
(V )
O
L
R
C
L
(I )
Input
F
Monitor
O
Z = 50Ω
Puls
e
Gen
e
r
a
t
o
r
tr =
5n
s(V )
E
In
p
u
t
M
n
o
r
GND
V
CC
O
(V )
Output
L
R
L
C
(V )
Output
O
Input
(V )
E
EHL
t
ELH
bypass
.1 f
bypass
.1µf
Fig. 12 T
est Circuit and W
T
est Circuit and W
T
a
v
e
f
o
rm
s
f
o
r
t
PLH
,
t
PHL
,
t
r
a
n
d
t
f
.
Fig. 13 T
est Circuit t
T
est Circuit t
T
EHL
a
n
d
t
ELH
.
t
1/7/04
Page 9 of 13
© 2004 Fairchild Semiconductor Corporation
HIGH SPEED-10 MBit/s
LOGIC GATE OPTOCOUPLERS
HCPL-0600 HCPL-0601
+5V
Peak
3
2
1
4
8
7
6
5
GND
V
CC
O
(V )
Output
350Ω
V
CM
FF
V
A
B
Pulse Gen
I
F
CM
V
0V
O
V
5V Switching Pos. (A), I = 0
F
O
V (Max)
CM
0.5 V
O
VSwitching Pos. (B), I = 7.5 mA
F
H
CM
L
V (Min)
O
bypass
.1
µf
Fig. 14 T
est Circuit Common Mode T
T
est Circuit Common Mode T
T
ransient Immunit
y
HIGH SPEED-10 MBit/s
LOGIC GATE OPTOCOUPLERS
HCPL-0600 HCPL-0601
1/7/04
Page 10 of 13
© 2004 Fairchild Semiconductor Corporation
8-Pin Small Outline
0.024 (0.61)
0.050 (1.27)
0.155 (3.94)
0.275 (6.99)
0.060 (1.52)
1/7/04
Page 11 of 13
© 2004 Fairchild Semiconductor Corporation
HIGH SPEED-10 MBit/s
LOGIC GATE OPTOCOUPLERS
HCPL-0600 HCPL-0601
MARKING INFORMATION
ORDERING INFORMATION
Option Order
Entry
Identifier Description
R1 .R1 Tape and Reel (500 per Reel)
R2 .R2 Tape and Reel (2500 per Reel)
1
2
6
43 5
Definitions
1 Fairchild logo
2 Device number
3VDE mark (Note: Only appears on parts ordered with VDE
option – See order entry table)
4 One digit year code, e.g., ‘3’
5 Two digit work week ranging from ‘01’ to ‘53’
6 Assembly package code
0600
SYYXV
HIGH SPEED-10 MBit/s
LOGIC GATE OPTOCOUPLERS
HCPL-0600 HCPL-0601
1/7/04
Page 12 of 13
© 2004 Fairchild Semiconductor Corporation
Carrier T ape Specifications
Reflow Profile
4.0 ± 0.1
Ø1.5 MIN
User Direction of Feed
2 ± 0.05
1.75 ± 0.10
5.5 ± 0.05
12.0 ± 0.3
8.0 ± 0.1
0.3 MAX
8.3 ± 0.1
3.5 ± 0.2
0.1 MAX6.4 ± 0.2
5.2 ± 0.2
Ø1.5 + 0.1/-0
Ramp up = 2–10°C/sec • Peak reflow temperature: 245°C (package surface temperature)
• Time of temperature higher than 183°C for 120–180 seconds
• One time soldering reflow is recommended
230°C, 10–30 s
Time (Minute)
0
300
250
200
150
100
50
00.5 1 1.5 2 2.5 3 3.5 4 4.5
Temperature (°C)
Time above 183°C, 120–180 sec
245°C peak
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body, or
(b) support or sustain life, and (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in a significant injury of the user.
2. A critical component in any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO
ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME
ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
1/7/04
Page 13 of 13
© 2004 Fairchild Semiconductor Corporation
HIGH SPEED-10 MBit/s
LOGIC GATE OPTOCOUPLERS
HCPL-0600 HCPL-0601