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LMV431
,
LMV431A
,
LMV431B
SNVS041G –MAY 2004–REVISED SEPTEMBER 2014
LMV431x Low-Voltage (1.24-V) Adjustable Precision Shunt Regulators
1 Features 3 Description
The LMV431, LMV431A and LMV431B are precision
1• Low-Voltage Operation/Wide Adjust Range 1.24 V shunt regulators capable of adjustment to 30
(1.24 V/30 V) V. Negative feedback from the cathode to the adjust
• 0.5% Initial Tolerance (LMV431B) pin controls the cathode voltage, much like a non-
• Temperature Compensated for Industrial inverting op amp configuration (Refer to Symbol and
Functional Diagrams). A two-resistor voltage divider
Temperature Range (39 PPM/°C for the terminated at the adjust pin controls the gain of a
LMV431AI) 1.24 V band-gap reference. Shorting the cathode to
• Low Operation Current (55 µA) the adjust pin (voltage follower) provides a cathode
• Low Output Impedance (0.25 Ω)voltage of a 1.24 V.
• Fast Turn-On Response The LMV431, LMV431A and LMV431B have
• Low Cost respective initial tolerances of 1.5%, 1%, and 0.5%,
and functionally lend themselves to several
2 Applications applications that require zener diode type
performance at low voltages. Applications include a 3
• Shunt Regulator V to 2.7 V low drop-out regulator, an error amplifier in
• Series Regulator a 3 V off-line switching regulator and even as a
• Current Source or Sink voltage detector. These parts are typically stable with
capacitive loads greater than 10 nF and less than 50
• Voltage Monitor pF.
• Error Amplifier The LMV431, LMV431A and LMV431B provide
• 3-V Off-Line Switching Regulator performance at a competitive price.
• Low Dropout N-Channel Series Regulator Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
LMV431 SOT-23 (5) 2.90 mm x 1.60 mm
LMV431 TO-92 (3) 4.30 mm x 4.30 mm
LMV431 SOT-23 (3) 2.92 mm x 1.30 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
4 Symbol and Functional Diagrams
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMV431
,
LMV431A
,
LMV431B
SNVS041G –MAY 2004–REVISED SEPTEMBER 2014
www.ti.com
Table of Contents
7.9 LMV431BC Electrical Characteristics ....................... 9
1 Features.................................................................. 17.10 LMV431BI Electrical Characteristics..................... 10
2 Applications ........................................................... 17.11 Typical Performance Characteristics .................... 11
3 Description............................................................. 18 Detailed Description............................................ 15
4 Symbol and Functional Diagrams........................ 18.1 Functional Block Diagram....................................... 15
5 Revision History..................................................... 29 Application and Implementation ........................ 16
6 Pin Configurations and Functions....................... 39.1 Typical Application ................................................. 16
7 Specifications......................................................... 49.2 DC/AC Test Circuit.................................................. 18
7.1 Absolute Maximum Ratings ...................................... 410 Device and Documentation Support................. 18
7.2 Handling Ratings ...................................................... 410.1 Documentation Support ....................................... 18
7.3 Recommended Operating Conditions....................... 410.2 Trademarks........................................................... 18
7.4 Thermal Information.................................................. 410.3 Electrostatic Discharge Caution............................ 18
7.5 LMV431C Electrical Characteristics.......................... 510.4 Glossary................................................................ 19
7.6 LMV431I Electrical Characteristics ........................... 611 Mechanical, Packaging, and Orderable
7.7 LMV431AC Electrical Characteristics ..................... 7Information ........................................................... 19
7.8 LMV431AI Electrical Characteristics......................... 8
5 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (May 2005) to Revision G Page
• Changed formatting to match new TI datasheet guidelines; added Device Information and Handling Ratings tables,
Layout, and Device and Documentation Support sections; reformatted Detailed Description and Application and
Implementation sections. ....................................................................................................................................................... 1
• Added spec............................................................................................................................................................................. 4
2Submit Documentation Feedback Copyright © 2004–2014, Texas Instruments Incorporated
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REF CATHODE
ANODE
LMV431
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LMV431A
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LMV431B
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SNVS041G –MAY 2004–REVISED SEPTEMBER 2014
6 Pin Configurations and Functions
TO-92: Plastic Package SOT-23
Top View Top View
SOT-23
Top View
*Pin 1 is not internally connected.
*Pin 2 is internally connected to Anode pin. Pin 2 should be either floating or connected to Anode pin.
Copyright © 2004–2014, Texas Instruments Incorporated Submit Documentation Feedback 3
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LMV431
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SNVS041G –MAY 2004–REVISED SEPTEMBER 2014
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
Industrial (LMV431AI, LMV431I) −40 85
Operating temperature Commercial (LMV431AC, LMV431C, LMV431BC) 0 70 °C
Lead temperature TO-92 Package/SOT-23 -5,-3 Package 265
(Soldering, 10 sec.)
Internal power dissipation(2) TO-92 0.78 W
SOT-23-5, -3 Package 0.28 W
Cathode voltage 35 V
Continuous cathode current −30 30 mA
Reference input current −.05 3
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Ratings apply to ambient temperature at 25°C. Above this temperature, derate the TO-92 at 6.2 mW/°C, and the SOT-23-5 at 2.2
mW/°C. See derating curve in Operating Condition section.
7.2 Handling Ratings MIN MAX UNIT
Tstg Storage temperature range −65 150 °C
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all 2000
V(ESD) Electrostatic discharge V
pins(1)
(1) The human body model is a 100 pF capacitor discharged through a 1.5kΩresistor into each pin. The machine model is a 200 pF
capacitor discharged directly into each pin. MIL-STD-883 3015.7.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT
Cathode voltage VREF 30 V
Cathode current 0.1 15 mA
Temperature LMV431AI −40 85 °C
Derating Curve (Slope = −1/RθJA)
7.4 Thermal Information LMV431 LMV431 LMV431
THERMAL METRIC(1) SOT-23 SOT-23 TO-92 UNIT
3 PINS 5 PINS 3 PINS
RθJA Junction-to-ambient thermal resistance (2) 455 455 161 °C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) TJ Max = 150°C, TJ= TA+ (RθJA PD), where PDis the operating power of the device.
4Submit Documentation Feedback Copyright © 2004–2014, Texas Instruments Incorporated
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LMV431
,
LMV431A
,
LMV431B
www.ti.com
SNVS041G –MAY 2004–REVISED SEPTEMBER 2014
7.5 LMV431C Electrical Characteristics
TA= 25°C unless otherwise specified
SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TA= 25°C 1.222 1.24 1.258
VZ= VREF, IZ= 10 mA
VREF Reference Voltage V
(See Figure 32 )TA= Full Range 1.21 1.27
Deviation of Reference Input Voltage VZ= VREF, IZ= 10 mA,
VDEV 4 12 mV
Over Temperature(1) TA= Full Range (See Figure 32)
Ratio of the Change in Reference IZ= 10 mA (see Figure 33 )
Voltage to the Change in Cathode VZfrom VREF to 6 V −1.5 −2.7 mV/V
Voltage R1= 10 kΩ, R2=∞and 2.6 kΩ
R1= 10 kΩ, R2=∞
IREF Reference Input Current 0.15 0.5 μA
II= 10 mA (see Figure 33)
Deviation of Reference Input Current R1= 10 kΩ, R2=∞,
∝IREF 0.05 0.3 μA
over Temperature II= 10 mA, TA= Full Range (see Figure 33)
Minimum Cathode Current for
IZ(MIN) VZ= VREF(see Figure 32)55 80 µA
Regulation
IZ(OFF) Off-State Current VZ= 6 V, VREF = 0 V (see Figure 34 )0.001 0.1 μA
VZ= VREF, IZ= 0.1 mA to 15 mA
rZDynamic Output Impedance(2) 0.25 0.4 Ω
Frequency = 0 Hz (see Figure 32)
(1) Deviation of reference input voltage, VDEV, is defined as the maximum variation of the reference input voltage over the full temperature
range. See the following:
The average temperature coefficient of the reference input voltage, ∝VREF, is defined as:
Where: T2−T1= full temperature change. ∝VREF can be positive or negative depending on whether the slope is positive or negative.
Example: VDEV = 6 mV, VREF = 1240 mV, T2−T1= 125°C.
(2) The dynamic output impedance, rZ, is defined as:
When the device is programmed with two external resistors, R1 and R2, (see Figure 33 ), the dynamic output impedance of the overall
circuit, rZ, is defined as:
Copyright © 2004–2014, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Links: LMV431 LMV431A LMV431B
Z
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6.0 mV 10
1240 mV
V 39 ppm / C
125 C
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q
6 6
Max Min DEV
REF REF
REF 2 1 2 1
V V V
10 10
V (at 25 C) V (at 25 C)
ppm
VC T T T T
§ · § ·
r r
¨ ¸ ¨ ¸
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LMV431
,
LMV431A
,
LMV431B
SNVS041G –MAY 2004–REVISED SEPTEMBER 2014
www.ti.com
7.6 LMV431I Electrical Characteristics
TA= 25°C unless otherwise specified
SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VREF Reference Voltage VZ= VREF, IZ= 10 mA TA= 25°C 1.222 1.24 1.258
(See Figure 32 )V
TA= Full 1.202 1.278
Range
VDEV Deviation of Reference Input Voltage VZ= VREF, IZ= 10 mA, 6 20 mV
Over Temperature(1) TA= Full Range (See Figure 32)
Ratio of the Change in Reference IZ= 10mA (see Figure 33 )
Voltage to the Change in Cathode VZfrom VREF to 6V −1.5 −2.7 mV/V
Voltage R1= 10 kΩ, R2=∞and 2.6kΩ
IREF Reference Input Current R1= 10 kΩ, R2=∞0.15 0.5 μA
II= 10 mA (see Figure 33)
∝IREF Deviation of Reference Input Current R1= 10 kΩ, R2=∞,0.1 0.4 μA
over Temperature II= 10 mA, TA= Full Range (see Figure 33)
IZ(MIN) Minimum Cathode Current for VZ= VREF(see Figure 32)55 80 µA
Regulation
IZ(OFF) Off-State Current VZ= 6 V, VREF = 0V (see Figure 34 )0.001 0.1 μA
rZDynamic Output Impedance(2) VZ= VREF, IZ= 0.1 mA to 15 mA 0.25 0.4 Ω
Frequency = 0 Hz (see Figure 32)
(1) Deviation of reference input voltage, VDEV, is defined as the maximum variation of the reference input voltage over the full temperature
range. See the following:
The average temperature coefficient of the reference input voltage, ∝VREF, is defined as:
Where: T2−T1= full temperature change. ∝VREF can be positive or negative depending on whether the slope is positive or negative.
Example: VDEV = 6 mV, VREF = 1240 mV, T2−T1= 125°C.
(2) The dynamic output impedance, rZ, is defined as:
When the device is programmed with two external resistors, R1 and R2, (see Figure 33 ), the dynamic output impedance of the overall
circuit, rZ, is defined as:
6Submit Documentation Feedback Copyright © 2004–2014, Texas Instruments Incorporated
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Z
Z Z
Z
VR1
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I R2
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6.0 mV 10
1240 mV
V 39 ppm / C
125 C
§ ·
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6 6
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REF REF
REF 2 1 2 1
V V V
10 10
V (at 25 C) V (at 25 C)
ppm
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LMV431
,
LMV431A
,
LMV431B
www.ti.com
SNVS041G –MAY 2004–REVISED SEPTEMBER 2014
7.7 LMV431AC Electrical Characteristics
TA= 25°C unless otherwise specified
SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VREF Reference Voltage VZ= VREF, IZ= 10 mA TA= 25°C 1.228 1.24 1.252 V
(See Figure 32 )TA= Full Range 1.221 1.259
Deviation of Reference Input Voltage Over VZ= VREF, IZ= 10 mA,
VDEV 4 12 mV
Temperature(1) TA= Full Range (See Figure 32)
IZ= 10 mA (see Figure 33 )
Ratio of the Change in Reference Voltage VZfrom VREF to 6 V −1.5 −2.7 mV/V
to the Change in Cathode Voltage R1= 10 kΩ, R2=∞and 2.6 kΩ
R1= 1 kΩ, R2=∞
IREF Reference Input Current 0.15 0.50 μA
II= 10 mA (see Figure 33)
Deviation of Reference Input Current over R1= 10 kΩ, R2=∞,
∝IREF 0.05 0.3 μA
Temperature II= 10 mA, TA= Full Range (see Figure 33)
IZ(MIN) Minimum Cathode Current for Regulation VZ= VREF(see Figure 32)55 80 µA
IZ(OFF) Off-State Current VZ= 6 V, VREF = 0V (see Figure 34 )0.001 0.1 μA
VZ= VREF, IZ= 0.1mA to 15mA
rZDynamic Output Impedance(2) 0.25 0.4 Ω
Frequency = 0 Hz (see Figure 32)
(1) Deviation of reference input voltage, VDEV, is defined as the maximum variation of the reference input voltage over the full temperature
range. See the following:
The average temperature coefficient of the reference input voltage, ∝VREF, is defined as:
Where: T2−T1= full temperature change. ∝VREF can be positive or negative depending on whether the slope is positive or negative.
Example: VDEV = 6 mV, VREF = 1240 mV, T2−T1= 125°C.
(2) The dynamic output impedance, rZ, is defined as:
When the device is programmed with two external resistors, R1 and R2, (see Figure 33 ), the dynamic output impedance of the overall
circuit, rZ, is defined as:
Copyright © 2004–2014, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Links: LMV431 LMV431A LMV431B
Z
Z Z
Z
VR1
r r 1
I R2
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1240 mV
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125 C
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REF 2 1 2 1
V V V
10 10
V (at 25 C) V (at 25 C)
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LMV431
,
LMV431A
,
LMV431B
SNVS041G –MAY 2004–REVISED SEPTEMBER 2014
www.ti.com
7.8 LMV431AI Electrical Characteristics
TA= 25°C unless otherwise specified
SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TA= 25°C 1.228 1.24 1.252 V
VZ= VREF, IZ= 10mA
VREF Reference Voltage (See Figure 32 )TA= Full Range 1.215 1.265 V
Deviation of Reference Input Voltage Over VZ= VREF, IZ= 10mA,
VDEV 6 20 mV
Temperature(1) TA= Full Range (See Figure 32)
IZ= 10mA (see Figure 33 )
Ratio of the Change in Reference Voltage VZfrom VREF to 6 V −1.5 −2.7 mV/V
to the Change in Cathode Voltage R1= 10 kΩ, R2=∞and 2.6 kΩ
R1= 10 kΩ, R2=∞
IREF Reference Input Current 0.15 0.5 μA
II= 10 mA (see Figure 33)
Deviation of Reference Input Current over R1= 10 kΩ, R2=∞,
∝IREF 0.1 0.4 μA
Temperature II= 10 mA, TA= Full Range (see Figure 33)
IZ(MIN) Minimum Cathode Current for Regulation VZ= VREF(see Figure 32)55 80 µA
IZ(OFF) Off-State Current VZ= 6 V, VREF = 0 V (see Figure 34 )0.001 0.1 μA
VZ= VREF, IZ= 0.1 mA to 15 mA
rZDynamic Output Impedance(2) 0.25 0.4 Ω
Frequency = 0 Hz (see Figure 32)
(1) Deviation of reference input voltage, VDEV, is defined as the maximum variation of the reference input voltage over the full temperature
range. See the following:
The average temperature coefficient of the reference input voltage, ∝VREF, is defined as:
Where: T2−T1= full temperature change. ∝VREF can be positive or negative depending on whether the slope is positive or negative.
Example: VDEV = 6 mV, VREF = 1240 mV, T2−T1= 125°C.
(2) The dynamic output impedance, rZ, is defined as:
When the device is programmed with two external resistors, R1 and R2, (see Figure 33 ), the dynamic output impedance of the overall
circuit, rZ, is defined as:
8Submit Documentation Feedback Copyright © 2004–2014, Texas Instruments Incorporated
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Z
Z Z
Z
VR1
r r 1
I R2
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6
REF
6.0 mV 10
1240 mV
V 39 ppm / C
125 C
§ ·
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q
6 6
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REF REF
REF 2 1 2 1
V V V
10 10
V (at 25 C) V (at 25 C)
ppm
VC T T T T
§ · § ·
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q q
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LMV431
,
LMV431A
,
LMV431B
www.ti.com
SNVS041G –MAY 2004–REVISED SEPTEMBER 2014
7.9 LMV431BC Electrical Characteristics
TA= 25°C unless otherwise specified
SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TA= 25°C 1.234 1.24 1.246 V
VZ= VREF, IZ= 10 mA
VREF Reference Voltage (See Figure 32 )TA= Full Range 1.227 1.253 V
Deviation of Reference Input Voltage Over VZ= VREF, IZ= 10 mA,
VDEV 4 12 mV
Temperature(1) TA= Full Range (See Figure 32)
IZ= 10 mA (see Figure 33 )
Ratio of the Change in Reference Voltage VZfrom VREF to 6 V −1.5 −2.7 mV/V
to the Change in Cathode Voltage R1= 10 kΩ, R2=∞and 2.6 kΩ
R1= 10 kΩ, R2=∞
IREF Reference Input Current 0.15 0.50 μA
II= 10 mA (see Figure 33)
Deviation of Reference Input Current over R1= 10 kΩ, R2=∞,
∝IREF 0.05 0.3 μA
Temperature II= 10 mA, TA= Full Range (see Figure 33)
IZ(MIN) Minimum Cathode Current for Regulation VZ= VREF(see Figure 32)55 80 µA
IZ(OFF) Off-State Current VZ= 6 V, VREF = 0V (see Figure 34 )0.001 0.1 μA
VZ= VREF, IZ= 0.1mA to 15mA
rZDynamic Output Impedance(2) 0.25 0.4 Ω
Frequency = 0 Hz (see Figure 32)
(1) Deviation of reference input voltage, VDEV, is defined as the maximum variation of the reference input voltage over the full temperature
range. See the following:
The average temperature coefficient of the reference input voltage, ∝VREF, is defined as:
Where: T2−T1= full temperature change. ∝VREF can be positive or negative depending on whether the slope is positive or negative.
Example: VDEV = 6 mV, VREF = 1240 mV, T2−T1= 125°C.
(2) The dynamic output impedance, rZ, is defined as:
When the device is programmed with two external resistors, R1 and R2, (see Figure 33 ), the dynamic output impedance of the overall
circuit, rZ, is defined as:
Copyright © 2004–2014, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Links: LMV431 LMV431A LMV431B
Z
Z Z
Z
VR1
r r 1
I R2
'ª º
§ ·
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rI
'
'
6
REF
6.0 mV 10
1240 mV
V 39 ppm / C
125 C
§ ·
¨ ¸
© ¹
v q
q
6 6
Max Min DEV
REF REF
REF 2 1 2 1
V V V
10 10
V (at 25 C) V (at 25 C)
ppm
VC T T T T
§ · § ·
r r
¨ ¸ ¨ ¸
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© ¹ © ¹
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q
REF
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VV
'
'
LMV431
,
LMV431A
,
LMV431B
SNVS041G –MAY 2004–REVISED SEPTEMBER 2014
www.ti.com
7.10 LMV431BI Electrical Characteristics
TA= 25°C unless otherwise specified
SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TA= 25°C 1.234 1.24 1.246 V
VZ= VREF, IZ= 10 mA
VREF Reference Voltage (See Figure 32 )TA= Full Range 1.224 1.259 V
Deviation of Reference Input Voltage Over VZ= VREF, IZ= 10 mA,
VDEV 6 20 mV
Temperature(1) TA= Full Range (See Figure 32)
IZ= 10 mA (see Figure 33 )
Ratio of the Change in Reference Voltage VZfrom VREF to 6V −1.5 −2.7 mV/V
to the Change in Cathode Voltage R1= 10 kΩ, R2=∞and 2.6 kΩ
R1= 10 kΩ, R2=∞
IREF Reference Input Current 0.15 0.50 μA
II= 10 mA (see Figure 33)
Deviation of Reference Input Current over R1= 10 kΩ, R2=∞,
∝IREF 0.1 0.4 μA
Temperature II= 10 mA, TA= Full Range (see Figure 33)
IZ(MIN) Minimum Cathode Current for Regulation VZ= VREF(see Figure 32)55 80 µA
IZ(OFF) Off-State Current VZ= 6 V, VREF = 0 V (see Figure 34 )0.001 0.1 μA
VZ= VREF, IZ= 0.1 mA to 15 mA
rZDynamic Output Impedance(2) 0.25 0.4 Ω
Frequency = 0 Hz (see Figure 32)
(1) Deviation of reference input voltage, VDEV, is defined as the maximum variation of the reference input voltage over the full temperature
range. See the following:
The average temperature coefficient of the reference input voltage, ∝VREF, is defined as:
Where: T2−T1= full temperature change. ∝VREF can be positive or negative depending on whether the slope is positive or negative.
Example: VDEV = 6 mV, VREF = 1240 mV, T2−T1= 125°C.
(2) The dynamic output impedance, rZ, is defined as:
When the device is programmed with two external resistors, R1 and R2, (see Figure 33 ), the dynamic output impedance of the overall
circuit, rZ, is defined as:
10 Submit Documentation Feedback Copyright © 2004–2014, Texas Instruments Incorporated
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,
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,
LMV431B
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SNVS041G –MAY 2004–REVISED SEPTEMBER 2014
7.11 Typical Performance Characteristics
Figure 1. Reference Voltage vs. Junction Temperature Figure 2. Reference Input Current vs. Junction Temperature
Figure 4. Cathode Current vs. Cathode Voltage 2
Figure 3. Cathode Current vs. Cathode Voltage 1
Figure 6. Delta Reference Voltage Per Delta Cathode Voltage
Figure 5. Off-State Cathode Current vs. Junction vs. Junction Temperature
Temperature
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Typical Performance Characteristics (continued)
Figure 7. Input Voltage Noise vs. Frequency Figure 8. Test Circuit For Input Voltage Noise vs. Frequency
BW = 0.1 Hz To 10 Hz
Figure 9. Low Frequency Peak To Peak Noise Figure 10. Test Circuit For Peak To Peak Noise
Figure 12. Test Circuit For Voltage Gain And Phase Shift vs.
Figure 11. Small Signal Voltage Gain And Phase Shift vs. Frequency
Frequency
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Typical Performance Characteristics (continued)
Figure 14. Test Circuit For Reference Impedance vs.
Figure 13. Reference Impedance vs. Frequency Frequency
Figure 16. Test Circuit For Pulse Response 1
Figure 15. Pulse Response 1
Figure 18. Test Circuit For Pulse Response 2
Figure 17. Pulse Response 2
Copyright © 2004–2014, Texas Instruments Incorporated Submit Documentation Feedback 13
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150:
IZ
VZ
CLVSUPPLY
+
-
R1
10k:
R2
0.001 0.01 0.1 1 10
LOAD CAPACITANCE CL (nF)
0
3
6
9
12
15
CATHODE CURRENT IZ (mA)
10k
100 1k
STABLE
STABLE
TA = 25°C
IZ = 15mA
UNSTABLE
REGION
VZ=3V
VZ=2V
FOR VZ = VREF, STABLE FOR CL = 1pF
TO 10k nF
150:
IZ
VZ
CLVSUPPLY
+
-
LMV431
,
LMV431A
,
LMV431B
SNVS041G –MAY 2004–REVISED SEPTEMBER 2014
www.ti.com
Typical Performance Characteristics (continued)
Figure 19. LMV431 Stability Boundary Condition Figure 20. Test Circuit For VZ= VREF
Extrapolated from life-test data taken at 125°C; the activation
energy assumed is 0.7eV.
Figure 22. Percentage Change In VREF vs.
Figure 21. Test Circuit For VZ= 2V, 3V Operating Life At 55°C
14 Submit Documentation Feedback Copyright © 2004–2014, Texas Instruments Incorporated
Product Folder Links: LMV431 LMV431A LMV431B
O REF
R1
V 1 V
R2
§ ·
|
¨ ¸
© ¹
LIMIT REF
R1
V 1 V
R2
§ ·
|
¨ ¸
© ¹
O REF
OMIN REF
R1
V 1 V
R2
V V 5 V
§ ·
¨ ¸
© ¹
O REF
R1
V 1 V
R2
§ ·
|
¨ ¸
© ¹
LMV431
,
LMV431A
,
LMV431B
SNVS041G –MAY 2004–REVISED SEPTEMBER 2014
www.ti.com
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Typical Application
Figure 23. Series Regulator Figure 24. Output Control of a Three-Terminal
Fixed Regulator
Figure 26. Crow Bar
Figure 25. Higher Current Shunt Regulator
16 Submit Documentation Feedback Copyright © 2004–2014, Texas Instruments Incorporated
Product Folder Links: LMV431 LMV431A LMV431B
REF
V
DELAY R C n(V ) V
Ü
REF
OCL
V
IR
REF BE
REF
R1B
LOW LIMIT V 1 V
R2B
R1A
HIGHLIMIT V 1 R2A
§ ·
|
¨ ¸
© ¹
§ ·
|
¨ ¸
© ¹
REF
REF
R1B
LOW LIMIT V 1 R2B
R1A
HIGHLIMIT V 1 R2A
§ ·
|
¨ ¸
© ¹
§ ·
|
¨ ¸
© ¹
LED ON WHEN
LOW LIMIT V HIGH LIMIT
LMV431
,
LMV431A
,
LMV431B
www.ti.com
SNVS041G –MAY 2004–REVISED SEPTEMBER 2014
Typical Application (continued)
Figure 28. Voltage Monitor
Figure 27. Overvoltage/Undervoltage Protection Circuit
Figure 29. Delay Timer Figure 30. Current Limiter or Current Source
Figure 31. Constant Current Sink
Copyright © 2004–2014, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links: LMV431 LMV431A LMV431B
LMV431
,
LMV431A
,
LMV431B
SNVS041G –MAY 2004–REVISED SEPTEMBER 2014
www.ti.com
9.2 DC/AC Test Circuit
Figure 33. Test Circuit For VZ> VREF
Figure 32. Test Circuit For VZ= VREF
Figure 34. Test Circuit For Off-State Current
10 Device and Documentation Support
10.1 Documentation Support
10.1.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 1. Related Links
TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER SAMPLE & BUY DOCUMENTS SOFTWARE COMMUNITY
LMV431 Click here Click here Click here Click here Click here
LMV431A Click here Click here Click here Click here Click here
LMV431B Click here Click here Click here Click here Click here
10.2 Trademarks
All trademarks are the property of their respective owners.
10.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
18 Submit Documentation Feedback Copyright © 2004–2014, Texas Instruments Incorporated
Product Folder Links: LMV431 LMV431A LMV431B
LMV431
,
LMV431A
,
LMV431B
www.ti.com
SNVS041G –MAY 2004–REVISED SEPTEMBER 2014
10.4 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2004–2014, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Links: LMV431 LMV431A LMV431B
PACKAGE OPTION ADDENDUM
www.ti.com 23-Jun-2017
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LMV431ACM5 NRND SOT-23 DBV 5 1000 TBD Call TI Call TI 0 to 70 N09A
LMV431ACM5/NOPB ACTIVE SOT-23 DBV 5 1000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM 0 to 70 N09A
LMV431ACM5X/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM 0 to 70 N09A
LMV431AIM5 NRND SOT-23 DBV 5 1000 TBD Call TI Call TI -40 to 85 N08A
LMV431AIM5/NOPB ACTIVE SOT-23 DBV 5 1000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 N08A
LMV431AIM5X NRND SOT-23 DBV 5 3000 TBD Call TI Call TI -40 to 85 N08A
LMV431AIM5X/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 N08A
LMV431AIMF NRND SOT-23 DBZ 3 1000 TBD Call TI Call TI -40 to 85 RLA
LMV431AIMF/NOPB ACTIVE SOT-23 DBZ 3 1000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 RLA
LMV431AIMFX NRND SOT-23 DBZ 3 3000 TBD Call TI Call TI -40 to 85 RLA
LMV431AIMFX/NOPB ACTIVE SOT-23 DBZ 3 3000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 RLA
LMV431AIZ/LFT3 ACTIVE TO-92 LP 3 2000 Green (RoHS
& no Sb/Br) CU SN N / A for Pkg Type LMV431
AIZ
LMV431AIZ/NOPB ACTIVE TO-92 LP 3 1800 Green (RoHS
& no Sb/Br) CU SN N / A for Pkg Type -40 to 85 LMV431
AIZ
LMV431BCM5/NOPB ACTIVE SOT-23 DBV 5 1000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM N09C
LMV431BCM5X/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM N09C
LMV431BIMF NRND SOT-23 DBZ 3 1000 TBD Call TI Call TI -40 to 85 RLB
LMV431BIMF/NOPB ACTIVE SOT-23 DBZ 3 1000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 RLB
LMV431BIMFX/NOPB ACTIVE SOT-23 DBZ 3 3000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 RLB
LMV431CM5 NRND SOT-23 DBV 5 1000 TBD Call TI Call TI 0 to 70 N09B
LMV431CM5/NOPB ACTIVE SOT-23 DBV 5 1000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM 0 to 70 N09B
PACKAGE OPTION ADDENDUM
www.ti.com 23-Jun-2017
Addendum-Page 2
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LMV431CM5X/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM 0 to 70 N09B
LMV431CZ/NOPB ACTIVE TO-92 LP 3 1800 Green (RoHS
& no Sb/Br) CU SN N / A for Pkg Type 0 to 70 LMV431
CZ
LMV431IM5 NRND SOT-23 DBV 5 1000 TBD Call TI Call TI -40 to 85 N08B
LMV431IM5/NOPB ACTIVE SOT-23 DBV 5 1000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 N08B
LMV431IM5X/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 N08B
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
PACKAGE OPTION ADDENDUM
www.ti.com 23-Jun-2017
Addendum-Page 3
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LMV431ACM5 SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LMV431ACM5/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LMV431ACM5X/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LMV431AIM5 SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LMV431AIM5/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LMV431AIM5X SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LMV431AIM5X/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LMV431AIMF SOT-23 DBZ 3 1000 178.0 8.4 3.3 2.9 1.22 4.0 8.0 Q3
LMV431AIMF/NOPB SOT-23 DBZ 3 1000 178.0 8.4 3.3 2.9 1.22 4.0 8.0 Q3
LMV431AIMFX SOT-23 DBZ 3 3000 178.0 8.4 3.3 2.9 1.22 4.0 8.0 Q3
LMV431AIMFX/NOPB SOT-23 DBZ 3 3000 178.0 8.4 3.3 2.9 1.22 4.0 8.0 Q3
LMV431BCM5/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LMV431BCM5X/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LMV431BIMF SOT-23 DBZ 3 1000 178.0 8.4 3.3 2.9 1.22 4.0 8.0 Q3
LMV431BIMF/NOPB SOT-23 DBZ 3 1000 178.0 8.4 3.3 2.9 1.22 4.0 8.0 Q3
LMV431BIMFX/NOPB SOT-23 DBZ 3 3000 178.0 8.4 3.3 2.9 1.22 4.0 8.0 Q3
LMV431CM5 SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LMV431CM5/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
PACKAGE MATERIALS INFORMATION
www.ti.com 20-Dec-2016
Pack Materials-Page 1
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LMV431CM5X/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LMV431IM5 SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LMV431IM5/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LMV431IM5X/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LMV431ACM5 SOT-23 DBV 5 1000 210.0 185.0 35.0
LMV431ACM5/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0
LMV431ACM5X/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0
LMV431AIM5 SOT-23 DBV 5 1000 210.0 185.0 35.0
LMV431AIM5/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0
LMV431AIM5X SOT-23 DBV 5 3000 210.0 185.0 35.0
LMV431AIM5X/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0
LMV431AIMF SOT-23 DBZ 3 1000 210.0 185.0 35.0
LMV431AIMF/NOPB SOT-23 DBZ 3 1000 210.0 185.0 35.0
LMV431AIMFX SOT-23 DBZ 3 3000 210.0 185.0 35.0
LMV431AIMFX/NOPB SOT-23 DBZ 3 3000 210.0 185.0 35.0
LMV431BCM5/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0
LMV431BCM5X/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 20-Dec-2016
Pack Materials-Page 2
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LMV431BIMF SOT-23 DBZ 3 1000 210.0 185.0 35.0
LMV431BIMF/NOPB SOT-23 DBZ 3 1000 210.0 185.0 35.0
LMV431BIMFX/NOPB SOT-23 DBZ 3 3000 210.0 185.0 35.0
LMV431CM5 SOT-23 DBV 5 1000 210.0 185.0 35.0
LMV431CM5/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0
LMV431CM5X/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0
LMV431IM5 SOT-23 DBV 5 1000 210.0 185.0 35.0
LMV431IM5/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0
LMV431IM5X/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 20-Dec-2016
Pack Materials-Page 3
www.ti.com
PACKAGE OUTLINE
C
TYP
0.22
0.08
0.25
3.0
2.6
2X 0.95
1.9
1.45 MAX
TYP
0.15
0.00
5X 0.5
0.3
TYP
0.6
0.3
TYP
8
0
1.9
A
3.05
2.75
B
1.75
1.45
(1.1)
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
4214839/C 04/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
0.2 C A B
1
34
5
2
INDEX AREA
PIN 1
GAGE PLANE
SEATING PLANE
0.1 C
SCALE 4.000
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MAX
ARROUND 0.07 MIN
ARROUND
5X (1.1)
5X (0.6)
(2.6)
(1.9)
2X (0.95)
(R0.05) TYP
4214839/C 04/2017
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
PKG
1
34
5
2
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED METAL
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
EXPOSED METAL
www.ti.com
EXAMPLE STENCIL DESIGN
(2.6)
(1.9)
2X(0.95)
5X (1.1)
5X (0.6)
(R0.05) TYP
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
4214839/C 04/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
SYMM
PKG
1
34
5
2
www.ti.com
PACKAGE OUTLINE
C
TYP
0.22
0.08
0.25
3.0
2.6
2X 0.95
1.9
1.45 MAX
TYP
0.15
0.00
5X 0.5
0.3
TYP
0.6
0.3
TYP
8
0
1.9
A
3.05
2.75
B
1.75
1.45
(1.1)
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
4214839/C 04/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
0.2 C A B
1
34
5
2
INDEX AREA
PIN 1
GAGE PLANE
SEATING PLANE
0.1 C
SCALE 4.000
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MAX
ARROUND 0.07 MIN
ARROUND
5X (1.1)
5X (0.6)
(2.6)
(1.9)
2X (0.95)
(R0.05) TYP
4214839/C 04/2017
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
PKG
1
34
5
2
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED METAL
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
EXPOSED METAL
www.ti.com
EXAMPLE STENCIL DESIGN
(2.6)
(1.9)
2X(0.95)
5X (1.1)
5X (0.6)
(R0.05) TYP
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
4214839/C 04/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
SYMM
PKG
1
34
5
2
www.ti.com
PACKAGE OUTLINE
3X 2.67
2.03
5.21
4.44
5.34
4.32
3X
12.7 MIN
2X 1.27 0.13
3X 0.55
0.38
4.19
3.17
3.43 MIN
3X 0.43
0.35
(2.54)
NOTE 3
2X
2.6 0.2
2X
4 MAX
SEATING
PLANE
6X
0.076 MAX
(0.51) TYP
(1.5) TYP
TO-92 - 5.34 mm max heightLP0003A
TO-92
4215214/B 04/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Lead dimensions are not controlled within this area.
4. Reference JEDEC TO-226, variation AA.
5. Shipping method:
a. Straight lead option available in bulk pack only.
b. Formed lead option available in tape and reel or ammo pack.
c. Specific products can be offered in limited combinations of shipping medium and lead options.
d. Consult product folder for more information on available options.
EJECTOR PIN
OPTIONAL
PLANE
SEATING
STRAIGHT LEAD OPTION
321
SCALE 1.200
FORMED LEAD OPTION
OTHER DIMENSIONS IDENTICAL
TO STRAIGHT LEAD OPTION
SCALE 1.200
www.ti.com
EXAMPLE BOARD LAYOUT
0.05 MAX
ALL AROUND
TYP
(1.07)
(1.5) 2X (1.5)
2X (1.07)
(1.27)
(2.54)
FULL R
TYP
( 1.4)0.05 MAX
ALL AROUND
TYP
(2.6)
(5.2)
(R0.05) TYP
3X ( 0.9) HOLE
2X ( 1.4)
METAL
3X ( 0.85) HOLE
(R0.05) TYP
4215214/B 04/2017
TO-92 - 5.34 mm max heightLP0003A
TO-92
LAND PATTERN EXAMPLE
FORMED LEAD OPTION
NON-SOLDER MASK DEFINED
SCALE:15X
SOLDER MASK
OPENING
METAL
2X
SOLDER MASK
OPENING
123
LAND PATTERN EXAMPLE
STRAIGHT LEAD OPTION
NON-SOLDER MASK DEFINED
SCALE:15X
METAL
TYP
SOLDER MASK
OPENING
2X
SOLDER MASK
OPENING
2X
METAL
12 3
www.ti.com
TAPE SPECIFICATIONS
19.0
17.5
13.7
11.7
11.0
8.5
0.5 MIN
TYP-4.33.7
9.75
8.50
TYP
2.9
2.4 6.75
5.95
13.0
12.4
(2.5) TYP
16.5
15.5
32
23
4215214/B 04/2017
TO-92 - 5.34 mm max heightLP0003A
TO-92
FOR FORMED LEAD OPTION PACKAGE
4203227/C
www.ti.com
PACKAGE OUTLINE
C
TYP
0.20
0.08
0.25
2.64
2.10 1.12 MAX
TYP
0.10
0.01
3X 0.5
0.3
TYP
0.6
0.2
1.9
0.95
TYP-80
A
3.04
2.80
B
1.4
1.2
(0.95)
SOT-23 - 1.12 mm max heightDBZ0003A
SMALL OUTLINE TRANSISTOR
4214838/C 04/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Reference JEDEC registration TO-236, except minimum foot length.
0.2 C A B
1
3
2
INDEX AREA
PIN 1
GAGE PLANE
SEATING PLANE
0.1 C
SCALE 4.000
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MAX
ALL AROUND 0.07 MIN
ALL AROUND
3X (1.3)
3X (0.6)
(2.1)
2X (0.95)
(R0.05) TYP
4214838/C 04/2017
SOT-23 - 1.12 mm max heightDBZ0003A
SMALL OUTLINE TRANSISTOR
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
SYMM
LAND PATTERN EXAMPLE
SCALE:15X
PKG
1
3
2
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
www.ti.com
EXAMPLE STENCIL DESIGN
(2.1)
2X(0.95)
3X (1.3)
3X (0.6)
(R0.05) TYP
SOT-23 - 1.12 mm max heightDBZ0003A
SMALL OUTLINE TRANSISTOR
4214838/C 04/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 THICK STENCIL
SCALE:15X
SYMM
PKG
1
3
2
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