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   
SCHS051D − NOVEMBER 1998 − REVISED SEPTEMBER 2003
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D15-V Digital or ±7.5-V Peak-to-Peak
Switching
D125-Ω Typical On-State Resistance for 15-V
Operation
DSwitch On-State Resistance Matched to
Within 5 Ω Over 15-V Signal-Input Range
DOn-State Resistance Flat Over Full
Peak-to-Peak Signal Range
DHigh On/Off Output-Voltage Ratio: 80 dB
Typical at fis = 10 kHz, RL = 1 kΩ
DHigh Degree of Linearity: <0.5% Distortion
Typical at fis = 1 kHz, Vis = 5 V p-p,
VDD − VSS ≥ 10 V, RL = 10 kΩ
DExtremely Low Off-State Switch Leakage,
Resulting in Very Low Offset Current and
High Effective Off-State Resistance: 10 pA
Typical at VDD − VSS = 10 V, TA = 25°C
DExtremely High Control Input Impedance
(Control Circuit Isolated From Signal
Circuit): 1012 Ω Typical
DLow Crosstalk Between Switches: −50 dB
Typical at fis = 8 MHz, RL = 1 kΩ
DMatched Control-Input to Signal-Output
Capacitance: Reduces Output Signal
Transients
DFrequency Response, Switch On = 40 MHz
Typical
D100% Tested for Quiescent Current at 20 V
D5-V, 10-V, and 15-V Parametric Ratings
DMeets All Requirements of JEDEC Tentative
Standard No. 13-B, Standard Specifications
for Description of “B” Series CMOS
Devices
DApplications:
− Analog Signal Switching/Multiplexing:
Signal Gating, Modulator, Squelch
Control, Demodulator, Chopper,
Commutating Switch
− Digital Signal Switching/Multiplexing
− Transmission-Gate Logic Implementation
− Analog-to-Digital and Digital-to-Analog
Conversion
− Digital Control of Frequency, Impedance,
Phase, and Analog-Signal Gain
description/ordering information
The CD4066B is a quad bilateral switch intended for the transmission or multiplexing of analog or digital signals.
It is pin-for-pin compatible with the CD4016B, but exhibits a much lower on-state resistance. In addition, the
on-state resistance is relatively constant over the full signal-input range.
The CD4066B consists of four bilateral switches, each with independent controls. Both the p and the n devices
in a given switch are biased on or off simultaneously by the control signal. As shown in Figure 1, the well of the
n-channel device on each switch is tied to either the input (when the switch is on) or to VSS (when the switch
is off). This configuration eliminates the variation of the switch-transistor threshold voltage with input signal and,
thus, keeps the on-state resistance low over the full operating-signal range.
The advantages over single-channel switches include peak input-signal voltage swings equal to the full supply
voltage and more constant on-state impedance over the input-signal range. However, for sample-and-hold
applications, the CD4016B is recommended.
Copyright 2003, Texas Instruments Incorporated
    !"   #!$% &"'
&!   #" #" (" "  ") !"
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",  %% #""'
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
14
13
12
11
10
9
8
SIG A IN/OUT
SIG A OUT/IN
SIG B OUT/IN
SIG B IN/OUT
CONTROL B
CONTROL C
VSS
VDD
CONTROL A
CONTROL D
SIG D IN/OUT
SIG D OUT/IN
SIG C OUT/IN
SIG C IN/OUT
E, F, M, NS, OR PW PACKAGE
(TOP VIEW)
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SCHS051D − NOVEMBER 1998 − REVISED SEPTEMBER 2003
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description/ordering information (continued)
ORDERING INFORMATION
TAPACKAGE†ORDERABLE
PART NUMBER TOP-SIDE
MARKING
CDIP − F Tube of 25 CD4066BF3A CD4066BF3A
PDIP − E Tube of 25 CD4066BE CD4066BE
Tube of 50 CD4066BM
−55°C to 125°C
SOIC − M Reel of 2500 CD4066BM96 CD4066BM
−55
°
C to 125
°
C
SOIC − M
Reel of 250 CD4066BMT
CD4066BM
SOP − NS Reel of 2000 CD4066BNSR CD4066B
TSSOP − PW
Tube of 90 CD4066BPW
CM066B
TSSOP − PW
Reel of 2000 CD4066BPWR
CM066B
†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
†All control inputs are protected by the CMOS protection network.
NOTES: A. All p substrates are connected to VDD.
B. Normal operation control-line biasing: switch on (logic 1), VC = VDD; switch off (logic 0), VC = VSS
C. Signal-level range: V
SS
≤V
is
≤ V
DD
Control
VC†
VDD
VSS
VSS
n
n
pOut
Vos
Control
Switch
In
92CS-29113
n
p
Vis
Figure 1. Schematic Diagram of One-of-Four Identical Switches and Associated Control Circuitry
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SCHS051D − NOVEMBER 1998 − REVISED SEPTEMBER 2003
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
DC supply-voltage range, VDD (voltages referenced to VSS terminal) −0.5 V to 20 V. . . . . . . . . . . . . . . . . . . .
Input voltage range, Vis (all inputs) −0.5 V to VDD + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC input current, IIN (any one input) ±10 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 1): E package 80°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
M package 86°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package 76°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 113°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature (during soldering):
At distance 1/16 ±1/32 inch (1,59 ±0,79 mm) from case for 10 s max 265°C. . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions
MIN MAX UNIT
VDD Supply voltage 3 18 V
TAOperating free-air temperature −55 125 °C
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SCHS051D − NOVEMBER 1998 − REVISED SEPTEMBER 2003
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics
LIMITS AT INDICATED TEMPERATURES
PARAMETER TEST CONDITIONS
VIN
VDD
−55°C
−40°C
85°C
25°CUNIT
PARAMETER
TEST CONDITIONS
VIN
(V)
VDD
(V) −55°C −40°C 85°C
°
TYP MAX
0, 5 5 0.25 0.25 7.5 7.5 0.01 0.25
IDD
Quiescent device
0, 10 10 0.5 0.5 15 15 0.01 0.5
IDD
Quiescent device
current 0, 15 15 1 1 30 30 0.01 1 µA
current
0, 20 20 5 5 150 150 0.02 5
Signal Inputs (Vis) and Outputs (Vos)
VC = VDD,
RL = 10 k
Ω
returned
5 800 850 1200 1300 470 1050
ron On-state resistance
(max)
RL = 10 kΩ
returned
to ,
ǒVDD *VSSǓ
2
10 310 330 500 550 180 400 Ω
on
(max)
to ,
Vis = VSS to VDD
2
15 200 210 300 320 125 240
On-state resistance
5 15
∆r
on
On-state resistance
difference between
any two switches
R
L
= 10 kΩ, V
C
= V
DD
10 10 Ω
∆ron
difference between
any two switches
RL = 10 kΩ, VC = VDD
15 5
THD Total harmonic
distortion
VC = VDD = 5 V, VSS = −5 V,
Vis(p-p) = 5 V (sine wave centered o n 0 V ),
RL = 10 kΩ, fis = 1-kHz sine wave 0.4 %
−3-dB cutoff
frequency
(switch on)
VC = VDD = 5 V, VSS = −5 V, Vis(p-p) = 5 V
(sine wave centered on 0 V), RL = 1 kΩ40 MHz
−50-dB feedthrough
frequency (switch off) VC = VSS = −5 V, Vis(p-p) = 5 V
(sine wave centered on 0 V), RL = 1 kΩ1 MHz
Iis Input/output leakage
current (switch off)
(max)
VC = 0 V, Vis = 18 V, Vos = 0 V;
and
VC = 0 V, Vis = 0 V, Vos = 18 V 18 ±0.1 ±0.1 ±1±1±10−5 ±0.1 µA
−50-dB crosstalk
frequency
VC(A) = VDD = 5 V,
VC(B) = VSS = −5 V,
Vis(A) = 5 Vp-p, 50-Ω source,
RL = 1 kΩ
8 MHz
Propagation delay
RL = 200 kΩ, VC = VDD,
VSS = GND, CL = 50 pF,
5 20 40
tpd
Propagation delay
(signal input to
signal output)
V
SS
= GND, C
L
= 50 pF,
Vis = 10 V
(square wave centered on 5 V),
10 10 20 ns
pd
(signal input to
signal output)
is
(square wave centered on 5 V),
tr, tf = 20 ns 15 7 15
Cis Input capacitance VDD = 5 V, VC = VSS = −5 V 8 pF
Cos Output capacitance VDD = 5 V, VC = VSS = −5 V 8 pF
Cios Feedthrough VDD = 5 V, VC = VSS = −5 V 0.5 pF
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SCHS051D − NOVEMBER 1998 − REVISED SEPTEMBER 2003
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electrical characteristics (continued)
LIMITS AT INDICATED TEMPERATURES
CHARACTERISTIC TEST CONDITIONS
VDD
−55°C
−40°C
85°C
25°CUNIT
CHARACTERISTIC
TEST CONDITIONS
VDD
(V) −55°C −40°C 85°C
°
TYP MAX
UNIT
Control (VC)
Control input,
|Iis| < 10 µA,
5 1 1 1 1 1
V
ILC
Control input,
low voltage (max)
|Iis| < 10 µA,
V
is
= V
SS
, V
OS
= V
DD
, and
V = V , V = V
10 2 2 2 2 2 V
VILC
low voltage (max)
Vis = VSS, VOS = VDD, and
Vis = VDD, VOS = VSS 15 2 2 2 2 2
V
Control input,
53.5 (MIN)
V
IHC
Control input,
high voltage
See Figure 6 10 7 (MIN) V
VIHC
high voltage
See Figure 6
15 11 (MIN)
V
IIN Input current (max) Vis ≤VDD, VDD − VSS = 18 V,
VCC ≤VDD − VSS 18 ±0.1 ±0.1 ±1±1±10−5 ±0.1 µA
Crosstalk (control input
to signal output) VC = 10 V (square wave),
tr, tf = 20 ns, RL = 10 kΩ10 50 mV
Turn-on and turn-off
VIN = VDD, tr, tf = 20 ns,
5 35 70
Turn-on and turn-off
propagation delay
VIN = VDD, tr, tf = 20 ns,
CL = 50 pF, RL = 1 kΩ
10 20 40 ns
propagation delay
CL = 50 pF, RL = 1 kΩ
15 15 30
ns
Vis = VDD, VSS = GND,
RL = 1 kΩ to GND, CL = 50 pF,
5 6
Maximum control inpu
t
repetition rate
R
L
= 1 k
Ω
to GND, C
L
= 50 pF,
VC = 10 V (square wave
centered on 5 V), tr, tf = 20 ns,
10 9 MHz
repetition rate
C
centered on 5 V), tr, tf = 20 ns,
Vos = 1/2 Vos at 1 kHz 15 9.5
CIInput capacitance 5 7.5 pF
switching characteristics
VDD
SWITCH INPUT SWITCH
OUTPUT, Vos
VDD
(V) V
is
(V)
Iis (mA)
OUTPUT, V
os
(V)
(V)
Vis
(V) −55°C −40°C 25°C 85°C 125°C MIN MAX
5 0 0.64 0.61 0.51 0.42 0.36 0.4
5 5 −0.64 −0.61 −0.51 −0.42 −0.36 4.6
10 0 1.6 1.5 1.3 1.1 0.9 0.5
10 10 −1.6 −1.5 −1.3 −1.1 −0.9 9.5
15 0 4.2 4 3.4 2.8 2.4 1.5
15 15 −4.2 −4 −3.4 −2.8 −2.4 13.5
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SCHS051D − NOVEMBER 1998 − REVISED SEPTEMBER 2003
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TYPICAL CHARACTERISTICS
Vis − Input Signal Voltage − V
600
500
400
300
200
100
0−4 −3 −2 −1 0 1 2 3 4
TYPICAL ON-STATE RESISTANCE
vs
INPUT SIGNAL VOLTAGE (ALL TYPES)
92CS-27326RI
Figure 2
TA = 125°C
+25°C
−55°C
Supply Voltage (VDD − VSS) = 5 V
− Channel On-State Resistance −
on Ω
r
Figure 3
TYPICAL ON-STATE RESISTANCE
vs
INPUT SIGNAL VOLTAGE (ALL TYPES)
300
250
200
150
100
50
0
−10 −7.5 −5 −2.5 0 2.5 5 7.5 10
Supply Voltage (VDD − VSS) = 10 V
TA = 125°C
Vis − Input Signal Voltage − V
+25°C
−55°C
92CS-27327RI
− Channel On-State Resistance −
on Ω
r
Vis − Input Signal Voltage − V
TYPICAL ON-STATE RESISTANCE
vs
INPUT SIGNAL VOLTAGE (ALL TYPES)
Figure 4
300
250
200
150
100
50
0
−10 −7.5 −5 −2.5 0 2.5 5 7.5 10
Supply Voltage (VDD − VSS) = 15 V
TA = 125°C
+25°C
−55°C
92CS-27329RI
− Channel On-State Resistance −
on Ω
r
Vis − Input Signal Voltage − V
Figure 5
TYPICAL ON-STATE RESISTANCE
vs
INPUT SIGNAL VOLTAGE (ALL TYPES)
600
500
400
300
200
100
0
−10 −7.5 −5 −2.5 0 2.5 5 7.5 10
Supply Voltage (VDD − VSS) = 5 V
TA = 125°C
10 V −15 V
92CS-27330RI
− Channel On-State Resistance −
on Ω
r
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SCHS051D − NOVEMBER 1998 − REVISED SEPTEMBER 2003
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
CD4066B
1 of 4 Switches
Iis
Vis Vos
92CS-30966
|Vis − Vos|
|Iis|
ron =
Figure 6. Determination of ron as a Test Condition for Control-Input High-Voltage (VIHC) Specification
X-Y
Plotter
1-kΩ
Range
TG
On
Keithley
160 Digital
Multimeter
H. P.
Moseley
7030A
X
VSS
VDD
10 kΩ
92CS-22716
Y
Figure 7. Channel On-State Resistance Measurement Circuit
Figure 8
TYPICAL ON CHARACTERISTICS
FOR 1 OF 4 CHANNELS
3
2
1
0
−1
−2
−3
−3 −2 −1 0 1 2 3 4
VI − Input Voltage − V
92CS-30919
Output Voltage − V
V −
VDD
VC = VDD
Vis Vos
RL
VSS
All unused terminals are
connected to VSS
CD4066B
1 of 4
Switches
O
Figure 9
10 10210
3
10
101
102
103
104
f − Switching Frequency − kHz
POWER DISSIPATION PER PACKAGE
vs
SWITCHING FREQUENCY
TA = 25°C
Power Dissipation Per Package − W
Dµ
6
4
2
6
4
2
6
4
2
6
4
2
246246
92C-30920
5 V
10 V
VSS
VDD
5
6
13
12
7
CD4066B
P −
14
Supply Voltage
(VDD) = 15 V
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SCHS051D − NOVEMBER 1998 − REVISED SEPTEMBER 2003
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
VDD = 5 V
VC = −5 V
VSS = −5 V
C
ios
Cis Cos
CD4066B
1 of 4
Switches
Measured on Boonton capacitance bridge, model 75a (1 MHz);
test-fixture capacitance nulled out.
92CS-30921
Figure 10. Typical On Characteristics
for One of Four Channels
V
DD
VC = VSS Vos
VSS
CD4066B
1 of 4
Switches
Vis = VDD
I
92CS-3092
2
Figure 11. Off-Switch Input or Output Leakage
All unused terminals are connected to VSS.
V
DD
VC = VDD Vos
VSS
CD4066B
1 of 4
Switches
Vis
Figure 12. Propagation Delay Time Signal Input
(V
is
) to Signal Output (V
os
)
92CS-30923
200 kΩ
50 pF
VDD tr = tf = 20 ns
All unused terminals are connected to VSS.
VDD
VC
Vos
VSS
CD4066B
1 of 4
Switches
Vis
Figure 13. Crosstalk-Control Input
to Signal Output
+10 V
tr = tf = 20 ns
92CS-30924
10 kΩ
1 kΩ
All unused terminals are connected to VSS.

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SCHS051D − NOVEMBER 1998 − REVISED SEPTEMBER 2003
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
VDD
VC = VDD Vos
VSS
CD4066B
1 of 4
Switches
VDD
92CS-30925
1 kΩ
50 pF
VDD
NOTES: A. All unused terminals are connected to VSS.
B. Delay is measured at V
os
level of +10% from ground (turn-on) or on-state output level (turn-off).
tr = tf = 20 ns
Figure 14. Propagation Delay, tPLH, tPHL Control-Signal Output
VDD = 10 V
VC
VSS
CD4066B
1 of 4
Switches
Vis = 10 V
92CS-30925
1 kΩ
50 pF
tr = tf = 20 ns
VC
Vos
90%
10%
All unused terminals are connected to V
SS
.
VOS +VOS at 1 kHz
2
VOS +VOS at 1 kHz
2
Repetition
Rate
50%
trtf10 V
0 V
Figure 15. Maximum Allowable Control-Input Repetition Rate

   
SCHS051D − NOVEMBER 1998 − REVISED SEPTEMBER 2003
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Inputs
VSS
Measure inputs sequentially to both VDD and VSS. Connect all unused inputs to either VDD or VSS. Measure control inputs only.
I
VSS
VDD
92CS-27555
Figure 16. Input Leakage-Current Test Circuit
VDD
Channel 1
Channel 2
Channel 3
Channel 4
Channel 1
Channel 2
Channel 3
Channel 4
1/4 CD4066B CD4066B
CD4066B
CD4018B
CD4018B
1/4 CD4066B
CD4001B
LPF
LPF
LPF
LPF
1
10237912
54
14
15 13
12
3
5
2
4
1
2
5
6
8
9
12
13
3
4
10
1
8
4
11
11
12
6513
9
10
2
3
10 2 3 7 9 12
14
15
1
54
7
9
6
10
13 12 9 8 6 5 2 1
11 10 4 3
12 6 5 11
11 12
5
8
43
11
4
1
2
3
9
10
PEJ1J2J3J4J5
Q2
Q1
1/3 CD4049B
CD4001B
Signal
Inputs
Clock
Reset
Package Count
2 - CD4001B
1 - CD4049B
3 - CD4066B
2 - CD4018B
1/3 CD4049B
1/6 CD4049B 10 k
Signal
Outputs
PEJ1J2J3J4J5
Q2
Q1
External
Reset
Clock
Chan 1 Chan 2 Chan 3 Chan 4
VDD
30% (VDD − VSS)
Clock
Maximum
Allowable
Signal Level VSS
92CM-30928
Ω
10 kΩ
10 kΩ
10 kΩ
10 kΩ
Figure 17. Four-Channel PAM Multiplex System Diagram

   
SCHS051D − NOVEMBER 1998 − REVISED SEPTEMBER 2003
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
SWA
SWB
SWC
SWD
92CS-30927
Analog Inputs (±5 V)
VDD = 5 V
VDD = 5 V
5 V
−5 V
5 V CD4066B
Analog Outputs (±5 V) VSS = −5 V
CD4054B
VSS = 0 V
VEE = −5 V
IN0
Digital
Control
Inputs
0
Figure 18. Bidirectional Signal Transmission Via Digital Control Logic

   
SCHS051D − NOVEMBER 1998 − REVISED SEPTEMBER 2003
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
In applications that employ separate power sources to drive VDD and the signal inputs, the VDD current capability
should exceed VDD/RL (RL = effective external load of the four CD4066B bilateral switches). This provision avoids
any permanent current flow or clamp action on the VDD supply when power is applied or removed from the CD4066B.
In certain applications, the external load-resistor current can include both VDD and signal-line components. To avoid
drawing VDD current when switch current flows into terminals 1, 4, 8, or 11, the voltage drop across the bidirectional
switch must not exceed 0.8 V (calculated from ron values shown).
No VDD current will flow through RL if the switch current flows into terminals 2, 3, 9, or 10.
PACKAGE OPTION ADDENDUM
www.ti.com 25-Jan-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
CD4066BE ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
CD4066BEE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
CD4066BF ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type
CD4066BF3A ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type
CD4066BF3AS2283 OBSOLETE CDIP J 14 TBD Call TI Call TI
CD4066BF3AS2534 OBSOLETE CDIP J 14 TBD Call TI Call TI
CD4066BM ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD4066BM96 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD4066BM96E4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD4066BM96G4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD4066BME4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD4066BMG4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD4066BMT ACTIVE SOIC D 14 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD4066BMTE4 ACTIVE SOIC D 14 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD4066BMTG4 ACTIVE SOIC D 14 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD4066BNSR ACTIVE SO NS 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD4066BNSRE4 ACTIVE SO NS 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD4066BNSRG4 ACTIVE SO NS 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD4066BPW ACTIVE TSSOP PW 14 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 25-Jan-2012
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
CD4066BPWE4 ACTIVE TSSOP PW 14 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD4066BPWG4 ACTIVE TSSOP PW 14 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD4066BPWR ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD4066BPWRE4 ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD4066BPWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
JM38510/05852BCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type
M38510/05852BCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 25-Jan-2012
Addendum-Page 3
OTHER QUALIFIED VERSIONS OF CD4066B, CD4066B-MIL :
•Catalog: CD4066B
•Automotive: CD4066B-Q1, CD4066B-Q1
•Military: CD4066B-MIL
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•Military - QML certified for Military and Defense Applications
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
CD4066BM96 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
CD4066BM96 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
CD4066BMT SOIC D 14 250 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
CD4066BNSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
CD4066BPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CD4066BM96 SOIC D 14 2500 367.0 367.0 38.0
CD4066BM96 SOIC D 14 2500 333.2 345.9 28.6
CD4066BMT SOIC D 14 250 367.0 367.0 38.0
CD4066BNSR SO NS 14 2000 367.0 367.0 38.0
CD4066BPWR TSSOP PW 14 2000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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