APPLICATION NOTE
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Features
• Industry's first TotalCMOS™ PLD - both CMOS design
and process technologies
• Fast Zero Power (FZP™) design technique provides
ultra-low power and very high speed
• High speed pin-to-pin delays of 7.5 ns
• Ultra-low static power of less than 100 µA
• 100% routable with 100% utilization while all pins and
all macrocells are fixed
• Determi nistic timing model that is extremely simple to
use
• Up to 12 clocks with programmab le polarity at every
macrocell
• 5V, In-System Programmable (ISP) using a JTAG
interface
- On-chip supervoltage generation
- ISP commands include: Enable, Erase, Progr am,
Verify
- Supported by multiple ISP progr amming platforms
-Four pin JTAG interface (TCK, TMS, TDI, TDO)
- JTAG commands include: Bypass, Idcode
• Support for complex asynchronous clocking
• Innovative XPLA™ architecture com bines high speed
with extreme flexibility
• 1000 erase/program cycles guaranteed
• 20 years data retention guaranteed
• Logic expandable to 37 product ter m s
• PCI compliant
• Advanced 0.5µ E2CMOS process
• Security bit prevents unauthorized access
• Design entry and verification using industry standard
and Xilinx CAE tools
• Reprogrammable using industry standard device
programmers
• Innovative Control Term structure provides either sum
terms or product terms in each logic block for:
- Programmable 3-state buffer
- Asynchronous macrocell register preset/reset
- Up to two asynchronous clocks
• Programmable global 3-state pin facilitates "bed of
nails" testing without using logic resources
• Available in PLCC and VQFP packages
• A vailab le in both Commercial and Industrial grades
Description
The XCR5064C CPLD (Complex Programmable Logic
Device) is the second in a family of CoolRunner™ CPLDs
from Xilinx Semiconductors. These devices combine high
speed and zero power in a 64 macrocell CPLD. With the
FZP design technique, the XCR5064C offers true pin-to-pin
speeds of 7.5 ns, while simultaneously delivering power
that is less than 100 µA at standby without the need for
`turbo bits' or other power down schemes. By replacing
conventional sense amplifier methods for implementing
product terms (a technique that has been used in PLDs
since the bipolar era) with a cascaded chain of pure CMOS
gates, the dynamic power is also substantially lower than
any competing CPLDz. These devices are the first TotalC-
MOS PLDs, as they use both a CMOS process tec hnology
and the patented full CMOS FZP design technique.
The Xilinx FZP CPLDs utilize the patented XPLA
(eXtended Programmable Logic Array) architecture. The
XPLA architecture combines the best features of both PLA
and PAL type structures to deliver high speed and flexible
logic allocation that results in superior ability to make
design changes with fixed pinouts. The XPLA structure in
each logic block provides a fast 7.5 ns PAL path with five
dedicated product terms per output. This PAL path is joined
by an additional PLA structure that deploys a pool of 32
product terms to a fully programmable OR array that can
allocate the PLA product terms to any output in the logic
block. This combination allows logic to be allocated effi-
ciently throughout the logic block and supports as many as
37 product terms on an output. The speed with which logic
is allocated from the PLA array to an output is only 2.0 ns,
regardless of the number of PLA product terms used, which
results in worst case tPD's of only 9.5 ns from any pin to any
other pin. In addition, logic that is common to multiple out-
puts can be placed on a single PLA product term and
shared across multiple outputs via the OR array, eff ectively
increasing design density.
The XCR5084C CPLDs are supported by industry stan-
dard CAE tools (Cadence/OrCAD , Ex emplar Logic , Mentor,
Synopsys, Synario, Viewlogic, and Synplicity), using text
(ABEL, VHDL, Verilog) and/or schematic entry. Design v er-
ification uses industry standard simulators for functional
and timing simulation. Development is supported on per-
sonal computer, Sparc, and HP platforms. Device fitting
uses Xilinx developed tools including WebFITTER.
The XCR5064C CPLD is reprogrammable using industry
standard device programmers from vendors such as Data
I/O, BPMicrosystems, SMS, and others. The XCR5064C
also includes an industry-standard, IEEE 1149.1, JTAG
interface through which In-System Programming (ISP) and
reprogramming of the device are suppor ted.
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XPLA Architecture
Figure 1 shows a high lev el block diagr am of a 64 macrocell
device implementing the XPLA architecture. The XPLA
architecture consists of logic b locks that are interconnected
by a Zero-power Interconnect Array (ZIA). The ZI A is a v ir-
tual crosspoint switch. Each logic block is essentially a
36V16 device with 36 inputs from the ZIA and 16 macro-
cells. Each logic bl ock also pro vides 32 ZIA f eedback pat hs
from the macrocells and I/O pins.
From this point of view, this architecture looks like many
other CPLD architectures. What makes the CoolRunner
family unique is what is inside each logic block and the
design technique used to implement these logic blocks.
The contents of the logic block will be described next.
Logic Block Architecture
Figure 2 illustrates the logic block architecture. Each logic
block contains control term s, a PAL array, a PLA array, and
16 macrocells. The 6 control terms can individually be con-
figured as either SUM or PRODUCT terms, and are used to
control the preset/reset and out put enables of the 16 mac-
rocells’ flip-flops. In addition, two of the control terms can
be used as clock signals (see Macrocell Ar chitecture Sec-
tion f or details). The PAL array consists of a programmable
AND array with a fixed OR array, while the PLA array con-
sists of a programmable AND array with a programmable
OR array. The PAL array provides a high speed path
through the array, while the PLA array provides increased
product term density.
Each macroc ell has five dedicated product t erms f rom the
PAL array. The pin-to-pin tPD of the XCR5064C device
through the PAL array is 7.5 ns. If a macrocell needs more
than five product terms, it simply gets the additional product
terms from the PLA array. The PLA array consists of 32
product ter ms, which are available for use by all 16 macr o-
cells. The additional propagation delay incurred by a mac-
rocell using one or all 32 PLA product ter ms is just 2.0 ns.
So the total pin-t o-pin tPD for the XCR5064C using six to 37
product ter ms is 9.5 ns (7. 5 ns for the PAL + 2. 0 ns for the
PLA)..
Figure 1: Xilinx XPLA CPLD Architecture
LOGIC
BLOCK
I/O 36
16
16
36
16
16
MC0
MC1
MC15
I/O
MC0
MC1
MC15
SP00439
ZIA
LOGIC
BLOCK
LOGIC
BLOCK
I/O 36
16
16
MC0
MC1
MC15
36
16
16
I/O
MC0
MC1
MC15
LOGIC
BLOCK
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Figure 2: Xilinx XPLA Logic Block Architecture
TO 16 MACROCELLS
6
5
CONTROL
PAL
ARRAY
36 ZIA INPUTS
PLA
ARRAY
(32) SP00435A
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Macrocell Architecture
Figure 3 shows the architecture of the macrocell used in
the CoolRunner XCR5064C. The macrocell can b e config-
ured as either a D- or T- type flip-flop or a combinatorial
logic function. A D-type flip-flop is generally more useful for
implementing state machines and data buffering while a
T-type flip-flop is generally more useful in implementing
counters. Each of these flip-flops can be clocked from any
one of six sources. F our of the clock sources (CLK0, CLK1,
CLK2, CLK3) are connected to low-ske w , device-wide clock
networks designed to preserve the integrity of the clock sig-
nal by reducing skew between rising and falling edges.
Clock 0 (CLK0) is designated as a “synchronous” clock and
must be driven by an external source. Clock 1 (CLK1),
Clock 2 (CLK2), and Clock 3 (CLK3) can be used as “syn-
chronous” clocks that are driven by an exter nal source, or
as “asynchronous” clocks that are driven by a macrocell
equation. CLK0, CLK1, CLK2 and CLK3 can clock the mac-
rocell flip-flops on either the r ising edge or the falling edge
of the clock signal. The other c lock sources are two of the
six control terms (CT2 and CT3) provided in each logic
bloc k. These clocks can be individually configured as either
a PRODUCT ter m or SUM ter m equation created from the
36 signals available inside the logic block. The timing for
asynchronous and control term clocks is different in that the
TCO time is extended by the amount of time that it takes for
the signal to propagate through the array and reach the
clock network, and the TSU time is reduced.
The six control terms of each logic block are used to control
the asynchronous Preset/Reset of the flip-flops and the
enable/disab le of the output buff ers in each macrocell. Con-
trol terms CT0 an d CT1 are used to control the asynchro-
nous Preset/Reset of the macrocell's flip-flop. Note that the
Power-on Reset leaves all macrocells in the “zero” state
when power is properly applied, and that the Preset/Reset
feature for each macrocell can also be disabled. Control
terms CT2 and CT3 can be used as a clock signal to the
flip-flops of the macrocells, and as the Output Enable of the
macrocell's output buffer. Control terms CT4 and CT5 can
be used to control the Output Enable of the macrocell's out-
put buffer. Having four dedicated Output Enable control
terms ensures that the C oolRunner devices are PCI com-
pliant. The output buffers can also be always enabled or
always disabled. All CoolRunner devices also provide a
Global 3-State (GTS) pin, which, w hen enabled and pulled
Low, will 3-state all the outputs of the device. This pin is
provided to support “In-Circuit Testing” or “Bed-of-Nails
Testing”.
There are two feedbac k paths to the ZIA: one from the mac-
rocell, and one from the I/O pin. The ZIA feedback path
before the output buffer is the macrocell feedback path,
while the ZIA f eedback path after the output buff er is the I/O
pin feedback path. When the macrocell is used as an out-
put, the output buffer is enabled, and the macrocell feed-
back path can be used to feedback the logic implemented
in the macrocell. When the I/O pin is used as an input, the
output buffer will be 3-stated and the i nput signal will be f ed
into the ZIA via the I/O feedback path, and the logic imple-
mented in the buried macroc ell can be fed back to the ZIA
via the macrocell feedback path. It should be noted that
unused inputs or I/Os should be properly terminated (see
the section on Terminations in this data sheet and the appli-
cation note Terminating Unused CoolRunner I/O Pins).
INIT
(P or R)
D/T Q
SP00551
CLK0
PAL
PLA
CLK0
CLK1
CLK1
TO ZIA
GND
CT0
GTS
CT2
CT3
CT4
CT5
V
GND
CC
GND
Figure 3: XCR5064C Macrocell Architecture
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Simple Timing Model
Figure 4 shows the CoolRunner Timing Model. The Cool-
Runner timing model looks very much like a 22V10 timing
model in that there are three main timing parameters,
including tPD, tSU, and tCO. In other architect ures, the user
may be able to fit the des ign into the CPLD, but is not sure
whether system t iming requirement s can be met until a fter
the design has been fit into the device. This is because the
timing models of competing architectures are very complex
and include such things as timing dependencies on the
number of parallel expanders borrowed, sh arable expand-
ers, varying number of X and Y routing channels used, etc.
In the XPLA architecture, the user knows up front whether
the design will meet system timing requirements. This is
due to the simplicity of the timing model. For example, in
the XCR5064C device, the user knows up front that if a
given output uses five product terms or less, the
tPD = 7.5 ns, the tSU_PAL = 4 ns, and the tCO = 5.5 n s. If a n
output is using six to 37 product terms, an additional 2ns
must be added to the tPD and tSU timing parameters to
account for the time to propagate through the PLA array.
TotalCMOS Design Technique for Fast Zero
Power
Xilinx is the first to offer a TotalCMOS CPLD, both in pro-
cess technology and design technique. Xilinx employs a
cascade of CMOS gat es to im plement its Sum of Products
instead of the traditional sense amp approach. This CMOS
gate implementation allows Xilinx to off er CPLDs which are
both high performance and low power, breaking the para-
digm that to have low power, you must have low perfor-
mance. Refer to Figure 5 and Table 1 showing the ICC vs.
Frequency of our XCR5064C TotalCMOS CPL .
Figur e 4 : Co ol R unne r Ti ming M o de l
OUTPUT PININPUT PIN
SP00441
tPD_PAL = COMBINATORIAL PAL ONLY
tPD_PLA = COMBINATORIAL PAL + PLA
OUTPUT PININPUT PIN DQ
REGISTERED
tSU_PAL = PAL ONLY
tSU_PLA = PAL + PLA REGISTERED
tCO
GLOBAL CLOCK PIN
Table 1: ICC vs. Frequency (VCC = 5.0V, 25°C)
Frequency (MHz) 0 1 20 40 60 80 100 120 140 160 180 200
Typical ICC (mA) 0.1 0.5 8.6 17.1 25.6 33.9 42.2 50.3 58.3 66.4 74.7 82.7
TYPICAL
I
CC
(mA)
FREQUENCY (MHz)
SP00663
0 20 40 60 80 100 120 200
0
20
40
60
80
100
140 160 180
Figure 5: ICC vs. Frequency at VCC = 5V, 25°C
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JTAG Testing Capability
JTAG is the commonly-used acronym for the Boundary
Scan Test (BST) feature defined for integrated circuits by
IEEE Standard 1149.1. This s tandard defines input/output
pins, logic control f unctions, and commands which facilitate
both board and device level testing without the use of spe-
cialized test equipment. The Xilinx X CR5064C devices use
the JTAG interface for In-System Programming/Repro-
gramming. Although only a subset of the full JTAG com-
mand set is implemented (see Table 2), the devices are
fully capable of sitting in a JTAG scan chain.
The Xilinx XCR5064C’s JTAG interface includes a TAP P ort
defined by the IEEE 1149.1 JTAG Specification. As imple-
mented in the Xilinx XCR5064C, the TAP P ort includes four
of the five pins (refer to Table 3) described in the JTAG
specification: TCK, TMS, TDI, and TDO. The fifth signal
defined by the JTAG specification is TRST* (Test Reset).
TRST* is considered an optional signal, since it is not actu-
ally required to perform BS T or ISP. The Xilinx XCR5064C
sav es an I/O pin for general purpose use by not implement-
ing the optional TRST* signal in the JTAG interface.
Instead, the Xilinx XCR5064C supports the test reset func-
tionality through the use of its power up reset circuit, which
is included in al l Xilinx CPLDs. The pins associat ed with the
TAP Port should connect to an external pull-up resistor to
keep the JTAG signs from floating when they are not being
used.
In the Xilinx XCR5064C, the four mandatory JTAG pins
each require a unique, dedicated pin on the device. The
devices come from the factory with these I/O pins set to
perform JTAG functions, but through the software, the final
function of these pins can be controlled. If the end applica-
tion will require the device to be reprogrammed at some
future time with ISP, then the pins can be left as dedicated
JTAG functions, which means they are not available for use
as general purpose I/O pins. However, unlike competing
CPLDs, the Xilinx XCR5064C allow the macroc ells associ-
ated with these pins to be used as buried logic when the
JTAG/ISP function is enabled. This is the default state for
the software, and no action is required to leave these pins
enabled for the JTAG/ISP functions. If, however, JTAG/ISP
is not required in the end application, the software can
specify that this function be turned off and that these pins
be used as general pur pose I/O. Because the devices ini-
tially have the JTAG/ISP functions e nabled, the JEDEC file
can be downloaded into the device once, after which the
JTAG/ISP pins will become general purpose I/O. This fea-
ture is good for manufacturing because the devices can be
programmed during test and assembly of the end product
and yet still use all of the I/O pins after the pr ogramming is
done. It eliminat es the need for a costly, separate program-
ming step in the manufacturing process. Of course, if the
JTAG/ISP function is never required, this feature can be
turned off in the software and the device can be pro-
grammed with an industry-standard programmer, leaving
the pins availabl e f or I/O functions . Table 4 defines the ded-
icated pins used by the four mandatory JTAG signals for
each of the XCR5064C package types.
5-Volt, In-System Programming (ISP)
ISP is the ability to reconfigure the logic and functionality of
a device, printed circuit bo ard, or complete electronic sys-
tem before , during, and after its manufacture and shipment
to the end customer. ISP provides substantial benefits in
each of the following areas:
•Design
- Faster time-to -market
- Debug partitioning and simplified prototyping
- Printed circuit board reconfiguration during debug
- Better device and board level testing
•Manufacturing
- Multi-Functional hardware
- Reconfigurability f or Test
- Eliminates handling of “fine lead-pitch” components
for programming
- Reduced Inventory and manufacturing costs
- Improved quality and reliability
•Field Suppor t
- Easy remote upgrades and repair
- Support for field configuration, re-configuration, and
customization
The Xilinx XCR5064C allows for 5V, in-system program-
ming/reprogramming of its EEPROM cells via its JTAG
interface. An on-chip charge pump eliminates the need for
externally-provided supervoltages, so that the XCR5064C
may be easily programmed on th e circuit board using only
the 5-volt supply required by the device for normal opera-
tion. A set of low-le vel ISP basic commands implemented in
the XCR5064C enable this feature. The ISP commands
implemented in the Xilinx XCR5064C are specified in
Table 5. Please not e that an ENAB LE com mand must pre-
cede all ISP commands unless an ENABLE command has
already been given for a preceding ISP comm and.
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Table 2: XCR5064C Low-Level JTAG Boundary- Scan Com man ds
Instruction
(Instructio n Code)
Register Used Description
Bypass
(1111)
Bypass Register
Places the 1 bit bypass register between the TDI and TDO pins, which allows the BST data
to pass synchronously through the selected device to adjacent devices during normal device
operation. The Bypass instruction can be entered by holding TDI at a constant high value
and completing an Instruction-Scan cycle.
Idcode
(0001)
Boundary-Scan Register
Selects the IDCODE register and places it between TDI and TDO, allowing the IDCODE to
be serially shifted out of TDO. The IDCOD E instruction permits blind interrogation of the
components assembled onto a printed circuit board. Thus, in circumstances where the
component population may vary, it is possible to determine what components exist in a
product.
Table 3: JTAG Pin Description
Pin Name Description
TCK Test Clock Output Clock pin to shift the serial data and instructions in and out of the TDI and TDO pins,
respectively.
TMS Test Mode Select Serial input pin selects the JTAG instruction mode. TMS should be driven high during
user mode operation.
TDI Test Data Input Serial input pin for instructions and test data. Data is shifted in on the rising edge of
TCK.
TDO Test Data Output Serial output pin for instructions and test data. Data is shifted out on the falling edge
of TCK. The signal is tri-stated if data is not being shifted out of the device.
Table 4: XCR5064C JTAG Pinout by Packag e Type
Device
XCR5064C (Pin Number / Macrocell #)
TCK TMS TDI TDO
44-pin PLCC 32/C15 13/B15 7/A8 38/D8
44-pin VQFP 26/C15 7/B15 1/A8 32/D8
100-pin VQFP 62/C15 15/B15 4/A8 73/D8
Table 5: Low Level ISP Commands
Instruction
(Register Used) Instruction
Code Description
Enable
(ISP Shift Register) 1001 Enables the Erase, Program, and Verify commands .
Erase
(ISP Shift Register) 1010 Erases the entire EEPROM array.
Program
(ISP Shift Register) 1011 Programs the data in the ISP Shift Register into the addressed EEPROM row.
Verify
(ISP Shift Register) 1100 Transfers the data from the addressed row to the ISP Shift Register. The data can
then be shifted out and compared with the JEDEC file. The outputs during this op-
eration can be defined by the user.
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Terminations
The CoolRunner XCR5064C CPLDs are TotalCMOS™
devices. As with other CMOS devices, it is important to
consider how to properly terminate unused inputs and I/O
pins when fabricating a PC board. Allowing unused inputs
and I/O pins to float can cause the volt age to be in the linear
region of the CMOS input structures, which can increase
the power consumption of the device. The XCR5064C
CPLDs have programmable on-chip pull-down resist ors on
each I/O pin. These pull-downs are automatically activated
by the fitter softw are for all unused I/O pins. Note that an I/O
macrocell used as buried logic that does not have the I/O
pin used for input is considered to be unused, and the
pull-down resistors will be turned on. We recommend that
any unused I/O pins on the XCR5064C device be left
unconnected.
There are no on-chip pull-down struc tures associated with
the dedicated input pins. Xilinx recommends that any
unused dedicated inputs be terminated with external 10k Ω
pull-up resistors. These pins can be directly connected to
VCC or GND, but using the external pull-up resistors main-
tains maximum design flexibility should one of the unused
dedicated inputs be needed due to future design changes.
When using the JTAG/ISP functions, it is also recom-
mended that 10KΩ pull-up resistors be used on each of the
four mandatory signals. Letting these signals float can
cause the voltage on TMS to come close to ground, which
could cause the device to enter JTAG/ISP mode at unspec-
ified times. See the application notes JTAG and ISP Over-
view for Xilinx XPLA1 an d XPLA 2 CPLDs and Terminating
Unused I/O Pins in Xilinx XPLA1 and XPLA2
CoolRunner™ CPLDs for more information.
JTAG and ISP Interfacing
A number of industry-established methods exist for
JTAG/ISP interfacing with CPLD ’s and other integrated cir-
cuits. The Xilinx XCR5064C supports the following meth-
ods:
•PC parallel port
•Workstation or PC serial por t
•Embedded processor
•Automated test equipment
•Third party programmers
•High-End ISP Tools
For more details on JTAG and ISP for the XCR5064C, ref er
to the related application note: JTAG and ISP Over view for
Xilinx XPLA1 and XPLA2 CPLDs.
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Pr ogrammi ng Specifications
Symbol Parameter Min. Max. Unit
DC Parameters
VCCP VCC supply program/verify 4.5 5.5 V
ICCP ICC limit program/verify 200 mA
VIH Input voltage (High) 2.0 V
VIL Input voltage (Low) 0.8 V
VSOL Output voltage (Low) 0.5 V
VSOH Output voltage (High) 2.4 V
TDO_IOL Output current (Low) 8 mA
TDO_IOH Output current (High) 8 mA
AC Parameters
fMAX TCK m aximum frequency 10 MHz
PWE Pulse width erase 100 ms
PWP Pulse width program 10 ms
PWV Pulse width verify 10 µs
INIT Initialization time 100 µs
TMS_SU TMS setup time before TCK ↑10 ns
TDI_SU TDI setup time before TCK ↑10 ns
TMS_H TMS hold time after TCK ↑25 ns
TDI_H TDI hold time after TCK ↑25 ns
TDO_CO TDO valid after TCK ↓40 ns
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Absolute Maximum Ratings1
Operating Range
DC Electrical Characteristics For Commercial Grade Devices
Commercial: 0°C ≤ TAMB ≤ +70°C; 4.75V ≤ VCC ≤ 5.25V
Symbol Parameter Min. Max. Unit
VCC Supply voltage2-0.5 7.0 V
VIInput voltage -1.2 VCC+0.5 V
VOUT Output voltage -0.5 VCC+0.5 V
IIN Input current -30 30 mA
IOUT Output current -100 100 m A
TJMaximum junction temperature -40 150 °C
Tstr Storage temperature -65 150 °C
Note: 1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only.
Functional operation at these or any other condition above those indicated in the operational and programming specification
is not implied.
2. The chip supply voltage must rise monotonically.
Product Grade Temper a ture Volta ge
Commercial 0 to +70°C5.0V +5%
Industrial -40 to +85°C5.0V +10%
Symbol Par a m eter Test Conditions Min. Max. Unit
VIL Input voltage low VCC = 4.75V 0.8 V
VIH Input voltage high VCC = 5.25V 2.0 V
VIInput clamp voltage3VCC = 4.75V, IIN = -18 mA -1.2 V
VOL Output voltage low VCC = 4.75V, IOL = 12 mA 0.5 V
VOH Output voltage high VCC = 4.75V, IOH = -12 mA 2.4 V
IIInput leakage current VIN = 0 to VCC -10 10 µA
IOZ 3-stated output leakage current VIN = 0 to VCC -10 10 µA
ICCQ1Standby current VCC = 5.25V, TAMB = 0°C80µA
ICCD1, 2 Dynamic current VCC = 5.25V, TAMB = 0°C at 1 MHz 1 mA
VCC = 5.25V, TAMB = 0°C at 50 MHz 25 mA
IOS Short circuit output current3One pin at a time for no longer than 1
second -50 -200 mA
CIN Input pin capacitance3TAMB = 25°C, f = 1 MHz 84pF
CCLK Clock input capacitance3TAMB = 25°C, f = 1 MHz 5 12 pF
CI/O I/O pin capacitance3TAMB = 25°C, f = 1 MHz 10 pF
Notes: 1. See Table 1 on page 5 for typical values.
2. This parameter measured with a 16-bit, loadable up/down counter loaded into every logic block, with all outputs disabled
and unloaded. Inputs are tied to VCC or ground. This parameter guaranteed by design and characterization, not testing.
3. This parameter guaranteed by design and characterization, not by test.
4. Except IN1 and IN2 = 10 pF.
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AC Electrical Characteristics1 For Commercial Grade Devices
Commercial: 0°C ≤ TAMB ≤ +70°C; 4.75V ≤ VCC ≤ 5.25V
Symbol Parameter -7 -10 Unit
Min. Max. Min. Max.
tPD_PAL Propagation delay time, input (or feedback node) to output through PAL 2 7.5 2 10 ns
tPD_PLA Propagation delay time, input (or feedback node) to output through PAL
& PLA 39312ns
tCO Clock to out (global synchronous clock from pin) 2 5 2 6.5 ns
tSU_PAL Setup time (from input or feedback node) through PAL 4. 5 6 ns
tSU_PLA Setup time (from input or feedback node) through PAL + PLA 6 8 ns
tHHold time200ns
tCH Clock High time234ns
tCL Clock Low time234ns
tRInput Rise time 20 20 ns
tFInput Fall time 20 20 ns
fMAX1 Maximum FF toggle rate2 (1/tCH + tCL) 167 125 MHz
fMAX2 Maximum internal frequency2 (1/tSUPAL + tCF) 133 95 MHz
fMAX3 Maximum exter nal frequency2 (1/tSUPAL + tCO) 105 80 MHz
tBUF Output buffer delay time 22.5 2.5 ns
tPDF_PAL Input (or feedback node) to internal feedback node delay time through
PAL 57.5ns
tPDF_PLA Input (or feedback node) to internal feedback node delay time through
PAL+PLA 6.5 9.5 ns
tCF Clock to internal feedback node delay time 3 4.5 ns
tINIT Delay from valid VCC to valid reset 50 50 µs
tER Input to output disable2, 3 7.5 10 ns
tEA Input to output valid27.5 10 ns
tRP Input to register preset2911ns
tRR Input to register reset2911ns
Notes: 1. Specifications measured with one output switching. See Figure 6 and Table 6 for derating.
2. This parameter guaranteed by design and characterization, not by test.
3. Output CL = 5 pF.
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DC Electrical Characteristics For Industrial Grade Devices
Industrial: -40°C ≤ TAMB ≤ +85°C; 4.5V ≤ VCC ≤ 5.5V
Symbol Par a m eter Test Conditions Min. Max. Unit
VIL Input voltage low VCC = 4.5V 0.8 V
VIH Input voltage high VCC = 5.5V 2.0 V
VIInput clamp voltage3VCC = 4.5V, IIN = -18 mA -1.2 V
VOL Output voltage low VCC = 4.5V, IOL = 12 mA 0.5 V
VOH Output voltage high VCC = 4.5V, IOH = -12 mA 2.4 V
IIInput leakage current VIN = 0 to VCC -10 10 µA
IOZ 3-stated output leakage current VIN = 0 to VCC -10 10 µA
ICCQ1Standby current VCC = 5.5V, TAMB = -40°C 100 µA
ICCD1, 2 Dynamic current VCC = 5.5V, TAMB = -40°C at 1 MHz 1 mA
VCC = 5.5V, TAMB = -40°C at 50 MHz 30 mA
IOS Short circuit output current3One pin at a time for no longer than 1
second -50 -230 mA
CIN Input pin capacitance TAMB = 25°C, f = 1 MHz 84pF
CCLK Clock input capacitance TAMB = 25°C, f = 1 MHz 5 12 pF
CI/O I/O pin capacitance TAMB = 25°C, f = 1 MHz 10 pF
Notes: 1. See Table 1 on page 5 for typical values.
2. This parameter measured with a 16-bit, loadable up/down counter loaded into every logic block, with all outputs disabled
and unloaded. Inputs are tied to VCC or ground. This parameter guaranteed by design and characterization, not testing.
3. This parameter guaranteed by design and characterization, not by test.
4. Except IN1 and IN2 = 10 pF.
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AC Electrical Characteristics1 For Industrial Grade Devices
Industrial: -40°C ≤ TAMB ≤ +85°C; 4.5V ≤ VCC ≤ 5.5V
Symbol Parameter I10 I12 Unit
Min. Max. Min. Max.
tPD_PAL Propagation delay time, input (or feedback node) to output through PAL 2 10 2 12 ns
tPD_PLA Propagation delay time, input (or feedback node) to output through
PAL + PLA 312314ns
tCO Clock to out (global synchr onous clock from pin) 2 7 2 8 ns
tSU_PAL Setup time (from input or feedback node) through PAL 6 7 ns
tSU_PLA Setup time (from input or feedback node) through PAL + PLA 8 9 ns
tHHold time 00ns
tCH Clock High time 4 5 ns
tCL Clock Low time 4 5 ns
tRInput Rise time 20 20 ns
tFInput Fall time 20 20 ns
fMAX1 Maximum FF toggle rate2 (1/tCH + tCL) 125 100 MHz
fMAX2 Maximum internal frequency 2 (1/tSUPAL + tCF)9580MHz
fMAX3 Maximum ext ernal frequency2 (1/tSUPAL + tCO)7767MHz
tBUF Output buffer delay time 2.5 2.5 ns
tPDF_PAL Input (or feedback node) to internal feedback node delay time through
PAL 7.5 9.5 ns
tPDF_PLA Input (or feedback node) to internal feedback node delay time through
PAL+PLA 9.5 11.5 ns
tCF Clock to internal feedback node delay time 4.5 5.5 ns
tINIT Delay from valid VCC to valid reset 50 50 µs
tER Input to output disable2, 3 10 12 ns
tEA Input to output valid210 12 ns
tRP Input to register preset211 12.5 ns
tRR Input to register reset211 12.5 ns
Notes: 1. Specifications measured with one output switching. See Figure 6 and Table 6 for derating.
2. This parameter guaranteed by design and characterization, not by test.
3. Output CL = 5 pF.
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Switching Characteristics
The test load circuit and load values for the AC Electrical Characteristics are illustrated below.
Voltage Waveform
VCC
VIN
VOUT
C1
R1
R2
S1
S2
COMPONENT VALUES
R1 390Ω
R2 390Ω
C1 35 pF
MEASUREMENT S1 S2
t
PZH
Open Closed
t
PZL
Closed Closed
t
P
Closed Closed
SP00618
Note: For t
PHZ
and t
PLZ
C = 5 pF, and 3-state levels are
measured 0.5V from steady state active level.
SP00664
NUMBER OF OUTPUTS SWITCHING
1 2 4 8 12 16
VCC = 5V, 25°C
5.10
5.30
5.50
5.70
5.20
5.40
5.60
tPD_PAL
(ns)
5.80
Figure 6: tPD_PAL vs. Outputs Switching
Table 6: tPD_PAL vs. Number of Outputs Switching
(VCC = 5.0V)
Number Of
Outputs 12481216
Typical (ns) 5.10 5.22 5.30 5.35 5.36 5.38
90%
10%
1.5ns1.5ns
+3.0V
0V
t
R
t
F
MEASUREMENTS:
All circuit delays are measured at the +1.5V level of
inputs and outputs, unless otherwise specified.
Input Pulses
SP00368
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Pin Descriptions
XCR5064C - 44-pin PLCC
XCR5064C - 44-pin VQFP
XCR5064C - 100-pin VQFP
PLCC
6140
7
17
39
29
18 28
Pin Function
1 IN1
2 IN3
3V
DD
4 I/O-A0/CK3
5 I/O-A2
6 I/O-A5
7 I/O-A8 (TDI)
8 I/O-A11
9 I/O-A12
10 GND
11 I/O-A13
12 I/O-A15
13 I/O-B15 (TMS)
14 I/O-B13
15 VDD
Pin Function
16 I/O-B10
17 I/O-B8
18 I/O-B4
19 I/O-B3
20 I/O-B2
21 I/O-B0/CK2
22 GND
23 VDD
24 I/O-C0/CK1
25 I/O-C2
26 I/O-C3
27 I/O-C4
28 I/O-C7
29 I/O-C8
30 GND
Pin Function
31 I/O-C13
32 I/O-C15 (TCK)
33 I/O-D15
34 I/O-D13
35 VDD
36 I/O-D12
37 I/O-D11
38 I/O-D8 (TDO)
39 I/O-D7
40 I/O-D2
41 I/O-D0
42 GND
43 IN0-CK0
44 IN2-gtsn
SP00554
VQFP
44 34
1
11
33
23
12 22
Pin Function
1 I/O-A8 (TDI)
2 I/O-A11
3 I/O-A12
4 GND
5 I/O-A13
6 I/O-A15
7 I/O-B15 (TMS)
8 I/O-B13
9V
DD
10 I/O-B10
11 I/O-B8
12 I/O-B4
13 I/O-B3
14 I/O-B2
15 I/O-B0/CK2
Pin Function
16 GND
17 V
DD
18 I/O-C0/CK1
19 I/O-C2
20 I/O-C3
21 I/O-C4
22 I/O-C7
23 I/O-C8
24 GND
25 I/O-C13
26 I/O-C15 (TCK)
27 I/O-D15
28 I/O-D13
29 V
DD
30 I/O-D12
Pin Function
31 I/O-D11
32 I/O-D8 (TDO)
33 I/O-D7
34 I/O-D2
35 I/O-D0
36 GND
37 IN0/CK0
38 IN2-gtsn
39 IN1
40 IN3
41 V
DD
42 I/O-A0/CK3
43 I/O-A2
44 I/O-A5
SP00555
Pin Function
1 I/O-A6
2 I/O-A7
3V
DD
4 I/O-A8 (TDI)
5NC
6 I/O-A9
7NC
8 I/O-A10
9 I/O-A11
10 I/O-A12
11 GND
12 I/O-A13
13 I/O-A14
14 I/O-A15
15 I/O-B15 (TMS)
16 I/O-B14
17 I/O-B13
18 V
DD
19 I/O-B12
20 I/O-B11
21 I/O-B10
22 NC
23 I/O-B9
24 NC
25 I/O-B8
26 GND
27 NC
28 NC
29 I/O-B7
30 I/O-B6
31 I/O-B5
32 I/O-B4
Pin Function
33 I/O-B3
34 V
DD
35 I/O-B2
36 I/O-B1
37 I/O-B0/CK2
38 GND
39 V
DD
40 I/O-C0/CK1
41 I/O-C1
42 I/O-C2
43 GND
44 I/O-C3
45 I/O-C4
46 I/O-C5
47 I/O-C6
48 I/O-C7
49 NC
50 NC
51 V
DD
52 I/O-C8
53 NC
54 I/O-C9
55 NC
56 I/O-C10
57 I/O-C11
58 I/O-C12
59 GND
60 I/O-C13
61 I/O-C14
62 I/O-C15 (TCK)
63 I/O-D15
64 I/O-D14
65 I/O-D13
66 V
DD
Pin Function
67 I/O-D12
68 I/O-D11
69 I/O-D10
70 NC
71 I/O-D9
72 NC
73 I/O-D8 (TDO)
74 GND
75 I/O-D7
76 I/O-D6
77 NC
78 NC
79 I/O-D5
80 I/O-D4
81 I/O-D3
82 V
DD
83 I/O-D2
84 I/O-D1
85 I/O-D0
86 GND
87 IN0/CK0
88 IN2-gtsn
89 IN1
90 IN3
91 V
DD
92 I/O-A0/CK3
93 I/O-A1
94 I/O-A2
95 GND
96 I/O-A3
97 I/O-A4
98 I/O-A5
99 NC
100 NC
SP00556
VQFP
100 76
1
25
75
51
26 50
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Ordering Information
Revision History
Component Availability
Pins 44 100
Type Plastic VQFP Plastic PLCC Plastic VQFP
Code VQ44 PC44 VQ100
XCR5064C -12 I I I
-10 C, I C, I C, I
-7 C C C
Date Version $ Revision
8/5/99 1.0 Initial Xilinx release.
2/10/00 1.1 Converted to Xilnx format and updated.
Example: XCR5064C -7 PC 44 C
Temperature Range
Number of Pins
Package Type
Speed Options
-12: 12 ns pin-to-pin delay
-10: 10 ns pin-to-pin delay
-7: 7.5 ns pin-to-pin delay
Temperature Range
C = Commercial, TA = 0°C to +70°C
I = Industrial, TA = –40°C to +8 5 °C
Packaging Op t ion s
VQ44: 44-pin VQFP
PC44: 44-pin PLCC
VQ100: 100-pin VQFP
Device Type
Speed Options
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