CS1600 Low-cost PFC Controller for Electronic Ballasts Features & Description Description Lowest PFC System Cost for Electronic Ballasts CS1600 is a high-performance Variable Frequency Discontinuous Conduction Mode (VF - DCM), active Power Factor Correction (PFC) controller, optimized to deliver the lowest PFC system cost for electronic ballast applications. Variable Frequency Discontinuous Conduction Mode Improved Efficiency Due to Variable Switching Frequency A variable ON time / variable frequency algorithm is used to achieve near unity power factor. This algorithm spreads the EMI frequency spectrum, which reduces the conducted EMI filtering requirements. The feedback loop is closed through an integrated compensation network within the IC, eliminating the need for additional external components. Protection features such as overvoltage, overcurrent, overpower, open- and short-circuit protection, overtemperature, and brownout help protect the device during abnormal transient conditions. EMI Signature Reduction from Digital Noise Shaping Integrated Feedback Compensation Overvoltage Protection with Hysteresis Overpower Protection with Shutdown UVLO with Wide Hysteresis Thermal Shutdown with Hysteresis Ordering Information See page 13. LB D1 VDD BR1 R3 BR1 R1 C2 R2 AC Mains R4 7 VDD 4 IFB C1 C3 3 IAC BR 1 Cirrus Logic, Inc. http://www.cirrus.com BR 1 CS1600 GD 6 R5 Q1 Regulated DC Output GND 5 Copyright Cirrus Logic, Inc. 2010 (All Rights Reserved) NOV `10 DS904F1 CS1600 1. INTRODUCTION VDD Voltage Regulator POR + - VDD V th(ST) V th(STP) 7 VDD 6 GD 5 GND VZ 15k IAC 24k 3 ADC VDD 15k IFB 4 24k ADC Figure 1. CS1600 Block Diagram The CS1600 digital power factor controller operates in variable on-time, variable frequency, discontinuous conduction mode (DCM). The CS1600 uses a proprietary digital algorithm to maximize the efficiency and reduce the conductive EMI. The analog-to-digital converter (ADC) shown in the CS1600 block diagram in Figure 9 is used to sense the PFC output voltage ( Vlink ) and the rectified AC line voltage ( Vrect ) by measuring currents through their respective resistors. The magnitudes of these currents are measured as a proportion of a reference current (IREF) that functions as the reference for the ADCs. The digital signal is then processed in a control algorithm which determines the behavior of the CS1600 during start-up, normal operation, and under fault conditions, such as overvoltage, and over-temperature conditions. The CS1600 PFC switching frequency varies with the Vrect on a cycle-by-cycle basis, and its digital algorithm calculates the on-time accordingly for unity power factor. Unlike traditional Critical Conduction Mode (CRM) PFC controller, CS1600 operates at its low switching frequency near the zero-crossing point of the AC input voltage, and it operates at its high switching frequency at the peak of its AC input voltage (this is the opposite of the switching frequency profile for a CRM PFC controller), thus CS1600 reduces switching losses especially under light-load conditions, spreads conducted EMI energy peaks over a wide frequency band and increases overall system efficiency. The proprietary digital control engine optimizes the feedback error signal using an adaptive control algorithm, improves 2 system stability and transient response. No external feedback error signal compensation components are required. The CS1600s digital controller algorithm limits the ON time of the Power MOSFET by the following equation: 0.001827VS T on ------------------------------------V rect Where Ton is the max time that the power MOSFET is turned on and Vrect is the rectified line voltage. In the event of a sudden line surge or sporadic, high dv/dt line voltages, this equation may not limit the ON time appropriately. For this type of line disturbance, additional protection mechanisms such as fusible resistors, fast-blow fuses, or other current-limiting devices are recommended. Under steady-state conditions, the voltage loop keeps PFC output voltage close to its nominal value. Under light load startup or feedback loop open conditions, the output voltage may pass the overvoltage protection threshold. The digital control engine initiates a fast response loop to shut down gate driving signal to reduce the energy delivered to the output for PFC capacitor protection. When the link voltage drop below VOVP - VOVP(Hy), PFC resumes normal operation. DS904F1 CS1600 2. PIN DESCRIPTION No Connection NC No Connection NC Rectifier V oltage S ens e IAC Link V oltage S ens e IFB 1 2 3 4 8 7 6 5 NC No Connec tion V DD IC S upply V oltage GD P FC Gate Driver GND Ground 8-lead S OIC Figure 2. CS1600 Pin Assignments Table 1. Pin Descriptions Pin Name Pin # I/O NC 1,2,8 - IAC 3 IN Rectifier Voltage Sense -- A current proportional to the rectified line voltage (Vrect) is fed into this pin. The current is measured with an A/D converter. IFB 4 IN Link Voltage Sense -- A current proportional to the output link voltage (Vlink) of the PFC is fed into this pin. The current is measured with an A/D converter. GND 5 PWR Ground -- Current return for both the input signal portion of the IC and the gate driver. GD 6 OUT Gate Driver Output -- The totem pole stage is able to drive the power MOSFET with a peak current of 0.5 A source and 1.0 A sink. The high-level voltage of this pin is clamped at VZ to avoid excessive gate voltages. VDD 7 PWR IC Supply Voltage -- Supply voltage of both the input signal portion of the IC and the gate driver. DS904F1 Description NC -- No connections 3 CS1600 3. CHARACTERISTICS AND SPECIFICATIONS 3.1 Electrical Characteristics Typical characteristics conditions: TA = 25 C, VDD = 13 V, GND = 0 V All voltages are measured with respect to GND. Unless otherwise specified, all currents are positive when flowing into the IC. Parameter Minimum/Maximum characteristics conditions: TJ = -40 to +125 C, VDD = 10 V to 15 V, GND = 0 V Condition Symbol Min Typ Max Unit Turn-on Threshold Voltage VDD Increasing VDD(on) 8.4 8.8 9.3 V Turn-off Threshold Voltage (UVLO) VDD Decreasing VDD(off) 7.1 7.4 7.9 V VHys - 1.4 - V IDD = 20 mA VZ 17.0 17.9 18.5 V VDD = VDD(on) IST - 68 80 A CL=1nF, fsw=70kHz IDD - 1.7 1.9 mA Output Source Resistance IGD = 100mA,VDD = 13V ROH - 9 - Output Sink Resistance IGD = -200mA,VDD = 13V ROL - 6 - Rising Time CL=1nF,VDD = 13V tr - 32 60 ns Falling Time CL=1nF,VDD = 13V tf - 15 30 ns VDD Supply Voltage UVLO Hysteresis Zener Voltage VDD Supply Current Start-up Supply Current Operating Supply Current PFC Gate Drive Output Voltage Low State IGD = -200mA,VDD = 13V Vol - 0.9 1.3 V Output Voltage High State IGD = 100mA,VDD = 13V Voh 11.3 11.8 - V Output Voltage at Startup Mode VO(startup) - 414 - V Output Voltage at Normal Mode VO(nom) - 460 - V VOVP - 492 - V VOVP(Hy) - 5 - V Thermal Shutdown Threshold TSD 130 143 155 C Thermal Shutdown Hysteresis TSD(Hy) - 9 - C Overvoltage Protection (OVP) 2 OVP Threshold OVP Hysteresis Thermal Protection 1 Notes: 1. Specifications guaranteed by design and are characterized and correlated using statistical process methods. Specification are based upon a PFC system configured for AC input of 108-305 VAC (Sine), 45/65 Hz, Vlink= 460 V, RIAC = 3.45 M, RIFB = 3.45 M, C3 = 23.5 F, LB = 380 H, 115 W. 3. Overpower protection is scaled to rated power. 4. Normal operation mode, see 5.2 Start-up vs. Normal Operation Mode on page 8. 2. 4 DS904F1 CS1600 3.2 Absolute Maximum Ratings Pin Symbol 7 VDD 1,3,4,5 - 1,3,4,5 - 7 VGD 7 Parameter Value Unit VZ V Analog Input Maximum Voltage -0.5 to VZ V Analog Input Maximum Current 50 mA Gate Drive Output Voltage -0.3 to VZ V IGD Gate Drive Output Current -1.0 / +0.5 A - PD Total Power Dissipation @ TA=50 C 600 mW - JA Junction-to-Ambient Thermal Impedance 107 C / W - TA Operating Ambient Temperature Range1 -40 to +125 C - TJ Junction Temperature Operating Range -40 to +125 C - TStg Storage Temperature Range -65 to +150 C All Pins ESD 2000 200 500 V IC Supply Voltage Electrostatic Discharge Capability Human Body Model Machine Model Charged Device Model Notes: 5. The CS1501 has an internal shunt regulator that controls the voltage on the VDD pin. VZ, the shunt regulation voltage, can be a maximum of 20 V but may also be as low as 10 V. 6. Long term operation at the maximum junction temperature will result in reduced product life. Derate internal power dissipation at the rate of 50 mW / C for variation over temperature. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. DS904F1 5 CS1600 4. TYPICAL ELECTRICAL PERFORMANCE 3.5 13 CL = 1 nF 3 11 VDD (V) IDD (mA) 12 fSW = 70 kHz TA = 25 C 2.5 2 10 1.5 Rising 1 9 Startup Falling 8 0.5 UVLO 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 7 -50 0 50 100 150 TEMP (o C) VDD (V) Figure 3. Supply Current vs. Supply Voltage Figure 4. Start-up & UVLO vs. Temp 19 2 18.5 1.5 VZ (V) UVLO Hysteresis (V) IDD = 20 mA 1 17.5 0.5 0 17 -50 0 50 100 TEMP ( o C) Figure 5. UVLO Hysteresis vs. Temp 6 18 150 -50 0 50 100 150 TEMP ( oC) Figure 6. VDD Zener Voltage vs. Temp DS904F1 CS1600 100 1.8 Operating 90 80 VDD = 13 V 1.4 Frequency (kHz) Supply Current (mA) 1.6 CL = 1 nF 1.2 fSW(max) = 70 kHz 1.0 0.8 0.6 70 Max Freq 60 50 40 30 0.4 Min Freq 20 0.2 10 Start-up 0 0 -50 0 50 100 150 -60 -40 -20 0 TEMP ( o C) 80 100 120 140 500 12 490 Source OVP 480 10 Vlink (V) Zout (Ohm) 60 Figure 8. Min/Max Operating Frequency vs. Temp 14 8 6 VDD = 13 V Isource = 100 mA Isink = 200 mA Sink 4 470 460 Normal 450 440 2 430 -40 -20 0 20 40 60 80 100 120 Gate Resistor (ROH, ROL) Temp (oC) Figure 9. Gate Resistance (ROH, ROL) vs. Temp DS904F1 40 TEMP ( oC) Figure 7. Supply Current (ISB, IST, IDD) vs. Temp 0 -60 20 140 420 -50 0 50 100 150 Temperature (C) Figure 10. OVP vs. Temp 7 CS1600 5. GENERAL DESCRIPTION One key feature of the CS1600 is its operating frequency profile. Figure 11 illustrates how the frequency varies over half cycle of the line voltage in steady-state operation. When power is first applied to the CS1600, it examines the line voltage and adapts its operating frequency to the line voltage as shown in Figure 11. The operating frequency is varied from the peak to the trough of the AC input. During start-up the control algorithm's goal is to generate maximum power while maintaining DCM operation, providing an approximate square-wave envelop current within every half line cycle by adjusting the operating frequency for fast startup behavior. CS1600 has two discrete operation modes: Start-up and Normal. Start-up mode will be activated when Vlink is less than 90% of nominal value and remains active until Vlink reaches 100% of nominal value, as shown in Figure 13. Startup mode is activated during initial system power-up. Any Vlink drop to less than 90% of nominal value, such as load change, can cause the system to enter Start-up mode until Vlink is brought back into regulation. Vlink [V] 100% 90% 120 Switching Freq. (% of Max.) Startup Mode 5.1 PFC Operation 5.2 Start-up vs. Normal Operation Mode Startup Mode The CS1600 offers numerous features, options, and functional capabilities to the designer of switching power converters. This digital PFC control IC is designed to replace legacy analog PFC controllers with minimal design effort. Normal Mode Normal Mode % of Max 100 t [ms] 80 Figure 13. Start-up and Normal Modes 60 40 Line Voltage (% of Max.) 20 0 0 45 90 135 180 Rectified Line Voltage Phase (Deg.) Figure 11. Switching Frequency vs. Phase Angle Figure 12 illustrates how the operating frequency (as a percentage of maximum frequency) changes with output power and the peak of the line voltage. Vin < 182 VAC 50 48 40 5.3 Burst Mode Burst mode is utilized to improve system efficiency when the system output power (Po) is < 5% of nominal. Burst mode is implemented by intermittently disabling the PFC over a full half-line period cycle under light load conditions, as shown in Figure 14. Po [W] 60 56 Burst Threshold Burst Mode F SW max (kHz) 70 Startup mode is defined as a surge of current delivering maximum power to the output regardless of the load. During every active switch cycle, the 'ON' time is calculated to drive a constant peak current over the entire line cycle. However, the 'OFF' time is calculated based on the DCM/CCM boundary equation. Burst Mode Active Vin > 156 VAC t [ms] Vin [V] 20 Vin PFC Disable 0 5 20 40 60 80 FET Vgs 100 % PO max Figure 12. Max Switching Frequency vs. Output Power When Po falls below 5% the CS1600 changes to Burst Mode (See 5.3 Burst Mode on page 8). 8 t [ms] Figure 14. Burst Modes DS904F1 CS1600 5.4 Output Power and PFC Boost Inductor 5.5 PFC Output Capacitor In normal operating mode, the nominal output power is estimated by the following equation. The value of the PFC output capacitor should be chosen based upon voltage ripple and hold-up requirements. To ensure system stability with the digital controller, the recommended value of the capacitor is within the range of 0.25 F / watt to 0.5 F / watt. 2 V link - ( V in ( min ) x 2 ) Po = x x ( V in ( min ) ) x --------------------------------------------------------2 x f max x L B x V link [Eq.1] 5.6 Output IFB Sense & Input IAC Sense where: Po rated output power of the system efficiency of the boost converter (estimated as 100% by the PFC algorithm) Vin(min) minimum RMS line voltage is 108V, measured after the rectifier and EMI filter nominal PFC output voltage must be 460 V Vlink fmax maximum switching frequency is 70 kHz LB boost inductor specified by rated power requirement margin factor to guarantee rated output power (Po) against boost inductor tolerances. A current proportional to the PFC output voltage, Vlink, is supplied to the IC on pin IFB and is used as a feedback control signal. This current is compared against an internal fixedvalue current. The ADC is used to measure the magnitude of the IFB current through resistor RIFB. The magnitude of the IFB current is then compared to an internal fixed-value current. V link R3 IFB RIFB V DD 7 R4 Equation 1 is provided for explanation purposes only. Using substituted required design values for Vlink and fmax gives the following equation. CS1600 15k 24k IFB 4 460V - ( 108V x 2 ) 2 Po = x x ( 108V ) x ------------------------------------------------------------2 x 70kHz x L B x 460V [Eq.2] Figure 16. Feedback Input Pin Model Changing values for application-specific devices such as the boost inductor or Vlink voltage is not recommended and requires changing internal register values. Solving Equation 2 for the PFC boost inductor LB gives the following equation.: 460V - ( 108V x 2 ) 2 L B = x x ( 108V ) x ------------------------------------------------------------2 x 70kHz x Po x 460V ADC [Eq.3] If a value of the boost inductor other than that obtained from Equation 3 above is used, the total output power capability as well as the minimum input voltage threshold will differ according to Equation 2. L < LB / Resistor RIFB sets the feedback current and is calculated as follows: 460V - V dd V link - V dd [Eq.4] R IFB = ---------------------------- = -----------------------------I fixed 129A By using digital loop compensation, the voltage feedback signal does not require an external compensation network. A current proportional to the AC input voltage is supplied to the IC on pin IAC and is used by the PFC control algorithm. V rec t R1 IAC RIAC V DD 7 R2 CS1600 15k L = LB 24k IA C Po(max) 3 ADC L > L B/ Figure 17. IAC Input Pin Model 108 305 VAC(rms) Figure 15. Relative Effects of Varying Boost Inductance DS904F1 Resistor RIAC sets the IAC current and is derived as follows: R IAC = R IFB [Eq.5] For optimal performance, resistors RIAC & RIFB should use 1% tolerance or better resistors. 9 CS1600 5.7 Brownout Protection As an added protection to the PFC boost stage, the CS1600 includes a failure mechanism that detects high average currents that occur under abnormal brownout conditions. The brownout protection feature monitors the Vrect input signal and suspends the gate-drive switching when a brownout threshold breach is detected. Under normal conditions, the CS1600 will never reach the brownout threshold, as the PFC stage is automatically protected by the power limitation of Equation 2, see section 5.4 Output Power and PFC Boost Inductor on page 9. In the event that the boost inductor is significantly less than the target value of LB, the brownout protection threshold may be breached. However, under normal operating conditions with proper boost inductance, this will not occur. If a brownout event is detected, the CS1600 enters standby, and upon recovery from brownout enters normal operation mode. In order to avoid an erroneous brownout detection, hysteresis and minimum detection time is implemented to avoid brownout detection during input transients. Figure 5.8 illustrates the brownout entry and exit timing. If the input line voltage is lower than the threshold for a fixed period of time, a brownout is declared. The measured voltage decreases at a rate of 5 V / half-line-cycle (~8 ms for 60 Hz line frequency). The CS1600 triggers a timer when the measured voltage falls below the lower brownout threshold. The IC asserts the brownout protection and stops the gate-drive switching only if the timer reaches more than 56 ms, which is determined by the minimum line frequency.. TBrownout Brownout Thresholds Upper 56 ms 56 ms Lower Start Timer Enter Standby Start Timer Figure 18. Brownout Sequence 10 Exit Standby During the brownout state, the device continues monitoring the input line voltage. The device exits the brownout state when the input voltage peak value exceeds the brownout upper threshold for at least 56 ms. The maximum response time of the brownout protection normally happens at light-load conditions. It can be calculated by the following equation: 8 ms T Brownout = 8 ms + ------------ ( 128 V - V BP ( th ) ) + 56 ms 5V [Eq.6] 8 = 8 + --- ( 128 - 95 ) + 56 5 = 116.8 ms 5.8 Overvoltage Protection The overvoltage protection (OVP) will trigger immediately and stop the gate drive when the current into the IFB pin (IOVP) exceeds 105% of the reference current value (Iref). The IC resumes gate drive switching when the link voltage drops below VOVP - VOVP(HY). 5.9 Open/Short Loop Protection If the PFC output sense resistor RIFB fails (open or short to GND), the measured output voltage decreases at a slew rate of about 2V / s, which is determined by ADC sampling rate. The IC stops the gate drive when the measured output voltage is lower than the measured line voltage. The IC resumes gate drive switching when the current into the IFB pin becomes larger than or equal to the current into the IAC pin and Vlink is greater than the peak of the line voltage (Vrect(pk)). The maximum response time of open/short loop protection for RIFB is about 150 s in the CS1600. If the PFC input sense resistor RIAC fails (open or short to GND), the current reference signal supplied to the IC on pin IAC falls to zero. DS904F1 CS1600 6. SUMMARY OF EQUATIONS Eq. # Equation Variables/Recommended Values Output Power (page 9) 1 2 V link - ( V in ( min ) x 2 ) Po = x x ( V in ( min ) ) x --------------------------------------------------------2 x f max x L B x V link Output Power w/ required values (page 9) 2 460V - ( V in ( min ) x 2 ) 2 Po = x x ( V in ( min ) ) x ------------------------------------------------------------2 x 70kHz x L B x 460V Boost Inductor (page 9) 3 460V - ( V in ( min ) x 2 ) L B = x x ( V in ( min ) ) x ------------------------------------------------------------2 x 70kHz x Po x 460V Po rated output power of the system efficiency of the boost converter (estimated as 100% by the PFC algorithm) Vin(min) minimum RMS line voltage is 108V, measured after the rectifier and EMI filter nominal PFC output voltage must be 460 V Vlink fmax maximum switching frequency is 70 kHz LB boost inductor requirement margin factor to guarantee rated output power (Po) against boost inductor tolerances. 2 specified by rated power Output IFB Sense Resistor (page 9) 4 460V - V dd V link - V dd R IFB = ---------------------------- = -----------------------------I fixed 129A Input IAC Sense Resistor (page 9) 5 R IAC = R IFB Boost Inductor Peak Current 6 4 x PO I LB ( pk ) = ------------------------------------------- x V in ( min ) x 2 Boost Inductor RMS Current 7 PO I LB ( rms ) = -----------------------------V in ( min ) x Vlink Voltage Ripple 8 DS904F1 PO V link ( rip ) = ---------------------------------------------------------------------2 x f line ( min ) x 460 x C out Cout Value of the output capacitor in microfarads. fline(min) Minimum line frequency. 11 CS1600 7. SUMMARY OF TERMS Variable The efficiency factor. A margin factor to guarantee rated power against tolerances and transients. fline(min) The minimum AC line frequency. IAC The current generated by Vrect that flows into the IAC pin. IFB The current generated by Vlink that flows into the IFB pin. IFET(pk) The PFC MOSFET peak current, which is equal to the peak current in the PFC boost inductor. Irms The magnitude of the RMS current. Isat The boost inductor LB saturation current. Ist The sum of the current into the IAC and IFB pins. IST The startup current of the chip. LB The PFC boost inductor. Po The nominal output power from the CS1600 PFC circuit. Po(max) The maximum value of the output power from the CS1600 PFC circuit. RIAC The sense resistor used to measure current into the IAC pin. RIFB The sense resistor used to measure current into the IFB pin. Vin(min) The minimum specified line voltage for proper operation (volts RMS). Vlink The magnitude of the output voltage from the PFC. Vlink(min) The magnitude of the output voltage from the PFC. Vlink(rip) Vlink(rip), is the output voltage ripple requirement in volts peak-to-peak Vrect 12 Definition The instantaneous value of the rectified line voltage (volts). DS904F1 CS1600 8. PACKAGE DRAWING 8L SOIC (150 MIL BODY) PACKAGE DRAWING E H 1 b c D SEATING PLANE A L e A1 INCHES DIM A A1 B C D E e H L MIN 0.053 0.004 0.013 0.007 0.189 0.150 0.040 0.228 0.016 0 MAX 0.069 0.010 0.020 0.010 0.197 0.157 0.060 0.244 0.050 8 MILLIMETERS MIN MAX 1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 4.80 5.00 3.80 4.00 1.02 1.52 5.80 6.20 0.40 1.27 0 8 JEDEC # MS-012 9. ORDERING INFORMATION Part # Temperature Range Package Description CS1600-FSZ -40 C to +125 C 8-lead SOIC, Lead (Pb) Free 10.ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION Model Number Peak Reflow Temp MSL Ratinga Max Floor Lifeb CS1600-FSZ 260 C 2 365 Days a. MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020. b. Stored at 30 C, 60% relative humidity. DS904F1 13 CS1600 11.REVISION HISTORY Revision Date Changes A8 SEP 2010 Replaced typical connection, pinout, and block diagram. F1 NOV 2010 Revised Brownout section. Finalized data sheet for QPL 1. Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find one nearest you go to http://www.cirrus.com IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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