© Semiconductor Components Industries, LLC, 2016
April, 2019 − Rev. 1
1Publication Order Number:
ESDL2031/D
ESDL2031
ESD Protection Diodes
Ultra Low Capacitance ESD Protection
Diode for High Speed Data Line
The ESDL2031 ESD protection diodes are designed to protect high
speed data lines from ESD. Ultra−low capacitance and low ESD
clamping voltage make this device an ideal solution for protecting
voltage sensitive high speed data lines.
Features
•Ultra Low Capacitance (0.40 pF Typ, I/O to GND)
•Protection for the Following IEC Standards:
IEC 61000−4−2 (Level 4)
•Low ESD Clamping Voltage
•These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Typical Applications
•USB 3.x
•MHL 2.0
•SATA/SAS
•PCI Express
•HDMI
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating Symbol Value Unit
Operating Junction Temperature Range TJ−55 to +125 °C
Storage Temperature Range Tstg −55 to +150 °C
Lead Solder Temperature −
Maximum (10 Seconds)
TL260 °C
IEC 61000−4−2 Contact (ESD)
IEC 61000−4−2 Air (ESD)
ESD
ESD
±30
±30
kV
kV
Maximum Peak Pulse Current
8/20 ms @ TA = 25°C
Ipp 9.75 A
Maximum Peak Pulse Power
8/20 ms @ TA = 25°C
Ppk 72 W
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
See Application Note AND8308/D for further description of
survivability specs.
MARKING
DIAGRAM
X4DFN2 (0201)
CASE 152AX
PIN CONFIGURATION
AND SCHEMATIC
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=
12
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
ORDERING INFORMATION
J = Specific Device Code
(Rotated 270 degrees)
J
ESDL2031
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2
ELECTRICAL CHARACTERISTICS
(TA = 25°C unless otherwise noted)
Symbol Parameter
VRWM Working Peak Voltage
IRMaximum Reverse Leakage Current @ VRWM
VBR Breakdown Voltage @ IT
ITTest Current
VHOLD Holding Reverse Voltage
IHOLD Holding Reverse Current
RDYN Dynamic Resistance
IPP Maximum Peak Pulse Current
VCClamping Voltage @ IPP
VC = VHOLD + (IPP * RDYN)
I
V
VCVRWM
VHOLD
VBR
RDYN
VC
IR
IT
IHOLD
−IPP
RDYN
IPP
VC = VHOLD + (IPP * RDYN)
VRWM
VHOLD
IR
IT
IHOLD
VBR
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise specified)
Parameter Symbol Conditions Min Typ Max Unit
Reverse Working Voltage VRWM I/O Pin to GND 4.0 V
Breakdown Voltage VBR IT = 1 mA, I/O Pin to GND 5.1 8.5 V
Reverse Leakage Current IRVRWM = 4.0 V, I/O Pin to GND 0.05 mA
Reverse Holding Voltage VHOLD I/O Pin to GND 2.5 V
Holding Reverse Current IHOLD I/O Pin to GND 55 mA
Clamping Voltage
TLP (Note 2)
VCIPP = 8 A IEC61000−4−2 Level 2 Equivalent
(±4 kV Contact, ±8 kV Air)
5.25 V
IPP = 16 A IEC61000−4−4 Level 2 Equivalent
(±8 kV Contact, ±16 kV Air)
7.1
Reverse Peak Pulse Current IPP per IEC61000−4−5 (8x20 ms) Figure 11 9.75 A
Clamping Voltage 8/20 ms
Waveform per Figure 11
VCIPP = 9.75 A 7.4 V
Dynamic Resistance RDYN Pin1 to Pin2
Pin2 to Pin1
0.22
0.22
W
Junction Capacitance CJVR = 0 V, f = 1 MHz 0.40 0.55 pF
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
1. For test procedure see Figure 12 and application note AND8307/D.
2. ANSI/ESD STM5.5.1 − Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model.
TLP conditions: Z0 = 50 W, tp = 100 ns, tr = 1 ns, averaging window: t1 = 70 ns to t2 = 90 ns.
Figure 1. ESD Clamping Voltage Screenshot
Positive 8 kV Contact per IEC61000−4−2
Figure 2. ESD Clamping Voltage Screenshot
Negative 8 kV Contact per IEC61000−4−2
TIME (ns) TIME (ns)
140100806040200−20
−10
0
10
20
40
50
70
1008060 14040200−20
VOLTAGE (V)
VOLTAGE (V)
30
60
−70
−50
−40
−30
−10
0
−20
10
120
−60
120
80
100
90
−100
−80
−90
ESDL2031
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3
TYPICAL CHARACTERISTICS
Figure 3. Positive TLP I−V Curve Figure 4. Negative TLP I−V Curve
Figure 5. Positive Clamping Voltage vs. Peak
Pulse Current (tp = 8/20 ms)
Figure 6. Negative Clamping Voltage vs. Peak
Pulse Current (tp = 8/20 ms)
Figure 7. Breakdown Voltage Figure 8. Reverse Leakage Current
ITLP (A)
VOLTAGE (V)
0
2
4
6
8
10
12
14
16
18
02456 913 78
20
10 11 12
0121024 6 8
IPK (A)
VC @ IPK (V)
8
7
6
5
4
3
2
1
0
012102468
IPK (A)
VC @ IPK (V)
9
7
6
5
4
3
2
1
0
IR (A)
VR (V)
1.E−11
1.E−10
1.E−09
1.E−08
1.E−07
1.E−06
1.E−05
1.E−04
1.E−03
−8−4048
0
1
2
3
4
5
6
7
8
9
10
VIEC Eq (kV)
ITLP (A)
VOLTAGE (V)
0
2
4
6
8
10
12
14
16
18
02456 913 78
20
10 11 12
0
1
2
3
4
5
6
7
8
9
10
VIEC Eq (kV)
−6−22 6
8
−5−1−7−31 537
IR (A)
VR (V)
1.E−11
1.E−10
1.E−09
1.E−08
1.E−07
1.E−06
1.E−05
1.E−04
1.E−03
−8−4048−6−22 6−5−1−7−31 537
1.E−13
1.E−12
ESDL2031
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4
TYPICAL CHARACTERISTICS
Figure 9. Insertion Loss
S21 (dB)
FREQUENCY (Hz)
−2.0
−1.8
−1.6
−1.4
−1.2
−1.0
−0.8
−0.6
−0.4
1.E+07 1.E+08 1.E+09 1.E+10
−0.2
0
−3.0
−2.8
−2.6
−2.4
−2.2
m1
m3
m2
m4
m5
m6
Interface
Data Rate
(Gb/s)
Fundamental Frequency
(GHz)
3rd Harmonic Frequency
(GHz) ESDL2031 Insertion Loss (dB)
USB 3.0 52.5 (m1) 7.5 (m2) m1 = −0.23
m2 = −0.81
USB 3.1 10 5.0 (m3) 15 (m4) m3 = −0.53
m4 = −1.47
HDMI 2.1 12 6.0 (m5) 18 (m6) m5 = −0.65
m6 = −1.82
Figure 10. ESDL2031 Insertion Loss
Figure 11. 8 X 20 ms Pulse Waveform
TIME (ms)
50
0
Ipp - PEAK PULSE CURRENT - %Ipp
100
tr = rise time to peak value [8 ms]
tf = decay time to half value [20 ms]
trtf
Peak
Value
Half Value
0
ESDL2031
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5
IEC 61000−4−2 Spec.
Level
Test Volt-
age (kV)
First Peak
Current
(A)
Current at
30 ns (A)
Current at
60 ns (A)
1 2 7.5 4 2
2 4 15 8 4
3 6 22.5 12 6
4 8 30 16 8
Ipeak
90%
10%
IEC61000−4−2 Waveform
100%
I @ 30 ns
I @ 60 ns
tP = 0.7 ns to 1 ns
Figure 12. IEC61000−4−2 Spec
Transmission Line Pulse (TLP) Measurement
Transmission Line Pulse (TLP) provides current versus
voltage (I−V) curves in which each data point is obtained
from a 100 ns long rectangular pulse from a charged
transmission line. A simplified schematic of a typical TLP
system is shown in Figure 13. TLP I−V curves of ESD
protection devices accurately demonstrate the product’s
ESD capability because the 10s of amps current levels and
under 100 ns time scale match those of an ESD event. This
is illustrated in Figure 14 where an 8 kV IEC 61000−4−2
current waveform is compared with TLP current pulses at
8 A and 16 A. A TLP I−V curve shows the voltage at which
the device turns on as well as how well the device clamps
voltage over a range of current levels.
Figure 13. Simplified Schematic of a Typical TLP
System
DUT
LS
÷
Oscilloscope
Attenuator
10 MW
VC
VM
IM
50 W Coax
Cable
50 W Coax
Cable
Figure 14. Comparison Between 8 kV IEC 61000−4−2 and 8 A and 16 A TLP Waveforms
ESDL2031
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7
PACKAGE DIMENSIONS
DFN2, 0.60x0.30, 0.36P
CASE 152AX
ISSUE F
ÈÈ
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
A
B
E
D
BOTTOM VIEW
b
L
TOP VIEW
A
A1
CSEATING
PLANE
SIDE VIEW
DIM MIN NOM
MILLIMETERS
A0.175 0.200
A1
b0.205 0.215
D
E
SOLDER FOOTPRINT*
DIMENSIONS: MILLIMETERS
0.65
0.27
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
1
L0.145 0.155
0.26
RECOMMENDED
1
e0.36 BSC
A
M
0.05 BC
A
M
0.05 BC
2X
e
2X
2X
0.01 C
0.02 C
0.575 0.600
0.275 0.300
PIN 1
INDICATOR
MAX
0.225
0.225
0.165
0.625
0.325
0.018 REF
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ESDL2031/D
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