LTC2752
1
2752f
Typical applicaTion
FeaTures
applicaTions
DescripTion
Dual16-Bit
SoftSpan IOUT DACs
The LTC
®
2752 is a dual 16-bit multiplying serial-input,
current-output digital-to-analog converter. It operates from
a single 3V to 5V supply and is guaranteed monotonic
over temperature. The LTC2752A provides full 16-bit
performance (±1LSB INL and DNL, max) over temperature
without any adjustments. This SoftSpan™ DAC offers
six output ranges (up to ±10V) that can be programmed
through the 3-wire SPI serial interface, or pinstrapped for
operation in a single range.
Any on-chip register (including DAC output-range set-
tings) can be read for verification in just one instruction
cycle; and if you change register content, the altered
register will be automatically read back during the next
instruction cycle.
Voltage-controlled offset and gain adjustments are also
provided; and the power-on reset circuit and CLR pin both
reset the DAC outputs to 0V regardless of output range.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
SoftSpan is a trademark of Linear Technology Corporation. All other trademarks are the property
of their respective owners. Protected by U.S. Patents, including 5481178.
Dual 16-Bit VOUT DAC with Software-Selectable Ranges
n Program or Pin-Strap Six Output Ranges
0V to 5V, 0V to 10V, –2.5V to 7.5V, ±2.5V, ±5V, ±10V
n Maximum 16-Bit INL Error: ±1 LSB over
Temperature
n Guaranteed Monotonic over Temperature
n Glitch Impulse 0.6nV•s (3V), 2.2nV•s (5V)
n Serial Readback of All On-Chip Registers
n 1μA Maximum Supply Current
n 2.7V to 5.5V Single-Supply Operation
n 16-Bit Settling Time: 2µs
n Voltage-Controlled Offset and Gain Trims
n Clear and Power-On-Reset to 0V Regardless of
Output Range
n 48-Pin 7mm × 7mm LQFP Package
n High Resolution Offset and Gain Adjustment
n Process Control and Industrial Automation
n Automatic Test Equipment
n Data Acquisition Systems
LTC2752
VDD
GND
GEADJB
SPI with READBACK
–
+
+
–
DAC B
REFERENCE
5V
VOUTB
RINA
REFA
REFERENCE
5V
REFB
ROFSA
ROFSB
RCOMB RCOMA
RINB
VOSADJB
ALL AMPLIFIERS 1/2 LT1469
IOUT1B
IOUT2B
RFBB
GEADJA
+
–
2752 TA01
VOUTA
VOSADJA
IOUT1A
IOUT2A
RFBA
+
–
DAC A
CODE
0
–1.0
INL (LSB)
–0.8
–0.4
–0.2
0
1.0
0.4
16384 32768
2752 TA01b
–0.6
0.6
0.8
0.2
49152 65535
±10V RANGE
Integral Nonlinearity (INL)
LTC2752
2
2752f
absoluTe MaxiMuM raTings
IOUT1X, IOUT2X to GND ............................................±0.3V
RINX, RCOMX, REFX, RFBX, ROFSX, VOSADJX,
GEADJX to GND ....................................................... ±18V
VDD to GND ..................................................–0.3V to 7V
Digital Inputs to GND ................................... –0.3V to 7V
Digital Outputs to GND ..... –0.3V to VDD+0.3V (max 7V)
Operating Temperature Range
LTC2752C ................................................ 0°C to 70°C
LTC2752I .............................................–40°C to 85°C
Maximum Junction Temperature .......................... 150°C
Storage Temperature Range ..................–65°C to 150°C
Lead Temperature (Soldering, 10 sec)...................300°C
(Notes 1, 2)
pin conFiguraTion
orDer inForMaTion
LEAD FREE FINISH PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC2752BCLX#PBF LTC2752LX 48-Lead (7mm × 7mm) Plastic LQFP 0°C to 70°C
LTC2752BILX#PBF LTC2752LX 48-Lead (7mm × 7mm) Plastic LQFP –40°C to 85°C
LTC2752ACLX#PBF LTC2752LX 48-Lead (7mm × 7mm) Plastic LQFP 0°C to 70°C
LTC2752AILX#PBF LTC2752LX 48-Lead (7mm × 7mm) Plastic LQFP –40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
This product is only offered in trays. For more information go to: http://www.linear.com/packaging/
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
REFA
REFA
RCOMA
GEADJA
RINA
RINA
GND
IOUT2AS
IOUT2AF
GND
CS/LD
SDI
13
14
15
16
17
18
19
20
21
22
23
24
SCK
SRO
GND
VDD
GND
GND
CLR
RFLAG
DNC
M-SPAN
S0
S1
48
47
46
45
44
43
42
41
40
39
38
37
ROFSA
ROFSA
RFBA
RFBA
IOUT1A
VOSADJA
VOSADJB
IOUT1B
RFBB
RFBB
ROFSB
ROFSB
REFB
REFB
RCOMB
GEADJB
RINB
RINB
GND
IOUT2BS
IOUT2BF
GND
LDAC
S2
TOP VIEW
LX PACKAGE
48-LEAD (7mm s 7mm) PLASTIC LQFP
TJMAX = 150°C, θJA = 58°C/W
LTC2752
3
2752f
elecTrical characTerisTics
VDD = 5V, VRINX = 5V unless otherwise specified. The l denotes the
specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
SYMBOL PARAMETER CONDITIONS
LTC2752B LTC2752A
UNITSMIN TYP MAX MIN TYP MAX
Static Performance
Resolution l16 16 Bits
Monotonicity l16 16 Bits
DNL Differential Nonlinearity l±1 ±0.2 ±1 LSB
INL Integral Nonlinearity l±2 ±0.4 ±1 LSB
GE Gain Error All Output Ranges l±20 ±2 ±12 LSB
Gain Error Temperature
Coefficient
∆Gain/∆Temp ±0.25 ±0.25 ppm/°C
BZE Bipolar Zero Error All Bipolar Ranges l±12 ±1 ±8 LSB
Bipolar Zero Temperature
Coefficient
±0.15 ±0.15 ppm/°C
Unipolar Zero-Scale Error Unipolar Ranges (Note 3) l±0.01 ±1 ±0.01 ±1 LSB
PSR Power Supply Rejection VDD = 5V, ±10%
VDD = 3V, ±10%
l
l
±0.4
±1
±0.03
±0.1
±0.2
±0.5
LSB/V
LSB/V
ILKG IOUT1 Leakage Current TA = 25°C
TMIN to TMAX
l
±0.05 ±2
±5
±0.05 ±2
±5
nA
nA
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Analog Pins
Reference Inverting Resistors (Note 4) l16 20 kΩ
RREF DAC Input Resistance (Notes 5, 6) l8 10 kΩ
RFB Feedback Resistors (Note 6) l8 10 kΩ
ROFS Bipolar Offset Resistors (Note 6) l16 20 kΩ
RVOSADJ Offset Adjust Resistors l1024 1280 kΩ
RGEADJ Gain Adjust Resistors l2048 2560 kΩ
CIOUT1 Output Capacitance Full-Scale
Zero-Scale
90
40
pF
Dynamic Performance
Output Settling Time Span Code = 0000, 10V Step. To ±0.0015% FS
(Note 7)
2 μs
Glitch Impulse VDD = 5V (Note 8)
VDD = 3V (Note 8)
2.2
0.6
nV•s
nV•s
Digital-to-Analog Glitch Impulse (Note 9) 2 nV•s
Reference Multiplying BW 0V to 5V Range, VREF = 3VRMS,
Code = Full Scale, –3dB BW
1 MHz
Multiplying Feedthrough Error 0V to 5V Range, VREF = ±10V, 10kHz
Sine Wave
0.4 mV
Analog Crosstalk (Note 10) –109 dB
THD Total Harmonic Distortion (Note 11) Multiplying –108 dB
Output Noise Voltage Density (Note 12) at IOUT1 13 nV/√Hz
VDD = 5V, VRINX = 5V unless otherwise specified. The l denotes specifications that apply over the full operating temperature range,
otherwise specifications are at TA = 25°C.
LTC2752
4
2752f
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Power Supply
VDD Supply Voltage l2.7 5.5 V
IDD VDD Supply Current Digital Inputs = 0V or VDD l0.5 1 μA
Digital Inputs
VIH Digital Input High Voltage 3.3V ≤ VDD ≤ 5.5V
2.7V ≤ VDD < 3.3V
l
l
2.4
2
V
V
VIL Digital Input Low Voltage 4.5V < VDD ≤ 5.5V
2.7V ≤ VDD ≤ 4.5V
l
l
0.8
0.6
V
V
Hysteresis Voltage 0.1 V
IIN Digital Input Current VIN = GND to VDD l±1 µA
CIN Digital Input Capacitance VIN = 0V (Note 13) l6 pF
Digital Outputs
VOH Digital Output High Voltage IOH = 200µA, 2.7V ≤ VDD ≤ 5.5V lVDD – 0.4 V
VOL Digital Output Low Voltage IOL = 200µA, 2.7V ≤ VDD ≤ 5.5V l0.4 V
TiMing characTerisTics
The l denotes specifications that apply over the full operating temperature range,
otherwise specifications are at TA = 25°C.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VDD = 4.5V to 5.5V
t1SDI Valid to SCK Set-Up l7 ns
t2SDI Valid to SCK Hold l7 ns
t3SCK High Time l11 ns
t4SCK Low Time l11 ns
t5CS/LD Pulse Width l9 ns
t6LSB SCK High to CS/LD High l4 ns
t7CS/LD Low to SCK Positive Edge l4 ns
t8CS/LD High to SCK Positive Edge l4 ns
t9SRO Propagation Delay CLOAD = 10pF l18 ns
t10 CLR Pulse Width Low l36 ns
t11 LDAC Pulse Width Low l15 ns
t12 CLR Low to RFLAG Low CLOAD = 10pF (Note 13) l50 ns
t13 CS/LD High to RFLAG High CLOAD = 10pF (Note 13) l40 ns
SCK Frequency 50% Duty Cycle (Note 14) l40 MHz
VDD = 2.7V to 3.3V
t1SDI Valid to SCK Set-Up l9 ns
t2SDI Valid to SCK Hold l9 ns
t3SCK High Time l15 ns
t4SCK Low Time l15 ns
t5CS/LD Pulse Width l12 ns
t6LSB SCK High to CS/LD High l5 ns
t7CS/LD Low to SCK Positive Edge l5 ns
elecTrical characTerisTics
VDD = 5V, VRINX = 5V unless otherwise specified. The l denotes the
specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
LTC2752
5
2752f
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
t8CS/LD High to SCK Positive Edge l5 ns
t9SRO Propagation Delay CLOAD = 10pF l26 ns
t10 CLR Pulse Width Low l60 ns
t11 LDAC Pulse Width Low l20 ns
t12 CLR Low to RFLAG Low CLOAD = 10pF (Note 13) l70 ns
t13 CS/LD High to RFLAG high CLOAD = 10pF (Note 13) l60 ns
SCK Frequency 50% Duty Cycle (Note 14) l25 MHz
TiMing characTerisTics
The l denotes specifications that apply over the full operating temperature range,
otherwise specifications are at TA = 25°C.
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Continuous operation above the specified maximum operating
junction temperature may impair device reliability.
Note 3: Calculation from feedback resistance and IOUT1 leakage current
specifications; not production tested. In most applications, unipolar zero-
scale error is dominated by contributions from the output amplifier.
Note 4: Input resistors measured from RINX to RCOMX; feedback resistors
measured from RCOMX to REFX.
Note 5: DAC input resistance is independent of code.
Note 6: Parallel combination of the resistances from the specified pin to
IOUT1X and from the specified pin to IOUT2X.
Note 7: Using LT1468 with CFEEDBACK = 27pF. A ±0.0015% settling time
of 1.7μs can be achieved by optimizing the time constant on an individual
basis. See Application Note 74, Component and Measurement Advances
Ensure 16-Bit DAC Settling Time.
Note 8: Measured at the major carry transition, 0V to 5V range. Output
amplifier: LT1468; CFB = 50pF.
Note 9. Full-scale transition; REF = 0V.
Note 10. Analog Crosstalk is defined as the AC voltage ratio VOUTB/VREFA,
expressed in dB. REFB is grounded, and DAC B is set to 0V-5V span and
zero-, mid- or full- scale code. VREFA is a 3VRMS, 1kHz sine wave.
Note 11. REF = 6VRMS at 1kHz. 0V to 5V range. DAC code = FS. Output
amplifier = LT1469.
Note 12. Calculation from Vn = √4kTRB, where k = 1.38E-23 J/°K
(Boltzmann constant), R = resistance (Ω), T = temperature (°K), and
B = bandwidth (Hz). 0V to 5V Range; zero-, mid-, or full- scale.
Note 13. Guaranteed by design, not subject to test.
Note 14. When using SRO, maximum SCK frequency fMAX is limited by
SRO propagation delay t9 as follows:
ft t
MAX
S
=+
( )
1
29
, where tS is the setup time of the receiving device.
LTC2752
6
2752f
TEMPERATURE (°C)
–40
–1.0
DNL (LSB)
–0.8
–0.4
–0.2
0.0
1.0
0.4
–20 20
040
–0.6
0.6
0.8
0.2
60 80
2752 G04
+DNL
–DNL
±10V RANGE
DNL vs Temperature
Gain Error vs Temperature
Bipolar Zero Error vs Temperature
TEMPERATURE (°C)
–40
GE (LSB)
–2
0
2
20 60
2752 G05
–4
–6
–8 –20 0 40
4
6
8
80
±0.25ppm/°C TYP
±2.5V
±5V
±10V
0V TO 5V
0V TO 10V
–2.5V TO 7.5V
TEMPERATURE (°C)
–40
BZE (LSB)
–2
0
2
20 60
2752 G06
–4
–6
–8 –20 0 40
4
6
8
80
±0.15ppm/°C TYP
±2.5V
±5V
±10V
–2.5V TO 7.5V
Typical perForMance characTerisTics
VDD = 5V, VRINX = 5V, TA = 25°C, unless otherwise noted.
TEMPERATURE (°C)
–40
–1.0
INL (LSB)
–0.8
–0.4
–0.2
0.0
1.0
0.4
–20 20
040
–0.6
0.6
0.8
0.2
60 80
2752 G03
+INL
–INL
±10V RANGE
INL vs Temperature
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
CODE
0
–1.0
INL (LSB)
–0.8
–0.4
–0.2
0
1.0
0.4
16384 32768
2752 G01
–0.6
0.6
0.8
0.2
49152 65535
±10V RANGE
CODE
0
–1.0
DNL (LSB)
–0.8
–0.4
–0.2
0
1.0
0.4
16384 32768
2752 G02
–0.6
0.6
0.8
0.2
49152 65535
±10V RANGE
LTC2752
7
2752f
INL vs Reference Voltage
DNL vs Reference Voltage
Typical perForMance characTerisTics
VDD (V)
2.5
–1.0
INL (LSB)
–0.8
–0.4
–0.2
0.0
1.0
0.4
34
3.5 4.5
–0.6
0.6
0.8
0.2
55.5
2752 G09
+INL
–INL
±10V RANGE
INL vs VDD
Multiplying Frequency Response
vs Digital Code
ALL BITS ON
ALL BITS OFF
FREQUENCY (Hz)
100 1k 10k
–140
ATTENUATION (dB)
–100
–120
–60
–80
–40
–20
0
1M100k 10M
2752 G10
0V TO 5V OUTPUT RANGE
LT1468 OUTPUT AMPLIFIER
CFEEDBACK = 15pF
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
VDD = 5V, VRINX = 5V, TA = 25°C, unless otherwise noted.
VDD (V)
2.5
–1.0
DNL (LSB)
–0.8
–0.4
–0.2
0.0
1.0
0.4
34
3.5 4.5
–0.6
0.6
0.8
0.2
55.5
2752 G17
+INL
–INL
±10V RANGE
DNL vs VDD
LTC2752
8
2752f
500ns/DIV
UPD
5V/DIV
GATED
SETTLING
WAVEFORM
100µV/DIV
(AVERAGED)
2752 G14
LT1468 AMP; CFEEDBACK = 20pF
0V TO 10V STEP
VREF = –10V; SPAN CODE = 0000
tSETTLE = 1.7µs to 0.0015% (16 BITS)
Typical perForMance characTerisTics
VDD (V)
2.5
0.5
LOGIC THRESHOLD (V)
0.75
1
1.25
1.5
2
33.5 4 4.5 5 5.5
1.75
2752 G12
RISING
FALLING
Logic Threshold
vs Supply Voltage
Supply Current
vs Logic Input Voltage
Supply Current
vs Clock Frequency
Midscale Glitch (VDD = 3V)
Settling Full-Scale Step
DIGITAL INPUT VOLTAGE (V)
0
SUPPLY CURRENT (mA)
3
4
5
4
2752 G11
2
1
01235
VDD = 5V
CLR,LDAC, SDI, SCK,
CS/LD TIED TOGETHER
VDD = 3V
SCK FREQUENCY (Hz)
1
0.0001
SUPPLY CURRENT (mA)
0.001
0.01
0.1
1
10
100
VDD = 5V
100 10k 1M 100M
2752 G13
VDD = 3V
ALTERNATING ZERO
AND FULL-SCALE
Midscale Glitch (VDD = 5V)
500ns/DIV
CS/LD
5V/DIV
VOUT
5mV/DIV
(AVERAGED)
2752 G15
0V TO 5V RANGE
LT1468 OUTPUT AMPLIFIER
CFEEDBACK = 50pF
FALLING MAJOR CARRY TRANSITION.
RISING TRANSITION IS SIMILAR OR BETTER.
0.6nV•s TYP
500ns/DIV
CS/LD
5V/DIV
VOUT
5mV/DIV
(AVERAGED)
2752 G16
0V TO 5V RANGE
LT1468 OUTPUT AMPLIFIER
CFEEDBACK = 50pF
FALLING MAJOR CARRY TRANSITION.
RISING TRANSITION IS SIMILAR OR BETTER.
2.2nV•s TYP
VDD = 5V, VRINX = 5V, TA = 25°C, unless otherwise noted.
LTC2752
9
2752f
pin FuncTions
REFA (Pins 1, 2): Feedback Resistor for the DAC A Refer-
ence Inverting Amplifier, and Reference Input for DAC A.
The 20k feedback resistor is connected internally from
REFA to RCOMA. For normal operation tie this pin to the
output of the DAC A reference inverting amplifier (see
Typical Applications). Typically –5V; accepts up to ±15V.
Pins 1 and 2 are internally shorted together.
RCOMA (Pin 3): Virtual Ground Point for the DAC A Ref-
erence Amplifier Inverting Resistors. The 20k reference
inverting resistors are connected internally from RINA to
RCOMA and from RCOMA to REFA, respectively (see Block
Diagram). For normal operation tie RCOMA to the negative
input of the external reference inverting amplifier (see
Typical Applications).
GEADJA (Pin 4): Gain Adjust Pin for DAC A. This control
pin can be used to null gain error or to compensate for
reference errors. The gain change expressed in LSB is
the same for any output range. See System Offset and
Gain Adjustments in the Operation section. Tie to ground
if not used.
RINA (Pins 5, 6): Input Resistor for External Reference
Inverting Amplifier. The 20k input resistor is connected
internally from RINA to RCOMA. For normal operation tie
RINA to the external positive reference voltage (see Typical
Applications). Either or both of these precision-matched
resistor sets (each set comprising RINX, RCOMX and REFX)
may be used to invert positive references to provide the
negative voltages needed by the DACs. Typically 5V; accepts
up to ±15V. Pins 5 and 6 are internally shorted together.
GND (Pins 7, 10, 15, 17, 18, 27, 30): Ground; tie to
ground.
IOUT2AS, IOUT2AF (Pins 8, 9): DAC A Current Output
Complement Sense and Force Pins. Tie to ground via a
clean, low-impedance path. These pins may be used with
a precision ground buffer amp as a Kelvin sensing pair
(see the Typical Applications section).
CS/LD (Pin 11): Synchronous Chip Select and Load Input
Pin.
SDI (Pin 12): Serial Data Input. Data is clocked in on the
rising edge of the serial clock (SCK) when CS/LD is low.
SCK (Pin 13): Serial Clock Input.
SRO (Pin 14): Serial Readback Output. Data is clocked out
on the falling edge of SCK. Readback data begins clocking
out after the last address bit A0 is clocked in. SRO is an
active output only when the chip is selected (i.e., when
CS/LD is low). Otherwise SRO presents a high impedance
output in order to allow other parts to control the bus.
VDD (Pin 16): Positive Supply Input; 2.7V ≤ VDD ≤ 5.5V. By-
pass with a 0.1μF low ESR ceramic capacitor to ground.
CLR (Pin 19): Asynchronous Clear Input. When this pin is
low, all DAC registers (both code and span) are cleared to
zero. All DAC outputs are cleared to zero volts.
RFLAG (Pin 20): Reset Flag Output. An active low output
is asserted when there is a power-on reset or a clear event.
Returns high when an Update command is executed.
DNC (Pin 21): Do not connect this pin.
M-SPAN (Pin 22): Manual Span Control Pin. M-SPAN is
used in conjunction with pins S2, S1 and S0 (Pins 25, 24
and 23) to configure all DACs for operation in a single,
fixed output range.
To configure the part for manual span use, tie M-SPAN
directly to VDD. The DAC output range is then set via
hardware pin strapping of pins S2, S1 and S0 (rather than
through the SPI port); and Write and Update commands
have no effect on the active output span.
To configure the part for SoftSpan use, tie M-SPAN directly
to GND. The output ranges are then individually control-
lable through the SPI port; and pins S2, S1 and S0 have
no effect.
See Manual Span Configuration in the Operation section.
M-SPAN must be connected either directly to GND (SoftSpan
configuration) or to VDD (manual span configuration).
S0 (Pin 23): Span Bit 0 Input. In Manual Span mode
(M-SPAN tied to VDD), pins S0, S1 and S2 are pin-strapped
to select a single fixed output range for all DACs. These
pins should be tied to either GND or VDD even if they are
unused.
S1 (Pin 24):
Span Bit 1 Input. In Manual Span mode (M-SPAN
tied to VDD), pins S0, S1 and S2 are pin-strapped to select
a single fixed output range for all DACs. These pins should
be tied to either GND or VDD even if they are unused.
LTC2752
10
2752f
pin FuncTions
S2 (Pin 25): Span Bit 2 Input. In Manual Span mode (M-
SPAN tied to VDD), pins S0, S1 and S2 are pin-strapped
to select a single fixed output range for all DACs. These
pins should be tied to either GND or VDD even if they are
unused.
LDAC (Pin 26): Asynchronous DAC Load Input. When
LDAC is a logic low, all DACs are updated (CS/LD must
be high).
IOUT2BF, IOUT2BS (Pins 28, 29): DAC B Current Output
Complement Force and Sense Pins. Tie to ground via a
clean, low impedance path. These pins may be used with
a precision ground buffer amp as a Kelvin sensing pair
(see the Typical Applications section).
RINB (Pins 31, 32): Input Resistor for the External Reference
Inverting Amplifier. The 20k input resistor is connected
internally from RINB to RCOMB. For normal operation tie
RINB to the external positive reference voltage (see Typical
Applications). Either or both of these precision matched
resistor sets (each set comprising RINX, RCOMX and REFX)
may be used to invert positive references to provide the
negative voltages needed by the DACs. Typically 5V; ac-
cepts up to ±15V. Pins 31 and 32 are internally shorted
together.
GEADJB (Pin 33): Gain Adjust Pin for DAC B. This control
pin can be used to null gain error or to compensate for
reference errors. The gain change expressed in LSB is
the same for any output range. See System Offset and
Gain Adjustments in the Operation section. Tie to ground
if not used.
RCOMB (Pin 34): Virtual Ground Point for the DAC B Ref-
erence Amplifier Inverting Resistors. The 20k reference
inverting resistors are connected internally from RINB to
RCOMB and from RCOMB to REFB, respectively (see Block
Diagram). For normal operation tie RCOMB to the negative
input of the external reference inverting amplifier (see
Typical Applications).
REFB (Pins 35, 36): Feedback Resistor for the DAC B
Reference Inverting Amplifier, and Reference Input for
DAC B. The 20k feedback resistor is connected internally
from REFB to RCOMB. For normal operation tie this pin to
the output of the DAC B reference inverting amplifier (see
Typical Applications). Typically –5V; accepts up to ±15V.
Pins 35 and 36 are internally shorted together.
ROFSB (Pins 37, 38): Bipolar Offset Resistor for DAC B.
These pins provide the translation of the output voltage
range for bipolar spans. Accepts up to ±15V; for normal
operation tie to the positive reference voltage at RINB (Pins
31, 32). Pins 37 and 38 are internally shorted together.
RFBB (Pins 39, 40): DAC B Feedback Resistor. For normal
operation tie to the output of the I/V converter amplifier for
DAC B (see Typical Applications). The DAC output current
from IOUT1B flows through the feedback resistor to the RFBB
pins. Pins 39 and 40 are internally shorted together.
IOUT1B (Pin 41): DAC B Current Output. This pin is a virtual
ground when the DAC is operating and should reside at
0V. For normal operation tie to the negative input of the I/V
converter amplifier for DAC B (see Typical Applications).
VOSADJB (Pin 42): DAC B Offset Adjust Pin. This voltage
control pin can be used to null unipolar offset or bipolar zero
error. The offset change expressed in LSB is the same for
any output range. See System Offset and Gain Adjustments
in the Operation section. Tie to ground if not used.
VOSADJA (Pin 43): DAC A Offset Adjust Pin. This voltage
control pin can be used to null unipolar offset or bipolar zero
error. The offset change expressed in LSB is the same for
any output range. See System Offset and Gain Adjustments
in the Operation section. Tie to ground if not used.
IOUT1A (Pin 44): DAC A Current Output. This pin is a virtual
ground when the DAC is operating and should reside at
0V. For normal operation tie to the negative input of the I/V
converter amplifier for DAC A (see Typical Applications).
RFBA (Pins 45, 46): DAC A Feedback Resistor. For normal
operation tie to the output of the I/V converter amplifier for
DAC A (see Typical Applications). The DAC output current
from IOUT1A flows through the feedback resistor to the RFBA
pins. Pins 45 and 46 are internally shorted together.
ROFSA (Pins 47, 48): Bipolar Offset Resistor for DAC A.
This pin provides the translation of the output voltage
range for bipolar spans. Accepts up to ±15V; for normal
operation tie to the positive reference voltage at RINA (Pins
5, 6). Pins 47 and 48 are internally shorted together.
LTC2752
11
2752f
block DiagraM
16
3
CODE REGISTERS
SPAN REGISTERS
33
34
41
29
42
(37, 38) ROFSB
(35, 36) REFB
(31, 32) RINB
SROSCKSDIS2S1S0M-SPAN CS/LD LDACCLRRFLAG
GEADJB
RCOMB
IOUT1B
IOUT2BS
VOSADJB
(39, 40) RFBB
28
IOUT2BF
9IOUT2AF
26131211192025242322
16
3
CODE REGISTERS
SPAN REGISTERS
DAC REG
DAC REG
4
3
44
8
43
ROFSA (47, 48)
REFA (1, 2)
RINA (5, 6)
GEADJA
RCOMA
IOUT1A
IOUT2AS
VOSADJA
RFBA (45, 46) DAC A
16-BIT WITH
SPAN SELECT
GND (7, 10, 15, 17, 18, 27, 30)
14
VDD
16
INPUT REG
INPUT REG
INPUT REG
INPUT REG
DAC REG
DAC REG
DAC B
16-BIT WITH
SPAN SELECT
CONTROL AND READBACK LOGIC
POWER-ON
RESET
2752 BD
2.56M 2.56M
20k
20k
20k
20k
LTC2752
12
2752f
TiMing DiagraM
SDI
SRO Hi-Z
CS/LD
SCK
LSB 2752 TD
LSB
t2
t9
t8
t5t7
1 2 31 32
t6
t1
LDAC
t3t4
t11
LTC2752
13
2752f
Output Ranges
The LTC2752 is a dual, current-output, serial-input precision
multiplying DAC with selectable output ranges. Ranges
can either be programmed in software for maximum flex-
ibility—each of the DACs can be programmed to any one
of six output ranges—or hardwired through pin-strapping.
Two unipolar ranges are available (0V to 5V and 0V to 10V),
and four bipolar ranges (±2.5V, ±5V, ±10V and –2.5V to
7.5V). These ranges are obtained when an external pre-
cision 5V reference is used. The output ranges for other
reference voltages are easy to calculate by observing that
each range is a multiple of the external reference voltage.
The ranges can then be expressed: 0 to 1×, 0 to 2×, ±0.5×,
±1×, ±2×, and –0.5× to 1.5×.
Manual Span Configuration
Multiple output ranges are not needed in some applica-
tions. To configure the LTC2752 to operate in a single span
without additional operational overhead, tie the M-SPAN
pin directly to VDD. The active output range for all DACs is
then set via hardware pin strapping of pins S2, S1 and S0
(rather than through the SPI port); and Write and Update
commands have no effect on the active output span. See
Figure 1 and Table 3.
Figure 1. Using M-SPAN to Configure the LTC2752
for Single-Span Operation (±10V Range Shown)
LTC2752
M-SPAN
S2
S1
S0
2752 F01
CS/LD SDI SCK
VDD
VDD
DAC A ±10V
±10V
DAC B
–
+
–
+
operaTion
Tie the M-SPAN pin to ground for normal SoftSpan
operation.
Input and DAC Registers
The LTC2752 has 5 internal registers for each DAC, a total
of 10 registers (see Block Diagram). Each DAC channel
has two sets of double-buffered registers—one set for the
code data, and one for the output range of the DAC—plus
one readback register. Double buffering provides the ca-
pability to simultaneously update the span (output range)
and code, which allows smooth voltage transitions when
changing output ranges. It also permits the simultaneous
updating of multiple DACs.
Each set of double-buffered registers comprises an Input
register and a DAC register.
Input register: The Write operation shifts data from the
SDI pin into a chosen Input register. The Input registers
are holding buffers; Write operations do not affect the
DAC outputs.
DAC register: The Update operation copies the contents
of an Input register to its associated DAC register. The
contents of a DAC register directly updates the associated
DAC output voltage or output range.
Note that updates always include both Code and Span
register sets; but the values held in the DAC registers will
only change if the associated Input register values have
previously been changed via a Write operation.
Serial Interface
When the CS/LD pin is taken low, the data on the SDI
pin is loaded into the shift register on the rising edge of
the clock (SCK pin). The minimum (24-bit wide) loading
sequence required for the LTC2752 is a 4-bit command
word (C3 C2 C1 C0), followed by a 4-bit address word
(A3 A2 A1 A0) and 16 data (span or code) bits, MSB first.
Figure 2 shows the SDI input word syntax to use when
LTC2752
14
2752f
writing code or span. If a 32-bit input sequence is used,
the first eight bits must be zeros, followed by the same
sequence as for a 24-bit wide input. Figure 3 shows the
input and readback sequences for both 24-bit and 32-bit
operations.
When CS/LD is low, the SRO pin (Serial Readback Output)
is an active output.The readback data begins after the
command (C3-C0) and address (A3-A0) words have been
shifted into SDI. SRO outputs a logic low (when CS/LD
is low) until the readback data begins. For a 24-bit input
sequence, the 16 readback bits are shifted out on the
falling edges of clocks 8-23, suitable for shifting into a
microprocessor on the rising edges of clocks 9-24. For a
32-bit sequence, the bits are shifted out on clocks 16-31;
see Figure 3b.
When CS/LD is high, the SRO pin presents a high imped-
ance (three-state) output.
LDAC is an asynchronous update pin. When LDAC is
taken low, all DACs are updated with code and span data
(data in the Input buffers is copied into the DAC buffers).
CS/LD must be high during this operation; otherwise
LDAC is locked out and will have no effect. The use of
LDAC is functionally identical to the “Update All DACs”
serial input command.
The codes for the command word (C3-C0) are defined in
Table 1; Table 2 defines the codes for the address word
(A3-A0).
Readback
In addition to the Input and DAC registers, each DAC has
one Readback register associated with it. When a Read
command is issued to a DAC, the contents of one of its
four buffers (Input and DAC registers for each of Span
operaTion
and Code) is copied into its Readback register and seri-
ally shifted out through the SRO pin. Figure 3 shows the
loading and readback sequences.
In the data field (D15-D0) of any non-read instruction cycle,
SRO shifts out the contents of the buffer that was specified
in the preceding command. This “rolling readback” default
mode of operation can dramatically reduce the number
of instruction cycles needed, since any command can be
verified during succeeding commands with no additional
overhead. See Figure 4. Table 1 shows the storage location
(‘readback pointer’) of the data which will be output from
SRO during the next instruction.
For Read commands, the data is shifted out during the Read
instruction itself (on the 16 falling SCK edges immediately
after the last address bit is shifted in on SDI). When check-
ing the span of a DAC using SRO, the span bits are the last
four bits shifted out, corresponding to their sequence and
positions when writing a span. See Figure 3.
Span Readback in Manual Span Configuration
If a Span DAC register is chosen for readback, SRO re-
sponds by outputting the actual output span; this is true
whether the LTC2752 is configured for SoftSpan (M-SPAN
tied to GND) or manual span (M-SPAN tied to VDD) use.
In SoftSpan configuration, SRO outputs the span code
from the Span DAC register (programmed through the
SPI port). In manual span configuration, the active span
is controlled by pins S2, S1 and S0, so SRO outputs the
logic values of these pins. The span code bits S2, S1 and
S0 always appear in the same order and positions in the
SRO output sequence; see Figure 3.
LTC2752
15
2752f
operaTion
C2 C1 C0 A3 A2 A1 A0 D15
MSB
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LSB
C3
(WRITE CODE)
COMMAND WORD ADDRESS WORD 16-BIT CODE
SDI
C2 C1 C0 A3 A2 A1 A0 0 0 0 0 0 0 0 0 0 0 0 0 S3 S2 S1 S0C3
(WRITE SPAN)
COMMAND WORD ADDRESS WORD 12 ZEROS SPAN
2752 F02
Figure 2. Serial Input Write Sequence
LTC2752
16
2752f
operaTion
12345678910 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
C2 C1 C0 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0C300000000
CS/LD
SCK
SDI
COMMAND WORD ADDRESS WORD DAC CODE OR DAC SPAN
32-BIT DATA STREAM
0 0 0 0 0 0 0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0000000000
SRO
t2
t3t4
t1
t9
D15
17
SCK
SDI
SRO D14D15
18
D14
8 ZEROS
Hi-Z
Hi-Z
READBACK CODE
2752 F04
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 S3 S2 S1 S0000000000
SRO
READBACK SPAN
SPAN
12345678910 11 12 13 14 15 16 17 18 19 20 21 22 23 24
C2 C1 C0 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0C3
0 0 0 0 0 0 0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D00
CS/LD
SCK
SDI
SRO Hi-Z
Hi-Z
COMMAND WORD
READBACK CODE
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 S3 S2 S1 S00
SRO
READBACK SPAN
ADDRESS WORD DAC CODE OR DAC SPAN
24-BIT DATA STREAM
2752 F03
SPAN
Figure 3a. 24-Bit Instruction Sequence
Figure 3b. 32-Bit Instruction Sequence
LTC2752
17
2752f
operaTion
Table 1. Command Codes
CODE
COMMAND
READBACK POINTER–
CURRENT INPUT WORD W0
READBACK POINTER–
NEXT INPUT WORD W+1
C3 C2 C1 C0
0 0 1 0 Write Span DAC n Set by Previous Command Input Span Register DAC n
0 0 1 1 Write Code DAC n Set by Previous Command Input Code Register DAC n
0 1 0 0 Update DAC n Set by Previous Command DAC Span Register DAC n
0 1 0 1 Update All DACs Set by Previous Command DAC Code Register DAC n
0 1 1 0 Write Span DAC n
Update DAC n
Set by Previous Command DAC Span Register DAC n
0 1 1 1 Write Code DAC n
Update DAC n
Set by Previous Command DAC Code Register DAC n
1 0 0 0 Write Span DAC n
Update All DACs
Set by Previous Command DAC Span Register DAC n
1 0 0 1 Write Code DAC n
Update All DACs
Set by Previous Command DAC Code Register DAC n
1 0 1 0 Read Input Span Register DAC n Input Span Register DAC n
1 0 1 1 Read Input Code Register DAC n Input Code Register DAC n
1 1 0 0 Read DAC Span Register DAC n DAC Span Register DAC n
1 1 0 1 Read DAC Code Register DAC n DAC Code Register DAC n
1 1 1 1 No Operation Set by Previous Command DAC Code Register DAC n
– System Clear – DAC Span Register DAC A
– Initial Power-Up or Power Interupt – DAC Span Register DAC A
Codes not shown are reserved–do not use
Table 2. Address Codes
A3 A2 A1 A0 n
000
×
DAC A
001
×
DAC B
111
×
All DACs (Note 1)
Codes not shown are reserved–do not use.
×
= Don’t Care.
Note 1. If readback is taken using the All DACs address, the LTC2752
defaults to DAC A.
Table 3. Span Codes
S3 S2 S1 S0 SPAN
0 0 0 0 Unipolar 0V to 5V
0 0 0 1 Unipolar 0V to 10V
0 0 1 0 Bipolar –5V to 5V
0 0 1 1 Bipolar –10V to 10V
0 1 0 0 Bipolar –2.5V to 2.5V
0 1 0 1 Bipolar –2.5V to 7.5V
Codes not shown are reserved–do not use
SDI
SRO ...
WRITE CODE
DAC A
READ
CODE INPUT
REGISTER DAC A
WRITE CODE
DAC B
READ
CODE INPUT
REGISTER DAC B
WRITE SPAN
DAC C
READ
SPAN INPUT
REGISTER DAC A
WRITE SPAN
DAC B
READ
SPAN INPUT
REGISTER DAC B
UPDATE
ALL DACs
READ
CODE DAC
REGISTER DAC A
...
2754 F04
Figure 4. Rolling Readback
LTC2752
18
2752f
a) CS/LD↓ (Note that after power-on, the code in
Input register is zero)
Clock SDI =
0000 0000 0011 0010 1000 0000 0000 0000
b) CS/LD↑
Code Input register- Code of DAC B set to
midscale setting.
c) CS/LD↓
Clock SDI =
0000 0000 0010 0010 0000 0000 0000 0100
Data out on SRO = 1000 0000 0000 0000 Verifies
that Code Input register- DAC B is at midscale
setting.
d) CS/LD↑
Span Input register- Range of DAC B set to
Bipolar ±2.5V range.
e) CS/LD↓
Clock SDI =
0000 0000 1010 0010 XXXX XXXX XXXX XXXX
Data Out on SRO = 0000 0000 0000 0100
Verifies that Span Input register- range of DAC B
set to Bipolar ±2.5V Range.
CS/LD↑
f) CS/LD↓
Clock SDI =
0000 0000 0100 0010 XXXX XXXX XXXX XXXX
g) CS/LD↑
Update DAC B for both Code and Range
h) Alternatively steps f and g could be replaced with
LDAC .
System Offset and Reference Adjustments
Many systems require compensation for overall system
offset. This may be an order of magnitude or more greater
than the offset of the LTC2752, which is so low as to be
dominated by external output amplifier errors even when
using the most precise op amps.
operaTion
Examples
1. Using a 24-bit instruction, load DAC A with the unipolar
range of 0V to 10V, output at zero volts and DAC B with
the bipolar range of ±10V, outputs at zero volts. Note all
DAC outputs should change at the same time.
a) CS/LD↓
Clock SDI = 0010 1111 0000 0000 0000 0011
b) CS/LD↑
Span Input register- Range of all DACs set to
bipolar ±10V
.
c) CS/LD↓
Clock SDI = 0010 0000 0000 0000 0000 0001
d) CS/LD↑
Span Input register- Range of DAC A set to
unipolar 0V to 10V
.
e) CS/LD↓
Clock SDI = 0011 1111 1000 0000 0000 0000
f) CS/LD↑
Code Input register- Code of all DACs set to
midscale.
g) CS/LD↓
Clock SDI = 0011 0000 0000 0000 0000 0000
h) CS/LD↑
Code Input register- Code of DAC A set to
zero code.
i) CS/LD↓
Clock SDI = 0100 1111 XXXX XXXX XXXX XXXX
j) CS/LD↑
Update all DACs for both Code and Range.
k) Alternatively steps i and j could be replaced with
LDAC .
2. Using a 32-bit load sequence, load DAC B with bipolar
±2.5V and its output at zero volts. Use readback to check
Input register contents before updating the DAC output
(i.e., before copying Input register contents into DAC
register).
LTC2752
19
2752f
operaTion
The offset adjust pin VOSADJX can be used to null unipolar
offset or bipolar zero error. The offset change expressed
in LSB is the same for any output range:
∆V LSB V
V
OS VOSADJX
RINX
[ ]
=–• 512
A 5V control voltage applied to VOSADJX produces ∆VOS =
–512 LSB in any output range, assuming a 5V reference
voltage at RINX.
In voltage terms, the offset delta is attenuated by a factor
of 32, 64 or 128, depending on the output range. (These
functions hold regardless of reference voltage.)
∆VOS = –(1/128)VOSADJX [0V to 5V, ±2.5V spans]
∆VOS = –(1/64)VOSADJX [0V to 10V, ±5V, –2.5V to
7.5V spans]
∆VOS = –(1/32)VOSADJX [±10V span]
The gain error adjust pins GEADJX can be used to null
gain error or to compensate for reference errors. The
gain error change expressed in LSB is the same for any
output range:
∆GE V
V
GEADJX
RINX
=• 512
The gain-error delta is non-inverting for positive reference
voltages.
Note that this pin compensates the gain by altering the
inverted reference voltage VREFX. In voltage terms, the VREFX
delta is inverted and attenuated by a factor of 128.
∆VREFX = –(1/128)GEADJX
The nominal input range of these pins is ±5V; other volt-
ages of up to ±15V may be used if needed. However, do
not use voltages divided down from power supplies; ref-
erence-quality, low-noise inputs are required to maintain
the best DAC performance.
The VOSADJX pins have an input impedance of 1.28MΩ.
These pins should be driven with a Thevenin-equivalent
impedance of 10k or less to preserve the settling perfor-
mance of the LTC2752. They should be shorted to GND
if not used.
The GEADJX pins have an input impedance of 2.56MΩ, and
are intended for use with fixed reference voltages only.
They should be shorted to GND if not used.
Power-On Reset and Clear
When power is first applied to the LTC2752, all DACs
power-up in unipolar 5V mode (S3 S2 S1 S0 = 0000). All
internal DAC registers are reset to 0 and the DAC outputs
initialize to zero volts.
If the part is configured for manual span operation, all
DACs will be set into the pin-strapped range at the first
Update command. This allows the user to simultaneously
update span and code for a smooth voltage transition into
the chosen output range.
When the CLR pin is taken low, a system clear results.
The DAC buffers are reset to 0 and the DAC outputs are
all reset to zero volts. The Input buffers are left intact, so
that any subsequent Update command (including the use
of LDAC) restores the addressed DACs to their respective
previous states.
If CLR is asserted during an instruction, i.e., when CS/LD
is low, the instruction is aborted. Integrity of the relevant
Input buffers is not guaranteed under these conditions,
therefore the contents should be checked using readback
or replaced.
The RFLAG pin is used as a flag to notify the system of a
loss of data integrity. The RFLAG output is asserted low
at power-up, system clear, or if the supply VDD dips below
approximately 2V; and stays asserted until any valid Update
command is executed.
LTC2752
20
2752f
applicaTions inForMaTion
Op Amp Selection
Because of the extremely high accuracy of the 16-bit
LTC2752, careful thought should be given to op amp
selection in order to achieve the exceptional performance
of which the part is capable. Fortunately, the sensitivity of
INL and DNL to op amp offset has been greatly reduced
compared to previous generations of multiplying DACs.
Tables 4 and 5 contain equations for evaluating the ef-
fects of op amp parameters on the LTC2752’s accuracy
when programmed in a unipolar or bipolar output range.
These are the changes the op amp can cause to the INL,
DNL, unipolar offset, unipolar gain error, bipolar zero and
bipolar gain error.
Table 6 contains a partial list of Linear Technology preci-
sion op amps recommended for use with the LTC2752.
The easy-to-use design equations simplify the selection
of op amps to meet the system’s specified error budget.
Select the amplifier from Table 6 and insert the specified
op amp parameters in Table 5. Add up all the errors for
each category to determine the effect the op amp has on
the accuracy of the part. Arithmetic summation gives an
(unlikely) worst-case effect. A root-sum-square (RMS)
summation produces a more realistic estimate.
Table 4. Coefficients for the Equations of Table 5
OUTPUT RANGE A1 A2 A3 A4 A5
5V 1.1 2 1 1
10V 2.2 3 0.5 1.5
±5V 2 2 1 1 1.5
±10V 4 4 0.83 1 2.5
±2.5V 1 1 1.4 1 1
–2.5V to 7.5V 1.9 3 0.7 0.5 1.5
A3 • VOS1 • 19.6 •
IB1 • 0.13 •
0
A4 • VOS2 • 13.1 •
A4 • IB2 • 0.13 •
A4 •
5V
VREF
5V
VREF
16.5
AVOL1
VOS1 (mV)
IB1 (nA)
AVOL1 (V/mV)
VOS2 (mV)
IB2 (nA)
AVOL2 (V/mV)
OP AMP
VOS1 • 3 •
IB1 • 0.0003 •
A1 •
0
0
0
INL (LSB)
5V
VREF
5V
VREF
1.5
AVOL1
66
AVOL2
131
AVOL1
131
AVOL1
131
AVOL2
131
AVOL2
VOS1 • 0.78 •
IB1 • 0.00008 •
A2 •
0
0
0
DNL (LSB)
5V
VREF
5V
VREF
A3 • VOS1 • 13.1 •
IB1 • 0.13 •
0
0
0
0
UNIPOLAR
OFFSET (LSB)
5V
VREF
5V
VREF
5V
VREF
VOS1 • 13.1 •
IB1 • 0.0018 •
A5 •
VOS2 • 26.2 •
IB2 • 0.26 •
BIPOLAR GAIN
ERROR (LSB)
5V
VREF
5V
VREF
5V
VREF
5V
VREF
BIPOLAR ZERO
ERROR (LSB)
UNIPOLAR GAIN
ERROR (LSB)
5V
VREF
5V
VREF
5V
VREF
5V
VREF
5V
VREF
VOS1 • 13.1 •
IB1 • 0.0018 •
A5 •
VOS2 • 26.2 •
IB2 • 0.26 •
Table 5. Easy-to-Use Equations Determine Op Amp Effects on DAC Accuracy in All Output Ranges (Circuit of Page 1). Subscript 1
Refers to Output Amp, Subscript 2 Refers to Reference Inverting Amp.
Table 6. Partial List of LTC Precision Amplifiers Recommended for Use with the LTC2752 with Relevant Specifications
AMPLIFIER
AMPLIFIER SPECIFICATIONS
VOS
µV
IB
nA
AVOL
V/mV
VOLTAGE
NOISE
nV/√Hz
CURRENT
NOISE
pA/√Hz
SLEW
RATE
V/µs
GAIN BANDWIDTH
PRODUCT
MHz
tSETTLING
with LTC2752
µs
POWER
DISSIPATION
mW
LT1001 25 2 800 10 0.12 0.25 0.8 120 46
LT1097 50 0.35 1000 14 0.008 0.2 0.7 120 11
LT1112 (Dual) 60 0.25 1500 14 0.008 0.16 0.75 115 10.5/Op Amp
LT1124 (Dual) 70 20 4000 2.7 0.3 4.5 12.5 19 69/Op Amp
LT1468 75 10 5000 5 0.6 22 90 2 117
LT1469 (Dual) 125 10 2000 5 0.6 22 90 2 123/Op Amp
LTC2752
21
2752f
applicaTions inForMaTion
Op amp offset will contribute mostly to output offset and
gain error, and has minimal effect on INL and DNL. For
example, for the LTC2752 with a 5V reference in 5V unipolar
mode, a 250µV op amp offset will cause a 3.3LSB zero-
scale error and a 3.3LSB gain error; but only 0.75LSB of
INL degradation and 0.2LSB of DNL degradation.
While not directly addressed by the simple equations in
Tables 4 and 5, temperature effects can be handled just
as easily for unipolar and bipolar applications. First, con-
sult an op amp’s data sheet to find the worst-case VOS
and IB over temperature. Then, plug these numbers into
the VOS and IB equations from Table 5 and calculate the
temperature-induced effects.
For applications where fast settling time is important, Ap-
plication Note 74, Component and Measurement Advances
Ensure 16-Bit DAC Settling Time, offers a thorough discus-
sion of 16-bit DAC settling time and op amp selection.
Precision Voltage Reference Considerations
Much in the same way selecting an operational amplifier
for use with the LTC2752 is critical to the performance of
the system, selecting a precision voltage reference also
requires due diligence. The output voltage of the LTC2752
is directly affected by the voltage reference; thus, any
voltage reference error will appear as a DAC output volt-
age error.
There are three primary error sources to consider
when selecting a precision voltage reference for 16-bit
applications: output voltage initial tolerance, output voltage
temperature coefficient and output voltage noise.
Initial reference output voltage tolerance, if uncorrected,
generates a full-scale error term. Choosing a reference
with low output voltage initial tolerance, like the LT1236
(±0.05%), minimizes the gain error caused by the reference;
however, a calibration sequence that corrects for system
zero- and full-scale error is always recommended.
A reference’s output voltage temperature coefficient af-
fects not only the full-scale error, but can also affect the
circuit’s apparent INL and DNL performance. If a refer-
ence is chosen with a loose output voltage temperature
coefficient, then the DAC output voltage along its transfer
characteristic will be very dependent on ambient conditions.
Minimizing the error due to reference temperature coef-
ficient can be achieved by choosing a precision reference
with a low output voltage temperature coefficient and/or
tightly controlling the ambient temperature of the circuit
to minimize temperature gradients.
As precision DAC applications move to 16-bit and higher
performance, reference output voltage noise may contrib-
ute a dominant share of the system’s noise floor. This in
turn can degrade system dynamic range and signal-to-noise
ratio. Care should be exercised in selecting a voltage refer-
ence with as low an output noise voltage as practical for the
system resolution desired. Precision voltage references,
like the LT1236 and LTC6655, produce low output noise in
the 0.1Hz to 10Hz region, well below the 16-bit LSB level
Table 7. Partial List of LTC Precision References Recommended
for Use with the LTC2752 with Relevant Specifications
REFERENCE
INITIAL
TOLERANCE
TEMPERATURE
DRIFT
0.1Hz to 10Hz
NOISE
LT1019A-5,
LT1019A-10
±0.05% Max 5ppm/°C Max 12µVP-P
LT1236A-5,
LT1236A-10
±0.05% Max 5ppm/°C Max 3µVP-P
LT1460A-5,
LT1460A-10
±0.075% Max 10ppm/°C Max 20µVP-P
LT1790A-2.5 ±0.05% Max 10ppm/°C Max 12µVP-P
LTC6652A-2.048 ±0.05% Max 5ppm/°C Max 2.1ppmP-P
LTC6652A-2.5 2.1ppmP-P
LTC6652A-3 2.1ppmP-P
LTC6652A-3.3 2.2ppmP-P
LTC6652A-4.096 2.3ppmP-P
LTC6652A-5 2.8ppmP-P
LT6655A-25,
LT6655A-5
±0.025% Max 2ppm/°C Max 0.25ppmP-P
LTC2752
22
2752f
in 5V or 10V full-scale systems. However, as the circuit
bandwidths increase, filtering the output of the reference
may be required to minimize output noise.
Grounding
As with any high resolution converter, clean grounding
is important. A low impedance analog ground plane is
necessary, as are star grounding techniques. Keep the
board layer used for star ground continuous to minimize
ground resistances; that is, use the star-ground concept
without using separate star traces. The IOUT2 pins are
of particular concern; INL will be degraded by the code
dependent currents carried by the IOUT2XF and IOUT2XS
pins if voltage drops to ground are allowed to develop.
applicaTions inForMaTion
The best strategy here is to tie the pins to the star ground
plane by multiple vias located directly underneath the part.
Alternatively, the pins may be routed to the star ground
point if necessary; join the force and sense pins together
at the part and route one trace for each channel of no more
than 120 squares of 1oz. copper.
In the rare case in which neither of these alternatives is
practicable, a force/sense amplifier should be used as a
ground buffer (see Typical Applications). Note, however,
that the voltage offset of the ground buffer amp directly
contributes to the effects on accuracy specified in Table
5 under VOS1. The combined effects of the offsets can be
calculated by substituting the total offset from IOUT1X to
IOUT2XS for VOS1 in the equations.
Figure 5. Optional Circuits for Driving IOUT2 from GND with a Force/Sense Amplifier
–
+
–
+
1/2 LT1469
1/2 LT1469
DAC A
LTC2752
VREF
5V
2
1
3
44
45, 46
47, 48
5, 6
4
3
1
1, 2
IOUT1A
15pF
IOUT2A
RFBA
VOSADJA
REFA
RCOMA
RINA
ROFSA
VOUTA
8, 9
43
2752 F05
150pF
3
2
DAC B –
+
GEADJA
–
+
69
8
1
2 3
IOUT2AF
IOUT2AS
2
3
*SCHOTTKY BARRIER DIODE
ZETEX*
BAT54S
LT1012
1000pF
ALTERNATE AMPLIFIER FOR OPTIMUM SETTLING TIME PERFORMANCE
69
1
2 3
8
–
+
LT1468
3
ZETEX
BAT54S
2
200Ω
200Ω
IOUT2AS
IOUT2AF
LTC2752
23
2752f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
package DescripTion
LX48 LQFP 0907 REVØ
0° – 7°
11° – 13°
0.45 – 0.75
1.00 REF
11° – 13°
9.00 BSC
A A
7.00 BSC
1
2
7.00 BSC
9.00 BSC
48
1.60
MAX
1.35 – 1.45
0.05 – 0.150.09 – 0.20 0.50
BSC 0.17 – 0.27
GAUGE PLANE
0.25
NOTE:
1. PACKAGE DIMENSIONS CONFORM TO JEDEC #MS-026 PACKAGE OUTLINE
2. DIMENSIONS ARE IN MILLIMETERS
3. DIMENSIONS OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.25mm ON ANY SIDE, IF PRESENT
4. PIN-1 INDENTIFIER IS A MOLDED INDENTATION, 0.50mm DIAMETER
5. DRAWING IS NOT TO SCALE
SEE NOTE: 4
C0.30 – 0.50
R0.08 – 0.20
7.15 – 7.25
5.50 REF
1
2
5.50 REF
7.15 – 7.25
48
PACKAGE OUTLINE
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
SECTION A – A
0.50 BSC
0.20 – 0.30
1.30 MIN
LX Package
48-Lead Plastic LQFP (7mm × 7mm)
(Reference LTC DWG # 05-08-1760 Rev Ø)
LTC2752
24
2752f
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
LINEAR TECHNOLOGY CORPORATION 2010
LT 0510 • PRINTED IN USA
relaTeD parTs
Typical applicaTion
ROFSA
47, 48 5, 6
45, 46
39, 40
RINA REFA
1, 2
RCOMA
3
ROFSB RCOMB REFB
37, 38
11 12 13 14 31, 32 34 35, 36
C5
100pF
2752 TA02
VOUT DACB
LT1012A
LT1012A
15V
–15V
–
+
76
3
2
4
2
3
4
76
IOUT2B
GND
28, 29
7, 10, 15, 17, 18, 27, 30
C4
27pF 15V
–15V
IOUT1B
RFBB
41
+
–
VOSADJA
GEADJA
–15V
15V
–
+
76
3
2
4
LTC2752
RINB
26
VDD
VOSADJB
GEADJB
5V REFERENCE
16
4
43
33
42
M-SPAN
22
S0
23
S1
24
S2
25
SDI
CS/LD SCK SRO
SDI
CS1SCK SRO
LDAC
19
CLR
LT1236-5
IN OUT
4
62
15V
CS2
SDISPI BUS
SCK
4
6
5
C2
0.1µF
C7
10µF
C6
10µF 10k 10k
REF
VOUTA
VOUTB
VOUTC
VOUTD
2
3
8
9
VCC
10, 11
GND
LTC2634-MSELMX12
71
C1
100pF
VOUT DACA
2
3
4
76
IOUT2A 8, 9
C3
27pF 15V
–15V
IOUT1A
RFBA
44
+
–
LT1468
LT1468
CS/LD
SDI
SCK
SPI BUS
10
7
4
16
+
–
LT1991
450k
450k
450k
10
16
LT1991
10
16
LT1991
10
16
LT1991
15V
–15V
Digitally Controlled Offset and Gain Trim Circuit. Powering VDD from LT1236 Ensures Quiet Supply
PART NUMBER DESCRIPTION COMMENTS
LTC2757 Single Parallel 18-Bit IOUT SoftSpan DAC ±1LSB INL/DNL, Software-Selectable Ranges, 7mm × 7mm LQFP-48 Package
LTC2754 Quad Serial 16-Bit/12-Bit IOUT SoftSpan DACs ±1LSB INL/DNL, Software-Selectable Ranges, 7mm × 8mm QFN-52 Package
LTC2751 Single Parallel 16-Bit/14-Bit/12-Bit IOUT SoftSpan DAC ±1LSB INL/DNL, Software-Selectable Ranges, 5mm × 7mm QFN-38 Package
LTC2753 Dual Parallel 16-Bit/14-Bit/12-Bit IOUT SoftSpan DACs ±1LSB INL/DNL, Software-Selectable Ranges, 7mm × 7mm QFN-48 Package
LTC2755 Quad Parallel 16-Bit/14-Bit/12-Bit IOUT SoftSpan DACs ±1LSB INL/DNL, Software-Selectable Ranges, 9mm × 9mm QFN-64 Package
LTC1590 Dual Serial 12-Bit Multiplying IOUT DAC ± 0.5LSB INL/DNL 2-Quadrant, 16-Pin Narrow SO and PDIP Packages
LTC1592 Single Serial 16-Bit/14-Bit/12-Bit IOUT SoftSpan DAC ±1LSB INL/DNL, Software-Selectable Ranges, 16-Lead SSOP Package
LTC1591/LTC1597 Single Parallel 16-Bit/14-Bit IOUT DACs ±1LSB INL/DNL, Integrated 4-Quadrant Resistors, 28-Lead SSOP Package
LTC2704 Quad Serial 16-Bit/14-Bit/12-Bit VOUT SoftSpan DACs ±1LSB INL/DNL, Software-Selectable Ranges, Integrated Amplifiers
References
LTC6655 Precision Reference 0.025% Maximum Tolerance, 0.25ppmP-P 0.1Hz to 10Hz Noise
LT1027 Precision Reference 2ppm/°C Maximum Drift
LT1236A-5 Precision Reference 0.05% Maximum Tolerance, 1ppmP-P 0.1Hz to 10Hz Noise
Amplifiers
LT1012 Precision Operational Amplifier 25µV Max Offset, 100pA Max Bias Current, 0.5µVP-P Noise, 380µA Supply
Current
LT1001 Precision Operational Amplifier 25µV Max Offset, 0.3µVP-P Noise, High Output Drive
LT1468/LT1469 Single/Dual 16-Bit Accurate Op-Amp 90MHz GBW, 22V/μs Slew Rate, 0.3µVP-P Noise