F Semiconductor March 1997 82C84A CMOS Clock Generator Driver Features * Generates the System Clock For CMOS or NMOS Microprocessors Up to 25MHz Operation * Uses a Parallel Mode Crystal Circuit or External Frequency Source * Provides Ready Synchronization * Generates System Reset Output From Schmitt Trigger Input TTL Compatible Inputs/Outputs * Very Low Power Consumption * Single 5V Power Supply Description The Harris 82C84A is a high performance CMOS Clock Generator- driver which is designed to service the requirements of both CMOS and NMOS microprocessors such as the 80C86, 80C88, 8086 and the 8088. The chip contains a crystal controlled oscillator, a divide-by- three counter and complete Ready synchronization and reset logic. Static CMOS circuit design permits operation with an external fre- quency source from DC to 25MHz. Crystal controlled operation to 25MHz is guaranteed with the use of a parallel, fundamental mode crystal and two small load capacitors. All inputs (except X1 and RES) are TTL compatible over tempera- ture and voltage ranges. Power consumption is a fraction of that of the equivalent bipolar cir- cuits. This speed-power characteristic of CMOS permits the designer to custom tailor his system design with respect to power and/or speed requirements. Copyright Harris Corporation 1997 * Operating Temperature Ranges Ordering Information - C82CB84A.. 1... ee eee eee 0C to +70C PART PKG. - IB2CB84A. ees -40C to +85C NUMBER _ PACKAGE NO. - M82C84A..........2--2---e eee -55C to +1259 = FCP 82C84A OCto+70C JIStd PDIP LENS. IP82C84A -40C to +85C E18.3 CS82C84A 0C to +70C 20 Ld PLCC N20.35 IS82C84A -40C to +85C N20.35 CD82C84A 0C to +70C 18 Ld CERDIP | F18.3 ID82C84A -40C to +85C F18.3 MD82C84A/B -55C to +125C F18.3 8406801VA SMD# F18.3 MR82C84A/B -55C to +125C +} 20 Pad CLCC |J20.A 84068012A SMD# J20.A Pinouts 82C84A (PDIP, CERDIP) 82C84A (PLCC, CLCC) TOP VIEW TOP VIEW VU csync [7 18] Voc POLK [2] 7] x1 AEN [3 16] x2 AEN fF 6] x2 RDY1 [4] 5] ASYNC SYNE READY [5 14] EFI EFI RDY2 [] 3] F/C FG AEN2 [7] 2] osc NC cLk [8 11] RES Viet at GND [e Ho} RESET CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. File Number 2974.1 4-28782C84A Functional Diagram 11 17 16 XTAL OSCILLATOR 10 p RESET P PCLK RDY2 - ct aK AEN2 D Q D FFA FF2 _ 15 ASYNC CONTROL PIN LOGICAL 1 LOGICAL 0 FIC External Clock Crystal Drive RES Normal Reset RDY1, RDY2 Bus Ready Bus Not Ready AEN1, AEN2 Address Disabled Address Enable ASYNC 1 Stage Ready 2 Stage Ready 5 > READY Synchronization Synchronization 4-28882C84A Pin Description SYMBOL | NUMBER TYPE DESCRIPTION AEN1, 3,7 I ADDRESS ENABLE: AEN is an active LOW signal. AEN serves to qualify its respective Bus AEN2 Ready Signal (RDY1 or RDY2). AEN1 validates RDY1 while AEN2 validates RDY2. Two AEN signal inputs are useful in system configurations which permit the processor to access two Multi- Master System Busses. In non-Multi-Master configurations, the AEN signal inputs are tied true (LOW). RDY1, 4,6 BUS READY (Transfer Complete). RDY is an active HIGH signal which is an indication from a RDY2 device located on the system data bus that data has been received, or is available RDY 1 is qual- ified by AEN1 while RDY2 is qualified by AEN2. ASYNG 15 READY SYNCHRONIZATION SELECT: ASYNC is an input which defines the synchronization mode of the READY logic. When ASYNC is low, two stages of READY synchronization are pro- vided. When ASYNC is left open or HIGH, a single stage of READY synchronization is provided. READY 5 Oo READY: READY is an active HIGH signal which is the synchronized RDY signal input. READY is cleared after the guaranteed hold time to the processor has been met. X1, X2 17,16 10 CRYSTAL IN: X1 and X2 are the pins to which a crystal is attached. The crystal frequency is 3 times the desired processor clock frequency, (Note 1). FIC 13 FREQUENCY/CRYSTAL SELECT: F/C is a strapping option. When strapped LOW. F/C permits the processor's clock to be generated by the crystal. When F/C is strapped HIGH, CLK is gen- erated for the EFI input, (Note 1). EFI 14 EXTERNAL FREQUENCY IN: When F/C is strapped HIGH, CLK is generated from the input fre- quency appearing on this pin. The input signal is a square wave 3 times the frequency of the de- sired CLK output. CLK 8 oO PROCESSOR CLOCK: CLK is the clock output used by the processor and all devices which di- rectly connect to the processors local bus. CLK has an output frequency which is 1/3 of the crys- tal or EFI input frequency and a 1/3 duty cycle. PCLK 2 Oo PERIPHERAL CLOCK: PCLK is a peripheral clock signal whose output frequency is 1/2 that of CLK and has a 50% duty cycle. OSC 12 oO OSCILLATOR OUTPUT: OSC is the output of the internal oscillator circuitry. Its frequency is equal to that of the crystal. RES 11 RESET IN: RES is an active LOW signal which is used to generate RESET. The 82C84A pro- vides a Schmitt trigger input so that an RC connection can be used to establish the power-up reset of proper duration. RESET 10 oO RESET: RESET is an active HIGH signal which is used to reset the 80C86 family processors. Its timing characteristics are determined by RES. CSYNG 1 CLOCK SYNCHRONIZATION: CSYNC is an active HIGH signal which allows multiple 82C84As to be synchronized to provide clocks that are in phase. When CSYNC is HIGH the internal counters are reset. When CSYNC goes LOW the internal counters are allowed to resume count- ing. CSYNC needs to be externally synchronized to EFI. When using the internal oscillator CSYNC should be hardwired to ground. GND 9 Ground Vec 18 Vcc: The +5V power supply pin. A 0.1,F capacitor between Vcc and GND is recommended for decoupling. NOTE: 1. If the crystal inputs are not used X1 must be tied to Vcc or GND and X2 should be left open. 4-28982C84A Functional Description Oscillator The oscillator circuit of the 82C84A is designed primarily for use with an external parallel resonant, fundamental mode crystal from which the basic operating frequency is derived. The crystal frequency should be selected at three times the required CPU clock. X1 and X2 are the two crystal input crystal connections. For the most stable operation of the oscillator (OSC) output circuit, two capacitors (C1 = C2) as shown in the waveform figures are recommended. The out- put of the oscillator is buffered and brought out on OSC so that other system timing signals can be derived from this sta- ble, crystal-controlled source. TABLE 1. CRYSTAL SPECIFICATIONS Clock Outputs The CLK output is a 33% duty cycle clock driver designed to drive the 80C86, 80C88 processors directly. PCLK is a periph- eral clock signal whose output frequency is 1/2 that of CLK. PCLK has a 50% duty cycle. Reset Logic The reset logic provides a Schmitt trigger input (RES) and a synchronizing flip-flop to generate the reset timing. The reset signal is synchronized to the falling edge of CLK. A simple RC network can be used to provide power-on reset by utilizing this function of the 82C84A. READY Synchronization Two READY input (RDY1, RDY2) are provided to accommo- date two system busses. Each input has a qualifier (AEN1 and AEN2, respectively). The AEN signals validate their respective RDY signals. If a Multi-Master system is not being used the PARAMETER TYPICAL CRYSTAL SPEC Frequency 2.4 - 25MHz, Fundamental, AT cut Type of Operation Parallel Unwanted Modes 6dB (Minimum) Load Capacitance 18 - 32pF Capacitors C1, C2 are chosen such that their combined capacitance C1 x C2 C14+C2 CT= (Including stray capacitance) matches the load capacitance as specified by the crystal manufacturer. This ensures operation within the frequency tolerance specified by the crystal manufacturer. Clock Generator The clock generator consists of a synchronous divide-by- three counter with a special clear input that inhibits the counting. This clear input (CSYNC) allows the output clock to be synchronized with an external event (such as another 82C84A clock). It is necessary to synchronize the CSYNC input to the EFI clock external to the 82C84A. This is accom- plished with two flip-flops. (See Figure 1). The counter out- put is a 33% duty cycle clock at one-third the input frequency. NOTE: The F/C input is a strapping pin that selects either the crystal oscillator or the EFI input as the clock for the + 3 counter. If the EFI input is selected as the clock source, the oscillator section can be used independently for another clock source. Output is taken from OSC. AEN pin should be tied LOW. Synchronization is required for all asynchronous active-going edges of either RDY input to guarantee that the RDY setup and hold times are met. Inactive-going edges of RDY in nor- mally ready systems do not require synchronization but must satisfy RDY setup and hold as a matter of proper system design. The ASYNC input defines two modes of READY synchroniza- tion operation. When ASYNC is LOW, two stages of synchronization are pro- vided for active READY input signals. Positive-going asynchro- nous READY inputs will first be synchronized to flip-flop one of the rising edge of CLK (requiring a setup time tR1VCH) and the synchronized to flip-flop two at the next falling edge of CLK, after which time the READY output will go active (HIGH). Negative-going asynchronous READY inputs will be synchro- nized directly to flip-flop two at the falling edge of CLK, after which the READY output will go inactive. This mode of opera- tion is intended for use by asynchronous (normally not ready) devices in the system which cannot be guaranteed by design to meet the required RDY setup timing, TR1VCL, on each bus cycle. When ASYNC is high or left open, the first READY flip-flop is bypassed in the READY synchronization logic. READY inputs are synchronized by flip-flop two on the falling edge of CLK before they are presented to the processor. This mode is avail- able for synchronous devices that can be guaranteed to meet the required RDY setup time. ASYNC can be changed on every bus cycle to select the appropriate mode of synchronization for each device in the system. CLOCK 5 D Q SYNCHRONIZE EFl > (TO OTHER 82C84As) NOTE: If EFl input is used, then crystal input X1 must be tied to Voc or GND and X2 should be left open. If the crystal inputs are used, then EFI should be tied to Vac or GND. FIGURE 1. CSYNC SYNCHRONIZATION 4-29082C84A Absolute Maximum Ratings Supply Voltage... eee +8.0V Input, Output or I/O Voltage ........... GND -0.5V to Vcc +0.5V ESD Classification ............0.. 0.000000. e eee Class 1 Operating Conditions Operating Voltage Range Operating Temperature Range +4.5V to +5.5V C82C84A 26. eee 0C to +70C I82C84A 00 eee -40C to +85C M82C84A .. 0. eee -55C to +125C Thermal Information Thermal Resistance Oya (C/W) 8yc (CCW) CERDIP Package ................ 80 20 CLCC Package .................. 95 28 PDIP Package................... 85 N/A PLCC Package .................. 85 N/A Storage Temperature Range.................. -65C to +150C Max Junction Temperature ..................0.0.000. +175C Lead Temperature (Soldering 10s).................... +300C (PLCC - Lead Tips Only) Die Characteristics Gate Count... 0... eee 50 Gates CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. DC Electrical Specifications Vcc = +5.0V +10%, Ta = 0C to +70C (C82C84A), Ta = -40C to +85C (182C84A), Ta = -55C to +125C (M82C84A) SYMBOL PARAMETER MIN MAX UNITS TEST CONDITIONS Vin Logical One Input Voltage 2.0 - Vv C82C84A, 182084 2.2 Vv M82C84<A, Notes 1, 2 VIL Logical Zero Input Voltage - 0.8 v Notes 1, 2,3 VIHR Reset Input High Voltage Vec -0.8 - v VILR Reset Input Low Voltage - 0.5 v VT+ - VT- | Reset Input Hysteresis 0.2 Vcc - - VoH Logical One Output Current Voc -0.4 - v loH = -4.0mA for CLK Output IOH = -2.5mA for All Others VoL Logical Zero Output Voltage - 0.4 v lot = +4.0mA for CLK Output lo, = +2.5mA for All Others II Input Leakage Current -1.0 1.0 LA Vin = Vcc or GND except ASYNC, X1: (Note 4) lecop | Operating Power Supply Current - 40 mA Crystal Frequency = 25MHz Outputs Open, Note 5 NOTES: 1. F/C is a strap option and should be held either < 0.8V or > 2.2V. Does not apply to X1 or X2 pins. 2. guaranteed. 3. CSYNC pin is tested with Vj, <0.8V. Due to test equipment limitations related to noise, the actual tested value may differ from that specified, but the specified limit is 4. ASYNC pin includes an internal 17.5kQ nominal pull-up resistor. For ASYNC input at GND, ASYNC input leakage current = 300uA nominal, X1 - crystal feedback input. 5. f= 25MHz may be tested using the extrapolated value based on measurements taken at f = 2MHz and f = 10MHz. Capacitance Ta = +25C SYMBOL PARAMETER TYPICAL UNITS TEST CONDITIONS CIN Input Capacitance 10 pF FREQ = 1MHz, all measurements are referenced to device GND CouT Output Capacitance 15 pF 4-29182C84A AC Electrical Specifications Vcc = +5V+ 10%, Ta = 0C to +70C (C82C84A), Ta = -40C to +85C (182C84A), Ta = -55C to +125C (M82C84A) LIMITS (NOTE 1) TEST SYMBOL PARAMETER MIN MAX UNITS CONDITIONS TIMING REQUIREMENTS (1) TEHEL External Frequency HIGH Time 13 - ns 90%-90% Vin (2) TELEH External Frequency LOW Time 13 - ns 10%-10% Vin (3) TELEL EFI Period 36 - ns XTAL Frequency 2.4 25 MHz Note 2 (4) TR2VCL RDY1, RDY2 Active Setup to CLK 35 - ns ASYNC = HIGH (5) TRIVCH RDY1, RDY2 Active Setup to CLK 35 - ns ASYNC = LOW (6) TRIVCL RDY1, RDY2 Inactive Setup to CLK 35 - ns (7) TCLR1X RDY1, RDY2 Hold to CLK 0 - ns (8) TAYVCL ASYNC Setup to CLK 50 - ns (9) TCLAYX ASYNC Hold to CLK 0 - ns (10) TAIVR1V AENT, AEN2 Setup to RDY1, RDY2 15 - ns (11) TCLA1X AENT, AEN2 Hold to CLK 0 - ns (12) TYHEH CSYNC Setup to EFI 20 - ns (13) TEHYL CSYNC Hold to EFI 20 - ns (14) TYHYL CSYNC Width 2 TELEL - ns (15) TIWHCOL RES Setup to CLK 65 - ns Note 3 (16) TCLITH RES Hold to CLK 20 - ns Note 3 TIMING RESPONSES (17) TCLCOL CLK Cycle Period 125 - ns Note 6 (18) TCHCL CLK HIGH Time (1/3 TCLCL) +2.0 - ns Note 6 (19) TCLCH CLK LOW Time (2/3 TCLCL) -15.0 - ns Note 6 (20) TCH1CH2 CLK Rise or Fall Time - 10 ns 1.0V to 3.0V (21) TCL2CL1 (22) TPHPL PCLK HIGH Time TCLCL-20 - ns Note 6 (23) TPLPH PCLK LOW Time TCLCL-20 - ns Note 6 (24) TRYLCL Ready Inactive to CLK (See Note 4) -8 - ns Note 4 (25) TRYHCH Ready Active to CLK (See Note 3) (2/3 TCLCL) -15.0 - ns Note 5 (26) TCLIL CLK to Reset Delay - 40 ns (27) TCLPH CLK to PCLK HIGH Delay - 22 ns (28) TCLPL CLK to PCLK LOW Delay - 22 ns (29) TOLCH OSC to CLK HIGH Delay 5 22 ns (30) TOLCL OSC to CLK LOW Delay 2 35 ns NOTES: 1. Tested as follows: f = 2.4MHz, Viy = 2.6V, Vi_ = 0.4V, CL = 50pF, Voy 2 1.5V, Vo < 1.5V, unless otherwise specified. RES and F/C must switch between 0.4V and Vcc -0.4V. Input rise and fall times driven at 1ns/V. Vi, < Vi_ (max) - 0.4V for CSYNC pin. Voc = 4.5V and 5.5V. . Tested using EFI or X1 input pin. . Setup and hold necessary only to guarantee recognition at next clock. . Applies only to T3 TW states. 2 3 4. Applies only to T2 states. 5 6. Tested with EFI input frequency = 4.2MHz. 4-29282C84A Timing Waveforms NAME EFI PCLK CSYNC ES RESET -| (3) =e tELEL tELEH s|(2)/e- -|(1))<e tEHEL tOLCH ae tCL2CL1 (29) (21) / 7 tCH1CH2> |=] l tCLPH > (20) a (27) (30) we- tOLCL j<< tPLPH =e tY HEH (23) (12) tCLIiH , tHtHCL 2 | \ / (26) tCLIL_y |< NOTE: All timing measurements are made at 1.5V, unless otherwise noted. FIGURE 2. WAVEFORMS FOR CLOCKS AND RESETS SIGNALS PL CLK / t tCLRix=! (7) mo << RDY1, 2 (5) (6) talon tCLR1X >| (7) |J~< _ <_ AENT, 2 1 sy > |tAYVCLI= (8) as tCLA1X =!(11) tCLAYX as READY ______j (25) =|tRYHCH /~< (9) |< 52. (24) tRYLCL >| |<e FIGURE 3. WAVEFORMS FOR READY SIGNALS (FOR ASYNCHRONOUS DEVICES) PV. +S 7 CLK / 7 tCLR1X a| (7) se| (4) [etR1VCL - ~< RDY 1,2 j ze ' tA1VRIV>[10}<< tCLR1x >| (7) |< AENT, 2 1 - as (8)>| tAYVCL|< tCLA1x >| (11) ASYNC ec tCLAYX >1 (9) READY | | tRYHCH|* tRIVCL (6) (25) tRYLCL>| |<< FIGURE 4. WAVEFORMS FOR READY SIGNALS (FOR SYNCHRONOUS DEVICES) 4-29382C84A Test Load Circuits 2.25V R = 7402 FOR ALL OUTPUTS EXCEPT CLK OUTPUT FROM 4630. FOR CLK OUTPUT DEVICE UNDER TEST CL (SEE NOTE 3) NOTES: 1. Cy =100pF for CLK output. 2. Cy = 50pF for all outputs except CLK. 3. Cy. = Includes probe and jig capacitance. FIGURE 5. TEST LOAD MEASUREMENT CONDITIONS xt CLK LOAD PULSE EFt CLK LOAD [ r (SEE NOTE 1) GENERATOR (SEE NOTE 1) c1 oS GY px Veo c2 Lie v FIC CSYNC 5 CSYNC Vv FIGURE 6. TCHCL, TCLCH LOAD CIRCUITS Voc say LOAD PULSE LOAD L went ci (SEE NOTE 1) GENERATOR EFT CLK (SEE NOTE 1) Coot x1 a LOAD vee 24MHz Cl u READY (SEE NOTE 2) F/G L__ + X2 AENT C2 TRIGGER AENT READY TOAD v PULSE RDY2 (SEE NOTE 2) PULSE GENERATOR = GENERATOR RDY2 osc AEN2 TRIGGER = CSYNC FIC Vv BENZ CSYNC V FIGURE 7. TRYLCL, TRYHCH LOAD CIRCUITS AC Testing Input, Output Waveform INPUT OUTPUT Vin + 0.4V Vou 1.5V S< S 1.5V Vi, - 0.4V VoL NOTE: Input test signals must switch between Vj, (maximum) -0.4V and V\y (minimum) +0.4V. RES and F/C must switch between 0.4V and Voc -0.4V. Input rise and fall times driven at 1ns/V. Vi_ < Vi_ (max) -0.4V for CSYNC pin. Vcc -4.5V and 5.5V. 4-29482C84A Burn-in Circuits MD82C84A CERDIP Voc C1 a U 7 R2 Ri Voc GND R1 F6 ww 3 | 16} ______ open Ri R3 Voc R1 GND R1 R1 F7 _w 6 13} -ww F114 Ri Vv F8 ____.w_ 7 12 R2 vce Voc Re R1 GND RZ 3 Fa} WA F2 GND R2 9 10 R2 ce GND MR82C84A CLCC Veo gy N - oO ese gL st st st st ocja ao ao I R4 a tea r= rs awa fia OPEN Voo/2 ewe} (i7}--WA Fi0 Ra rs ria Lan et Fy Lapa t F141 OPEN 81 OPEN NOTES: Voc = 5.5V +0.5V, GND = OV. Vin =4.5V 410%. Vi_ = -0.2 to 0.4V. R1 = 47kQ, +5%. R2 = 10kQ, +5%. R3 = 2.2kQ, +5%. R4 = 1.2kQ, +5%. C1 =0.01uF (minimum). FO = 100kHz +10%. F1 = FO0/2,F2=F1/2,...F12=F11/2. 4-29582C84A Die Characteristics DIE DIMENSIONS: 66.1 x 70.5 x 19+ 1mils METALLIZATION: Type: Si- Al, 5 Thickness: 11kA+1kA GLASSIVATION: Type: SiOo_, . Thickness: 8kA + 1kA WORST CASE CURRENT DENSITY: 1.42 x 10 A/cm? Metallization Mask Layout RDY1 READY RDY2 CLK 82C84A AEN1 PCLK CSYNC Voc x1 X2 EFI FIC GND RESET ES osc 4-296