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Product Specification 1-800-255-7778
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XQ4000X Series Features
•Certified to MIL-PRF-38535 Appendix A QML
(Qualified Manufacturer Listing)
•Ceramic and plastic packages
•Also available under the following standard microcircuit
drawings (SMD)
- XQ4013XL 5962-98513
- XQ4036XL 5962-98510
- XQ4062XL 5962-98511
- XQ4085XL 5962-99575
•For more information contact the Def ense Supply
Center Columbus (DSCC)
http://www.dscc.dla.mis/v/va/smd/smdsrch.html
•Available in -3 speed
•System featured Field-Programmable Gate Arrays
-SelectRAM™ memory: on-chip ultra-fast RAM with
·synchronous write option
·dual-port RAM option
- Abundant flip-flops
- Flexible function generators
- Dedicated high-speed carry logic
- Wide edge decoders on each edge
- Hierarchy of interconnect lines
- Internal 3-state bus capability
- Eight global low-skew clock or signal distribution
networks
•System performance beyond 50 MHz
•Flexible array architecture
•Low power segmented routing architecture
•Systems-oriented features
- IEEE 1149.1-compatible boundary scan logic
support
- Individually programmable output slew rate
- Programmable input pull-up or pull-down resistors
- 12 mA sink current per XQ4000XL output
•Configured by loading binary file
- Unlimited reprogrammability
•Readback capability
- Program ver i fication
- Internal node observability
•Development system runs on most common computer
platforms
- Interfaces to popular design environments
- Fully automatic mapping, placement and routing
- Interactive design editor for design optimization
•Highest capacity—over 180,000 usable gates
•Additional routing over XQ4000E
- Almost twice the routing capacity for high-density
designs
•Buffered Interconnect for maximum speed
•New latch capability in configurable logic blocks
•Improved VersaRing™ I/O interconnect for better Fixed
pinout flexibility
- Virtually unlimited number of clock signals
•Optional multiplexer or 2-input function generator on
device outputs
•5V tolerant I/Os
•0.35
m
m SRAM process
Introduction
The QPRO™ XQ4000XL Series high-performance,
high-capacity Field Programmable Gate Arrays (FPGAs)
provide the benefits o f custom CM OS VLSI , while avoidin g
the initial cos t, long development cycle, and inh erent ri sk of
a conventional masked gate arra y.
The result of thirteen years of FPGA design experience and
feedbac k from thousands of customers, these FPGAs com-
bine architectural versatility, on-chip Select-RAM memory
with edge-triggered and dual-port modes, increased speed,
abundant routing resources, and new, sophisticated
soft-ware to achieve fully automated implementation of
complex, high-density, high-performance designs.
Refer to the complete Comm ercial XC4000X L Series Fi eld
Programmable Gate Arrays Data Sheet for more informa-
tion on devic e architec ture and ti ming, an d the late st Xili nx
databook for package pinouts other than the CB228
(included in this data sheet). (Pinouts for XQ4000XL device
are identical to XC4000XL.)
0QPRO XQ4000XL Series QML
High-Reliability FPGA s
DS029 (v1.3 ) June 25, 2000 02Product Specification
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QPRO XQ4000XL Series QML High-Reliability FPGAs
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Table 1: XQ4000XL Series High Reliability Field Progammable Gate Arrays
Device Logic
Cells
Max
Logic
Gates
(No
RAM)(1)
Max.
RAM
Bits (No
Logic)
Typical Gate
Range
(Logic and
RAM)(1) CLB
Matrix Total
CLBs
Number
of
Flip-Flops
Max.
User
I/O Packages
XQ4013XL 2432 13,000 18,432 10,000-30,000 24x24 576 1,536 192 PG223, CB228,
PQ240, BG256
XQ4036XL 3078 36,000 41,472 22,000-65,000 36x36 1,296 3,168 288 PG411, CB228,
HQ240, BG352
XQ4062XL 5472 62,000 73,728 40,000-130,000 48x48 2,304 5,376 384 PG475, CB228,
HQ240, BG432
XQ4085XL 7448 85,000 100,352 55,000-180,000 56x56 3,136 7,168 448 PG475, CB228,
HQ240, BG432
Notes:
1. Maximum values of typical gate range includes 20% to 30% of CLBs used as RAM.
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Product Specification 1-800-255-7778
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XQ4000XL Switching Chara cteristics
Defin ition o f Term s
In the following tables, some specifications may be designated as Advance or Preliminary. These terms are defined as
follows:
Advance: Initial estimates based on simulation and/or extrapolation from other speed grades, devices, or
devicefamilies. Values are subject to change. Use as estimates, not for production.
Preliminary: Based on preliminary characterization. Further changes are not expected.
Unmarked: Specifications not identified as either Advance or Preliminary are to be considered Final.
Except for pin-to-pin input and output parameters, the a.c. parameter delay specifications included in this document are
deriv ed from measuring internal test patterns. All specifications are representative of worst-case supply voltage and junction
temperature conditions.
All specifications subject to change without notice.
Additional Specifications
Except for pin-to-pin input and output parameters, the a.c.
parameter delay specifications included in this document
are derived from measuring internal test patterns. All speci-
fications are representative of worst-case supply voltage
and junction temperature conditions. The parameters
include d are c ommon to popu lar desig ns and typical a ppli-
cations. For design considerations requiring more detailed
timing information, see the appropriate family AC supple-
ments available on the Xilinx web site at:
http://www.xilinx.com/partinfo/databook.htm.
Absolute Maximum Ratings(1)
Recommended Operating Conditions(1)
Symbol Description Units
VCC Supply voltage relative to GND –0.5 to 4.0 V
VIN Input voltage relative to GND(2) –0.5 to 5.5 V
VTS Voltage applied to High-Z output(2) –0.5 to 5.5 V
VCCt Longest supply voltage rise time from 1V to 3V 50 ms
TSTG Storage temperature (ambient) –65 to +150
°
C
TSOL Maximum soldering temperature (10s @ 1/16 in. = 1.5 mm) +260
°
C
TJJunction temperature Ceramic package +150
°
C
Plastic package +125
°
C
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and func tio nal o peration o f the devi ce at the se o r any oth er co ndi tions beyond those listed und er Op erating Conditions
is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
2. Maximum DC overshoot or undershoot above VCC or below GND must be limited to either 0.5V or 10 mA, whichever is easier to
achie v e. During tr an sition s, the de v ice pi ns may un dersho ot to –2.0 V or overshoo t to VCC + 2.0 V, pro vide d this o v er- or und ershoo t
lasts less than 10 ns and with the forcing current being limited to 200 mA.
Symbol Description Min Max Units
VCC Supply voltage relative to GND, TJ = –55
°
C to +125
°
CPlastic 3.0 3.6 V
Supply voltage relative to GND, TC = –55
°
C to +125
°
C Ceramic 3.0 3.6 V
VIH High-level input voltage(2) 50% of VCC 5.5 V
VIL Low-level input voltage 0 30% of VCC V
TIN Input signal transition time - 250 ns
Notes:
1. At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.35% per °C.
2. Input and output measurement threshold is ~50% of VCC.
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XQ4000XL DC Characteristics Over Recommended Operating Conditions
Power-On Power Supply Requirements
Xilinx FPGAs require a minimum rated power supply current
capacity to insure proper initialization, and the power supply
ramp-up time does affect the current required. A fast
ramp-up time requires more current than a slow ramp-up
time. The slowest ramp-up t ime is 50 ms. Current c apacity
is not specified for a ramp-up time f aster than 2 ms. The cur-
rent capacity varies linealy with ramp-up time, e.g., an
XQ4036XL with a ramp-up time of 25 ms would require a
capacity predicted by the point on the straight line drawn
from 1A at 120
m
s to 500 mA at 50 ms at the 25 ms time
mark. This point is approximately 750 mA .
Symbol Description Min Max Units
VOH High-level output voltage at IOH = –4 mA, VCC min (LVTTL) 2.4 - V
High-level output voltage at IOH = –500
m
A, (LVCMOS) 90% VCC -V
VOL Low-level output voltage at IOL = 12 mA, VCC min (LVTTL)(1) -0.4V
Low-level output voltage at IOL = 1 500
m
A, (LVCMOS) - 10% VCC V
VDR Data retention supply voltage (below which configuration data may be lost) 2.5 - V
ICCO Qu ies c ent FPG A supp ly curr ent(2) -5mA
ILInput or output leakage current –10 +10
m
A
CIN Input capacitance (sample tested) BGA, PQ, HQ, packages - 10 pF
PGA packages - 16 pF
IRPU Pad pull-up (when selected) at VIN = 0V (sample tested) 0.02 0.25 mA
IRPD Pad pull-down (when selected) at VIN = 3.6V (sample tested) 0.02 0.15 mA
IRLL Horizontal longline pull-up (when selected) at logic Low 0.3 2.0 mA
Notes:
1. With up to 64 pins simultaneously sinking 12 mA.
2. With no output current loads, no active input or Longline pull-up resistors, all I/O pins in a High-Z state and floating.
Product Description
Ramp-up Time
Fast (120
m
s) Slow (50 ms)
XQ4013 - 36XL Minimum required current supply 1A 500 mA
XC4062XL Minimum required current supply 2A 500 mA
XC4085XL(1) Minimum required current supply 2A(1) 500 mA
Notes:
1. The XC4085XL fast ramp-up time is 5 ms.
2. Devices are guaranteed to initialize properly with the minimum current listed above. A larger capacity power supply may result in a
larger initialization current.
3. This specification applies to Commercial and Industrial grade products only.
4. Ramp-up Time is measured from 0VDC to 3.6VDC. Peak current required lasts less than 3 ms, and occurs near the internal power
on reset threshold voltage. After initialization and before configuration, ICC max is less than 10 mA.
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Product Specification 1-800-255-7778
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XQ4000XL AC Switching Characteristic
Testing of the switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
deri ved from measur ing in ter na l test patterns. Listed bel ow
are representative values where one global clock input
driv es one vertical clock line in each accessible column, and
where al l acce ssible IOB an d CLB flip-fl ops are c locked by
the global clock net.
When fe wer vertical clock lines are connected, the clock dis-
tribution is faster ; when multip le clock lin es per colu mn are
driven from the same glo bal clock, the delay is longer. For
more specific, more precise, and worst-case guaranteed
data, reflecting the actual routing structure, use the values
provided by the static timing analyzer (TRCE in the Xilinx
Dev elopment System) and back-annotated to the simulation
netlist. These path delays, provided as a guideline, have
been extracted from the static timing analyzer report. All
timing param ete rs assum e wors t- case op erati ng cond iti ons
(supply voltage and junction temperature)
Global Buffer Switching Characteristics
Global Early BUFGEs 1, 2, 5, and 6 to IOB Clock Characteristics
Global Early BUFGEs 3, 4, 7, and 8 to IOB Clock Characteristics
Symbol Description Device All
Min
-3 -1
UnitsMax Max
TGLS Delay from pad through Global Low Skew buffer, to any
clock K XQ4013XL 0.6 3.6 - ns
XQ4036XL 1.1 4.8 - ns
XQ4062XL 1.4 6.3 - ns
XQ4085XL 1.6 - 5.7 ns
Symbol Description Device All
Min
-3 -1
UnitsMax Max
TGE Delay from pad through Global Early buffer, to any IOB
clock. Values are for BUFGEs 1, 2, 5 and 6. XQ4013XL 0.4 2.4 - ns
XQ4036XL 0.3 3.1 - ns
XQ4062XL 0.3 4.9 - ns
XQ4085XL 0.4 - 4.7 ns
Symbol Description Device All
Min
-3 -1
UnitsMax Max
TGE Delay from pad through Global Early buffer, to any IOB
clock. Values are for BUFGEs 3, 4, 7 and 8. XQ4013XL 0.7 2.4 - ns
XQ4036XL 0.9 4.7 - ns
XQ4062XL 1.2 5.9 - ns
XQ4085XL 1.3 - 5.5 ns
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XQ4000XL CLB Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
deri ved from measur ing in ter na l test patterns. Listed bel ow
are rep resentat ive values. Fo r more spec ific, more p reci se,
and worst-case guaranteed data, use the values reported
by the static timing analyzer (TRCE in the Xilinx Develop-
ment Sys tem) and back-anno tated to the simulation netlist.
All timing parameters assume worst-case operating condi-
tions (supply voltage and junction temperature). Values
apply to a ll XQ40 00XL devices and expressed in nanose c-
onds unless otherwise noted.
CLB Switching Characteristics
Symbol Description
-3 -1
UnitsMin Max Min Max
Combinatorial Delays
TILO F/G inputs to X/Y outputs - 1.6 - 1.3 ns
TIHO F/G inputs via H’ to X/Y outputs - 2.7 - 2.2 ns
TITO F/G inputs via transparent latch to Q outputs - 2.9 - 2.2 ns
THH0O C inputs via SR/H0 via H to X/Y outputs - 2.5 - 2.0 ns
THH1O C inputs via H1 via H to X/Y outputs - 2.4 - 1.9 ns
THH2O C inputs via DIN/H2 via H to X/Y outputs - 2.5 - 2.0 ns
TCBYP C inputs via EC, DIN/H2 to YQ, XQ output (bypass) - 1.5 - 1.1 ns
CLB Fast Carry Logic
TOPCY Operand inputs (F1, F2, G1, G4) to COUT -2.7-2.0ns
TASCY Add/subtract input (F3) to COUT -3.3-2.5ns
TINCY Initialization inputs (F1, F3) to COUT -2.0-1.5ns
TSUM CIN through function generators to X/Y outputs - 2.8 - 2.4 ns
TBYP CIN to COUT, bypass function generators - 0.26 - 0.20 ns
TNET Carry net delay, COUT to CIN - 0.32 - 0.25 ns
Sequential Delays
TCKO Clock K to flip-flop outputs Q - 2.1 - 1.6 ns
TCKLO Clock K to latch outputs Q - 2.1 - 1.6 ns
Setup Time Before Clock K
TICK F/G inputs 1.1 - 0.9 - ns
TIHCK F/G inputs via H 2.2 - 1.7 - ns
THH0CK C inputs via H0 through H 2.0 - 1.6 - ns
THH1CK C inputs via H1 through H 1.9 - 1.4 - ns
THH2CK C inputs via H2 through H 2.0 - 1.6 - ns
TDICK C inputs via DIN 0.9 - 0.7 - ns
TECCK C inputs via EC 1.0 - 0.8 - ns
TRCK C inputs via S/R, going Low (inactive) 0.6 - 0.5 - ns
TCCK CIN input via F/G 2.3 - 1.9 - ns
TCHCK CIN input via F/G and H 3.4 - 2.7 - ns
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Hold Time After Clock K
TCKI F/G inputs 0 - 0 - ns
TCKIH F/G inputs via H 0 - 0 - ns
TCKHH0 C inputs via SR/H0 through H 0 - 0 - ns
TCKHH1 C inputs via H1 through H 0 - 0 - ns
TCKHH2 C inputs via DIN/H2 through H 0 - 0 - ns
TCKDI C inputs via DIN/H2 0 - 0 - ns
TCKEC C inputs via EC 0 - 0 - ns
TCKR C inputs via SR, going Low (inactive) 0 - 0 - ns
Clock
TCH Clock High time 3.0 - 2.5 - ns
TCL Clock Low time 3.0 - 2.5 - ns
Set/Reset Direct
TRPW Width (High) 3.0 - 2.5 - ns
TRIO Delay from C inputs via S/R, going High to Q - 3.7 - 2.8 ns
Global Set/Reset
TMRW Minimum GSR pulse width - 19.8 - 15.0 ns
TMRQ Delay from GSR input to any Q See page 95 for TRRI value s per device.
FTOG Toggle frequency (MHz) (for export control) - 166 - 200 MHz
CLB Switching Characteristics (Continued)
Symbol Description
-3 -1
UnitsMin Max Min Max
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XQ4000XL RAM Synchronous (Edge-Triggered) Write Operat ion Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
deri ved from measur ing in ter na l test patterns. Listed bel ow
are rep resentat ive values. Fo r more spec ific, more p reci se,
and worst-case guaranteed data, use the values reported
by the static timing analyzer (TRCE in the Xilinx Develop-
ment Sys tem) and back-anno tated to the simulation netlist.
All timing parameters assume worst-case operating condi-
tions (supply voltage and junction temperature). Values
apply to all X Q4 000 XL devices and are expressed in na no-
seconds unless otherwise noted.
Single-Port RAM Synchronous (Edge-Triggered) Write Operation Characteristics
Symbol Single Port RAM Size
-3 -1
UnitsMin Max Min Max
Write Operation
TWCS Address write cycle time (clock K period) 16x2 9.0 - 7.7 - ns
TWCTS 32x1 9.0 - 7.7 - ns
TWPS Clock K pulse width (active edge) 16x2 4.5 - 3.9 - ns
TWPTS 32x1 4.5 - 3.9 - ns
TASS Address setup time before clock K 16x2 2.2 - 1.7 - ns
TASTS 32x1 2.2 - 1.7 - ns
TAHS Address hold time after clock K 16x2 0 - 0 - ns
TAHTS 32x1 0 - 0 - ns
TDSS DIN setup time before clock K 16x2 2.0 - 1.7 - ns
TDSTS 32x1 2.5 - 2.1 - ns
TDHS DIN hold time after clock K 16x2 0 - 0 - ns
TDHTS 32x1 0 - 0 - ns
TWSS WE setup time before clock K 16x2 2.0 - 1.6 - ns
TWSTS 32x1 1.8 - 1.5 - ns
TWHS WE hold time after clock K 16x2 0 - 0 - ns
TWHTS 32x1 0 - 0 - ns
TWOS Data valid after clock K 16x2 - 6.8 - 5.8 ns
TWOTS 32x1 - 8.1 - 6.9 ns
Read Operation
TRC Address read cycle time 16x2 4.5 - 2.6 - ns
TRCT 32x1 6.5 - 3.8 - ns
TILO Data valid after address change (no Write Enable) 16x2 - 1.6 - 1.3 ns
TIHO 32x1 - 2.7 - 2.2 ns
TICK Address setup time before clock K 16x2 1.1 - 0.9 - ns
TIHCK 32x1 2.2 - 1.7 - ns
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Dual-Port RAM Synchronous (Edge-Triggered) Write Operation Characteristics
Symbol Dual Port RAM Size(1)
-3 -1
UnitsMin Max Min Max
Write Operation
TWCDS Address write cycle time (clock K period) 16x1 9.0 7.7 ns
TWPDS Clock K pulse width (active edge) 16x1 4.5 - 3.9 - ns
TASDS Address setup time before clock K 16x1 2.5 - 1.7 - ns
TAHDS Address hold time after clock K 16x1 0 - 0 - ns
TDSDS DIN setup time before clock K 16x1 2.5 - 2.0 - ns
TDHDS DIN hold time after clock K 16x1 0 - 0 - ns
TWSDS WE setup time before clock K 16x1 1.8 - 1.6 - ns
TWHDS WE hold time after clock K 16x1 0 - 0 - ns
TWODS Data v alid after clock K 16x1 - 7.8 - 6.7 ns
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XQ4000XL CLB Single-Port RAM Synchronous (Edge-Triggered) Write Timing
XQ4000XL CLB Dual-Port RAM Synchronous (Edge-Triggered) Write Timing
DS029_01_011300
WCLK (K)
WE
ADDRESS
DATA IN
D
ATA OUT
OLD NEW
T
DSS
T
DHS
T
ASS
T
AHS
T
WSS
T
WPS
T
WHS
T
WOS
T
ILO
T
ILO
DS029_02_011300
WCLK (K)
WE
ADDRESS
DATA IN
DATA OUT
OLD NEW
T
DSDS
T
DHDS
T
ASDS
T
AHDS
T
WSS
T
WPDS
T
WHS
T
WODS
T
ILO
T
ILO
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XQ4000XL Pin-to-Pin Output Parameter Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Pin-to-pin timing parameters are
derived from measuring external and inter nal test patter ns
and are guaranteed over worst-case operating conditions
(supply voltage and junction temperature). Listed below are
representative values for typical pin locations and normal
clock loading. For more specific, more precise, and
worst-case guaranteed data, reflecting the actual routing
str ucture, use the value s provided by the stat ic timin g ana-
lyzer (TRCE in the Xilinx Development System) and
back-annotated to the simulation netlist. These path dela ys,
provided as a guideline, hav e been extracted from the static
timing analyzer report. Values are expressed in nanosec-
onds unless otherwise noted.
Output Flip-Flop, Clock to Out(1,2,3)
Output Flip-Flop, Clock to Out, BUFGEs 1, 2, 5, and 6
Symbol Description Device All
Min
-3 -1
UnitsMax Max
TICKOF Global low skew clock to output using OFF(4) XQ4013XL 1.5 8.6 - ns
XQ4036XL 2.0 9.8 - ns
XQ4062XL 2.3 11.3 - ns
XQ4085XL 2.5 - 9.5 ns
TSLOW For output SLOW option add All Devices 3.0 3.0 3.0 ns
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
2. Cloc k-to-out minim um dela y is mea sured with the f astest route and the lig htest load, C lock-to-out maximum delay is measure d using
the farthest distance and a reference load of one clock pin (IK or OK) per IOB as well as driving all accessible CLB flip-flops. For
designs w ith a smaller n umber of clo ck load s, the pad -to-IOB clock pin dela y as determined by the st atic timing anal yzer (TR CE) can
be added to the AC parameter Tokpof and used as a worst-case pin-to-pin clock-to-out delay for clocked outputs for FAST mode
configurations.
3. Output timing is measured at ~50% VCC threshold with 50 pF e x ternal capaciti ve load.
4. OFF = Output Flip-Flop
Symbol Description Device All
Min
-3 -1
UnitsMax Max
TICKEOF Global early clock to output using OFF
Values are for BUFGEs 1, 2, 5, and 6. XQ4013XL 1.3 7.4 - ns
XQ4036XL 1.2 8.1 - ns
XQ4062XL 1.2 9.9 - ns
XQ4085XL 1.3 - 8.5 ns
Notes:
1. Cloc k-to-out minim um dela y is mea sured with the f astest route and the lig htest load, C lock-to-out maximum delay is measure d using
the farthest distance and a reference load of one clock pin (IK or OK) per IOB as well as driving all accessible CLB flip-flops. For
designs w ith a smaller n umber of clo ck load s, the pad -to-IOB clock pin dela y as determined by the st atic timing anal yzer (TR CE) can
be added to the AC parameter Tokpof and used as a worst-case pin-to-pin clock-to-out delay for clocked outputs for FAST mode
configurations.
2. Output timing is measured at ~50% VCC threshold with 50 pF e x ternal capaciti ve load.
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Output Flip-Flop, Clock to Out, BUFGEs 3, 4, 7, and 8
Capacitive Load Factor
Figure 1 shows the relationship between I/O output delay
and load capacitance. It allows a user to adjust the specified
output d elay if the load capa citance is dif fe rent th an 50 pF.
For example, if the actual load capacitance is 120 pF, add
2.5 ns to the specified delay. If the load capacitance is
20 pF, subtract 0.8 ns from the specified output delay.
Figure 1 is usable over the specified operating conditions of
voltage and temperature and is independent of the output
slew rate control.
Symbol Description Device All
Min
-3 -1
UnitsMax Max
TICKEOF Global early clock to output using OFF
Values are for BUFGEs 3, 4, 7, and 8. XQ4013XL 1.8 8.8 - ns
XQ4036XL 1.8 9.7 - ns
XQ4062XL 2.0 10.9 - ns
XQ4085XL 2.2 - 9.3 ns
Notes:
1. Cloc k-to-out minim um dela y is mea sured with the f astest route and the lig htest load, C lock-to-out maximum delay is measure d using
the farthest distance and a reference load of one clock pin (IK or OK) per IOB as well as driving all accessible CLB flip-flops. For
designs w ith a smaller n umber of clo ck load s, the pad -to-IOB clock pin dela y as determined by the st atic timing anal yzer (TR CE) can
be added to the AC parameter Tokpof and used as a worst-case pin-to-pin clock-to-out delay for clocked outputs for FAST mode
configurations.
2. Output timing is measured at ~50% VCC threshold with 50 pF e x ternal capaciti ve load.
Figure 1: Delay Factor at Various Capacitive Loads
DS029_03_011300
-2 0 20406080
Capacitance (pF)
Delta Delay (ns)
100 120 140
-1
0
1
2
3
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XQ4000XL Pin-to-Pi n Input Parameter Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Pin-to-pin timing parameters are
derived from measuring external and inter nal test patter ns
and are guaranteed over worst-case operating conditions
(supply voltage and junction temperature). Listed below are
representative values for typical pin locations and normal
clock loading. For more specific, more precise, and
worst-case guaranteed data, reflecting the actual routing
str ucture, use the value s provided by the stat ic timin g ana-
lyzer (TRCE in the Xilinx Development System) and
back-annotated to the simulation netlist. These path dela ys,
provided as a guideline, hav e been extracted from the static
timing analyzer report. Values are expressed in nanosec-
onds unless otherwise noted.
Global Low Skew Clock, Input Setup and Hold Times(1,2)
Symbol Description Device(1)
-3 -1
UnitsMin Min
No Delay
TPSN/TPHN Global early clock and IFF(3)
Global early clock and FCL(4) XQ4013XL 1.2 / 3.2 - ns
XQ4036X L 1.2 / 5.5 - ns
XQ4062X L 1.2 / 7.0 - ns
XQ4085XL - 0.9 / 7.1 ns
Partial Delay
TPSP/TPHP Global early clock and IFF(3)
Global early clock and FCL(4) XQ4013XL 6.1 / 0.0 - ns
XQ4036X L 6.4 / 1.0 - ns
XQ4062X L 6.7 / 1.2 - ns
XQ4085XL - 9.8 / 1.2 ns
Full Delay
TPSD/TPHD Global early clock and IFF(3) XQ4013X L 6.4 / 0.0 - ns
XQ4036X L 6.6 / 0.0 - ns
XQ4062X L 6.8 / 0.0 - ns
XQ4085XL - 9.6 / 0.0 ns
Notes:
1. The XQ4013XL, XQ4036XL, and XQ4062XL have significantly faster partial and full delay setup times than other devices.
2. Input setu p time i s measured with the f astest rou te and th e lightes t load. In put hold time is measured using th e furthest di stan ce and
a ref eren ce load of one cl oc k pin pe r IOB as w ell as driving all ac cess ib le C LB flip-fl ops . F or des igns w ith a sm aller numb er of clock
loads, the pad-to-IOB clock pin delay as determined by the static timing analyzer (TRCE) can be used as a worst-case pin-to-pin
no-delay input hold specification.
3. IFF = Input Flip-Flop or Latch
4. FCL = Fast Capture Latch
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Global Early Clock BUFEs 1, 2, 5, and 6 Setup and Hold for IFF and FCL(1,2)
Symbol Description Device
-3 -1
Min Min
No Delay
TPSEN/TPHEN
TPFSEN/TPFHEN
Global early clock and IFF(3)
Global early clock and FCL(4) XQ4013XL 1.2 / 4.7 -
XQ4036XL 1.2 / 6.7 -
XQ4062XL 1.2 / 8.4 -
XQ4085XL - 0.9 / 6.6
Partial Delay
TPSEPN/TPHEP
TPFSEP/TPFHEP
Global early clock and IFF(3)
Global early clock and FCL(4) XQ4013XL 6.4 / 0.0 -
XQ4036XL 7.0 / 0.8 -
XQ4062XL 9.0 / 0.8 -
XQ4085XL - 11.0 / 0.0
Full Delay
TPSEPD/TPHED Global early clock and IFF(3) XQ 4013 XL 12.0 / 0.0 -
XQ4036 XL 13.8 / 0.0 -
XQ4062 XL 13.1 / 0.0 -
XQ4085XL - 13.6 / 0.0
Notes:
1. The XQ4013XL, XQ4036XL, and XQ4062XL have significantly faster partial and full delay setup times than other devices.
2. Input setu p time i s measured with the f astest rou te and th e lightes t load. In put hold time is measured using th e furthest di stan ce and
a ref eren ce load of one cl oc k pin pe r IOB as w ell as driving all ac cess ib le C LB flip-fl ops . F or des igns w ith a sm aller numb er of clock
loads, the pad-to-IOB clock pin delay as determined by the static timing analyzer (TRCE) can be used as a worst-case pin-to-pin
no-delay input hold specification.
3. IFF = Input Flip-Flop or Latch
4. FCL = Fast Capture Latch
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Global Early Clock BUFEs 3, 4, 7, and 8 Setup and Hold for IFF and FCL(1,2)
Symbol Description Device
-3 -1
Min Min
No Delay
TPSEN/TPHEN
TPFSEN/TPFHEN
Global early clock and IFF(3)
Global early clock and FCL(4) XQ4013XL 1.2 / 4.7 -
XQ4036XL 1.2 / 6.7 -
XQ4062XL 1.2 / 8.4 -
XQ4085XL - 0.9 / 6.6
Partial Delay
TPSEPN/TPHEP
TPFSEP/TPFHEP
Global early clock and IFF(3)
Global early clock and FCL(4) XQ4013XL 5.4 / 0.0 -
XQ4036XL 6.4 / 0.8 -
XQ4062XL 8.4 / 1.5 -
XQ4085XL - 11.0 / 0.0
Full Delay
TPSEPD/TPHED Global early clock and IFF(3) XQ 4013 XL 10.0 / 0.0 -
XQ4036 XL 12.2 / 0.0 -
XQ4062 XL 13.1 / 0.0 -
XQ4085XL - 13.6 / 0.0
Notes:
1. The XQ4013XL, XQ4036XL, and XQ4062XL have significantly faster partial and full delay setup times than other devices.
2. Input setu p time i s measured with the f astest rou te and th e lightes t load. In put hold time is measured using th e furthest di stan ce and
a ref eren ce load of one cl oc k pin pe r IOB as w ell as driving all ac cess ib le C LB flip-fl ops . F or des igns w ith a sm aller numb er of clock
loads, the pad-to-IOB clock pin delay as determined by the static timing analyzer (TRCE) can be used as a worst-case pin-to-pin
no-delay input hold specification.
3. IFF = Input Flip-Flop or Latch
4. FCL = Fast Capture Latch
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XQ4000XL IOB Input Switching Characteristic Guidel ines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
deri ved from measur ing in ter na l test patterns. Listed bel ow
are rep resentat ive values. Fo r more spec ific, more p reci se,
and worst-case guaranteed data, use the values reported
by the static timing analyzer (TRCE in the Xilinx Develop-
ment Sys tem) and back-anno tated to the simulation netlist.
These path delays, provided as a guideline, have been
extracted from the static timing analyzer report. All timing
parameters assume worst-case operating conditions (sup-
ply voltage and junction temperature).
Symbol Description Device
-3 -1
UnitsMin Max Min Max
Clocks
TECIK Clock enable (EC) to clock (IK) All devices 0.1 - 0.1 - ns
TOKIK Delay from FCL enable (OK) active edge to IFF
clock (IK) active edge All devices 2.2 - 1.6 - ns
Setup Times
TPICK Pad to clock (IK), no delay All devices 1.7 - 1.3 - ns
TPICKF Pad to clock (IK), via transparent f ast capture latch,
no delay All devices 2.3 - 1.8 - ns
TPOCK Pad to fast capture latch enable (OK), no delay All devices 1.2 - 0.9 - ns
Hold Times
All Hold Times All devices 0 - 0 - ns
Global Set/Reset
TMRW Minimum GSR pulse width All devices - 19.8 - 15.0 ns
TRRI Delay from GSR input to any Q(2) XQ4013XL - 15.9 - - ns
XQ4036XL - 22.5 - - ns
XQ4062XL - 29.1 - - ns
XQ4085XL - - - 26.0 ns
Propagation Delays
TPID Pad to I1, I2 All devices - 1.6 - 1.7 ns
TPLI Pad to I1, I2 via transparent input latch, no delay All devices - 3.1 - 2.4 ns
TPFLI Pad to I1, I2 via transparent FCL and input latch, no
delay All devices - 3.7 - 2.8 ns
TIKRI Clock (IK) to I1, I2 (flip-flop) All devices - 1.7 - 1.3 ns
TIKLI Clock (IK) to I1, I2 (latch enable, active Low) All devices - 1.8 - 1.4 ns
TOKLI FCL enable (OK) active edge to I1, I2
(via transparent standard input latch) All devices - 3.6 - 2.7 ns
Notes:
1. IFF = Input Flip-Flop or La tch, FCL = Fast Capt ure Latch
2. Indicates Minimum Amount of Time to Assure Valid Data.
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Product Specification 1-800-255-7778
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XQ4000XL IOB Output Switch ing Characteristic Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
deri ved from measur ing in ter na l test patterns. Listed bel ow
are rep resentat ive values. Fo r more spec ific, more p reci se,
and worst-case guaranteed data, use the values reported
by the static timing analyzer (TRCE in the Xilinx Develop-
ment Sys tem) and back-anno tated to the simulation netlist.
These path delays, provided as a guideline, have been
extracted from the static timing analyzer report. All timing
parameters assume worst-case operating conditions (sup-
ply voltage and junction temperature). For Propagation
Delays, slew-rate = fast unless otherwise noted. Values are
expressed in nanoseconds unless otherwise noted.
Symbol Description
-3 -1
UnitsMin Max Min Max
Clocks
TCH Clock High 3.0 - 2.5 - ns
TCL Clock Low 3.0 - 2.5 - ns
Propagation Delays
TOKPOF Cloc k (OK) to pad - 5.0 - 3.8 ns
TOPF Output (O) to pad - 4.1 - 3.1 ns
TTSHZ High-Z to pad High-Z (slew-rate independent) - 4.4 - 3.0 ns
TTSONF High-Z to pad active and v alid - 4.1 - 3.3 ns
TOFPF Output (O) to pad via fast output MUX - 5.5 - 4.2 ns
TOKFPF Select (OK) to pad via fast MUX - 5.1 - 3.9 ns
Setup and Hold Times
TOOK Output (O) to clock (OK) setup time 0.5 - 0.3 - ns
TOKO Output (O) to clock (OK) hold time 0 - 0 - ns
TECOK Clock Enable (EC) to clock (OK) setup time 0 - 0 - ns
TOKEC Clock Enable (EC) to clock (OK) hold time 0.3 - 0.1 - ns
Global Set/Reset
TMRW Minimum GSR pulse width 19.8 - 15.0 - ns
TRPO Delay from GSR input to any pad(2)
XQ4013XL - 20.5 - - ns
XQ4036XL - 27.1 - - ns
XQ4062XL - 33.7 - - ns
XQ4085XL - - 29.5 ns
Slew Rate Adjustment
TSLOW For output SLOW option add - 3.0 - 2.0 ns
Notes:
1. Output timing is measured at ~50% VCC threshold, with 50 pF external capacitive loads.
2. Indicates Minimum Amount of Time to Assure Valid Data.
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CB228 Pinouts
Table 2: CB228 Package Pinouts
Pin Name CB228
VTT
GND P1
BUFGP_TL_A16_GCK1_IO P2
A17_IO P3
IO P4
IO P5
TDI_IO P6
TCK_IO P7
IO P8
IO P9
IO P10
IO P11
IO P12
IO P13
GND P14
IO_FCLK1 P15
IO P16
TMS_IO P17
IO P18
IO P19
IO P20
IO P21
IO P22
IO P23
IO P24
IO P25
IO P26
GND P27
VCC P28
IO P29
IO P30
IO P31
IO P32
IO P33
IO P34
IO P35
IO P36
VCC P37
IO P38
IO P39
IO P40
IO_FCLK2 P41
GND P42
IO P43
IO P44
IO P45
IO P46
IO P47
IO P48
IO P49
IO P50
IO P51
IO P52
IO P53
BUFGS_BL_GCK2_IO P54
M1 P55
GND P56
M0 P57
VCC P58
M2 P59
BUFGP_BL_GCK3_IO P60
HDC_IO P61
IO P62
IO P63
IO P64
LDC_IO P65
IO P66
IO P67
IO P68
IO P69
IO P70
IO P71
GND P72
IO P73
IO P74
IO P75
IO P76
IO P77
IO P78
Table 2: CB228 Package Pinouts (Continued)
Pin Name CB228
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IO P79
IO P80
IO P81
IO P82
IO P83
/ERR_INIT_IO P84
VCC P85
GND P86
IO P87
IO P88
IO P89
IO P90
IO P91
IO P92
IO P93
IO P94
VCC P95
IO P96
IO P97
IO P98
IO P99
GND P100
IO P101
IO P102
IO P103
IO P104
IO P105
IO P106
IO P107
IO P108
IO P109
IO P110
IO P111
BUFGS_BR_GCK4_IO P112
GND P113
DONE P114
VCC P115
/PROGRAM P116
D7_IO P117
BUFGP_BR_GCK5_IO P118
Table 2: CB228 Package Pinouts (Continued)
Pin Name CB228 IO P119
IO P120
IO P121
IO P122
D6_IO P123
IO P124
IO P125
IO P126
IO P127
IO P128
GND P129
IO P130
IO P131
IO_FCLK3 P132
IO P133
D5_IO P134
/CS0_IO P135
IO P136
IO P137
IO P138
IO P139
D4_IO P140
IO P141
VCC P142
GND P143
D3_IO P144
/RS_IO P145
IO P146
IO P147
IO P148
IO P149
D2_IO P150
IO P151
VCC P152
IO P153
IO_FCLK4 P154
IO P155
IO P156
GND P157
IO P158
Table 2: CB228 Package Pinouts (Continued)
Pin Name CB228
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IO P159
IO P160
IO P161
IO P162
IO P163
D1_IO P164
BUSY_/RDY_RCLK_IO P165
IO P166
IO P167
D0_DIN_IO P168
BUFGS_TR_GCK6_DOUT_IO P169
CCLK P170
VCC P171
TDO P172
GND P173
A0_/WS_IO P174
BUFGP_TR_GCK7_A1_IO P175
IO P176
IO P177
CSI_A2_IO P178
A3_IO P179
IO P180
IO P181
IO P182
IO P183
IO P184
IO P185
GND P186
IO P187
IO P188
IO P189
IO P190
VCC P191
A4_IO P192
A5_IO P193
IO P194
IO P195
A21_IO P196
A20_IO P197
A6_IO P198
Table 2: CB228 Package Pinouts (Continued)
Pin Name CB228 A7_IO P199
GND P200
VCC P201
A8_IO P202
A9_IO P203
A19_IO P204
A18_IO P205
IO P206
IO P207
A10_IO P208
A11_IO P209
VCC P210
IO P211
IO P212
IO P213
IO P214
GND P215
IO P216
IO P217
IO P218
IO P219
A12_IO P220
A13_IO P221
IO P222
IO P223
IO P224
IO P225
A14_IO P226
BUFGS_TL_GCK8_A15_IO P227
VCC P228
Table 2: CB228 Package Pinouts (Continued)
Pin Name CB228
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Ordering Information
Revision History
The following table shows the revision history for this document
Device Type
XQ4085XL
XQ4062XL
XQ4036XL
XQ4013XL Package Type
CB = Top Brazed Ceramic Quad Flat Pack
PG = Ceramic Pin Grid Array
PQ/HQ = Plastic Quad Flat Back
BG = Plastic Ball Grid Array
Temperature Range
M = Military Ceramic (T C = –55oC to +125 oC)
N = Military Plastic (TJ = –55
°
C to +125
°
C)
Mil-PRF-38535
(QML) Processed
Number of Pins
XQ 4062XL -3 PG 475 M
Example for QPRO™ military temperature part:
Speed Grade
-3
-1 (XQ4085XL only)
Date Version Description
05/01/98 1.0 Original document release.
01/01/99 1.1 Addition of new packages, clarification of parameters.
02/09/00 1.2 Addition of XQ4085XL-1 speed grade part.
06/25/00 1.3 Updated timing specifications to match with commercial data sheet. Updated format.
Device Type
XQ4013XL = 98513
XQ4036XL = 98510
XQ4062XL = 98511
XQ4085XL = 99575
Package Type
X = Pin Grid
Y = Ceramic Quad Flat Pack (Base Mark )
Z = Ceramic Quad Flat Pack (Lid Mark)
T = Plastic Quad Flat Pack
U = Plas tic Ball Grid
Lead Finish
C = Gold
B = Solder
Generic Standard
Microcircuit Drawing (SMD)
Prefix
5962 98511 01 Q X C
Q = QML Certified
N = QML Plastic (N - Grade)
Example for SMD part:
Speed Grade
01 = -3 for XQ410 3X L/40 36X L/4 062X L
01 = -1 for XQ4085XL
