LMC6061AIM/NOPB - NATIONAL SEMICONDUCTOR

LMC6061

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SNOS648D –NOVEMBER 1994–REVISED MARCH 2013

PRECISION CMOS SINGLE MICROPOWER OPERATIONAL AMPLIFIER

Check for Samples: LMC6061

1FEATURES DESCRIPTION

The LMC6061 is a precision single low offset voltage,

2(Typical Unless Otherwise Noted) micropower operational amplifier, capable of

• Low Offset Voltage: 100 µV precision single supply operation. Performance

• Ultra Low Supply Current: 20 μAcharacteristics include ultra low input bias current,

high voltage gain, rail-to-rail output swing, and an

• Operates From 4.5V to 15V Single Supply input common mode voltage range that includes

• Ultra Low Input Bias Current: 10 fA ground. These features, plus its low power

• Output Swing Within 10 mV of Supply Rail, consumption, make the LMC6061 ideally suited for

100k Load battery powered applications.

• Input Common-mode Range Includes V−Other applications using the LMC6061 include

• High Voltage Gain: 140 dB precision full-wave rectifiers, integrators, references,

sample-and-hold circuits, and true instrumentation

• Improved Latchup Immunity amplifiers.

APPLICATIONS This device is built with TI's advanced double-Poly

Silicon-Gate CMOS process.

• Instrumentation Amplifier For designs that require higher speed, see the

• Photodiode and Infrared Detector Preamplifier LMC6081 precision single operational amplifier.

• Transducer Amplifiers For a dual or quad operational amplifier with similar

• Hand-held Analytic Instruments features, see the LMC6062 or LMC6064 respectively.

• Medical Instrumentation PATENT PENDING

• D/A Converter

• Charge Amplifier for Piezoelectric Transducers

Connection Diagrams

Figure 1. 8-Pin PDIP/SOIC Figure 2. Distribution of LMC6061 Input Offset

Voltage (TA= +25°C)

Top View

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

LMC6061

SNOS648D –NOVEMBER 1994–REVISED MARCH 2013

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Absolute Maximum Ratings(1)(2)(3)

Differential Input Voltage ±Supply Voltage

Voltage at Input/Output Pin (V+) +0.3V,

(V−)−0.3V

Supply Voltage (V+−V−) 16V

Output Short Circuit to V+See(4)

Output Short Circuit to V−See(5)

Lead Temperature (Soldering, 10 sec.) Storage Temp. Range −65°C to +150°C

Junction Temperature 150°C

ESD Tolerance(6) 2 kV

Current at Input Pin ±10 mA

Current at Output Pin ±30 mA

Current at Power Supply Pin 40 mA

Power Dissipation See(7)

(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for

which the device is intended to be functional, but do not ensure specific performance limits. For ensured specifications and test

conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed.

(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.

(3) For specified Military Temperature Range parameters see RETSMC6061X.

(4) Do not connect output to V+, when V+is greater than 13V or reliability witll be adversely affected.

(5) Applies to both single-supply and split-supply operation. Continous short circuit operation at elevated ambient temperature can result in

exceeding the maximum allowed junction temperature of 150°C. Output currents in excess of ±30 mA over long term may adversely

affect reliability.

(6) Human body model, 1.5 kΩin series with 100 pF.

(7) The maximum power dissipation is a function of TJ(Max),θJA, and TA. The maximum allowable power dissipation at any ambient

temperature is PD= (TJ(Max) −TA)/θJA.

Operating Ratings(1)

Temperature Range LMC6061AM −55°C ≤TJ≤+125°C

LMC6061AI, LMC6082I −40°C ≤TJ≤+85°C

Supply Voltage 4.5V ≤V+≤15.5V

Thermal Resistance (θJA)(2) P0008E Package, 8-Pin PDIP 115°C/W

D0008A Package, 8-Pin SOIC 193°C/W

Power Dissipation See(3)

(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for

which the device is intended to be functional, but do not ensure specific performance limits. For ensured specifications and test

conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed.

(2) All numbers apply for packages soldered directly into a PC board.

(3) For operating at elevated temperatures the device must be derated based on the thermal resistance θJA with PD= (TJ–TA)/θJA.

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DC Electrical Characteristics

Unless otherwise specified, all limits ensured for TJ= 25°C. Boldface limits apply at the temperature extremes. V+= 5V, V−=

0V, VCM = 1.5V, VO= 2.5V and RL> 1M unless otherwise specified. LMC6061AM LMC6061AI LMC6061I

Symbol Parameter Conditions Typ(1) Units

Limit(2) Limit(2) Limit(2)

VOS Input Offset Voltage 100 350 350 800 μV

1200 900 1300 Max

TCVOS Input Offset Voltage 1.0 μV/°C

Average Drift

IBInput Bias Current 0.010 pA

100 4 4 Max

IOS Input Offset Current 0.005 pA

100 2 2 Max

RIN Input Resistance >10 Tera Ω

CMRR Common Mode Rejection 0V ≤VCM ≤12.0V 85 75 75 66 dB

Ratio V+= 15V 70 72 63 Min

+PSRR Positive Power Supply 5V ≤V+≤15V 85 75 75 66 dB

Rejection Ratio VO= 2.5V 70 72 63 Min

−PSRR Negative Power Supply 0V ≤V−≤ −10V 100 84 84 74 dB

Rejection Ratio 70 81 71 Min

VCM Input Common-Mode V+= 5V and 15V −0.4 −0.1 −0.1 −0.1 V

Voltage Range for CMRR ≥60 dB 0 0 0 Max

V+−1.9 V+−2.3 V+−2.3 V+−2.3 V

V+−2.6 V+−2.5 V+−2.5 Min

AVLarge Signal Voltage Gain RL= 100 kΩ(3) Sourcing 4000 400 400 300 V/mV

200 300 200 Min

Sinking 3000 180 180 90 V/mV

70 100 60 Min

RL= 25 kΩ(3) Sourcing 3000 400 400 200 V/mV

150 150 80 Min

Sinking 2000 100 100 70 V/mV

35 50 35 Min

(1) For operating at elevated temperatures the device must be derated based on the thermal resistance θJA with PD= (TJ–TA)/θJA

(2) All limits are specified by testing or statistical analysis.

(3) V+= 15V, VCM = 7.5V and RLconnected to 7.5V. For Sourcing tests, 7.5V ≤VO≤11.5V. For Sinking tests, 2.5V ≤VO≤7.5V.

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DC Electrical Characteristics (continued)

Unless otherwise specified, all limits ensured for TJ= 25°C. Boldface limits apply at the temperature extremes. V+= 5V, V−=

0V, VCM = 1.5V, VO= 2.5V and RL> 1M unless otherwise specified. LMC6061AM LMC6061AI LMC6061I

Symbol Parameter Conditions Typ(1) Units

Limit(2) Limit(2) Limit(2)

VOOutput Swing V+= 5V 4.995 4.990 4.990 4.950 V

RL= 100 kΩto 2.5V 4.970 4.980 4.925 Min

0.005 0.010 0.010 0.050 V

0.030 0.020 0.075 Max

V+= 5V 4.990 4.975 4.975 4.950 V

RL= 25 kΩto 2.5V 4.955 4.965 4.850 Min

0.010 0.020 0.020 0.050 V

0.045 0.035 0.150 Max

V+= 15V 14.990 14.975 14.975 14.950 V

RL= 100 kΩto 7.5V 14.955 14.965 14.925 Min

0.010 0.025 0.025 0.050 V

0.050 0.035 0.075 Max

V+= 15V 14.965 14.900 14.900 14.850 V

RL= 25 kΩto 7.5V 14.800 14.850 14.800 Min

0.025 0.050 0.050 0.100 V

0.200 0.150 0.200 Max

IOOutput Current Sourcing, VO= 0V 22 16 16 13 mA

V+= 5V 8 10 8 Min

Sinking, VO= 5V 21 16 16 16 mA

7 8 8 Min

IOOutput Current Sourcing, VO= 0V 25 15 15 15 mA

V+= 15V 9 10 10 Min

Sinking, VO= 13V(4) 26 20 20 20 mA

7 8 8 Min

ISSupply Current V+= +5V, VO= 1.5V 20 24 24 32 μA

35 32 40 Max

V+= +15V, VO= 7.5V 24 30 30 40 μA

40 38 48 Max

(4) Do not connect output to V+, when V+is greater than 13V or reliability witll be adversely affected.

AC Electrical Characteristics

Unless otherwise specified, all limits ensured for TJ= 25°C, Boldface limits apply at the temperature extremes. V+= 5V, V−=

0V, VCM = 1.5V, VO= 2.5V and RL> 1M unless otherwise specified. LMC6061AM LMC6061AI LMC6061I

Symbol Parameter Conditions Typ(1) Units

Limit(2) Limit(2) Limit(2)

SR Slew Rate See(3) 35 20 20 15 V/ms

8 10 7 Min

GBW Gain-Bandwidth Product 100 kHz

θmPhase Margin 50 Deg

enInput-Referred Voltage Noise F = 1 kHz 83 nV/√Hz

inInput-Referred Current Noise F = 1 kHz 0.0002 pA/√Hz

(1) Typical values represent the most likely parametric norm.

(2) All limits are specified by testing or statistical analysis.

(3) V+= 15V. Connected as Voltage Follower with 10V step input. Number specified is the slower of the positive and negative slew rates.

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AC Electrical Characteristics (continued)

Unless otherwise specified, all limits ensured for TJ= 25°C, Boldface limits apply at the temperature extremes. V+= 5V, V−=

0V, VCM = 1.5V, VO= 2.5V and RL> 1M unless otherwise specified. LMC6061AM LMC6061AI LMC6061I

Symbol Parameter Conditions Typ(1) Units

Limit(2) Limit(2) Limit(2)

T.H.D. Total Harmonic Distortion F = 1 kHz, AV=−5

RL= 100 kΩ, VO= 2 VPP 0.01 %

±5V Supply

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Typical Performance Characteristics

VS= ±7.5V, TA= 25°C, Unless otherwise specified

Distribution of LMC6061 Distribution of LMC6061

Input Offset Voltage Input Offset Voltage

(TA= +25°C) (TA=−55°C)

Figure 3. Figure 4.

Distribution of LMC6061

Input Offset Voltage Input Bias Current

(TA= +125°C) vs Temperature

Figure 5. Figure 6.

Supply Current Input Voltage

vs Supply Voltage vs Output Voltage

Figure 7. Figure 8.

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Typical Performance Characteristics (continued)

VS= ±7.5V, TA= 25°C, Unless otherwise specified Power Supply Rejection

Common Mode Ratio

Rejection Ratio vs

vs Frequency Frequency

Figure 9. Figure 10.

Input Voltage Noise Output Characteristics

vs Frequency Sourcing Current

Figure 11. Figure 12.

Gain and Phase Response

Output Characteristics vs Temperature

Sinking Current (−55°C to +125°C)

Figure 13. Figure 14.

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Typical Performance Characteristics (continued)

VS= ±7.5V, TA= 25°C, Unless otherwise specified

Gain and Phase Gain and Phase

Response Response

vs vs

Capacitive Load Capacitive Load

with RL= 20 kΩwith RL= 500 kΩ

Figure 15. Figure 16.

Open Loop Inverting Small Signal

Frequency Response Pulse Response

Figure 17. Figure 18.

Inverting Large Signal Non-Inverting Small

Pulse Response Signal Pulse Response

Figure 19. Figure 20.

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SNOS648D –NOVEMBER 1994–REVISED MARCH 2013

Typical Performance Characteristics (continued)

VS= ±7.5V, TA= 25°C, Unless otherwise specified Stability

Non-Inverting Large Capacitive

Signal Pulse Response Load, RL= 20 kΩ

Figure 21. Figure 22.

Stability

Capacitive

Load RL= 1 MΩ

Figure 23.

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SNOS648D –NOVEMBER 1994–REVISED MARCH 2013

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APPLICATIONS HINTS

Amplifier Topology

The LMC6061 incorporates a novel op-amp design topology that enables it to maintain rail-to-rail output swing

even when driving a large load. Instead of relying on a push-pull unity gain output buffer stage, the output stage

is taken directly from the internal integrator, which provides both low output impedance and large gain. Special

feed-forward compensation design techniques are incorporated to maintain stability over a wider range of

operating conditions than traditional micropower op-amps. These features make the LMC6061 both easier to

design with, and provide higher speed than products typically found in this ultra-low power class.

Compensating for Input Capacitance

It is quite common to use large values of feedback resistance for amplifiers with ultra-low input current, like the

LMC6061.

Although the LMC6061 is highly stable over a wide range of operating conditions, certain precautions must be

met to achieve the desired pulse response when a large feedback resistor is used. Large feedback resistors and

even small values of input capacitance, due to transducers, photodiodes, and circuit board parasitics, reduce

phase margins.

When high input impedances are demanded, guarding of the LMC6061 is suggested. Guarding input lines will

not only reduce leakage, but lowers stray input capacitance as well. (See Printed-Circuit-Board Layout For High-

Impedance Work).

The effect of input capacitance can be compensated for by adding a capacitor. Place a capacitor, Cf, around the

feedback resistor (as in Figure 24) such that:

(1)

R1CIN ≤R2Cf(2)

Since it is often difficult to know the exact value of CIN, Cfcan be experimentally adjusted so that the desired

pulse response is achieved. Refer to the LMC660 and the LMC662 for a more detailed discussion on

compensating for input capacitance.

Figure 24. Canceling the Effect of Input Capacitance

Capacitive Load Tolerance

All rail-to-rail output swing operational amplifiers have voltage gain in the output stage. A compensation capacitor

is normally included in this integrator stage. The frequency location of the dominate pole is affected by the

resistive load on the amplifier. Capacitive load driving capability can be optimized by using an appropriate

resistive load in parallel with the capacitive load (see typical curves).

Direct capacitive loading will reduce the phase margin of many op-amps. A pole in the feedback loop is created

by the combination of the op-amp's output impedance and the capacitive load. This pole induces phase lag at the

unity-gain crossover frequency of the amplifier resulting in either an oscillatory or underdamped pulse response.

With a few external components, op amps can easily indirectly drive capacitive loads, as shown in Figure 25.

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Figure 25. LMC6061 Noninverting Gain of 10 Amplifier, Compensated to Handle Capacitive Loads

In the circuit of Figure 25, R1 and C1 serve to counteract the loss of phase margin by feeding the high frequency

component of the output signal back to the amplifier's inverting input, thereby preserving phase margin in the

overall feedback loop.

Capacitive load driving capability is enhanced by using a pull up resistor to V+Figure 26. Typically a pull up

resistor conducting 10 μA or more will significantly improve capacitive load responses. The value of the pull up

resistor must be determined based on the current sinking capability of the amplifier with respect to the desired

output swing. Open loop gain of the amplifier can also be affected by the pull up resistor (see electrical

characteristics).

Figure 26. Compensating for Large Capacitive Loads with a Pull Up Resistor

Printed-Circuit-Board Layout for High-Impedance Work

It is generally recognized that any circuit which must operate with less than 1000 pA of leakage current requires

special layout of the PC board. When one wishes to take advantage of the ultra-low bias current of the

LMC6061, typically less than 10 fA, it is essential to have an excellent layout. Fortunately, the techniques of

obtaining low leakages are quite simple. First, the user must not ignore the surface leakage of the PC board,

even though it may sometimes appear acceptably low, because under conditions of high humidity or dust or

contamination, the surface leakage will be appreciable.

To minimize the effect of any surface leakage, lay out a ring of foil completely surrounding the LMC6061's inputs

and the terminals of capacitors, diodes, conductors, resistors, relay terminals etc. connected to the op-amp's

inputs, as in Figure 27. To have a significant effect, guard rings should be placed on both the top and bottom of

the PC board. This PC foil must then be connected to a voltage which is at the same voltage as the amplifier

inputs, since no leakage current can flow between two points at the same potential. For example, a PC board

trace-to-pad resistance of 1012Ω, which is normally considered a very large resistance, could leak 5 pA if the

trace were a 5V bus adjacent to the pad of the input. This would cause a 100 times degradation from the

LMC6061's actual performance. However, if a guard ring is held within 5 mV of the inputs, then even a

resistance of 1011Ωwould cause only 0.05 pA of leakage current. See Figure 28 for typical connections of guard

rings for standard op-amp configurations..

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Figure 27. Example of Guard Ring in P.C. Board Layout

Inverting Amplifier

Non-Inverting Amplifier

Follower

Figure 28. Typical Connections of Guard Rings

The designer should be aware that when it is inappropriate to lay out a PC board for the sake of just a few

circuits, there is another technique which is even better than a guard ring on a PC board: Don't insert the

amplifier's input pin into the board at all, but bend it up in the air and use only air as an insulator. Air is an

excellent insulator. In this case you may have to forego some of the advantages of PC board construction, but

the advantages are sometimes well worth the effort of using point-to-point up-in-the-air wiring. See Figure 29.

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(Input pins are lifted out of PC board and soldered directly to components. All other pins connected to PC board).

Figure 29. Air Wiring

Latchup

CMOS devices tend to be susceptible to latchup due to their internal parasitic SCR effects. The (I/O) input and

output pins look similar to the gate of the SCR. There is a minimum current required to trigger the SCR gate

lead. The LMC6061 and LMC6081 are designed to withstand 100 mA surge current on the I/O pins. Some

resistive method should be used to isolate any capacitance from supplying excess current to the I/O pins. In

addition, like an SCR, there is a minimum holding current for any latchup mode. Limiting current to the supply

pins will also inhibit latchup susceptibility.

Typical Single-Supply Applications

(V+= 5.0 VDC)

The extremely high input impedance, and low power consumption, of the LMC6061 make it ideal for applications

that require battery-powered instrumentation amplifiers. Examples of these types of applications are hand-held

pH probes, analytic medical instruments, magnetic field detectors, gas detectors, and silicon based pressure

transducers.

Figure 30 shows an instrumentation amplifier that features high differential and common mode input resistance

(>1014Ω), 0.01% gain accuracy at AV= 100, excellent CMRR with 1 kΩimbalance in bridge source resistance.

Input current is less than 100 fA and offset drift is less than 2.5 μV/°C. R2provides a simple means of adjusting

gain over a wide range without degrading CMRR. R7is an initial trim used to maximize CMRR without using

super precision matched resistors. For good CMRR over temperature, low drift resistors should be used.

If R1= R5, R3= R6, and R4= R7; then

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∴AV≈100 for circuit shown (R2= 9.822k).

Figure 30. Instrumentation Amplifier

Figure 31. Low-Leakage Sample and Hold

Figure 32. 1 Hz Square Wave Oscillator

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SNOS648D –NOVEMBER 1994–REVISED MARCH 2013

REVISION HISTORY

Changes from Revision C (March 2013) to Revision D Page

• Changed layout of National Data Sheet to TI format .......................................................................................................... 14

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PACKAGE OPTION ADDENDUM

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Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead finish/

Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

LMC6061AIM/NOPB ACTIVE SOIC D 8 95 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 LMC60

61AIM

LMC6061AIMX/NOPB ACTIVE SOIC D 8 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 LMC60

61AIM

LMC6061IM/NOPB ACTIVE SOIC D 8 95 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 LMC60

61IM

LMC6061IMX/NOPB ACTIVE SOIC D 8 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 LMC60

61IM

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

PACKAGE OPTION ADDENDUM

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Addendum-Page 2

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

LMC6061AIMX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1

LMC6061IMX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 15-Sep-2018

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

LMC6061AIMX/NOPB SOIC D 8 2500 367.0 367.0 35.0

LMC6061IMX/NOPB SOIC D 8 2500 367.0 367.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 15-Sep-2018

Pack Materials-Page 2

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PACKAGE OUTLINE

.228-.244 TYP

[5.80-6.19]

.069 MAX

[1.75]

6X .050

[1.27]

8X .012-.020

[0.31-0.51]

.150

[3.81]

.005-.010 TYP

[0.13-0.25]

0 - 8 .004-.010

[0.11-0.25]

.010

[0.25]

.016-.050

[0.41-1.27]

4X (0 -15 )

.189-.197

[4.81-5.00]

NOTE 3

B .150-.157

[3.81-3.98]

NOTE 4

4X (0 -15 )

(.041)

[1.04]

SOIC - 1.75 mm max heightD0008A

SMALL OUTLINE INTEGRATED CIRCUIT

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.

Dimensioning and tolerancing per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed .006 [0.15] per side.

4. This dimension does not include interlead flash.

5. Reference JEDEC registration MS-012, variation AA.

.010 [0.25] C A B

PIN 1 ID AREA

SEATING PLANE

.004 [0.1] C

SEE DETAIL A

DETAIL A

TYPICAL

SCALE 2.800

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EXAMPLE BOARD LAYOUT

.0028 MAX

[0.07]

ALL AROUND

.0028 MIN

[0.07]

ALL AROUND

(.213)

[5.4]

6X (.050 )

[1.27]

8X (.061 )

[1.55]

8X (.024)

[0.6]

(R.002 ) TYP

[0.05]

SOIC - 1.75 mm max heightD0008A

SMALL OUTLINE INTEGRATED CIRCUIT

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

METAL SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

EXPOSED

METAL

OPENING

SOLDER MASK METAL UNDER

SOLDER MASK

DEFINED

EXPOSED

METAL

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:8X

SYMM

SEE

DETAILS

SYMM

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EXAMPLE STENCIL DESIGN

8X (.061 )

[1.55]

8X (.024)

[0.6]

6X (.050 )

[1.27] (.213)

[5.4]

(R.002 ) TYP

[0.05]

SOIC - 1.75 mm max heightD0008A

SMALL OUTLINE INTEGRATED CIRCUIT

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL

SCALE:8X

SYMM

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