AT89C52-24PC - Atmel Corporation - Datasheet.Directory

Features

•Compatible with MCS-51™ Products

•8K Bytes of In-System Reprogrammable Flash Memory

•Endurance: 1,000 Write/Erase Cycles

•Fully Static Operation: 0 Hz to 24 MHz

•Three-level Program Memory Lock

•256 x 8-bit Internal RAM

•32 Programmable I/O Lines

•Three 16-b it Timer/Co u nter s

•Eight Interrupt Sources

•Programmable Serial Channel

•Low -po w er Idle and Po w er-do wn Mode s

Description

The AT89C52 is a low-power, high-performance CMOS 8-bit microcomputer with 8K

bytes of Flash p rogram mable an d eras able rea d only me mory (PEROM ). The dev ice

is manufactured using Atmel’s high-density nonvolatil e memory technology and is

compat ible with the industry-standar d 80C51 and 80C52 instructi on set and pinout.

The on-chip Flash allows the program memory to be reprogrammed in-system or by a

conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU

with Flash on a monolithic chip, the Atmel AT89C52 is a powerful microcomputer

which pr ovid e s a high ly - flex i ble and cost- effe ct iv e s olu tio n to many emb edde d c ontrol

applications.

8-bit

Microcontroller

with 8K Bytes

Flash

AT89C52

Not Recommended

for New Designs.

Use AT89S52.

Rev. 0313H–02/00

Pin Configurations

PQFP/TQFP

P1.5

P1.6

P1.7

RST

(RXD) P3.0

(TXD) P3.1

(INT0) P3.2

(INT1) P3.3

(T0) P3.4

iT1) P3.5

P0.4 (AD4)

P0.5 (AD5)

P0.6 (AD6)

P0.7 (AD7)

EA/VPP

ALE/PROG

PSEN

P2.7 (A15)

P2.6 (A14)

P2.5 (A13)

(WR) P3.6

(RD) P3.7

XTAL2

XTAL1

GND

(A8) P2.0

(A9) P2.1

(A10) P2.2

(A11) P2.3

(A12) P2.4

P1.4

P1.3

P1.2

P1.1 (T2 EX)

P1.0 (T2)

VCC

P0.0 (AD0)

P0.1 (AD1)

P0.2 (AD2)

P0.3 (AD3)

PDIP

(T2) P1.0

(T2 EX) P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

RST

(RXD) P3.0

(TXD) P3.1

(INT0) P3.2

(INT1) P3.3

(T0) P3.4

(T1) P3.5

(WR) P3.6

(RD) P3.7

XTAL2

XTAL1

GND

VCC

P0.0 (AD0)

P0.1 (AD1)

P0.2 (AD2)

P0.3 (AD3)

P0.4 (AD4)

P0.5 (AD5)

P0.6 (AD6)

P0.7 (AD7)

EA/VPP

ALE/PROG

PSEN

P2.7 (A15)

P2.6 (A14)

P2.5 (A13)

P2.4 (A12)

P2.3 (A11)

P2.2 (A10)

P2.1 (A9)

P2.0 (A8)

PLCC

P1.5

P1.6

P1.7

RST

(RXD) P3.0

(TXD) P3.1

(INT0) P3.2

(INT1) P3.3

(T0) P3.4

(T1) P3.5

P0.4 (AD4)

P0.5 (AD5)

P0.6 (AD6)

P0.7 (AD7)

EA/VPP

ALE/PROG

PSEN

P2.7 (A15)

P2.6 (A14)

P2.5 (A13)

(WR) P3.6

(RD) P3.7

XTAL 2

XTAL1

GND

(A8) P2.0

(A9) P2.1

(A10) P2.2

(A11) P2.3

(A12) P2.4

P1.4

P1.3

P1.2

P1.1 (T2 EX)

P1.0 (T2)

VCC

P0.0 (AD0)

P0.1 (AD1)

P0.2 (AD2)

P0.3 (AD3)

AT89C52

Block Diag ram

PORT 2 DRIVERS

PORT 2

LATCH

P2.0 - P2.7

QUICK

FLASH

PORT 0

LATCH

RAM

PROGRAM

ADDRESS

BUFFER

INCREMENTER

PROGRAM

COUNTER

DPTR

RAM ADDR.

INSTRUCTION

INTERRUPT, SERIAL PORT,

AND TIMER BLOCKS

STACK

POINTER

ACC

TMP2 TMP1

ALU

PSW

TIMING

AND

CONTROL

PORT 3

LATCH

PORT 3 DRIVERS

P3.0 - P3.7

PORT 1

LATCH

PORT 1 DRIVERS

P1.0 - P1.7

OSC

GND

VCC

PSEN

ALE/PROG

EA / VPP

RST

PORT 0 DRIVERS

P0.0 - P0.7

AT89C52

The AT89C 52 pro vides the follo wing st andar d featur es: 8K

bytes o f Fla sh , 2 56 b yt es of RAM , 3 2 I/ O lines , t hr ee 16-bi t

timer/cou nters, a six-v ector two-l evel interrup t architectu re,

a full-dupl ex serial po rt, on- chip oscill ator, and clock cir-

cuitry. In addition, the AT89C52 is designed with static logic

for operation down to zero frequency and supports two

software selectable power saving modes. The Idle Mode

stops the CPU while allowing the RAM, timer/counters,

serial po rt, and inte rrupt system to continue fu nctioning.

The Power-down mode saves the RAM contents but

freezes th e os c illa tor , di sabl ing al l othe r ch ip func ti ons un til

the next hardware reset.

Pin Description

VCC

Supply voltage.

GND

Ground.

Port 0

Port 0 is an 8-bit open drain bi-directional I/O port. As an

output port, eac h pin can s ink eight TT L inputs . When 1s

are written to port 0 pins, the pins can be used as high-

impedance inputs.

Port 0 can also be configur ed to be the multiple xed low-

order address/data b us during accesses to external pro-

gram and data memory. In this mode, P0 has internal

pullups.

Port 0 also receives the code bytes during Flash program-

ming and outputs the code bytes during program

verific ation. Extern al pull ups are requi red dur ing pro gram

verification.

Port 1

Port 1 is an 8-bit bi-directional I/O port with internal pullups.

The Port 1 output buffers can sink/source four TTL inputs.

When 1s are written to Port 1 pins, they are pulled high by

the internal pullups and can be used as inputs. As inputs,

Port 1 pins that are externally being pulled low will source

current (IIL) because of the internal pullups.

In addition, P1.0 and P1.1 can be configured to be the

timer/counter 2 external count input (P1.0/T2) and the

timer/counter 2 trigger input (P1.1/T2EX ), respectively, as

shown in the followi ng table.

Port 1 also receives the low-order address bytes during

Flash programming and verification.

Port 2

Port 2 is an 8-bit bi-directional I/O port with internal pullups.

The Port 2 output buffers can sink/source four TTL inputs.

When 1s are written to Port 2 pins, they are pulled high by

the internal pullups and can be used as inputs. As inputs ,

Port 2 pins that are externally being pulled low will sourc e

current (IIL) because of the internal pullups.

Port 2 emits the high-order address byte during fetches

from external program memory and during accesses to

externa l d ata m em or y that use 16-bi t ad dr esses (MOV X @

DPTR). In this application, Port 2 uses strong internal pul-

lups when emitting 1s. During accesses to external data

memory that use 8-bit addresses (MOVX @ RI), Port 2

emits the contents of the P2 Special Function Register.

Port 2 also receives the high-order address bits and some

control signals during Flash programming and verification.

Port 3

Port 3 is an 8-bit bi-directional I/O port with internal pullups.

The Port 3 output buffers can sink/source four TTL inputs.

When 1s are written to Port 3 pins, they are pulled high by

the internal pullups and can be used as inputs. As inputs ,

Port 3 pins that are externally being pulled low will sourc e

current (IIL) becau se of the pullups .

Port 3 also serv es the fun ctions of v arious speci al fea tures

of the AT89C51, as shown in the foll owi ng tabl e.

Port 3 also receives some control signals for Flash pro-

gramming and verification.

RST

Reset input. A high on this pin for two machine cycles while

the oscillator is running resets the device.

ALE/PROG

Address Latch Enabl e is an output pulse for latching the

low byte of the address during accesses to external mem-

ory. This pin is also the program pulse input (PROG) during

Flash programming.

In normal operation, ALE is emitted at a constant rate of 1/6

the oscillator frequency and may be used for external

Port Pin Alternate Functions

P1.0 T2 (external count input to Timer/Counter 2),

clock-out

P1.1 T2EX (Timer/Counter 2 capture/reload trigger and

directi on co ntrol )

Port Pin Alternate Functions

P3.0 RXD (serial input port)

P3.1 TXD (serial output port)

P3.2 INT0 (external interrupt 0)

P3.3 INT1 (external interrupt 1)

P3.4 T0 (timer 0 external input)

P3.5 T1 (timer 1 external input)

P3.6 WR (external data memory write strobe)

P3.7 RD (external data memor y read strobe)

AT89C52

timing or clocking purpos es. Note, however, that one ALE

pulse is skipped during each access to external data

memory.

If desired, ALE operation can be disabled by setting bit 0 of

SFR loc ation 8 EH. Wi th the bit s et, ALE is active only dur -

ing a MOVX or MOVC instruction. Otherwise, the pin is

weakly pulled high. Setting the ALE-disable bit has no

effect if the microcontroller is in external execution mode.

PSEN

Program Store Enable is the read strobe to external pro-

gram memory.

When the AT89C52 is executing code from external pro-

gram memory, PSEN is activated twice each machine

cycle, except that two PSEN activati ons ar e sk i pped durin g

each access to external data memory.

EA/VPP

External Access Enable. EA must be strapped to GND in

order to e nable the device to fe tch code fr om extern al pro-

gram memory locations starting at 0000H up to FFFFH.

Note, howe ver, t hat if lock bit 1 is pro gram med, EA will be

internally latched on reset.

EA should be strapped to VCC for internal program

executions.

This pin also receives the 12-volt programming enable volt-

age (VPP) during Flash programming when 12-volt

programming is selected.

XTAL1

Input to the inverting os cillator ampli fier and input to th e

internal clock operating circuit.

XTAL2

Output from the inverting oscillator amplifier.

Table 1. AT89C52 SFR Ma p and Reset Values

0F8H 0FFH

0F0H B

00000000 0F7H

0E8H 0EFH

0E0H ACC

00000000 0E7H

0D8H 0DFH

0D0H PSW

00000000 0D7H

0C8H T2CON

00000000 T2MOD

XXXXXX00 RCAP2L

00000000 RCAP2H

00000000 TL2

00000000 TH2

00000000 0CFH

0C0H 0C7H

0B8H IP

XX000000 0BFH

0B0H P3

11111111 0B7H

0A8H IE

0X000000 0AFH

0A0H P2

11111111 0A7H

98H SCON

00000000 SBUF

XXXXXXXX 9FH

90H P1

11111111 97H

88H TCON

00000000 TMOD

00000000 TL0

00000000 TL1

00000000 TH0

00000000 TH1

00000000 8FH

80H P0

11111111 SP

00000111 DPL

00000000 DPH

00000000 PCON

0XXX0000 87H

AT89C52

Special Function Registers

A map of the on-chip memory area called the Special Func-

tion Register (SFR) space is shown in Table 1.

Note that not all of the addresses are occupied, and unoc-

cupied addresses may not be implemented on the chip.

Read accesses to these addr esses will in general return

random data, and write accesses will have an indetermi-

nate effect.

User software should not write 1s to these unlisted loca-

tions, since they may be used in future products to invoke

new feat ures. In that c ase, the res et or inactive v alues of

the new bits will always be 0.

Timer 2 Re gisters Control a nd sta t us bi ts a r e c onta ined i n

registers T2CON (shown in Table 2) and T2MOD (shown in

Table 4) for Ti mer 2. T he regi ster pai r (RCAP2H, RCAP2L)

are the Capture/Reload registers for Timer 2 in 16-bit cap-

ture mode or 16-bit auto-reload mode.

Interrupt Registers The individual interrupt enable bits are

in the IE register. Two priorities can be set for each of the

six interrupt sources in the IP register.r

Data Memory

The AT89C52 implements 256 bytes of on-chip RAM. The

upper 128 byte s occupy a parall el addres s space to the

Special Function Registers. That means the upper 128

bytes have the sam e ad dre sse s as the SFR spac e b ut a re

physically separate from SFR space.

When an instruction accesses an internal location above

address 7FH, the address mode used in the instruction

specifies whether the CPU ac cesses the upp er 128 bytes

of RAM or the SFR space. Instructions that use direct

addressing access SFR space.

For example, the following direct addressing instruction

accesses the SFR at location 0A0H (which is P2).

MOV 0A0H, #data

Table 2. T2CON – Timer/Counter 2 Control Registe

T2CO N Address = 0C8H Reset Value = 0000 0000B

Bit Addressable

Bit TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2

76543210

Symbol Function

TF2 Timer 2 overflow flag set by a Timer 2 overflow and must be clea red by so ftware. TF2 will not be set when either

RCLK = 1 or TCLK = 1.

EXF2 Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and

EXEN2 = 1. When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2 interrupt

routine. EXF2 must be cleared by software. EXF2 does not cause an interrupt in up/down counter mode

(DCEN = 1).

RCLK Receive clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its receive clock in serial

port Modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the receive clock.

TCLK Transmit clo c k enab l e. W hen se t, caus es the s erial port to use Timer 2 o v erfl ow pu lses for its trans mit cl ock in serial

port Modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock.

EXEN2 Timer 2 exter nal enable. When set, allows a capture or reload to occur as a result of a negative transition on T2EX

if Timer 2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to ignore events at T2EX.

TR2 Start/Stop control for Timer 2. TR2 = 1 star ts the timer.

C/T2 Timer or counter select for Timer 2. C/T2 = 0 for timer function. C/T2 = 1 for external event counter (falling edge

triggered).

CP/RL2 Capt ure/Reload select. CP /RL2 = 1 c auses capt ures to occu r on negati ve transiti ons at T2EX if EX EN2 = 1. C P/RL2

= 0 causes automatic reloads to occur when Timer 2 overflows or negative transitions occur at T2EX when EXEN2

= 1. When either RCLK or TCLK = 1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow.

AT89C52

Instructions that use indirect addressing access the upper

128 bytes of RAM. For example, the following indirect

address i ng i nst ructi on, where R0 con tains 0A0 H , accesses

the da ta byte at address 0A0H, rather than P2 (w hose

address is 0A0H).

MOV @R0, #data

Note that stack operations are examples of indirect

address ing, so th e upper 128 bytes o f data RAM ar e av ail-

able as stack space.

Timer 0 and 1

Timer 0 and Timer 1 in the AT89C52 operate the same way

as Timer 0 and Timer 1 in the AT89C51.

Timer 2

Timer 2 is a 16-bit Timer/Counter that can operate as either

a timer or an event counter. The type of operation is

selected by bit C/T2 in the SFR T2CON (shown in Table 2).

Timer 2 has three operating modes: capture, auto-reload

(up or down counting), and baud rate generator. The

modes are selected by bits in T2CON, as shown in Table 3.

Timer 2 co ns is ts of two 8-bit re gis ter s, T H2 a nd T L2 . In th e

Timer function, the TL2 register is incremented every

machine cycle. Since a machine cycle consists of 12 oscil-

lator periods, the count rate is 1/12 of the oscillator

frequency.

In the Counter function, the register is incremented in

response to a 1-to-0 transition at its corresponding external

input p in, T2 . I n this func tion, the e xterna l in put i s samp le d

during S5P2 of every machine cycle. When the samples

show a high in one cycle and a low in the next cycle, the

count is incremented. The new count value appears in the

the transition was detected. Since two machine cycles (24

oscillato r peri ods ) ar e required to r ecognize a 1-to- 0 trans i-

tion, the maximum count rate is 1/24 of the oscillator

frequen cy. To ensu re that a giv en level is samp led at leas t

once before it changes, the level should be held for at least

one full machi ne cycl e.

Capture Mode

In the capture mode, two options are selected by bit

EXEN2 in T2CON. If EXEN2 = 0, Timer 2 is a 16-bit timer

or counter which upon overflow sets bit TF2 in T2CON.

This bit can then be used to generate an interrupt. If

EXEN2 = 1, T imer 2 perf orms the sa me ope ration, but a 1-

to-0 transition at external input T2EX also causes the cur-

rent value in TH2 and TL2 to be captured into RCAP2H and

RCAP2L, respectively. In addition, the transition at T2EX

causes bi t EXF2 in T2CO N to be set. Th e EXF2 bit, like

TF2, can generate an interrupt. The capture mode is illus-

trated in Figu re 1.

Auto-reload (Up or Down Counter)

Timer 2 can be programmed to count up or down when

configured in its 16-bit auto-reload mode. This feature is

invoked by the DCEN (Down Counter Enable) bit located in

the SFR T2MOD (see Table 4). Upon reset, the DCEN bit

is set to 0 so that timer 2 will default to count up. When

DCEN is set, Ti mer 2 c an co unt up or d own, de pendin g on

the value of the T2EX pin.

Table 3. Timer 2 Operating Modes

RCLK +TCLK CP/RL2 TR2 MODE

0 0 1 16-bit Auto-reload

0 1 1 16-bit Capture

1 X 1 Baud Rate Generator

X X 0 (Off)

AT89C52

Figure 1. Timer in Capture Mode

Figure 2 shows Timer 2 automatically counting up when

DCEN = 0. In this mode, two options are selected by bit

EXEN2 in T2CON. If EXEN2 = 0, Timer 2 counts up to

0FFFFH and then sets the TF2 bit upon overflow. The

overflow also causes the timer registers to be reloaded with

the 16-bit value in RCAP2H and RCAP2L. The values in

Timer in Capture ModeRCAP2H and RCAP2L are preset

by soft ware. If EX EN2 = 1, a 1 6- bit rel oad c an be tri gge re d

either by an overflow or by a 1-to-0 transition at external

input T2EX . Thi s tran si tio n als o s ets the E X F2 bi t. Bo th th e

TF2 and EXF2 bits can generate an interrupt if enabled.

Setting the DCEN bit enab le s Ti mer 2 to cou nt up or down ,

as shown in Figure 3. In this mode, the T2EX pin controls

the direction of the count. A logic 1 at T2EX makes Timer 2

count up. T he timer will ov erflow a t 0FFFFH and set t he

TF2 bit. This overflow also causes the 16-bit value in

RCAP2H and RCAP2L to be reloaded into the timer regis-

ters, TH2 and TL2, respe ct ivel y.

A logic 0 at T2EX makes Timer 2 count down. The timer

underflows when TH2 and TL 2 equal the values s tored in

RCAP2H and RCAP2L. The underflow sets the TF2 bit and

causes 0FFFFH to be reloaded into the timer registers.

The EXF2 bit toggles whenever Timer 2 overflows or

underflows and can be used as a 17th bit of r esolution. In

this operating mode, EXF2 does not flag an interrupt.

OSC

EXF2

T2EX PIN

T2 PIN

TR2

EXEN2

C/T2 = 0

C/T2 = 1 CONTROL

CAPTURE

OVERFLOW

CONTROL

TRANSITION

DETECTOR TIMER 2

INTERRUPT

÷12

RCAP2LRCAP2H

TH2 TL2 TF2

AT89C52

Figure 2. Timer 2 Auto Reload Mode (DCEN = 0)

Table 4. T2MOD – Timer 2 Mode Control Register

T2MOD Address = 0C9H Reset Value = XXXX XX00B

Not Bit Addressable

––––––T2OEDCEN

Bit76543210

Symbol Function

– Not implemented, reserved for future

T2OE Timer 2 Output Enable bit.

DCEN When set, this bit allows Timer 2 to be configured as an up/down counter.

OSC

EXF2

TF2

T2EX PIN

T2 PIN

TR2

EXEN2

C/T2 = 0

C/T2 = 1

CONTROL

RELOAD

OVERFLOW

CONTROL

TRANSITION

DETECTOR

TIMER 2

INTERRUPT

÷12

RCAP2LRCAP2H

TH2 TL2

AT89C52

Figure 3. Timer 2 Auto Reload Mode (DCEN = 1)

Figure 4. Timer 2 in Baud Rate Generator Mode

OSC

EXF2

TF2

T2EX PIN

COUNT

DIRECTION

1=UP

0=DOWN

T2 PIN

TR2

CONTROL

OVERFLOW

(DOWN COUNTING RELOAD VALUE)

(UP COUNTING RELOAD VALUE)

TOGGLE

TIMER 2

INTERRUPT

RCAP2LRCAP2H

0FFH0FFH

TH2 TL2

C/T2 = 0

C/T2 = 1

OSC

SMOD1

RCLK

TCLK

CLOCK

T2EX PIN

T2 PIN

TR2

CONTROL

"1"

"0"

TIMER 1 OVERFLOW

NOTE: OSC. FREQ. IS DIVIDED BY 2, NOT 12

TIMER 2

INTERRUPT

RCAP2LRCAP2H

TH2 TL2

C/T2 = 0

C/T2 = 1

EXF2

CONTROL

TRANSITION

DETECTOR

EXEN2

AT89C52

Baud Rate Generator

Time r 2 is selected as the bau d rate gener ator by se tting

TCLK and/or RCLK in T2CON (Table 2). Note that the

baud rates for transmit and receive can be different if Timer

2 is used for the receiver or transmitter and Timer 1 is used

for the other function. Setting RCLK and/or TCLK puts

Timer 2 into its baud rate generator mode, as shown in Fig-

ure 4.

The baud rate ge nerator mode is simila r to the auto-reloa d

mode, in that a rollover in TH2 causes the Timer 2 registers

to be reloaded with the 16-bit value in registers RCAP2H

and RCAP2L, which are preset by software.

The baud rates i n Mode s 1 an d 3 ar e determi ned by Timer

2’s overflow rate according to the following equation.

The Timer can be configured for either timer or counter

operatio n. In most a pplications, i t is configu red for timer

operation (CP/T 2 = 0) . The timer o peration is different for

Timer 2 when it is used as a baud rate generator. Normally,

as a timer, i t increments e very machine c ycle (at 1/12 the

oscill ator freq uency ). As a bau d rate ge nerat or, howeve r, it

increments every state time (at 1/2 the oscillator fre-

quency). The baud rate formula is given below.

where (RCAP2 H, RCAP2 L) is the c ontent of RCAP2H an d

RCAP2L taken as a 16-bit unsigned integer.

Timer 2 as a baud rate generator is shown in Figure 4. This

figure is valid only if RCLK or TCLK = 1 in T2CON. Note

that a rollover in TH2 does not set TF2 and will not gener-

ate an interrupt. Note too, that if EXEN2 is set, a 1-to-0

transi tion in T2EX wi ll set EXF2 but will not caus e a reload

from (RCAP2H, RCAP2L) to ( TH2, TL2). Thu s when Ti mer

2 is in use as a baud rate g enera tor, T2E X can be us ed as

an extra external interrupt.

Note that when Timer 2 is running ( TR2 = 1) as a timer in

the baud r ate generator mode, TH2 or TL 2 should not be

read from or written to. Under these conditions, the Timer is

incremented every state time, and the results of a read or

write may not be accurate. The RCAP2 registers may be

read but should not be written to, because a write might

overlap a reload and cause write and/or reload errors. The

timer should be turned off (clear TR2) before accessing the

Timer 2 or RCAP2 registers.

Figure 5. Timer 2 in Clock-out Mode

Modes 1 and 3 Baud Rates Timer 2 Overflow Rate

------------------------------------------------------------=

Modes 1 and 3

Baud Rate

--------------------------------------- Oscillator Frequency

32 65536 RCAP2H RCAP2L(,)–[]×

----------------------------------------------------------------------------------------------=

OSC

EXF2

P1.0

(T2)

P1.1

(T2EX)

TR2

EXEN2

C/T2 BIT

TRANSITION

DETECTOR

TIMER 2

INTERRUPT

T2OE (T2MOD.1)

÷2 TL2

(8-BITS)

RCAP2L RCAP2H

TH2

(8-BITS)

÷2

AT89C52

Programmable Clock Out

A 50% duty cycle clock can be programmed to come out on

P1.0, as shown in Figure 5. This pin, besides being a regu-

lar I/O pin, has two alternate functions. It can be

programmed to input the external clock for Timer/Counter 2

or to output a 50% duty cycle clock ranging from 61 Hz to 4

MHz at a 16 MHz operating frequency.

To configure the Timer/Counter 2 as a clock generator, bit

C/T2 (T2CON.1) must be cleared and bit T2OE (T2MOD.1)

must be set. Bit TR2 (T2CON.2) starts and stops the timer.

The clock-out frequency depends on the oscillator fre-

quency and the reload value of Timer 2 capture registers

(RCAP2H, RCAP2L), as shown in the following equation.

In the clock-out mode, Timer 2 roll-overs will not generate

an interrupt. This behavior is similar to when Timer 2 is

used as a baud-rate generator. It is possible to use Timer 2

as a baud-rate generator and a clock generator simulta-

neous ly. Note, howe ver, tha t the baud-r ate and clock -out

freque ncies ca nnot be determi ned inde pend ently fro m one

another since they both use RCAP2H and RCAP2L.

UART

The UART in the AT89C52 operates the same way as the

UART in the AT89C51.

Interrupts

The AT89C52 has a total of six interrupt vectors: two exter-

nal interrupts (INT0 and INT1), three timer interrupts

(Timers 0 , 1, and 2), and the ser ial port interrupt. T hese

interrupts are all shown in Figure 6.

Each of these interrupt sources can be individually enabled

or disabled by setting or cl earing a bit in Specia l Function

disables all interrupts at once.

Note that Table shows that bit position IE.6 is unimple-

mented. In the AT89C51, bit position IE.5 is also

unimplem ent ed. User so ftwar e sh oul d n ot wr it e 1 s to th ese

bit positions, since they may be used in future AT89

products.

Timer 2 interrupt i s g ene rated by the lo gi ca l OR of b its T F2

and EXF2 in register T2CON. Neither of these flags is

cleared by hardwar e when the service routine is vect ored

to. In fact, the service routine may have to determine

whether it was TF2 or EXF2 that generated the interrupt,

and that bit will have to be cleared in software.

The Timer 0 and Timer 1 flags, TF0 and TF1, are set at

S5P2 of the c ycle in wh ich the t imers ove rflo w. The val ues

are then polled by the circuitry in the next cycle. However,

the Timer 2 flag, TF2, is set at S2P2 and is polled in the

same cyc le in which the tim er overflo ws .

Figure 6. Interrupt Sources

Clock-Out Frequency Oscill ator Fequency

4 65536 RCAP2H RCAP2L(,)–[]×

-------------------------------------------------------------------------------------------=

Table 5. Interrupt Enable (IE) Register

(MSB) (LSB)

EA – ET2 ES ET1 EX1 ET0 EX0

Enable Bit = 1 enables the interrupt.

Enable Bit = 0 disab les the interrupt.

Symbol Position Function

EA IE.7 Disables all interrupts. If EA = 0,

no interrupt is acknowledged. If

EA = 1, each interrupt source is

individually enabled or disabled

by setting or clearing its enable

bit.

– IE.6 Reserved.

ET2 IE.5 Timer 2 interrupt enable bit.

ES IE.4 Serial Po rt interrupt enable bit.

ET1 IE.3 Timer 1 interrupt enable bit.

EX1 IE.2 External interrupt 1 enable bit.

ET0 IE.1 Timer 0 interrupt enable bit.

EX0 IE.0 External interrupt 0 enable bit.

User software should never write 1s to unimplemented bits,

because they may be used in future AT89 products.

IE1

IE0

TF1

TF0

INT1

INT0

TF2

EXF2

AT89C52

Oscillator Characteristics

XTAL1 a nd XTAL2 ar e the inp ut and ou tput, resp ectively,

of an invertin g ampli fier that can be configured for use as

an on-c hip osci llator, as shown in Figure 7. Either a qua rtz

crystal or ceramic resonator may be used. To drive the

device from a n ext er nal cl ock so ur ce , XTAL 2 sh oul d be le ft

uncon nect ed whil e XTAL 1 is driv en, as shown in F igure 8.

There are no requirements on the duty cycle of the external

clock signal, since the input to the internal clocking circuitry

is through a divide-by-two flip-flop, but minimum and maxi-

mum voltage high and low time specifications must be

observed.

Idle Mode

In idle mode, the CPU puts itself to sleep while all the on-

chip peripherals remain active. The mode is invoked by

software. The content of the on-chip RAM and all the spe-

cial functions registers remain unchanged during this

mode. The i dle mode can be termi nated by any enable d

interrupt or by a hardware reset.

Note that when idle mode is terminated by a hardware

reset, the device normally resumes program execution

from where it left off, up to two machine cycles before the

internal reset algorithm takes control. On-chip hardw are

inhibi ts access to interna l RAM in this event, but ac cess to

the port pins is not inhibited. To eliminate the possibility of

an unexpected write to a port pin when idle mode is termi-

nated by a reset, the instruction following the one that

invo ke s id le mode s hould not write to a port pin or to exter -

nal memory.

Power-down Mode

In the power -dow n mode, the osc illator is sto pped, an d the

instruc tion that invoke s powe r-down is the las t instru ction

executed. The on-chip RAM and Special Function Regis-

ters retain their values until the power-down mode is

termina ted. The only exit from po wer-down is a hardwar e

reset. Re set rede fines the SFRs but does not change th e

on-chip RAM. The reset should not be activated before VCC

is re stored to its no rmal o peratin g level and mu st be h eld

active long enough to allow the oscillator to restart and

stabilize.

Figure 7. Osci ll ato r Conn ec tio ns

Note: C1, C2 = 30 pF ± 10 pF for Crystals

= 40 pF ± 10 pF for Ceramic Resonators

Figure 8. External Clock Drive Configuration

C2 XTAL2

GND

XTAL1

XTAL2

XTAL1

GND

EXTERNAL

OSCILLATOR

SIGNAL

Status of External Pins During Idle and Powe-down Modes

Mode Program Memory ALE PSEN PORT0 PORT1 PORT2 PORT3

Idle Internal 1 1 Data Data Data Data

Idle External 1 1 Float Data Address Data

Power-down Internal 0 0 Data Data Data Data

Power-down External 0 0 Float Data Data Data

AT89C52

Program Memory Lock Bits

The AT89C52 has three lock bits that can be lef t unpro-

grammed (U) or can be programmed (P) to obtain the

additional features listed in the following table.

When lock bit 1 is programmed, the logic level at the EA pin

is sample d and la tched during reset. If the device is pow-

ered up without a r eset, the latch ini tializes to a rando m

value and holds that value until reset is activated. The

latched value of EA must ag ree w ith the c urren t logi c lev el

at that pin in order for the device to function properly.

Programming the Flash

The AT89C52 is normally shipped with the on-chip Flash

memory array in the erased state (that is, contents = FFH)

and ready to be programmed. The programming interface

accepts either a high-voltage (12-volt) or a low-voltage

(VCC) pr ogram enable signal. T he Low-voltage progr am-

ming mode provides a convenient way to program the

AT89C52 inside the us er’s system, whi le the high-voltage

progra mming m ode is co mpatib le with convent ional th ird-

party Flash or EPROM programmers.

The AT89C52 is shipped with either the high-voltage or

low-voltage programming mode enabled. The respective

top-sid e marking and devi ce sig nature code s are l isted in

the foll owing table.

The AT89 C52 cod e memor y arr ay is pr ogramme d byte -by-

byte in either programming mode. To program any non-

blank byte in the on-chip Flas h Memory, the entire memory

must be erased using the Chip Erase Mode.

Programming Algorithm Before programming the

AT89 C52, the addres s, data and con trol si gnals s hould b e

set up according to the Flash programming mode table and

Figure 9 and Figure 10. To program the AT89C52, take the

following steps.

1. Input the desired memory location on the address

lines.

2. Input the appropriate data byte on the data lines.

3. Activate the correct combination of control signals.

4. Raise EA/VPP to 12V for the high-voltage program-

ming mode.

5. Pulse ALE/PROG once to program a byte in the

Flash array or the lock bits. The byte-write cycle is

self-timed and typically takes no more than 1.5 ms.

Repeat steps 1 through 5, changing the address

and data for the entire array or until the end of the

object file is reached.

Data Polling The AT89C52 features Data Polling to indi-

cate the end of a write cycle. During a write cycle, an

attempted read of the last byte written will result in the com-

plement of th e written data on PO.7 . Once the write cycl e

has been completed, true data is valid on all outputs, and

the next c ycle may be gin. Data Polling may begin any time

after a write cycle has been initiated.

Ready/Busy Th e progress of byte pro gramming can also

be monito red by th e RDY /BS Y outp ut sig nal . P 3.4 is pul le d

low after ALE goes h igh during programming to indicate

BUSY. P3.4 is pulled high again when programming is

done to indicate READY.

Program Verify If lock bi ts LB1 and L B2 have n ot been

programmed, the programmed code data can be read back

via the addr ess and da ta lines for verificati on. The lo ck bits

cannot be v erified directly . Verification of the lock bits is

achieved by observing that their features are enabled.

Chip Erase The entir e Flas h array is era sed el ectric ally by

using the proper combination of control signals and by

holding ALE/PROG low f or 10 ms. T he code arra y is writ ten

with all 1s. The chip erase operation must be executed

before the code memory can be reprogrammed.

Lock Bit Protection Modes

Program Lock Bits

LB1 LB2 LB3 Protection Type

1 U U U No program lock features.

2 P U U MOVC instructions executed

from external program

memory are disable d fr o m

fetching code bytes from

internal memory, EA is

sample d and latche d on reset,

and further programming of

the Flash memory is disabled.

3 P P U Same as mode 2, but verify is

also disabled.

4 P P P Same as m ode 3, but external

execution is also disabled.

VPP = 12V VPP = 5V

Top-side Mark AT89C52

xxxx

yyww

AT89C52

xxxx - 5

yyww

Signature (030H) = 1EH

(031H) = 52H

(032H) = FFH

(030H) = 1EH

(031H) = 52H

(032H) = 05H

VPP = 12V VPP = 5V

AT89C52

Reading th e Signature Bytes The signature bytes are

read by the same procedure as a normal verification of

locations 030H, 031H, and 032H, except that P3.6 and

P3.7 must be pul le d to a logi c low. The va lue s retur ne d ar e

as follows.

(030H) = 1EH indicates manufactured by Atmel

(031H) = 52H indicates 89C52

(032H) = FFH indicates 12V programming

(032H) = 05H indicates 5V programming

Pr ogramming Interface

Every code byte in the Flash array can be written, and the

entire array can be erased, by using the appropriate combi-

nation of control signals. T he write operation cycle is self-

timed and once initiated, will automatically time itself to

completion.

All maj or prog rammi ng ven dors off er world wide s uppor t for

the Atmel microcontroller series. Please contact your local

programming vendor for the appropriate software revision.

Note: 1. Chip Erase requires a 10 ms PROG pulse.

Flash Programming Modes

Mode RST PSEN ALE/PROG EA/VPP P2.6 P2.7 P3.6 P3.7

Write Code Data H L H/12V L H H H

Read Code Data H L H H L L H H

Write Lock Bit - 1 H L H/12V H H H H

Bit - 2 H L H/12V H H L L

Bit - 3 H L H/12V H L H L

Chip Erase H L H/12V H L L L

Read Signature Byte H L H H L L L L

(1)

AT89C52

Figure 9. Programming the Flash Memory Figure 10. Verifying the Flash Memory

Note: 1. Only used in 12-volt programming mode.

P2.6

P3.6

P2.0 - P2.4

A0 - A7

ADDR.

OOOOH/1FFFH

SEE FLASH

PROGRAMMING

MODES TABLE

3-24 MHz

A8 - A12 P0

+5V

P2.7

PGM

DATA

PROG

V/V

IH PP

ALE

P3.7

XTAL2 EA

RST

PSEN

XTAL1

GND

AT87F52

P2.6

P3.6

P2.0 - P2.4

A0 - A7

ADDR.

OOOOH/1FFFH

SEE FLASH

PROGRAMMING

MODES TABLE

3-24 MHz

A8 - A12 P0

+5V

P2.7

PGM DATA

(USE 10K

PULLUPS)

ALE

P3.7

XTAL2 EA

RST

PSEN

XTAL1

GND

AT87F52

Flash Programming and Verification Characteristics

TA = 0°C to 70°C, VCC = 5.0 ± 10%

Symbol Parameter Min Max Units

VPP(1) Programming Enable Voltage 11.5 12.5 V

IPP(1) Programming Enable Current 1.0 mA

1/tCLCL Oscillator Frequency 3 24 MHz

tAVGL Address Setup to PROG Low 48tCLCL

tGHAX Address Hold after PROG 48tCLCL

tDVGL Data Setup to PROG Low 48tCLCL

tGHDX Data Hold After PROG 48tCLCL

tEHSH P2.7 (ENABLE) High to VPP 48tCLCL

tSHGL VPP Setup to PROG Low 10 µs

tGHSL(1) VPP Hold after PROG 10 µs

tGLGH PROG Width 1 110 µs

tAVQV Address to Data Valid 48tCLCL

tELQV ENABLE Low to Data Valid 48tCLCL

tEHQZ Data Float after ENABLE 048t

CLCL

tGHBL PROG High to BUSY Low 1.0 µs

tWC Byte Write Cycle Time 2.0 ms

AT89C52

Flash Programming and Verificatio n Waveforms - High-voltage Mode (VPP=12V)

Flash Programming and Verificatio n Waveforms - Low-voltage Mode (VPP=5V)

tGLGH tGHSL

tAVGL

tSHGL

tDVGL tGHAX

tAVQV

tGHDX

tEHSH tELQV

tWC

BUSY READY

tGHBL

tEHQZ

P1.0 - P1.7

P2.0 - P2.4

ALE/PROG

PORT 0

LOGIC 1

LOGIC 0

EA/VPP

VPP

P2.7

(ENABLE)

P3.4

(RDY/BSY)

PROGRAMMING

ADDRESS VERIFICATION

ADDRESS

DATA IN DATA OUT

(2)

tGLGH

tAVGL

tSHGL

tDVGL tGHAX

tAVQV

tGHDX

tEHSH tELQV

tWC

BUSY READY

tGHBL

tEHQZ

P1.0 - P1.7

P2.0 - P2.4

ALE/PROG

PORT 0

LOGIC 1

LOGIC 0

EA/VPP

P2.7

(ENABLE)

P3.4

(RDY/BSY)

PROGRAMMING

ADDRESS VERIFICATION

ADDRESS

DATA IN DATA OUT

AT89C52

Notes: 1. Under steady state (non-transient) conditions, IOL must be externally limited as follows:

Maximum IOL per port pin: 10 mA

Maximum IOL per 8-bit port:

Port 0: 26 mA Ports 1, 2, 3: 15 mA

Maximum total IOL for all output pins: 71 mA

If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater

than the listed test conditions.

2. Minimum VCC for Power-down is 2V.

Absolute Maxim u m Ratings*

Operating Temperature.................................. -55°C to +125°C *NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam-

age to th e de vice . This is a stress rating o nly and

funct ional ope ration of the de vice at the se or an y

other conditions beyond those indicated in the

operational sections of this specification is not

implied. Exposure to absolute maximum rating

conditions for extended periods may affect

device reliability.

Storage Temperature..................................... -65°C to +150°C

Voltage on Any Pin

with Respect to Ground.....................................-1.0V to +7.0V

Maximu m Op er ati ng Voltage ....................... ...... ..... ...... .... 6.6V

DC Output Current...................... ............................ .... 15.0 mA

DC Characteristics

The values shown in this table are valid for TA = -40°C to 85°C and VCC = 5.0V ± 20%, unless otherwise noted.

Symbol Parameter Condition Min Max Units

VIL Input Low-voltage (Except EA)-0.50.2 V

CC-0.1 V

VIL1 Input Low-voltage (EA)-0.50.2 V

CC-0.3 V

VIH Input High-voltage (Except XTAL1, RST) 0.2 VCC+0.9 VCC+0.5 V

VIH1 Input High-voltage (XTAL1, RST) 0.7 VCC VCC+0.5 V

VOL Output Low-voltage(1) (Ports 1,2,3) IOL = 1.6 mA 0.45 V

VOL1 Output Low-voltage(1)

(Port 0, ALE, PSEN)IOL = 3.2 mA 0.45 V

VOH Output High-voltage

(Por ts 1,2,3, ALE , PSEN)IOH = -60 µA, VCC = 5V ± 10% 2.4 V

IOH = -25 µA 0.75 VCC V

IOH = -10 µA 0.9 VCC V

VOH1 Output High-voltage

(Port 0 in External Bus Mode) IOH = -800 µA, VCC = 5V ± 10% 2.4 V

IOH = -300 µA 0.75 VCC V

IOH = -80 µA 0.9 VCC V

IIL Logical 0 Input Current (Ports 1,2,3) VIN = 0.45V -50 µA

ITL Logical 1 to 0 Tr ansition Current

(Po rts 1,2,3) VIN = 2V, VCC = 5V ± 10% -650 µA

ILI Input Leakage Current (Port 0, EA) 0.45 < VIN < VCC ±10 µA

RRST Reset Pulldown Resistor 50 300 KΩ

CIO Pin Capacitance Test Freq. = 1 MHz, TA = 25°C10pF

ICC Power Supply Current Active Mode, 12 MHz 25 mA

Idle Mode, 12 MHz 6.5 mA

Power-down Mode(1) VCC = 6V 100 µA

VCC = 3V 40 µA

AT89C52

AC Characteristics

Under operating conditions, load capacitance for Port 0, ALE/PROG, and PSEN = 100 pF; load capacitance for all other

outputs = 80 pF.

External Program and Data Memory Characteri stics

Symbol Parameter

12 MHz Oscillator Variable Oscillator

UnitsMin Max Min Max

1/tCLCL Oscillator Frequency 0 24 MHz

tLHLL ALE Pulse Width 127 2tCLCL-40 ns

tAVLL Address Valid to ALE Low 43 tCLCL-13 ns

tLLAX Address Hold After ALE Low 48 tCLCL-20 ns

tLLIV ALE Low to Valid Instruction In 233 4tCLCL-65 ns

tLLPL ALE Low to PSEN Low 43 tCLCL-13 ns

tPLPH PSEN Pulse Width 205 3tCLCL-20 ns

tPLIV PSEN Low to Valid Instruction In 145 3tCLCL-45 ns

tPXIX Input Instruction Hold after PSEN 00ns

tPXIZ Input Instruction Float after PSEN 59 tCLCL-10 ns

tPXAV PSEN to Address Valid 75 tCLCL-8 ns

tAVIV Address to Valid Instruction In 312 5tCLCL-55 ns

tPLAZ PSEN Low to Address Float 10 10 ns

tRLRH RD Pulse Width 400 6tCLCL-100 ns

tWLWH WR Pulse Width 400 6tCLCL-100 ns

tRLDV RD Low to Valid Data In 252 5tCLCL-90 ns

tRHDX Data Hold After RD 00ns

tRHDZ Data Float After RD 97 2tCLCL-28 ns

tLLDV ALE Low to Valid Data In 517 8tCLCL-150 ns

tAVDV Address to Valid Data In 585 9tCLCL-165 ns

tLLWL ALE Low to RD or WR Low 200 300 3tCLCL-50 3tCLCL+50 ns

tAVWL Address to RD or WR Low 203 4tCLCL-75 ns

tQVWX Data Valid to WR Transition 23 tCLCL-20 ns

tQVWH Data Valid to WR High 433 7tCLCL-120 ns

tWHQX Data Hold After WR 33 tCLCL-20 ns

tRLAZ RD Low to Address Float 0 0 ns

tWHLH RD or WR High to ALE High 43 123 tCLCL-20 tCLCL+25 ns

AT89C52

External Program Memory Read Cycle

External Data Memory Read Cyc le

tLHLL

tLLIV

tPLIV

tLLAX tPXIZ

tPLPH

tPLAZ tPXAV

tAVLL tLLPL

tAVIV

tPXIX

ALE

PSEN

PORT 0

PORT 2

A8 - A15

A0 - A7 A0 - A7

A8 - A15

INSTR IN

tLHLL

tLLDV

tLLWL

tLLAX

tWHLH

tAVLL

tRLRH

tAVDV

tAVWL

tRLAZ tRHDX

tRLDV tRHDZ

A0 - A7 FROM RI OR DPL

ALE

PSEN

PORT 0

PORT 2

P2.0 - P2.7 OR A8 - A15 FROM DPH

A0 - A7 FROM PCL

A8 - A15 FROM PCH

DATA IN INSTR IN

AT89C52

External Data Memory Write Cycle

External Clock Drive Waveforms

tLHLL

tLLWL

tLLAX

tWHLH

tAVLL

tWLWH

tAVWL

tQVWX tQVWH tWHQX

A0 - A7 FROM RI OR DPL

ALE

PSEN

PORT 0

PORT 2

P2.0 - P2.7 OR A8 - A15 FROM DPH

A0 - A7 FROM PCL

A8 - A15 FROM PCH

DATA OUT INSTR IN

tCHCX tCHCX

tCLCX tCLCL

tCHCL

tCLCH

V - 0.5V

0.45V 0.2 V - 0.1V

0.7 V

External Clock Drive

Symbol Parameter Min Max Units

1/tCLCL Oscillator Frequency 0 24 MHz

tCLCL Clock Period 41.6 ns

tCHCX High Time 15 ns

tCLCX Low Time 15 ns

tCLCH Rise Time 20 ns

tCHCL Fall Time 20 ns

AT89C52

Shift Register Mode Timing Waveforms

AC Testing Input/Output Waveforms(1)

Note: 1. AC Inputs during testing are driven at VCC - 0.5V

for a logic 1 and 0.45V for a logic 0. Timing measure-

ments are ma de at V IH min. for a logic 1 and V IL max.

for a logic 0.

Float Waveforms(1)

Note: 1. For timing purposes, a port pin is no longer floating

when a 100 mV change from load voltage occurs. A

port pin begins to float when a 100 mV change from

the loaded VOH/VOL level occurs.

Serial Port Timing: Shift Register Mode Test Conditions

The values in this table are valid for VCC = 5.0V ± 20% and Load Capacitance = 80 pF.

Symbol Parameter

12 MHz Osc Variable Oscillator

UnitsMin Max Min Max

tXLXL Serial Port Clock Cy c le Time 1.0 12tCLCL µs

tQVXH Output Data Setup to Clock Rising Edge 700 10tCLCL-133 ns

tXHQX Output Data Hold After Clock Rising Edge 50 2tCLCL-117 ns

tXHDX Input Data Hold After Clock Rising Edge 0 0 ns

tXHDV Clock Rising Edge to Input Data Valid 700 10tCLCL-133 ns

tXHDV

tQVXH

tXLXL

tXHDX

tXHQX

ALE

INPUT DATA

CLEAR RI

OUTPUT DATA

WRITE TO SBUF

INSTRUCTION

CLOCK

SET TI

SET RI

VALID VALIDVALID VALIDVALID VALIDVALID VALID

0.45V

TEST POINTS

V - 0.5V

CC 0.2 V + 0.9V

0.2 V - 0.1V

VLOAD+ 0.1V

Timing Reference

Points

LOAD- 0.1V

LOAD VVOL+ 0.1V

VOL - 0.1V

AT89C52

Ordering In formation

Speed

(MHz) Power

Supply Ordering Code Package Operation Range

12 5V ± 20% AT89C52-12AC

AT89C52-12JC

AT89C52-12PC

AT89C52-12QC

44A

44J

40P6

44Q

Commercial

(0°C to 70°C)

AT89C52-12AI

AT89C52-12JI

AT89C52-12PI

AT89C52-12QI

44A

44J

40P6

44Q

Industrial

(-40°C to 85°C)

16 5V ± 20% AT89C52-16AC

AT89C52-16JC

AT89C52-16PC

AT89C52-16QC

44A

44J

40P6

44Q

Commercial

(0°C to 70°C)

AT89C52-16AI

AT89C52-16JI

AT89C52-16PI

AT89C52-16QI

44A

44J

40P6

44Q

Industrial

(-40°C to 85°C)

20 5V ± 20% AT89C52-20AC

AT89C52-20JC

AT89C52-20PC

AT89C52-20QC

44A

44J

40P6

44Q

Commercial

(0°C to 70°C)

AT89C52-20AI

AT89C52-20JI

AT89C52-20PI

AT89C52-20QI

44A

44J

40P6

44Q

Industrial

(-40°C to 85°C)

24 5V ± 20% AT89C52-24AC

AT89C52-24JC

AT89C52-24PC

AT89C52-24QC

44A

44J

40P6

44Q

Commercial

(0°C to 70°C)

AT89C52-24AI

AT89C52-24JI

AT89C52-24PI

AT89C52-24QI

44A

44J

40P6

44Q

Industrial

(-40°C to 85°C)

Package Type

44A 44-lead, Thin Plastic Gull Wing Quad Flatpack (TQFP)

44J 44-lead, Plastic J-leaded Chip Carrier (PLCC)

40P6 40-lead, 0.600" Wide, Plastic Dual Inline Package (PDIP)

44Q 44-lead, Plastic Gull Wing Quad Flatpack (PQFP)

AT89C52

Packaging Information

Controlling dimension: millimeters

1.20(0.047) MAX

10.10(0.394)

9.90(0.386) SQ

12.21(0.478)

11.75(0.458) SQ

0.75(0.030)

0.45(0.018) 0.15(0.006)

0.05(0.002)

0.20(.008)

0.09(.003)

0.80(0.031) BSC

PIN 1 ID

0.45(0.018)

0.30(0.012)

.045(1.14) X 45° PIN NO. 1

IDENTIFY .045(1.14) X 30° - 45° .012(.305)

.008(.203)

.021(.533)

.013(.330)

.630(16.0)

.590(15.0)

.043(1.09)

.020(.508)

.120(3.05)

.090(2.29)

.180(4.57)

.165(4.19)

.500(12.7) REF SQ

.032(.813)

.026(.660)

.050(1.27) TYP

.022(.559) X 45° MAX (3X)

.656(16.7)

.650(16.5)

.695(17.7)

.685(17.4)SQ

2.07(52.6)

2.04(51.8) PIN

.566(14.4)

.530(13.5)

.090(2.29)

MAX

.005(.127)

MIN

.065(1.65)

.015(.381)

.022(.559)

.014(.356)

.065(1.65)

.041(1.04)

15 REF

.690(17.5)

.610(15.5)

.630(16.0)

.590(15.0)

.012(.305)

.008(.203)

.110(2.79)

.090(2.29)

.161(4.09)

.125(3.18)

SEATING

PLANE

.220(5.59)

MAX

1.900(48.26) REF

Controlling dimension: millimeters

13.45 (0.525)

12.95 (0.506)

0.50 (0.020)

0.35 (0.014)

PIN 1 ID

0.80 (0.031) BSC

10.10 (0.394)

9.90 (0.386) SQ

0.17 (0.007)

0.13 (0.005)

1.03 (0.041)

0.78 (0.030)

2.45 (0.096) MAX

0.25 (0.010) MAX

44A, 44-lead, Thin (1.0 mm) Plastic Gull Wing Quad

Flatpack (TQFP)

Dimensions in Millimeters and (Inches)*

JEDEC STANDARD MS-026 ACB

44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC)

Dimensions in Inches and (Millimeters)

JEDEC STANDARD MS-018 AC

40P6, 40- le ad, 0.60 0" Wide, Plastic Dual Inli ne

Package (PDIP)

Dimensions in Inches and (Millimeters)

44Q, 44-lead, Plastic Quad Flat Package (PQFP)

Dimensions in Millimeters and (Inches)*

JEDEC STANDARD MS-022 AB

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0313H–02/00/xM

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