19-4230; Rev 0; 7/08 KIT ATION EVALU E L B AVAILA 110MHz, 16 x 16 Video Crosspoint Switch with Programmable Gain The MAX9675 is a nonblocking 16 x 16 video crosspoint switch with buffered inputs and outputs. The device operates on 5V analog supplies. Digital logic is supplied separately from an independent +2.7V to +5V supply. The MAX9675 inputs and outputs are buffered with all outputs able to drive a standard 75 reverseterminated video load. The switching matrix and programmable gain are controlled through an SPITM/QSPITM-compatible 3-wire serial interface. The serial interface is designed to operate in either of two modes to provide fast updates and initialization. All outputs are held in the disabled state during power-up to avoid signal conflicts in large switching arrays. The programmability and high level of integration make the MAX9675 an ideal choice for nonblocking video switch arrays in security, surveillance, and videoon-demand systems. The MAX9675 is available in a 100-pin TQFP package and specified over the extended -40C to +85C temperature range. Applications Features 16 x 16 Nonblocking Matrix with Buffered Inputs and Outputs Operates at 5V Supply Individually Programmable Output Buffer Gain (AV = +1V/V or +2V/V) High-Impedance Output Disable for Wired-OR Connections 0.1dB Gain Flatness to 14MHz -3dB Bandwidth 110MHz -62dB Crosstalk, -110dB Isolation at 6MHz Ordering Information PART TEMP RANGE PIN-PACKAGE MAX9675ECQ+ -40C to +85C 100 TQFP +Denotes a lead-free/RoHS-compliant package. Pin Configuration appears at end of data sheet. Security Systems Video Routing Video-on-Demand Systems Functional Diagram Typical Operating Circuit MAX9675 IN0 IN0 MONITOR IN1 OUT1 MAX9675 MONITOR IN2 AV * IN15 AV * RESET POWER-ON RESET THERMAL SHUTDOWN DISABLE ALL OUTPUTS 256 16 DECODE LOGIC IN15 OUT15 MONITOR AV * 16 x 16 SWITCH MATRIX OUT0 DIN SCLK UPDATE CE SERIAL INTERFACE LATCHES ENABLE/DISABLE IN1 CAMERAS OUT0 AV * OUT1 OUT2 OUT15 16 VCC VEE AGND VDD DGND MATRIX REGISTER 96 BITS DOUT UPDATE REGISTER 16 BITS AOUT A0-A3 MODE *AV = +1V/V OR +2V/V SPI and QSPI are trademarks of Motorola, Inc. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com. 1 MAX9675 General Description MAX9675 110MHz, 16 x 16 Video Crosspoint Switch with Programmable Gain ABSOLUTE MAXIMUM RATINGS Analog Supply Voltage (VCC - VEE) .....................................+11V Digital Supply Voltage (VDD - DGND) ...................................+6V Analog Supplies to Analog Ground (VCC - AGND) and (AGND - VEE) ......................................+6V Analog Ground to Digital Ground .........................-0.3V to +0.3V IN_ Voltage Range .......................... (VCC + 0.3V) to (VEE - 0.3V) OUT_ Short-Circuit Duration to AGND, VCC, or VEE ......Indefinite SCLK, CE, UPDATE, MODE, A_, DIN, DOUT, RESET, AOUT.........................(VDD + 0.3V) to (DGND - 0.3V) Current into Any Analog Input Pin (IN_) ...........................50mA Current into Any Analog Output Pin (OUT_).....................75mA Continuous Power Dissipation (TA = +70C) 100-Pin TQFP (derate 22.2mW/C above +70C).....1777mW Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) ................................ +300C Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS--DUAL SUPPLIES 5V (VCC = +5V, VEE = -5V, VDD = +5V, AGND = DGND = 0, VIN_ = 0, RL = 150 to AGND, and TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 5) PARAMETER Operating Supply Voltage Range Logic-Supply Voltage Range Gain (Note 1) Gain Matching (Channel to Channel) 2 SYMBOL VCC VEE CONDITIONS Guaranteed by PSRR test VDD to DGND AV MIN TYP MAX UNITS 4.5 10.5 V 2.7 5.5 V (VEE + 2.5V) < VIN_ < (VCC - 2.5V), AV = +1V/V, RL = 150 1 (VEE + 2.5V) < VIN_ < (VCC - 2.5V), AV = +1V/V, RL = 10k 1 (VEE + 3.75V) < VIN_ < (VCC - 3.75V), AV = +2V/V, RL = 150 2 (VEE + 3.75V) < VIN_ < (VCC - 3.75V), AV = +2V/V, RL = 10k 2 (VEE + 1V) < VIN_ < (VCC - 1.2V), AV = +1V/V, RL = 10k 1 V/V RL = 10k 0.5 1.5 RL = 150 0.5 2 _______________________________________________________________________________________ % 110MHz, 16 x 16 Video Crosspoint Switch with Programmable Gain (VCC = +5V, VEE = -5V, VDD = +5V, AGND = DGND = 0, VIN_ = 0, RL = 150 to AGND, and TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 5) PARAMETER Temperature Coefficient of Gain SYMBOL CONDITIONS TCAV Input Bias Current Output Offset Voltage RL = 150 VEE + 2.5 VCC 2.5 RL = 10k VEE + 3 VCC 3.1 RL = 150 VEE + 3.75 VCC 3.75 RL = 10k VEE + 1 VCC 1.2 V RL = 150 VEE + 2.5 VCC 2.5 V V VOUT_ VOFFSET 4 AV = +1V/V 5 20 AV = +2V/V 10 40 Sinking or sourcing, RL = 1 40 mA Enabled Output Impedance ZOUT (VEE + 1V) < VIN_ < (VCC - 1.2V) 0.2 IOD (VEE + 1V) < VOUT_ < (VCC - 1.2V) 0.004 PSRR ICC 4.5V < (VCC - VEE) < 10.5V RL = Quiescent Supply Current IEE RL = Outputs enabled, TA = +25C 60 M 1 70 100 Outputs enabled mV A dB 150 175 Outputs disabled 55 75 Outputs enabled, TA = +25C 95 150 Outputs enabled Outputs disabled IDD A 10 ISC DC Power-Supply Rejection Ratio 11 (VEE + 1V) < VIN_ < (VCC - 1.2V) Output Short-Circuit Current Output Leakage Current, Disable Mode ppm/C VCC 1.2 VIN_ RIN_ UNITS VEE +1 IB Input Resistance MAX RL = 10k AV = +2V/V Output Voltage Range TYP 10 AV = +1V/V Input Voltage Range MIN mA 175 50 75 4 8 _______________________________________________________________________________________ 3 MAX9675 DC ELECTRICAL CHARACTERISTICS--DUAL SUPPLIES 5V (continued) MAX9675 110MHz, 16 x 16 Video Crosspoint Switch with Programmable Gain LOGIC-LEVEL CHARACTERISTICS (VCC = +5V, VEE = -5V, VDD = +2.7V to +5.5V, AGND = DGND = 0, VIN_ = 0, RL = 150 to AGND, and TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Notes 2, 5) PARAMETER Input-Voltage High Level Input-Voltage Low Level Input Current High Level Input Current Low Level Output-Voltage High Level Output-Voltage Low Level Output Current High Level Output Current Low Level SYMBOL VIH VIL CONDITIONS VDD = +5V 3 VDD = +3V 2 0.6 VI < 1V IOL Excluding RESET -1 +0.01 RESET -30 -20 Excluding RESET -1 +0.01 -300 -235 ISOURCE = 1mA, VDD = +5V 4.7 4.9 ISOURCE = 1mA, VDD = +3V 2.7 2.9 RESET UNITS V 0.8 IIL IOH MAX VDD = +3V VI > 2V VOL TYP VDD = +5V IIH VOH MIN +1 +1 0.1 0.3 ISINK = 1mA, VDD = +3V 0.1 0.3 1 4 VDD = +3V, VO = +2.7V 1 8 VDD = +5V, VO = +0.1V 1 4 VDD = +3V, VO = +0.3V 1 8 A A V ISINK = 1mA, VDD = +5V VDD = +5V, VO = +4.9V V V mA mA AC ELECTRICAL CHARACTERISTICS--DUAL SUPPLIES 5V (VCC = +5V, VEE = -5V, VDD = +5V, AGND = DGND = 0, VIN_ = 0, RL = 150 to AGND, and TA = +25C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS Small-Signal -3dB Bandwidth BWSS VOUT_ = 20mVP-P Medium-Signal -3dB Bandwidth BWMS VOUT_ = 200mVP-P Large-Signal -3dB Bandwidth BWLS VOUT_ = 2VP-P Small-Signal 0.1dB Bandwidth BW0.1dB-SS VOUT_ = 20mVP-P Medium-Signal 0.1dB Bandwidth BW0.1dB-MS VOUT_ = 200mVP-P Large-Signal 0.1dB Bandwidth BW0.1dB-LS VOUT_ = 2VP-P Slew Rate 4 SR MIN TYP AV = +1V/V 110 AV = +2V/V 78 AV = +1V/V 80 AV = +2V/V 75 AV = +1V/V 40 AV = +2V/V 50 AV = +1V/V 14 AV = +2V/V 11 AV = +1V/V 14 AV = +2V/V 11 AV = +1V/V 14 AV = +2V/V 11 VOUT_ = 2V step, AV = +1V/V 150 VOUT_ = 2V step, AV = +2V/V 150 _______________________________________________________________________________________ MAX UNITS MHz MHz MHz MHz MHz MHz V/s 110MHz, 16 x 16 Video Crosspoint Switch with Programmable Gain (VCC = +5V, VEE = -5V, VDD = +5V, AGND = DGND = 0, VIN_ = 0, RL = 150 to AGND, AV = +1V/V, and TA = +25C, unless otherwise noted.) PARAMETER Settling Time SYMBOL tS 0.1% CONDITIONS VOUT_ = 0 to 2V step MIN TYP AV = +1V/V 60 AV = +2V/V 60 MAX UNITS ns Switching Transient (Glitch) (Note 3) AV = +1V/V 50 AV = +2V/V 45 AC Power-Supply Rejection Ratio f = 100kHz 70 f = 1MHz 68 Differential Gain Error (Note 4) RL = 1k 0.002 RL = 150 0.02 Differential Phase Error (Note 4) RL = 1k 0.02 RL = 150 0.12 Crosstalk, All Hostile f = 6MHz -62 dB Off-Isolation, Input to Output f = 6MHz -110 dB 73 VRMS 5 pF 3 pF 30 pF Input Noise-Voltage Density en Input Capacitance CIN Disabled Output Capacitance BW = 6MHz Amplifier in disable mode Capacitive Load at 3dB Output Peaking Output Impedance ZOUT f = 6MHz Output enabled 3 Output disabled 4k mV dB % degrees _______________________________________________________________________________________ 5 MAX9675 AC ELECTRICAL CHARACTERISTICS--DUAL SUPPLIES 5V (continued) MAX9675 110MHz, 16 x 16 Video Crosspoint Switch with Programmable Gain SWITCHING CHARACTERISTICS (VCC = +5V, VEE = -5V, VDD = +2.7V to +5.5V, DGND = AGND = 0, VIN_ = 0 for dual supplies, RL = 150 to AGND, CL = 100pF, AV = +1V/V, and TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 5) TYP MAX UNITS Delay: UPDATE to Video Out PARAMETER SYMBOL tPdUdVo VIN_ = 0.5V step CONDITIONS MIN 200 450 ns Delay: UPDATE to AOUT tPdUdAo MODE = 0, time to AOUT = low after UPDATE = low 30 200 ns Delay: SCLK to DOUT Valid tPdDo Logic state change in DOUT on active SCLK edge 30 200 ns Delay: Output Disable tPdHOe VOUT_ = 0.5V, 1k pulldown to AGND 300 800 ns tPdLOe Output disabled, 1k pulldown to AGND, VIN_ = 0.5V 200 800 ns 100 ns Delay: Output Enable Setup: CE to SCLK tSuCe Setup: DIN to SCLK tSuDi 100 ns Hold Time: SCLK to DIN tHdDi 100 ns Minimum High Time: SCLK tMnHCk 100 ns Minimum Low Time: SCLK tMnLCk 100 ns Minimum Low Time: UPDATE tMnLUd 100 ns Setup Time: UPDATE to SCLK tSuHUd Rising edge of UPDATE to falling edge of SCLK 100 ns Hold Time: SCLK to UPDATE tHdHUd Falling edge of SCLK to falling edge of UPDATE 100 ns Setup Time: MODE to SCLK tSuMd Minimum time from clock edge to MODE with valid data clocking 100 ns Hold Time: MODE to SCLK tHdMd Minimum time from clock edge to MODE with valid data clocking 100 ns Minimum Low Time: RESET tMnLRst Delay: RESET tPdRst 10k pulldown to AGND, 0.5V step 300 ns 600 ns Note 1: Associated output voltage may be determined by multiplying the input voltage by the specified gain (AV) and adding output offset voltage. Note 2: Logic-level characteristics apply to the following pins: DIN, DOUT, SCLK, CE, UPDATE, RESET, A3-A0, MODE, and AOUT. Note 3: Switching transient settling time is guaranteed by the settling time (tS) specification. Switching transient is a result of updating the switch matrix. Note 4: Input test signal: 3.58MHz sine wave of amplitude 40IRE superimposed on a linear ramp (0 to 100IRE). IRE is a unit of video-signal amplitude developed by the International Radio Engineers: 140IRE = 1.0V. Note 5: All devices are 100% production tested at TA = +25C. Specifications over temperature limits are guaranteed by design. 6 _______________________________________________________________________________________ 110MHz, 16 x 16 Video Crosspoint Switch with Programmable Gain SYMBOL TYPE DESCRIPTION Ao Signal Address Valid Flag (AOUT) Ce Signal Clock Enable (CE) Ck Signal Clock (SCLK) Di Signal Serial-Data In (DIN) Do Signal Serial-Data Output (DOUT) Md Signal MODE Oe Signal Output Enable Rst Signal Reset Input (RESET) Ud Signal UPDATE Vo Signal Video Out (OUT) H Property High- or Low-to-High Transition Hd Property Hold L Property Low- or High-to-Low Transition Mn Property Minimum Mx Property Maximum Pd Property Propagation Delay Su Property Setup Tr Property Transition W Property Width * All parameters with time units are given a "t" designation, with appropriate subscript modifiers. * Propagation delays for clocked signals are from the active edge of clock. * Propagation delay for level-sensitive signals is from input to output at the 50% point of a transition. * Setup and hold times are measured from the 50% point of signal transition to the 50% point of the clocking signal transition. * Setup time refers to any signal that must be stable before the active clock edge, even if the signal is not latched or clocked itself. * Hold time refers to any signal that must be stable during and after active clock edge, even if the signal is not latched or clocked. * Propagation delays to unobservable internal signals are modified to setup and hold designations applied to observable I/O signals. _______________________________________________________________________________________ 7 MAX9675 Naming Conventions Symbol Definitions MAX9675 110MHz, 16 x 16 Video Crosspoint Switch with Programmable Gain NAME DATA AND CONTROL TIMING tHdDi Ce: CE tSuCe tMnHCk tMnLCk tMnLUd tHdCe Ck: SCLK tMnHCk tSuDi tHdDi tMnLCk Di: DIN Do: DOUT tMnLUd tPdDo tHdUd Ud: UPDATE tSuUd tWTrVo tPdUdVo Hi-Z Vo: OUT_ Hi-Z Ao: AOUT tPdUdAo Rst: RESET tPdHOeVo Oe: OUTPUT ENABLE tPdLOeVo tPdRstVo tMnlRst TIMING PARAMETER DEFINITIONS DESCRIPTION Hold Time: Clock to Data In Min High Time: Clk Min Low Time: Clk tSuHUd Not Valid Min Low Time: Update Setup Time: UPDATE to Clk with UPDATE High Setup Time: UPDATE to Clk with UPDATE Low tHdHUd Not Valid Hold Time: Clk to UPDATE with UPDATE high Hold Time: Clk to UPDATE with UPDATE Low tPdDiDo tMnMd tMxTr tMnLRst tPdRstVo Asynchronous Delay: Data In to Data Out Min Low Time: MODE Max Rise Time: Clk, Update Min Low Time: Reset Delay: Reset to Video Output TIMING PARAMETER DEFINITIONS DESCRIPTION Delay: Update to Video Out Delay: UPDATE to Aout Delay: Clk to Data Out Delay: Output Enable to Video Output tPdHOeVo (High: Disable) Delay: Output Enable to Video Output tPdLOeVo (Low: Enable) tSuCe Setup: Clock Enable to Clock tSuDi Setup Time: Data In to Clock NAME tPdUdVo tPdUdAo tPdDo Figure 1. Timing Diagram 8 _______________________________________________________________________________________ 110MHz, 16 x 16 Video Crosspoint Switch with Programmable Gain 0 AV = +2V/V -2 AV = +1V/V -3 -4 AV = +1V/V 0 -1 -2 AV = +2V/V -3 -4 -6 -7 -7 100 1000 -7 0.1 1 -1 -2 AV = +2V/V -4 RL = 1k 1 AV = +2V/V 0 -1 -2 AV = +1V/V -3 1 -4 -1 -2 -4 -5 -6 -7 -7 100 10 100 0.1 1000 10 100 1000 LARGE-SIGNAL GAIN FLATNESS vs. FREQUENCY LARGE-SIGNAL GAIN FLATNESS vs. FREQUENCY LARGE-SIGNAL FREQUENCY RESPONSE (AV = +1V/V) AV = +2V/V -0.4 0 AV = +1V/V -0.1 -0.2 -0.3 AV = +2V/V -0.4 3 0 -2 -4 -0.6 -6 -7 -0.7 FREQUENCY (MHz) 1000 CL = 15pF -3 -0.6 100 CL = 30pF -1 -5 10 CL = 45pF 1 -0.5 1 RL = 150 2 -0.5 -0.7 MAX9675 toc09 0.1 NORMALIZED GAIN (dB) -0.1 RL = 1k NORMALIZED GAIN (dB) 0.2 MAX9675 toc08 0.3 MAX9675 toc07 AV = +1V/V 0 0.1 1 FREQUENCY (MHz) 0.1 -0.3 1 FREQUENCY (MHz) RL = 150 -0.2 0.1 FREQUENCY (MHz) 0.3 0.2 1000 AV = +2V/V -3 -6 10 AV = +1V/V 0 -6 1 1000 RL = 1k 2 -5 -7 100 SMALL-SIGNAL FREQUENCY RESPONSE MAX9675 toc05 2 10 3 -5 0.1 1 FREQUENCY (MHz) NORMALIZED GAIN (dB) AV = +1V/V -3 0.1 1000 MEDIUM-SIGNAL FREQUENCY RESPONSE NORMALIZED GAIN (dB) 1 0 100 3 MAX9675 toc04 RL = 1k 2 10 FREQUENCY (MHz) LARGE-SIGNAL FREQUENCY RESPONSE MAX9675 toc03 -4 -5 10 AV = +2V/V -3 -6 3 NORMALIZED GAIN (dB) -2 -6 1 AV = +1V/V 0 -1 -5 FREQUENCY (MHz) NORMALIZED GAIN (dB) 1 -5 0.1 RL = 150 2 MAX9675 toc06 -1 1 NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 1 RL = 150 2 3 MAX9675 toc02 MAX9675 toc01 RL = 150 2 SMALL-SIGNAL FREQUENCY RESPONSE MEDIUM-SIGNAL FREQUENCY RESPONSE 3 NORMALIZED GAIN (dB) LARGE-SIGNAL FREQUENCY RESPONSE 3 0.1 1 10 FREQUENCY (MHz) 100 1000 0.1 1 10 100 1000 FREQUENCY (MHz) _______________________________________________________________________________________ 9 MAX9675 Typical Operating Characteristics (VCC = +5V and VEE = -5V, VDD = +5V, AGND = DGND = 0, VIN_ = 0, RL = 150 to AGND, and TA = +25C, unless otherwise noted.) Typical Operating Characteristics (continued) (VCC = +5V and VEE = -5V, VDD = +5V, AGND = DGND = 0, VIN_ = 0, RL = 150 to AGND, and TA = +25C, unless otherwise noted.) -1 CL = 30pF -2 CL = 15pF -3 -4 -5 CL = 30pF 5 0 4 3 CL = 30pF 2 1 0 -1 CL = 15pF -2 -6 -7 -3 -10 1 10 100 0.1 1000 1 10 100 1000 0.1 1 FREQUENCY (MHz) FREQUENCY (MHz) CROSSTALK vs. FREQUENCY AV = +2V/V -50 CROSSTALK (dB) -60 -70 -80 -60 -70 -80 -90 -90 -100 -100 0 -10 AV = +1V/V -20 DISTORTION (dBc) AV = +1V/V -50 100 1000 DISTORTION vs. FREQUENCY CROSSTALK vs. FREQUENCY -40 MAX9675 toc13 -40 10 FREQUENCY (MHz) MAX9675 toc14 0.1 CROSSTALK (dB) CL = 45pF 5 CL = 15pF -5 MAX9675 toc12 6 NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 0 CL = 45pF 10 NORMALIZED GAIN (dB) CL = 45pF 1 7 MAX9675 toc11 RL = 150 2 15 MAX9675 toc10 3 MEDIUM-SIGNAL FREQUENCY RESPONSE (AV = +2V/V) MEDIUM-SIGNAL FREQUENCY RESPONSE (AV = +1V/V) MAX9675 toc15 LARGE-SIGNAL FREQUENCY RESPONSE (AV = +2V/V) -30 2ND HARMONIC -40 -50 -60 3RD HARMONIC -70 -80 -90 1 10 100 1 10 100 0.1 1000 1 10 100 FREQUENCY (MHz) DISTORTION vs. FREQUENCY ENABLED OUTPUT IMPEDANCE vs. FREQUENCY DISABLED OUTPUT IMPEDANCE vs. FREQUENCY 2ND HARMONIC -40 -50 -60 3RD HARMONIC -70 -80 100 10 1 MAX9675 toc18 100k OUTPUT IMPEDANCE () -20 1M MAX9675 toc17 1000 MAX9675 toc16 AV = +2V/V -30 0.1 FREQUENCY (MHz) 0 -10 1000 -100 FREQUENCY (MHz) OUTPUT IMPEDANCE () 0.1 DISTORTION (dBc) MAX9675 110MHz, 16 x 16 Video Crosspoint Switch with Programmable Gain 10k 1k 100 10 -90 -100 -0.1 0.1 1 10 FREQUENCY (MHz) 10 100 1 0.1 1 10 FREQUENCY (MHz) 100 1000 100k 1M 10M FREQUENCY (Hz) ______________________________________________________________________________________ 100M 1G 110MHz, 16 x 16 Video Crosspoint Switch with Programmable Gain POWER-SUPPLY REJECTION RATIO vs. FREQUENCY MAX9675 toc20 -70 -80 -90 -100 1000 VOLTAGE NOISE (nV/Hz) -55 -60 PSRR (dB) OFF-ISOLATION (dB) -50 INPUT VOLTAGE NOISE vs. FREQUENCY -50 MAX9675 toc19 -40 -60 -65 MAX9675 toc21 OFF-ISOLATION vs. FREQUENCY 100 -70 -110 -75 -120 100k 1M 10M 100M 1 10k 1G FREQUENCY (Hz) LARGE-SIGNAL PULSE RESPONSE (AV = +1V/V) MAX9675 toc22 100k 1M 10M 100M 10 1k 10k 100k MEDIUM-SIGNAL PULSE RESPONSE (AV = +1V/V) MAX9675 toc24 INPUT 0.5V/div INPUT 100mV/div OUTPUT 0.5V/div OUTPUT 0.5V/div OUTPUT 50mV/div 25ns/div 25ns/div MEDIUM-SIGNAL PULSE RESPONSE (AV = +2V/V) SWITCHING TIME (AV = +1V/V) MAX9675 toc25 10M LARGE-SIGNAL PULSE RESPONSE (AV = +2V/V) MAX9675 toc23 25ns/div 1M FREQUENCY (Hz) INPUT 1V/div SWITCHING TIME (AV = +2V/V) MAX9675 toc26 INPUT 50mV/div VUPDATE 5V/div VUPDATE 5V/div OUTPUT 50mV/div VOUT 500mV/div VOUT 1V/div 25ns/div 100 FREQUENCY (Hz) 20ns/div MAX9675 toc27 20ns/div ______________________________________________________________________________________ 11 MAX9675 Typical Operating Characteristics (continued) (VCC = +5V and VEE = -5V, VDD = +5V, AGND = DGND = 0, VIN_ = 0, RL = 150 to AGND, and TA = +25C, unless otherwise noted.) Typical Operating Characteristics (continued) (VCC = +5V and VEE = -5V, VDD = +5V, AGND = DGND = 0, VIN_ = 0, RL = 150 to AGND, and TA = +25C, unless otherwise noted.) SWITCHING TRANSIENT (GLITCH) (AV = +1V/V) SWITCHING TRANSIENT (GLITCH) (AV = +2V/V) OFFSET VOLTAGE DISTRIBUTION MAX9675 toc29 VUPDATE 5V/div 300 MAX9675 toc30 MAX9675 toc28 250 VUPDATE 5V/div 200 150 VOUT 25mV/div 100 VOUT 25mV/div 50 0 20ns/div 20ns/div -15 -13 -11 -9 -7 -5 -3 -1 1 3 5 OFFSET VOLTAGE (mV) DIFFERENTIAL GAIN AND PHASE (RL = 1k) 0.004 0.002 0 -0.002 -0.004 INPUT 1V/div DIFFERENTIAL PHASE () 0.03 0.02 0.01 0 -0.01 OUTPUT 0.5/Vdiv 0 10 20 30 40 50 60 70 80 90 100 0 10 20 30 40 50 60 70 80 90 100 IRE IRE LARGE-SIGNAL PULSE RESPONSE WITH CAPACITIVE LOAD (CL = 30pF, AV = +2V/V) MAX9675 toc34 MAX9675 toc33 0 10 20 30 40 50 60 70 80 90 100 0 10 20 30 40 50 60 70 80 90 100 0.15 0.10 0.05 0 -0.05 LARGE-SIGNAL PULSE RESPONSE WITH CAPACITIVE LOAD (CL = 30pF, AV = +1V/V) MAX9675 toc32 MAX9675 toc31 0.08 0.06 0.04 0.02 0 -0.02 DIFFERENTIAL GAIN (%) DIFFERENTIAL GAIN (%) DIFFERENTIAL GAIN AND PHASE (RL = 150) DIFFERENTIAL PHASE () MAX9675 110MHz, 16 x 16 Video Crosspoint Switch with Programmable Gain MEDIUM-SIGNAL PULSE RESPONSE WITH CAPACITIVE LOAD (CL = 30pF, AV = +1V/V) MAX9675 toc35 25ns/div MEDIUM-SIGNAL PULSE RESPONSE WITH CAPACITIVE LOAD (CL = 30pF, AV = +2V/V) MAX9675 toc36 INPUT 0.5V/div INPUT 100mV/div INPUT 50mV/div OUTPUT 0.5V/div OUTPUT 50mV/div OUTPUT 50mV/div 25ns/div 12 25ns/div 25ns/div ______________________________________________________________________________________ 110MHz, 16 x 16 Video Crosspoint Switch with Programmable Gain GAIN vs. TEMPERATURE RESET DELAY vs. RESET CAPACITANCE 1 100m RESET DELAY (s) 0.10 0.05 AV = +2V/V 0 -0.05 MAX9675 toc38 0.15 AV = +1V/V 10m 1m 100 10 -0.10 1 -0.15 100n 10n -0.20 -25 0 25 50 75 100 1p 10p 100p 1n TEMPERATURE (C) 10n 100n 1 10 100 CRESET (F) SUPPLY CURRENT vs. TEMPERATURE 70 MAX9675 toc39 -50 60 SUPPLY CURRENT (mA) NORMALIZED GAIN (dB) 10 MAX9675 toc37 0.20 50 ICC 40 IEE 30 20 10 IDD 0 -50 -25 0 25 50 75 100 TEMPERATURE (C) ______________________________________________________________________________________ 13 MAX9675 Typical Operating Characteristics (continued) (VCC = +5V and VEE = -5V, VDD = +5V, AGND = DGND = 0, VIN_ = 0, RL = 150 to AGND, and TA = +25C, unless otherwise noted.) MAX9675 110MHz, 16 x 16 Video Crosspoint Switch with Programmable Gain Pin Description PIN NAME 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23 IN4-IN15 2, 4, 6, 8, 10, 12, 14, 16, 45, 46, 82, 83, 84, 91, 93, 95, 97 AGND Analog Ground 18, 20, 22, 24 A3-A0 Address Programming Inputs. Connect to DGND or VDD to select the address for Individual Output Address Mode (see Table 3). 25, 47, 51, 55, 59, 63, 67, 71, 75, 81 VCC Positive Analog Supply. Bypass each pin with a 0.1F capacitor to AGND. Connect a single 10F capacitor from one VCC pin to AGND. 26, 27, 38-44, 76, 77, 85-89, 99, 100 N.C. No Connection. Not internally connected. Connect to AGND. 28 DOUT Serial-Data Output. In Complete Matrix Mode, data is clocked through the 96-bit Matrix Control shift register. In Individual Output Address Mode, data at DIN passes directly to DOUT. 29 DGND Digital Ground 30 AOUT Address Recognition Output. AOUT drives low after successful chip address recognition. 31 SCLK 32 CE 33 MODE Serial Interface Mode Select Input. Drive high for Complete Matrix Mode (Mode 1) or drive low for Individual Output Address Mode (Mode 0). 34 RESET Asynchronous Reset Input/Output. Drive RESET low to initiate hardware reset. All matrix settings are set to power up defaults and all analog outputs are disabled. Additional power-on-reset delay may be set by connecting a small capacitor from RESET to DGND. 35 UPDATE Update Input. Drive UPDATE low to transfer data from mode registers to the switch matrix. 36 DIN VDD 37 14 48, 50, 52, 54, 56, 58, 60, 62, 64, 66, 68, 70, 72, 74, 78, 80 OUT15-OUT0 49, 53, 57, 61, 65, 69, 73, 79, 98 VEE 90, 92, 94, 96 IN0-IN3 FUNCTION Buffered Analog Inputs Serial-Clock Input Clock Enable Input. Drive low to enable the serial data interface. Serial-Data Input. Data is clocked in on the falling edge of SCLK. Digital Logic Supply. Bypass VDD with a 0.1F capacitor to DGND. Buffered Analog Outputs. Gain is individually programmable for AV = +1V/V or AV = +2V/V through the serial interface. Outputs may be individually disabled (high impedance). On power-up, or assertion of RESET, all outputs are disabled. Negative Analog Supply. Bypass each pin with a 0.1F capacitor to AGND. Connect a single 10F capacitor from one VEE pin to AGND. Buffered Analog Inputs ______________________________________________________________________________________ 110MHz, 16 x 16 Video Crosspoint Switch with Programmable Gain MAX9675 IN0 AV* 16 x 16 SWITCH MATRIX IN2 AV* IN15 AV* POWER-ON RESET THERMAL SHUTDOWN DISABLE ALL OUTPUTS 256 16 DECODE LOGIC DIN SCLK UPDATE CE SERIAL INTERFACE LATCHES ENABLE/DISABLE IN1 RESET OUT0 AV* OUT1 OUT2 OUT15 16 VCC VEE AGND VDD DGND MATRIX REGISTER 96 BITS DOUT UPDATE REGISTER 16 BITS AOUT A0-A3 MODE *AV = +1V/V OR +2V/V Detailed Description The MAX9675 is a highly integrated 16 16 nonblocking video crosspoint switch matrix. All inputs and outputs are buffered, with all outputs able to drive standard 75 reverse-terminated video loads. A 3-wire interface programs the switch matrix and initializes with a single update signal. The unique serial interface operates in one of two modes: Complete Matrix Mode (Mode 1) or Individual Output Address Mode (Mode 0). In the Functional Diagram, the signal path of the MAX9675 is from the inputs (IN0-IN15), through the switching matrix, buffered by the output amplifiers, and presented at the output terminals (OUT0-OUT15). The other functional blocks are the serial interface and control logic. Each of the functional blocks is described in detail below. Analog Outputs The MAX9675 outputs are high-speed voltage feedback amplifiers capable of driving 150 (75 back-terminated) loads. The gain, AV = +1V/V or +2V/V, is selectable through programming bit 4 of the serial control word. Amplifier compensation is automatically optimized to maximize the bandwidth for each gain selection. Each output can be individually enabled and disabled through bit 5 of the serial control word. When disabled, the output is high impedance, presenting typically a 4k load, and 3pF output capacitance, allowing multiple outputs to be connected together in building large arrays. On power-up (or asynchronous RESET), all outputs are initialized in the disabled state to avoid output conflicts in large-array configurations. The programming and operation of the MAX9675 is output referred. Outputs are configured individually to connect to any one of the 16 analog inputs, programmed to the desired gain (AV = +1V/V or +2V/V), or disabled in a high-impedance state. Analog Inputs The MAX9675 offers 16 analog input channels. Each input is buffered before the crosspoint switch matrix, allowing one input to cross-connect to up to 16 outputs. The input buffers are voltage feedback amplifiers with high-input impedance and low-input bias current. This allows the use of very simple input clamp circuits. ______________________________________________________________________________________ 15 MAX9675 Functional Diagram MAX9675 110MHz, 16 x 16 Video Crosspoint Switch with Programmable Gain Table 1. Operation Truth Table CE UPDATE SCLK DIN DOUT MODE AOUT RESET 1 X X X X X X 1 No change in logic. 1 Data at DIN is clocked on the negative edge of the SCLK into the 96-bit Complete Matrix Mode register. DOUT supplies original data in 96 SCLK pulses later. 1 Data in the serial 96-bit Complete Matrix Mode register is transferred into parallel latches that control the switching matrix. 1 Data at DIN is routed to the Individual Output Address Mode shift register. DIN is also connected directly to DOUT so that all devices on the serial bus may be addressed in parallel. 0 0 0 1 0 1 X Di X Di Di-96 X Di 1 1 0 1 1 0 0 X Di Di 0 0 1 The 4-bit chip address A3 to A0 is compared to D13 to D10. If equal, the remaining 10 bits in the Individual Output Address Mode register are decoded, allowing reprogramming for a single output. AOUT signals a successful individual matrix update. X X X X X X X 0 Asynchronous reset. All outputs are disabled. Other logic remains unchanged. Switch Matrix The MAX9675 has 256 individual T-switches making a 16 x 16 switch matrix. The switching matrix is 100% nonblocking, which means that any input may be routed to any output. The switch matrix programming is output referred. Each output may be connected to any one of the 16 analog inputs. Any one input can be routed to all 16 outputs with no signal degradation. Digital Interface The digital interface consists of the following pins: DIN, DOUT, SCLK, AOUT, UPDATE, CE, A3-A0, MODE, and RESET. DIN is the serial-data input; DOUT is the serialdata output. SCLK is the serial-data clock that clocks data into the Data Input registers (Figure 2). Data at DIN is loaded at each falling edge of SCLK. DOUT is the data shifted out of the 96-bit Complete Matrix Mode (Mode = 1). DIN passes directly to DOUT when in Individual Output Address Mode (Mode = 0). 16 1 OPERATION/COMMENTS The falling edge of UPDATE latches the data and programs the matrix. When using Individual Output Address Mode, the address recognition output AOUT drives low when control word bits D13 to D10 match the address programming inputs (A3-A0) and UPDATE is low. Table 1 is the operation truth table. Programming the Matrix The MAX9675 offers two programming modes: Individual Output Address Mode and Complete Matrix Mode. These two distinct programming modes are selected by toggling a single MODE pin high or low. Both modes operate with the same physical board layout. This flexibility allows initial programming of the IC by daisy-chaining and sending one long data word while still being able to address immediately and update individual outputs in the matrix. Individual Output Address Mode (MODE = 0) Drive MODE to logic-low to select mode 0. Individual outputs are programmed through the serial interface ______________________________________________________________________________________ 110MHz, 16 x 16 Video Crosspoint Switch with Programmable Gain BIT NAME 0 (LSB) Input Address 0 1 Input Address 1 2 Input Address 2 3 Input Address 3 4 5 6 Table 3. Chip Address Programming for 16-Bit Control Word (Mode 0: Individual Output Address Mode) IC ADDRESS BIT FUNCTION LSB of input channel select address ADDRESS A1 A0 (LSB) CHIP ADDRESS (HEX) CHIP ADDRESS (DECIMAL) 0 0 0 0h 0 0 0 0 1 1h 1 0 0 1 0 2h 2 Gain Select for output buffer, 0 = gain of +1V/V, 1 = gain of +2V/V 0 0 1 1 3h 3 0 1 0 0 4h 4 0 1 0 1 5h 5 Output Enable Enable bit for output, 0 = disable, 1 = enable 0 1 1 0 6h 6 0 1 1 1 7h 7 Output Address B0 LSB of output buffer address 1 0 0 0 8h 8 1 0 0 1 9h 9 Gain Set A3 (MSB) A2 0 MSB of input channel select address 7 Output Address B1 1 0 1 0 Ah 10 8 Output Address B2 1 0 1 1 Bh 11 1 0 0 Ch 12 Output Address B3 MSB of output buffer address 1 1 1 0 1 Dh 13 10 IC Address A0 LSB of selected chip address 1 1 1 0 Eh 14 1 1 1 1 Fh 15 11 IC Address A1 12 IC Address A2 13 IC Address A3 MSB of selected chip address 14 X Don't care 15 (MSB) X Don't care 9 with a single 16-bit control word. The control word consists of two don't care MSBs, the chip address bits, output address bits, an output enable/disable bit, an output gain-set bit, and input address bits (Tables 2 through 6, and Figure 2). In mode 0, data at DIN passes directly to DOUT through the data routing gate (Figure 3). In this configuration, the 16-bit control word is simultaneously sent to all chips in an array of up to 16 addresses. first 6-bit control word (MSBs) programs output 15, and the last 6-bit control word (LSBs) programs output 0 (Table 7 and Figures 4 and 5). Data clocked into the 96-bit Complete Matrix Mode register is latched on the falling edge of UPDATE, and the outputs are immediately updated. Initialization String The Complete Matrix Mode (Mode = 1) is convenient to use to program the matrix at power-up. In a large matrix consisting of many MAX9675 devices, all the devices can be programmed by sending a single bit stream equal to n x 96 bits, where n is the number of MAX9675 devices on the bus. The first 96-bit data word programs the last MAX9675 in line (see the Matrix Programming section). Complete Matrix Mode (MODE = 1) Drive MODE to logic-high to select mode 1. A single 96-bit control word consisting of sixteen 6-bit control words programs all outputs. The 96-bit control word's ______________________________________________________________________________________ 17 MAX9675 Table 2. 16-Bit Serial Control Word Bit Assignments (Mode 0: Individual Output Address Mode) MAX9675 110MHz, 16 x 16 Video Crosspoint Switch with Programmable Gain 16-BIT INDIVIDUAL OUTPUT ADDRESS MODE: FIRST 2 BITS ARE DON'T CARE BITS, LAST 14 BITS CLOCKED INTO DIN WHEN MODE = 0 CREATE ADDRESS WORD; IC ADDRESS A3-A0 IS COMPARED TO DIN13-DIN10 WHEN UPDATE IS LOW; IF EQUAL, ADDRESSED OUTPUT IS UPDATED. UPDATE tHdMd tSuMd MODE SCLK IC ADDRESS = 5 OUTPUT ADDRESS = 3 INPUT ADDRESS 0 (LSB) = 0 INPUT ADDRESS 1 = 0 INPUT ADDRESS 2 = 1 INPUT ADDRESS 3 (MSB) = 1 GAIN SET = +1V/V OUTPUT ENABLED OUTPUT ADDRESS B0 OUTPUT ADDRESS B1 OUTPUT ADDRESS B2 OUTPUT ADDRESS B3 IC ADDRESS A0 IC ADDRESS A1 IC ADDRESS A2 IC ADDRESS A3 DON'T CARE X DON'T CARE X DIN OUTPUT (i) ENABLED, AV = +1V/V, CONNECTED TO INPUT 12 EXAMPLE OF 16-BIT SERIAL CONTROL WORD FOR OUTPUT CONTROL IN INDIVIDUAL OUTPUT ADDRESS MODE Figure 2. Mode 0: Individual Output Address Mode Timing and Programming Example Table 4. Chip Address A3-A0 Pin Programming PIN Table 5. Output Selection Programming ADDRESS CHIP CHIP ADDRESS ADDRESS (HEX) (DECIMAL) OUTPUT ADDRESS BIT B3 (MSB) B2 B1 B0 (LSB) SELECTED OUTPUT A3 A2 A1 A0 0 0 0 0 0 DGND DGND DGND DGND 0h 0 0 0 0 1 1 DGND DGND DGND VDD 1h 1 0 0 1 0 2 DGND DGND VDD DGND 2h 2 0 0 1 1 3 DGND DGND VDD VDD 3h 3 0 1 0 0 4 DGND VDD DGND DGND 4h 4 0 1 0 1 5 DGND VDD DGND VDD 5h 5 0 1 1 0 6 DGND VDD VDD DGND 6h 6 0 1 1 1 7 DGND VDD VDD VDD 7h 7 1 0 0 0 8 VDD DGND DGND DGND 8h 8 1 0 0 1 9 VDD DGND DGND VDD 9h 9 1 0 1 0 10 VDD DGND VDD DGND Ah 10 1 0 1 1 11 VDD DGND VDD VDD Bh 11 1 1 0 0 12 VDD VDD DGND DGND Ch 12 1 1 0 1 13 VDD VDD DGND VDD Dh 13 1 1 1 0 14 VDD VDD VDD DGND Eh 14 1 1 1 1 15 VDD VDD VDD VDD Fh 15 18 ______________________________________________________________________________________ 110MHz, 16 x 16 Video Crosspoint Switch with Programmable Gain MAX9675 A0-A3 CHIP ADDRESS SCLK CE 4 MODE 4 16-BIT INDIVIDUAL OUTPUT ADDRESS MODE REGISTER SCLK MODE 10 CE MODE A DIN B 96-BIT COMPLETE MATRIX MODE REGISTER 10 S DATA ROUTING GATE DOUT 96 MODE OUTPUT ADDRESS DECODE 7 MODE 1 UPDATE EN 96 AOUT 7 96-BIT PARALLEL LATCH 96 SWITCH DECODE 16 256 SWITCH MATRIX OUTPUT ENABLE Figure 3. Serial Interface Block Diagram Table 6. Input Selection Programming INPUT ADDRESS BIT SELECTED INPUT B3 (MSB) B2 B1 B0 (LSB) 0 0 0 0 0 0 0 0 1 1 0 0 1 0 2 0 0 1 1 3 0 1 0 0 4 0 1 0 1 5 0 1 1 0 6 0 1 1 1 7 1 0 0 0 8 1 0 0 1 9 1 0 1 0 10 1 0 1 1 11 1 1 0 0 12 1 1 0 1 13 1 1 1 0 14 1 1 1 1 15 Table 7. 6-Bit Serial Control Word Bit Assignments (Mode 1: Complete Matrix Mode) BIT NAME FUNCTION 5 (MSB) Output Enable Enable bit for output, 0 = disable, 1 = enable 4 Gain Set 3 Input Address 3 2 Input Address 2 1 Input Address 1 0 (LSB) Input Address 0 Gain Select for output buffer, 0 = gain of +1V/V, 1 = gain of +2V/V MSB of input channel select address LSB of input channel select address ______________________________________________________________________________________ 19 MAX9675 110MHz, 16 x 16 Video Crosspoint Switch with Programmable Gain tMnHCk tMnLCk SCLK tSuDi tHdDi DIN tSuHUd UPDATE tMnLUd tPdDo DOUT SCLK EXAMPLE OF 6-BIT SERIAL CONTROL WORD FOR OUTPUT CONTROL NEXT CONTROL WORD INPUT ADDRESS 0 (LSB) = 0 INPUT ADDRESS 1 = 1 INPUT ADDRESS 2 = 1 INPUT ADDRESS 3 (MSB) = 1 16 x 16 CROSSPOINT = 6-BIT CONTROL WORD GAIN SET = +1V/V OUTPUT ENABLED DIN OUTPUT (i) ENABLED, AV = +1V/V, CONNECTED TO INPUT 14 Figure 4. 6-Bit Control Word and Programming Example (Mode 1: Complete Matrix Mode Programming) UPDATE 1 MODE 1 0 0 6-BIT CONTROL WORD DIN OUT2 OUT1 OUT0 MOST-SIGNIFICANT OUTPUT BUFFER CONTROL BITS ARE SHIFTED IN FIRST, I.E., OUT15, THEN OUT14, ETC. LAST 6 BITS SHIFTED IN PRIOR TO UPDATE NEGATIVE EDGE PROGRAM OUT0. Figure 5. Mode 1: Complete Matrix Mode Programming 20 ______________________________________________________________________________________ 110MHz, 16 x 16 Video Crosspoint Switch with Programmable Gain Power-On Reset The power-on reset ensures all output buffers are in a disabled state when power is initially applied. A VDD voltage comparator generates the power-on reset. When the voltage at VDD is less than 2.5V, the poweron-reset comparator pulls RESET low through internal circuitry. As the digital supply voltage ramps up crossing 2.5V, the MAX9675 holds RESET low for 40ns (typ). Connecting a small capacitor from RESET to DGND extends the power-on-reset delay. See the RESET Delay vs. RESET Capacitance graph in the Typical Operating Characteristics. Thermal Shutdown The MAX9675 features thermal shutdown protection with temperature hysteresis. When the die temperature exceeds +150C, the MAX9675 pulls RESET low, disabling the output buffers. When the die cools by 20C, the RESET pulldown is deasserted, and output buffers remain disabled until the device is programmed again. Applications Information Building Large Video-Switching Systems The MAX9675 can be easily used to create larger switching matrices. The number of ICs required to implement the matrix is a function of the number of input channels, the number of outputs required, and whether the array needs to be nonblocking. The most straightforward technique for implementing nonblocking matrices is to arrange the building blocks in a grid. The inputs connect to each vertical bank of devices in parallel with the other banks. The outputs of each building block in a vertical column connect together in a wired-OR configuration. Figure 6 shows a 128-input, 32-output, nonblocking array using the MAX9675 16 x 16 crosspoint devices. The wired-OR connection of the outputs shown in the diagram is possible because the outputs of the IC devices can be placed in a disabled or high-impedance output state. This disable state of the output buffers is designed for a maximum impedance vs. frequency while maintaining a low-output capacitance. These characteristics minimize the adverse loading effects from the disabled outputs. Larger arrays are constructed by extending this connection technique to more devices. Driving a Capacitive Load Figure 6 shows an implementation requiring many outputs to be wired together. This creates a situation where each output buffer sees not only the normal load impedance, but also the disabled impedance of all the other outputs. This impedance has a resistive and a capacitive component. The resistive components reduce the total effective load for the driving output. Total capacitance is the sum of the capacitance of all the disabled outputs and is a function of the size of the matrix. Also, as the size of the matrix increases, the length of the PCB traces increases, adding more capacitance. The output buffers have been designed to drive more than 30pF of capacitance while still maintaining a good AC response. Depending on the size of the array, the capacitance seen by the output can exceed this amount. There are several ways to improve the situation. The first is to use more building-block crosspoint devices to reduce the number of outputs that need to be wired together (Figure 7). In Figure 7, the additional devices are placed in a second bank to multiplex the signals. This reduces the number of wired-OR connections. Another solution is to put a small resistor in series with the output before the capacitive load to limit excessive ringing and oscillations. Figure 8 shows the graph of the Optimal Isolation Resistor vs. Capacitive Load. A lowpass filter is created from the series resistor and parasitic capacitance to ground. A single R-C does not affect the performance at video frequencies, but in a very large system there may be many R-Cs cascaded in series. The cumulative effect is a slight rolling off of the high frequencies causing a "softening" of the picture. There are two solutions to achieve higher performance. One way is to design the PCB traces associated with the outputs such that they exhibit some inductance. By routing the traces in a repeating "S" configuration, the traces that are nearest each other exhibit a mutual inductance increasing the total inductance. This series inductance causes the ______________________________________________________________________________________ 21 MAX9675 RESET The MAX9675 features an asynchronous bidirectional RESET with an internal 20k pullup resistor to VDD. When RESET is pulled low, either by internal circuitry, or driven externally, the analog output buffers are latched into a high-impedance state. After RESET is released, the output buffers remain disabled. The outputs may be enabled by sending a new 96-bit data word or a 16-bit individual output address word. A reset is initiated from any of three sources. RESET can be driven low by external circuitry to initiate a reset, or RESET can be pulled low by internal circuitry during power-up (power-on reset) or thermal shutdown. Since driving RESET low only clears the output buffer enable bit in the matrix control latches, RESET can be used to disable all outputs simultaneously. If no new data has been loaded into the 96-bit complete matrix mode register, a single UPDATE restores the previous matrix control settings. MAX9675 110MHz, 16 x 16 Video Crosspoint Switch with Programmable Gain IN (0-15) IN (16-31) IN (32-47) IN (48-63) 16 16 IN MAX9675 OUT 16 16 IN MAX9675 OUT 16 16 IN MAX9675 OUT 16 16 IN MAX9675 OUT 16 16 IN MAX9675 OUT 16 16 IN MAX9675 OUT 16 IN 16 16 IN MAX9675 OUT 16 MAX9675 OUT OUTPUTS (0-15) IN (64-79) IN (80-95) IN (96-111) IN (112-127) 16 16 IN MAX9675 OUT 16 IN 16 16 16 IN MAX9675 OUT 16 16 IN MAX9675 OUT 16 16 IN MAX9675 OUT 16 16 IN MAX9675 OUT 16 16 IN MAX9675 OUT 16 16 IN MAX9675 OUT MAX9675 OUT OUTPUTS (16-32) Figure 6. 128 x 32 Nonblocking Matrix Using 16 x 16 Crosspoint Devices amplitude response to increase or peak at higher frequencies, offsetting the rolloff from the parasitic capacitance. Another solution is to add a small-value inductor to the output. Crosstalk Signal and Board Routing Issues Improper signal routing causes performance problems such as crosstalk. The MAX9675 has a typical crosstalk rejection of -62dB at 6MHz. A bad PCB layout degrades the crosstalk rejection by 20dB or more. To achieve the best crosstalk performance: 1) Place ground isolation between long critical signal PCB trace runs. These traces act as a shield to potential interfering signals. Crosstalk can be degraded by parallel traces as well as directly above and below on adjoining PCB layers. 2) Maintain controlled-impedance traces. Design as many of the PCB traces as possible to be 75 transmission lines. This lowers the impedance of the traces, reducing a potential source of crosstalk. More power is dissipated due to the output buffer driving a lower impedance. 3) Minimize ground-current interaction by using a good ground plane strategy. In addition to crosstalk, another key issue of concern is isolation. Isolation is the rejection of undesirable feedthrough from input to output with the output disabled. The MAX9675 achieves a -110dB isolation at 6MHz by selecting the pinout configuration such that the inputs and outputs are on opposite sides of the package. 22 IN (0-15) 16 16 IN MAX9675 OUT IN (16-31) 16 16 IN MAX9675 OUT IN (32-47) 16 16 IN MAX9675 OUT 16 16 IN MAX9675 OUT OUTPUTS (0-15) 16 16 IN MAX9675 OUT IN (48-63) 16 16 IN MAX9675 OUT Figure 7. 64 x 16 Nonblocking Matrix with Reduced Capacitive Loading Coupling through the power supply is a function of the quality and location of the supply bypassing. Use appropriate low-impedance components and locate them as close as possible to the IC. Avoid routing the inputs near the outputs. Power-Supply Bypassing The MAX9675 operates from a 5V supply. For dualsupply operation, bypass all supply pins to ground with 0.1F capacitors. ______________________________________________________________________________________ 110MHz, 16 x 16 Video Crosspoint Switch with Programmable Gain Matrix Programming The MAX9675's unique digital interface simplifies programming multiple MAX9675 devices in an array. Multiple devices are connected with DOUT of the first device connecting to DIN of the second device, and so on (Figure 9). Two distinct programming modes, individual output address mode (MODE = 0) and complete matrix mode (MODE = 1), are selected by toggling a single MODE control pin high or low. Both modes operate with the same physical board layout. This allows initial programming of the IC by daisy-chaining and sending one long data word while still being able to address immediately and update individual locations in the matrix. Individual Output Address Mode (Mode 0) In Individual Output Address Mode, the devices are connected in a serial bus configuration, with the data routing gate (Figure 3) connecting DIN to DOUT, making each device a virtual node on the serial bus. A single 16-bit control word is sent to all devices simultaneously. Only the device with the corresponding chip address responds to the programming word, and updates its output. In this mode, the chip address is set through hardware pin strapping of A3-A0. The host then communicates with the device by sending a 16-bit word consisting of 2 don't care MSB bits, 4 chip address bits, and 10 bits of data to make the word OPTIMAL ISOLATION RESISTANCE vs. CAPACITIVE LOAD 30 ISOLATION RESISTANCE () The MAX9675 output buffers can be programmed to either AV = +1V/V or +2V/V. The +1V/V configuration is typically used when driving a short-length (less than 3cm), high-impedance "local" PCB trace. To drive a cable or a 75 transmission line trace, program the gain of the output buffer to +2V/V and place a 75 resistor in series with the output. The series termination resistor and the 75 load impedance act as a voltagedivider that divides the video signal in half. Set the gain to +2V/V to transmit a standard 1V video signal down a cable. The series 75 resistor is called the back-match, reverse termination, or series termination. This 75 resistor reduces reflections, and provides isolation, increasing the output-capacitive-driving capability. MAX9675 Driving a PCB Interconnect or a Cable (AV = +1V/V or +2V/V) 25 20 15 10 5 0 0 100 200 300 400 500 CAPACITIVE LOAD (pF) Figure 8. Optimal Isolation Resistor vs. Capacitive Load exactly 2 bytes in length. The 10 data bits are broken down into 4 bits to select the output to be programmed; 1 bit to set the output enable; 1 bit to set gain; and 4 bits to select the input to be connected to that output. In this method, the matrix is programmed one output at a time. Complete Matrix Mode (Mode 1) In Complete Matrix Mode, the devices are connected in a daisy-chain fashion where n x 96 bits are sent to program the entire matrix, and where n = the number of MAX9675 devices connected in series. This long data word is structured such that the first bit is the LSB of the last device in the chain and the last data bit is the MSB of the first device in the chain. The total length of the data word is equal to the number of crosspoint devices to be programmed in series times 96 bits per crosspoint device. This programming method is most often used at startup to initially configure the switching matrix. ______________________________________________________________________________________ 23 MAX9675 110MHz, 16 x 16 Video Crosspoint Switch with Programmable Gain CHIP ADDRESS = 0 DOUT DIN HOST CONTROLLER CHIP ADDRESS = 1 DOUT DIN MAX9675 CHIP ADDRESS = 2 DOUT DIN MAX9675 NEXT DEVICE MAX9675 SCLK A3 SCLK A3 SCLK CE A2 CE A2 A3 CE A2 MODE A1 MODE UPDATE A0 UPDATE A1 MODE A1 A0 UPDATE A0 VDD VDD VIRTUAL SERIAL BUS (MODE 0: INDIVIDUAL OUTPUT ADDRESS MODE) Figure 9. Matrix Mode Programming Chip Information TRANSISTOR COUNT: 24,467 PROCESS: BiCMOS 24 ______________________________________________________________________________________ 110MHz, 16 x 16 Video Crosspoint Switch with Programmable Gain N.C. N.C. VEE AGND IN3 AGND IN2 AGND IN1 AGND IN0 N.C. N.C. N.C. N.C. N.C. AGND AGND AGND VCC OUT0 VEE OUT1 N.C. N.C. 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 TOP VIEW + 1 75 VCC AGND 2 74 OUT2 IN5 3 73 VEE AGND IN4 4 72 OUT3 IN6 5 71 VCC AGND 6 70 OUT4 IN7 7 69 VEE AGND 8 68 OUT5 IN8 9 67 VCC AGND 10 66 OUT6 IN9 11 65 VEE AGND 12 64 OUT7 IN10 MAX9675 13 63 VCC AGND 14 62 OUT8 IN11 15 61 VEE AGND 16 60 OUT9 IN12 17 59 VCC A3 18 58 OUT10 IN13 19 57 VEE A2 20 56 OUT11 IN14 21 55 VCC A1 40 41 42 43 44 45 46 47 48 49 50 N.C. N.C. N.C. N.C. N.C. AGND AGND VCC OUT15 VEE OUT14 DIN 39 36 UPDATE N.C. 35 RESET N.C. 34 MODE 38 33 CE 37 32 VDD 31 SCLK VCC 30 51 AOUT 25 DGND VCC 29 OUT13 DOUT 52 28 VEE 24 27 23 A0 N.C. OUT12 53 26 54 N.C. 22 IN15 TQFP ______________________________________________________________________________________ 25 MAX9675 Pin Configuration Package Information For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. 100L,TQFP.EPS MAX9675 110MHz, 16 x 16 Video Crosspoint Switch with Programmable Gain PACKAGE OUTLINE 100L TQFP, 14x14x1.0mm 21-0085 26 ______________________________________________________________________________________ B 1 2 110MHz, 16 x 16 Video Crosspoint Switch with Programmable Gain PACKAGE OUTLINE, 100L TQFP, 14x14x1.0mm 21-0085 PACKAGE TYPE PACKAGE CODE DOCUMENT NO. 100 TQFP C100-1 21-0085 B 2 2 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 27 (c) 2008 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc. MAX9675 Package Information (continued) For the latest package outline information and land patterns, go to www.maxim-ic.com/packages.