74HC4050 SSI HEX HIGH-TO-LOW LEVEL SHIFTER FEATURES TYPICAL UNIT @ Output capability: standard SYMBOL PARAMETER CONDITIONS Icc category: SSI Hc tpHL/ propagation delay CL = 15 pF GENERAL DESCRIPTION tPLH nA tony Veco=5V ? ns The 74HC4050 is a high-speed ; it 35 F Si-gate CMOS device and is pin i input capacitance p compatible with the 4050 of the dissipati "4000B" series. It is specified in Cpp papacitanee per buffer note 1 14 pF compliance with JEDEC standard no. 7A. The 74HC4050 provides six non-inverting buffers with a modified input protection structure, which has no diode connected to Vcc. Input voltages of up to 15 V may therefore be used. This feature enables the non-inverting buffers to be used as logic level translators, which will convert high level logic to low level logic, while operating from a low voltage power supply. For example 15 V logic ("4000B series) can be converted down to 2 V logic. The actual input switch level remains related to the Vcc and is the same as mentioned in the family characteristics. APPLICATIONS Converting 15 V logic (4000B series) down to 2 V logic. GND = OV; Tamb = 25 C; t, = te = 6 ns Note 1. Cpp is used to determine the dynamic power dissipation {Pp in uW): Pp =Cpp x Vcc? x fi t+ (CL x Vcc? x fo) where: fj = input frequency in MHz fo = output frequency in MHz Z (Cy x Voc? x fy) = sum of outputs PACKAGE OUTLINES cL = vec Hou SEE PACKAGE INFORMATION SECTION PIN DESCRIPTION output load capacitance in pF supply voltage in V PIN NO. SYMBOL NAME AND FUNCTION 1 Vee positive supply voltage 2, 4, 6, 10, 12, 15 1Y to 6Y data outputs 3,5, 7, 9, + 11, 14 1A to6A data inputs 8 GND ground (0 V} 13, 16 n.c, not connected Veo [4 U [16) n.c. wR] [is] ev ra[a | [v4] 6a ay [a 13] nc. a 4050 a ay (6] nn} SA saz] a ono [8 a]4a 7293757 Fig. 1 Pin configuration. 7293768 Fig. 2 Logic symbol. 7E93759.2 Fig. 3 1EC jogic symbol. December 1990 871 74HC4050 SSI 7293768 Fig. 4 Functional diagram. 1902 input -{}- 4. 2 lovie polysilicon fetimor fas 4 _ ND sl 7297018 Fig. 5 Input protection for HC4050. Single sided thick oxide field effect metal gate transistor as input protection. Dee Pep 7293900 Fig. 6 Logic diagram (one level shifter). FUNCTION TABLE INPUT OUTPUT nA ny L L H H H = HIGH voltage level L = LOW voltage level March 1988 Hex HiIGH-to-LOW level shifter 74HC4050 SS! RATINGS Limiting values in accordance with the Absolute Maximum System (IEC 134) Voltages are referenced to GND (ground = 0 V) SYMBOL | PARAMETER MIN. | MAX. | UNIT |} CONDITIONS Vec DC supply voltage -0.5 | +7 Vv Vik DC input voltage range 0.5 | +16 v -lhik OC input diode current 20 mA forV); <-0.5V tlow DC output diode current 20 mA for Vo <-0.5 Vor Vo > Vcc +0.5V tlo OC output source or sink for-O.5V <Vgo<VcctO05V current - standard outputs 25 mA tlec: DC Vcc or GND current +IGND for types with: - standard outputs 50 mA Tstg storage temperature range 65 | +150 | C power dissipation per package for temperature range: 40 to +125 C 74HC Prot plastic DIL 750 mw above +70 C: derate linearly with 12 mW/K plastic mini-pack (SO) 500 mw above +70 C: derate linearly with 8 mW/K RECOMMENDED OPERATING CONDITIONS 74HC SYMBOL | PARAMETER UNIT | CONDITIONS min. typ. max. Vee OC supply voltage 2.0 5.0 6.0 Vv vt DC input voltage range GND - 15 v Tamb operating ambient temperature range ~40 +85 c see DC and AC Tamb operating ambient temperature range 40 +125 c characteristics 1000 Veco #2.0V; VIN = 2.0V 500 Voc = 4.5 V; Vin =45V tr, tf input rise and fall times 6.0 400 ns Voc = 6.0 V; Vin =6.0V 650 Voc = 6.0 V; Vin = 10.0 V 1000 Vcc 2 6.0 V: Vin = 15.0 V March 1988 873 74HC4050 SSI DC CHARACTERISTICS FOR 74HC Voltages are referenced to GND (ground = 0 V) Tamb (C) TEST CONDITIONS 74HC SYMBOL | PARAMETER UNIT | Voc| Vv, | OTHER +25 ~40 to +85 | 40 to +125 v Min. | typ. | max. | min.) max. | min, | max. 15 1.3 15 1.6 2.0 Vi HIGH level input voltage [3.15 | 2.4 3.15 3.15 v 45 4.2 3.1 4.2 42 6.0 0.7 [05 0.5 0.5 2.0 VIL LOW level input voltage 1.B | 1.35 1.35 1.35 | Vv 45 2.9 )18 1.8 1.8 6.0 19 | 2.0 1.9 1.9 2.0 | Vin | -lo=20HA Vou Mower voltage | 44 | 45 44 44 v 45 | or | -I9=20uA 5.9 | 6.0 59 5.9 6.0 | Vit | -I9=20pnA V HIGH level output voltage | 3.98 3.84 37 v 45 | VIM | ig=4.0ma OH standard outputs 5.48 5.34 5.2 6.0 vit | 7IOF 5.2mA 0.1 0.1 0.1 2.0 | Vin | Io =20uA Vor ton ee voltage 0.1 0.1 ot |v 45 | or | Ig=20uA 0.1 0.1 0.1 6.0 | Vit | lo =20nA Vv LOW level output voltage 0.26 0,33 0.4 Vv 45 Vik Ig =4.0mA OL standard outputs 0.26 0.33 04 6.0 VIL to =5.2mA Vcc 0.1 1.0 1.0 BA 6.0 or GND +h input leakage current 2.0 0.5 5.0 5.0 pA to 15V 6.0 15V lec quiescent supply current 2.0 20.0 40.0 | pA 6.0 or GND AC CHARACTERISTICS FOR 74HC GND = OV; ty = tf = 6 ns; CL = 50 pF Tamb (C) TEST CONDITIONS 74HC SYMBOL | PARAMETER UNIT | Vcc | WAVEFORMS +25 40 to +86 | 40 to +125 v min, | typ. | max. | min.| max. | min. | max. . 25 | 8 105 1 tPHL! propagation delay g 21 6 ns ae Fig. 7 tPLH nA tony 7 | 14 18 22 6.0 , 19 | 75 95 110 2.0 THE! | output transition time 7 | 15 19 22 ns [45 | Fig. 7 TLH 6 | 13 16 19 6.0 874 January 1986 Hex HIGH-to-LOW level shifter 74HC4050 SSI AC WAVEFORMS nA INPUT n QUTPUT FZO3760 Fig. 7 Waveforms rowing the input (nA) to output (nY} prosagation delays and the Output transition times. Note to AC waveforms (1) HC: Vn = 50%; V) = GND to Vcc. HCT: Vy = 1.3 V; V) = GND to 3V. January 1986 875