MC14014BFG - ON Semiconductor - Datasheet.Directory

June, 2011 − Rev. 7

1Publication Order Number:

MC14014B/D

MC14014B, MC14021B

8-Bit Static Shift Register

The MC14014B and MC14021B 8−bit static shift registers are

constructed with MOS P−channel and N−channel enhancement mode

devices in a single monolithic structure. These shift registers find primary

use in parallel−to−serial data conversion, synchronous and asynchronous

parallel input, serial output data queueing; and other general purpose

register applications requiring low power and/or high noise immunity.

Features

•Synchronous Parallel Input/Serial Output (MC14014B)

•Asynchronous Parallel Input/Serial Output (MC14021B)

•Synchronous Serial Input/Serial Output

•Full Static Operation

•“Q” Outputs from Sixth, Seventh, and Eighth Stages

•Double Diode Input Protection

•Supply Voltage Range = 3.0 Vdc to 18 Vdc

•Capable of Driving Two Low−power TTL Loads or One Low−power

Schottky TTL Load Over the Rated Temperature Range

•MC14014B Pin−for−Pin Replacement for CD4014B

•MC14021B Pin−for−Pin Replacement for CD4021B

•These Devices are Pb−Free and are RoHS Compliant

MAXIMUM RATINGS (Voltages Referenced to VSS)

Symbol Parameter Value Unit

VDD DC Supply Voltage Range −0.5 to +18.0 V

Vin, Vout Input or Output Voltage Range

(DC or Transient)

−0.5 to VDD + 0.5 V

Iin, Iout Input or Output Current

(DC or Transient) per Pin

±10 mA

PDPower Dissipation, per Package

(Note 1)

500 mW

TAAmbient Temperature Range −55 to +125 °C

Tstg Storage Temperature Range −65 to +150 °C

TLLead Temperature

(8−Second Soldering)

260 °C

Maximum ratings are those values beyond which device damage can occur.

Maximum ratings applied to the device are individual stress limit values (not

normal operating conditions) and are not valid simultaneously. If these limits are

exceeded, device functional operation is not implied, damage may occur and

reliability may be affected.

1. Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C

This device contains protection circuitry to guard against damage due to high

static voltages or electric fields. However, precautions must be taken to avoid

applications of any voltage higher than maximum rated voltages to this

high−impedance circuit. For proper operation, Vin and Vout should be constrained

to the range VSS v (Vin or Vout) v VDD.

Unused inputs must always be tied to an appropriate logic voltage level

(e.g., either VSS or VDD). Unused outputs must be left open.

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MARKING

DIAGRAMS

PDIP−16

P SUFFIX

CASE 648

MC140xxBCP

AWLYYWWG

SOIC−16

D SUFFIX

CASE 751B

140xxBG

AWLYWW

xx = Specific Device Code

A = Assembly Location

WL, L = Wafer Lot

YY, Y = Year

WW, W = Work Week

G = Pb−Free Indicator

SOEIAJ−16

F SUFFIX

CASE 966

MC140xxB

ALYWG

See detailed ordering and shipping information in the package

dimensions section on page 6 of this data sheet.

ORDERING INFORMATION

16

1

16

1

16

MC14014B, MC14021B

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2

TRUTH TABLE

Q6 Q7 Q8

tClockD

SP/S t=n+6 t=n+7 t=n+8

n000??

n+1 1 0 1 0 ?

n+2 0 0 0 1 0

n+3 1 0 1 0 1

X 0 Q6 Q7 Q8

SERIAL OPERATION:

Clock

MC14014B MC14021B DSP/S Pn*Qn

XX100

XX111

*Q6, Q7, & Q8 are available externally

PARALLEL OPERATION:

X = Don’t Care

LOGIC DIAGRAM

CLOCK

DS

P/S

P1 P2 P3 P6 P7 P8

765 14151

10

11

9

D

C

QD

C

QD

C

QD

C

QD

C

QD

CQ Q Q

2123

Q8Q7Q6

VDD = PIN 16

VSS = PIN 8

P4 = PIN 4

P5 = PIN 13

PIN ASSIGNMENT

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

Q7

P5

P6

P7

VDD

P/S

C

DS

P4

Q8

Q6

P8

VSS

P1

P2

P3

MC14014B, MC14021B

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3

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎÎÎ

Characteristic

ÎÎÎÎ

Symbol

ÎÎÎ

VDD

Vdc

ÎÎÎÎÎ

− 55_C

ÎÎÎÎÎÎÎÎÎ

25_C

ÎÎÎÎÎ

125_C

ÎÎÎ

Unit

ÎÎÎ

Min

ÎÎÎ

Max

ÎÎÎÎ

Min

ÎÎÎ

Typ

(Note 2)

ÎÎÎÎ

Max

ÎÎÎ

Min

ÎÎÎ

Max

ÎÎÎÎÎÎÎÎÎÎ

Output Voltage “0” Level

Vin = VDD or 0

Vin = 0 or VDD “1” Level

ÎÎÎÎ

VOL

ÎÎÎ

5.0

10

15

ÎÎÎ

−

ÎÎÎ

0.05

ÎÎÎÎ

−

ÎÎÎ

0

ÎÎÎÎ

0.05

ÎÎÎ

−

ÎÎÎ

0.05

ÎÎÎ

Vdc

ÎÎÎÎ

VOH

ÎÎÎ

5.0

10

15

ÎÎÎ

4.95

9.95

14.95

ÎÎÎ

−

ÎÎÎÎ

4.95

9.95

14.95

ÎÎÎ

5.0

10

15

ÎÎÎÎ

−

ÎÎÎ

4.95

9.95

14.95

ÎÎÎ

−

ÎÎÎ

Vdc

ÎÎÎÎÎÎÎÎÎÎ

Input Voltage “0” Level

(VO = 4.5 or 0.5 Vdc)

(VO = 9.0 or 1.0 Vdc)

(VO = 13.5 or 1.5 Vdc)

(VO = 0.5 or 4.5 Vdc) “1” Level

(VO = 1.0 or 9.0 Vdc)

(VO = 1.5 or 13.5 Vdc)

ÎÎÎÎ

VIL

ÎÎÎ

5.0

10

15

ÎÎÎ

−

ÎÎÎ

1.5

3.0

4.0

ÎÎÎÎ

−

ÎÎÎ

2.25

4.50

6.75

ÎÎÎÎ

1.5

3.0

4.0

ÎÎÎ

−

ÎÎÎ

1.5

3.0

4.0

ÎÎÎ

Vdc

ÎÎÎÎ

VIH

ÎÎÎ

5.0

10

15

ÎÎÎ

3.5

7.0

11

ÎÎÎ

−

ÎÎÎÎ

3.5

7.0

11

ÎÎÎ

2.75

5.50

8.25

ÎÎÎÎ

−

ÎÎÎ

3.5

7.0

11

ÎÎÎ

−

ÎÎÎ

Vdc

ÎÎÎÎÎÎÎÎÎÎ

Output Drive Current

(VOH = 2.5 Vdc) Source

(VOH = 4.6 Vdc)

(VOH = 9.5 Vdc)

(VOH = 13.5 Vdc)

(VOL = 0.4 Vdc) Sink

(VOL = 0.5 Vdc)

(VOL = 1.5 Vdc)

ÎÎÎÎ

IOH

ÎÎÎ

5.0

10

15

ÎÎÎ

– 3.0

– 0.64

– 1.6

– 4.2

ÎÎÎ

−

ÎÎÎÎ

– 2.4

– 0.51

− 1.3

− 3.4

ÎÎÎ

– 4.2

– 0.88

– 2.25

− 8.8

ÎÎÎÎ

−

ÎÎÎ

– 1.7

− 0.36

– 0.9

− 2.4

ÎÎÎ

−

ÎÎÎ

mAdc

ÎÎÎÎ

IOL

ÎÎÎ

5.0

10

15

ÎÎÎ

0.64

1.6

4.2

ÎÎÎ

−

ÎÎÎÎ

0.51

1.3

3.4

ÎÎÎ

0.88

2.25

8.8

ÎÎÎÎ

−

ÎÎÎ

0.36

0.9

2.4

ÎÎÎ

−

ÎÎÎ

mAdc

ÎÎÎÎÎÎÎÎÎÎ

Input Current

ÎÎÎÎ

Iin

ÎÎÎ

15

ÎÎÎ

−

ÎÎÎ

± 0.1

ÎÎÎÎ

−

ÎÎÎ

±0.00001

ÎÎÎÎ

± 0.1

ÎÎÎ

−

ÎÎÎ

± 1.0

ÎÎÎ

mAdc

ÎÎÎÎÎÎÎÎÎÎ

Input Capacitance

(Vin = 0)

ÎÎÎÎ

Cin

ÎÎÎ

−

ÎÎÎ

−

ÎÎÎ

−

ÎÎÎÎ

−

ÎÎÎ

5.0

ÎÎÎÎ

7.5

ÎÎÎ

−

ÎÎÎ

−

ÎÎÎ

pF

ÎÎÎÎÎÎÎÎÎÎ

Quiescent Current

(Per Package)

ÎÎÎÎ

IDD

ÎÎÎ

5.0

10

15

ÎÎÎ

−

ÎÎÎ

5.0

10

15

ÎÎÎÎ

−

ÎÎÎ

0.005

0.010

0.015

ÎÎÎÎ

5.0

10

15

ÎÎÎ

−

ÎÎÎ

150

300

600

ÎÎÎ

mAdc

ÎÎÎÎÎÎÎÎÎÎ

Total Supply Current (Notes 3 & 4)

(Dynamic plus Quiescent,

Per Package)

(CL = 50 pF on all outputs, all

buffers switching)

ÎÎÎÎ

IT

ÎÎÎ

5.0

10

15

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

IT = (0.75 mA/kHz) f + IDD

IT = (1.50 mA/kHz) f + IDD

IT = (2.25 mA/kHz) f + IDD

ÎÎÎ

mAdc

2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

3. The formulas given are for the typical characteristics only at 25_C.

4. To calculate total supply current at loads other than 50 pF:

IT(CL) = IT(50 pF) + (CL − 50) Vfk

where: IT is in mA (per package), CL in pF, V = (VDD − VSS) in volts, f in kHz is input frequency, and k = 0.0015.

MC14014B, MC14021B

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4

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

SWITCHING CHARACTERISTICS (Note 5) (CL = 50 pF, TA = 25_C)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Characteristic

ÎÎÎÎÎ

Symbol

ÎÎÎÎ

VDD

Vdc

ÎÎÎÎ

Min

ÎÎÎÎ

Typ

(Note 6)

ÎÎÎÎ

Max

ÎÎÎ

Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Output Rise and Fall Time

tTLH, tTHL = (1.5 ns/pF) CL + 25 ns

tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns

tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns

ÎÎÎÎÎ

tTLH,

tTHL

ÎÎÎÎ

5.0

10

15

ÎÎÎÎ

−

ÎÎÎÎ

100

50

40

ÎÎÎÎ

200

100

80

ÎÎÎ

ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Propagation Delay Time (Clock to Q, P/S to Q)

tPHL, tPLH = (1.7 ns/pF) CL + 315 ns

tPHL, tPLH = (0.66 ns/pF) CL + 137 ns

tPHL, tPLH = (0.5 ns/pF) CL + 90 ns

ÎÎÎÎÎ

tPLH,

tPHL

ÎÎÎÎ

5.0

10

15

ÎÎÎÎ

−

ÎÎÎÎ

400

170

115

ÎÎÎÎ

800

340

230

ÎÎÎ

ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Clock Pulse Width

ÎÎÎÎÎ

tWH

ÎÎÎÎ

5.0

10

15

ÎÎÎÎ

400

175

135

ÎÎÎÎ

150

75

40

ÎÎÎÎ

−

ÎÎÎ

ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Clock Frequency

ÎÎÎÎÎ

fcl

ÎÎÎÎ

5.0

10

15

ÎÎÎÎ

−

ÎÎÎÎ

3.0

6.0

8.0

ÎÎÎÎ

1.5

3.0

4.0

ÎÎÎ

MHz

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parallel/Serial Control Pulse Width

ÎÎÎÎÎ

tWH

ÎÎÎÎ

5.0

10

15

ÎÎÎÎ

400

175

135

ÎÎÎÎ

150

75

40

ÎÎÎÎ

−

ÎÎÎ

ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Setup Time

P/S to Clock

ÎÎÎÎÎ

tsu

ÎÎÎÎ

5.0

10

15

ÎÎÎÎ

200

100

80

ÎÎÎÎ

100

50

40

ÎÎÎÎ

−

ÎÎÎ

ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Hold Time

Clock to P/S

ÎÎÎÎÎ

th

ÎÎÎÎ

5.0

10

15

ÎÎÎÎ

20

25

ÎÎÎÎ

– 2.5

– 10

0

ÎÎÎÎ

−

ÎÎÎ

ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Setup Time

Data (Parallel or Serial) to

Clock or P/S

ÎÎÎÎÎ

tsu

ÎÎÎÎ

5.0

10

15

ÎÎÎÎ

350

80

60

ÎÎÎÎ

150

50

30

ÎÎÎÎ

−

ÎÎÎ

ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Hold Time

Clock to Ds

ÎÎÎÎÎ

th

ÎÎÎÎ

5.0

10

15

ÎÎÎÎ

45

35

ÎÎÎÎ

0

5

ÎÎÎÎ

−

ÎÎÎ

ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Hold Time

Clock to Pn

ÎÎÎÎÎ

th

ÎÎÎÎ

5.0

10

15

ÎÎÎÎ

50

45

ÎÎÎÎ

25

20

ÎÎÎÎ

−

ÎÎÎ

ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Input Clock Rise Time

ÎÎÎÎÎ

tr(cl)

ÎÎÎÎ

5.0

10

15

ÎÎÎÎ

−

ÎÎÎÎ

−

ÎÎÎÎ

15

5

4

ÎÎÎ

ms

5. The formulas given are for the typical characteristics only at 25_C.

6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

MC14014B, MC14021B

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5

Figure 1. Output Source Current Test Circuit Figure 2. Output Sink Current Test Circuit

PULSE

GENERATOR

PULSE

GENERATOR

VDD Vout

IOH

EXTERNAL

POWER

SUPPLY

EXTERNAL

POWER

SUPPLY

P/S

C

P6

P7

P8

DSQ8

Q7

Q6

Preset output under test to a logic “1” level.

VDD Vout

P/S

C

P6

P7

P8

DSQ8

Q7

Q6

IOL

Figure 3. Power Dissipation Test Circuit and Waveform

PULSE

GENERATOR 1

VDD

P/S

C

P6

P7

P8

DS

Q8

Q7

Q6

PULSE

GENERATOR 2

500 mFID

0.01 mF

CERAMIC

CL

VSS

P5

P4

P3

P2

P1

CLOCK

DATA

50%

1

f

MC14014B, MC14021B

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6

Figure 4. Switching Time Test Circuit and Waveforms

PULSE

GENERATOR 1

PULSE

GENERATOR 2

VDD

1

2

22

11

VDD

VSS

SW 1

SW 2

CL

Q8

Q7

Q6

P/S

C

P6

P7

P8

DS

P5

P4

P3

P2

P1

VDD

VSS

VDD

VSS

VOH

VOL

20 ns 20 ns

PARALLEL OR

SERIAL DATA

INPUT

CLOCK OR P/S

INPUT

Q

OUTPUT

90%

50%

10%

tsu

tWH tTHL

90%

50%

10%

tWH tWL

tPLH tPHL

90%

50%

10%

tTLH tTHL

tWL = tWH = 50% DUTY CYCLE

SWITCH POSITION 1 = PARALLEL IN

SWITCH POSITION 2 = SERIAL IN

ORDERING INFORMATION

Device Package Shipping†

MC14014BCPG PDIP−16

(Pb−Free)

500 Units / Rail

MC14014BDG SOIC−16

(Pb−Free)

48 Units / Rail

MC14014BDR2G SOIC−16

(Pb−Free)

2500 Units / Tape & Reel

MC14014BFELG SOEIAJ−16 2000 Units / Tape & Reel

MC14021BCPG PDIP−16

(Pb−Free)

500 Units / Rail

MC14021BDG SOIC−16

(Pb−Free)

48 Units / Rail

MC14021BDR2G SOIC−16

(Pb−Free)

2500 Units / Tape & Reel

MC14021BFELG SOEIAJ−16 2000 Units / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

MC14014B, MC14021B

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7

PACKAGE DIMENSIONS

PDIP−16

P SUFFIX

PLASTIC DIP PACKAGE

CASE 648−08

ISSUE T

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS

WHEN FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE

MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

−A−

B

FC

S

H

GD

J

L

M

16 PL

SEATING

18

916

K

PLANE

−T−

M

A

M

0.25 (0.010) T

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A0.740 0.770 18.80 19.55

B0.250 0.270 6.35 6.85

C0.145 0.175 3.69 4.44

D0.015 0.021 0.39 0.53

F0.040 0.70 1.02 1.77

G0.100 BSC 2.54 BSC

H0.050 BSC 1.27 BSC

J0.008 0.015 0.21 0.38

K0.110 0.130 2.80 3.30

L0.295 0.305 7.50 7.74

M0 10 0 10

S0.020 0.040 0.51 1.01

____

SOEIAJ−16

F SUFFIX

PLASTIC EIAJ SOIC PACKAGE

CASE 966−01

ISSUE A

HE

A1

DIM MIN MAX MIN MAX

INCHES

--- 2.05 --- 0.081

MILLIMETERS

0.05 0.20 0.002 0.008

0.35 0.50 0.014 0.020

0.10 0.20 0.007 0.011

9.90 10.50 0.390 0.413

5.10 5.45 0.201 0.215

1.27 BSC 0.050 BSC

7.40 8.20 0.291 0.323

0.50 0.85 0.020 0.033

1.10 1.50 0.043 0.059

0

0.70 0.90 0.028 0.035

--- 0.78 --- 0.031

A1

HE

Q1

LE

_10 _0

_10 _

LE

Q1

_

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS D AND E DO NOT INCLUDE

MOLD FLASH OR PROTRUSIONS AND ARE

MEASURED AT THE PARTING LINE. MOLD FLASH

OR PROTRUSIONS SHALL NOT EXCEED 0.15

(0.006) PER SIDE.

4. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

5. THE LEAD WIDTH DIMENSION (b) DOES NOT

INCLUDE DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.08 (0.003)

TOTAL IN EXCESS OF THE LEAD WIDTH

DIMENSION AT MAXIMUM MATERIAL CONDITION.

DAMBAR CANNOT BE LOCATED ON THE LOWER

RADIUS OR THE FOOT. MINIMUM SPACE

BETWEEN PROTRUSIONS AND ADJACENT LEAD

TO BE 0.46 ( 0.018).

M

L

DETAIL P

VIEW P

c

A

b

e

M

0.13 (0.005) 0.10 (0.004)

1

16 9

8

D

Z

E

A

b

c

D

E

e

L

M

Z

MC14014B, MC14021B

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8

SOIC−16

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751B−05

ISSUE K NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE MOLD

PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR PROTRUSION

SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D

DIMENSION AT MAXIMUM MATERIAL CONDITION.

18

16 9

SEATING

PLANE

F

J

M

RX 45_

G

8 PLP

−B−

−A−

M

0.25 (0.010) B S

−T−

D

K

C

16 PL

S

B

M

0.25 (0.010) A S

T

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A9.80 10.00 0.386 0.393

B3.80 4.00 0.150 0.157

C1.35 1.75 0.054 0.068

D0.35 0.49 0.014 0.019

F0.40 1.25 0.016 0.049

G1.27 BSC 0.050 BSC

J0.19 0.25 0.008 0.009

K0.10 0.25 0.004 0.009

M0 7 0 7

P5.80 6.20 0.229 0.244

R0.25 0.50 0.010 0.019

____

6.40

16X

0.58

16X 1.12

1.27

DIMENSIONS: MILLIMETERS

1

PITCH

SOLDERING FOOTPRINT

16

89

8X

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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should

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MC14014B/D

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