DATA SH EET
Objective specification
Supersedes data of 2003 Apr 07 2003 Dec 09
TDA8769
12-bit, 60/80/105 Msps
Analog-to-Digital Converter (ADC)
Nyquist/high IF sampling
INTEGRATED CIRCUITS
2003 Dec 09 2
Philips Semiconductors Objective specification
12-bit, 60/80/105 Msps Analog-to-Digital Converter
(ADC) Nyquist/high IF sampling TDA8769
CONTENTS
1 FEATURES
2 APPLICATIONS
3 GENERAL DESCRIPTION
4 QUICK REFERENCE DATA
5 ORDERING INFORMATION
6 BLOCK DIAGRAM
7 PINNING
8 LIMITING VALUES
9 THERMAL CHARACTERISTICS
10 CHARACTERISTICS
11 APPLICATION INFORMATION
11.1 Output coding and control signals
11.2 TDA8769 in 3G radio receivers
11.3 Application diagrams
11.4 Demonstration board
11.5 Definitions
11.5.1 Static parameters
11.5.1.1 Integral non-linearity (INL)
11.5.1.2 Differential non-linearity (DNL)
11.5.2 Dynamic parameters
11.5.2.1 Signal-to-noise and distortion (SINAD)
11.5.2.2 Effective number of bits (ENOB)
11.5.2.3 Total harmonic distortion (THD)
11.5.2.4 Signal-to-noise ratio (SNR)
11.5.2.5 Spurious free dynamic range (SFDR)
11.5.2.6 Intermodulation distortion (IMD2 and IMD3)
12 PACKAGE OUTLINE
13 SOLDERING
13.1 Introduction to soldering surface mount
packages
13.2 Reflow soldering
13.3 Wave soldering
13.4 Manual soldering
13.5 Suitability of surface mount IC packages for
wave and reflow soldering methods
14 DATA SHEET STATUS
15 DEFINITIONS
16 DISCLAIMERS
2003 Dec 09 3
Philips Semiconductors Objective specification
12-bit,60/80/105 MspsAnalog-to-DigitalConverter
(ADC) Nyquist/high IF sampling TDA8769
1 FEATURES
•12-bit resolution
•Optimized for both Nyquist and high IF sampling
•High-speed sampling rate up to 105 MHz
•Maximum analog input frequency of 330 MHz (see
Application section)
•Only 2 clock cycles latency
•5 V power supplies and 3.3 V output power supply
•Binary or two’s-complement CMOS outputs
•Programmable Complete Conversion Signal (CCS)
CMOS output
•In-range CMOS compatible output
•CMOS compatible static digital inputs
•LVTTL and LVCMOS compatible digital outputs
•Differential clock input PECL; sine wave and TTL
compatible
•Integrated track-and-hold amplifier
•Differential analog input
•External amplitude range control
•Full-scale controllable from 1.5 to 1.9 V (p-p)
•Voltage controlled regulator included
•Temperature range from −40 to +85 °C.
2 APPLICATIONS
•Cellular infrastructure (2.5G, 3G, etc.)
•Base stations and “Zero-IF” or direct IF sampling
subsystems
•Wireless and wired broadband communications
•Wireless Local Loop (WLL)
•Local Multipoint Distribution Service (LMDS)
•Advanced Frequency Modulation (FM) radio
•Imaging (camera scanner and medical)
•Cable modem or set top box
•Radar and satellite hub systems.
3 GENERAL DESCRIPTION
The TDA8769 is a BiCMOS 12-bit Analog-to-Digital
Converter(ADC)optimizedforGSM/EDGE,W-CDMAand
CDMA2000 radio transceivers, high data rate radios and
other applications such as advanced FM radio and
professional imaging. Its main innovation is the RF
sampling, based on a high-speed clock of up to 105 Msps
combined with high input frequencies of up to 250 MHz.
It converts the analog input signal into 12-bit binary coded
digital words at a maximum sampling rate of 105 MHz.
The TDA8769 analog performances have been proven in
various multi-carrier 3G radio receivers, providing the
best-in-class Adjacent Channel Selectivity (ACS) up to
80 dB.
Moreover the TDA8769 offers the lowest clock cycle
latency, which enables competitive and optimized
feedback loops in controlled systems.
All static digital inputs (TH, CEN, OTC, DEL0 and DEL1)
are CMOS compatible and all outputs are LVTTL and
LVCMOS compatible. A sine wave clock input signal can
also be used.
4 QUICK REFERENCE DATA
Tbf.
5 ORDERING INFORMATION
TYPE NUMBER PACKAGE SAMPLING
FREQUENCY
(MHz)
NAME DESCRIPTION VERSION
TDA8769HW/6 HTQFP48 plastic thermal enhanced thin quad flat package;
48 leads; body 7 ×7×1.0 mm; heatsink SOT545-2 60
TDA8769HW/8 80
TDA8769HW/10 105
2003 Dec 09 4
Philips Semiconductors Objective specification
12-bit,60/80/105 MspsAnalog-to-DigitalConverter
(ADC) Nyquist/high IF sampling TDA8769
6 BLOCK DIAGRAM
handbook, full pagewidth
MBL884
12
VREF
REFERENCE
CLOCK
DRIVER
POWER
MANAGEMENT
CMADC
REFERENCE
LATCH
LATCH
ADC&
AMP
FSREF
D0 to D11
VCCO
CENDEC
13
11
47
46
42
1
16 38
35
205
19
23 to 34
22 IR
OTC
DEL0 CLKN
2
VCCA1
3
VCCA3
44
VCCA4
40
VCCD1
17
VCCD2
VREF
INN
IN
TH
CMADC
TDA8769
TRACK
HOLD
n.c.
6 to 10, 12,
14, 21, 45
AGND1
48
AGND3
4
AGND4
43
DGND1
41
DGND2
18
OGND
37
CCS
39
CLK
15
DEL1
36
Fig.1 Block diagram.
7 PINNING
SYMBOL PIN TYPE(1) DESCRIPTION
CMADC 1 O regulator output common mode ADC output
VCCA1 2 P analog supply voltage 1 (5.0 V)
VCCA3 3 P analog supply voltage 3 (5.0 V)
AGND3 4 G analog ground 3
DEC 5 I/O decoupling node
n.c. 6 −not connected
n.c. 7 −not connected
n.c. 8 −not connected
n.c. 9 −not connected
n.c. 10 −not connected
VREF 11 I reference voltage input
n.c. 12 −not connected
FSREF 13 O reference output
n.c. 14 −not connected
DEL1 15 I complete conversion sampling delay input 1
DEL0 16 I complete conversion sampling delay input 0
VCCD2 17 P digital supply voltage 2 (5.0 V)
2003 Dec 09 5
Philips Semiconductors Objective specification
12-bit, 60/80/105 Msps Analog-to-Digital Converter
(ADC) Nyquist/high IF sampling TDA8769
Note
1. P = power supply, G = ground, I = input and O = output.
DGND2 18 G digital ground 2
OTC 19 I control input two’s complement output (active HIGH)
CEN 20 I chip enable input (CMOS level; active LOW)
n.c. 21 −not connected
IR 22 O in-range output
D11 23 O data output bit 11 (MSB)
D10 24 O data output bit 10
D9 25 O data output bit 9
D8 26 O data output bit 8
D7 27 O data output bit 7
D6 28 O data output bit 6
D5 29 O data output bit 5
D4 30 O data output bit 4
D3 31 O data output bit 3
D2 32 O data output bit 2
D1 33 O data output bit 1
D0 34 O data output bit 0 (LSB)
VCCO 35 P supply voltage of data output (3.3 V)
CCS 36 O complete conversion signal output
OGND 37 G ground of data output
CLKN 38 I complementary clock input
CLK 39 I clock input
VCCD1 40 P digital supply voltage 1 (5.0 V)
DGND1 41 G digital ground 1
TH 42 I track-and-hold enable input (CMOS level; active HIGH)
AGND4 43 G analog ground 4
VCCA4 44 P analog supply voltage 4 (5.0 V)
n.c. 45 −not connected
IN 46 I analog input voltage
INN 47 I complementary analog input voltage
AGND1 48 G analog ground 1
AGND5 exposed
die pad G analog ground 5
SYMBOL PIN TYPE(1) DESCRIPTION
2003 Dec 09 6
Philips Semiconductors Objective specification
12-bit,60/80/105 MspsAnalog-to-DigitalConverter
(ADC) Nyquist/high IF sampling TDA8769
handbook, full pagewidth
TDA8769HW
MBL885
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
AGND1
INN
IN
n.c.
VCCA4
AGND4
TH
DGND1
VCCD1
CLK
CLKN
OGND
FSREF
n.c.
DEL1
DEL0
VCCD2
DGND2
OTC
CEN
n.c.
IR
D11
D10
CMADC
VCCA1
VCCA3
AGND3
DEC
n.c.
n.c.
n.c.
n.c.
n.c.
VREF
n.c.
CCS
VCCO
D0
D1
D2
D3
D4
D5
D6
D7
D8
exposed die pad
D9
Fig.2 Pin configuration.
8 LIMITING VALUES
Tbf.
9 THERMAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS VALUE UNIT
Rth(j-a) thermal resistance from junction to ambient in free air; (tbf) 25 K/W
Rth(c-a) thermal resistance from case to ambient in free air; (tbf) (tbf) K/W
2003 Dec 09 7
Philips Semiconductors Objective specification
12-bit, 60/80/105 Msps Analog-to-Digital Converter
(ADC) Nyquist/high IF sampling TDA8769
10 CHARACTERISTICS
VCCA = 4.75 to 5.25 V; VCCD = 4.75 to 5.25 V; VCCO = 2.7 to 3.6 V; AGND connected to DGND; Tamb =−40 to +85 °C;
VIN(p−p) −VINN(p−p) = 1.9 V −0.5 dBFS; VVREF =V
CCA3 −1.75 V; Vi(CM ) =V
CCA3 −1.6 V; typical values measured at
VCCA =V
CCD =5V, V
CCO = 3.0 V, Tamb =25°C and CL= 10 pF; unless otherwise specified.
SYMBOL PARAMETER CONDITIONS TEST(1) MIN. TYP. MAX. UNIT
Supplies
VCCA analog supply
voltage 4.75 5.0 5.25 V
VCCD digital supply
voltage 4.75 5.0 5.25 V
VCCO output supply
voltage 2.7 3.0 3.6 V
ICCA analog supply
current −109 (tbf) mA
ICCD digital supply
current −48 (tbf) mA
ICCO output supply
current fCLK = 80 Msps;
fi= 21.4 MHz −17.5 (tbf) mA
Ptot total power
dissipation fCLK = 60 Msps;
fi= 21.4 MHz −825 (tbf) mW
fCLK = 80 Msps;
fi= 21.4 MHz −840 (tbf) mW
fCLK = 105 Msps;
fi= 21.4 MHz −855 (tbf) mW
Clock inputs: pins CLK and CLKN; note 2
INPUTS
VIL LOW-level input
voltage referenced to DGND;
VCCD =5V
PECL mode 3.19 −3.52 V
TTL mode DGND −0.8 V
VIH HIGH-level input
voltage referenced to DGND;
VCCD =5V
PECL mode 3.83 −4.12 V
TTL mode 2.0 −VCCD V
IIL LOW-level input
current VCLK or VCLKN = 3.52 V (tbf) −−µA
VCLK or VCLKN = 0.80 V (tbf) −−mA
IIH HIGH-level input
current VCLK or VCLKN = 3.83 V −− (tbf) µA
VCLK or VCLKN = 2.00 V −− (tbf) mA
∆VCLK differential AC
input voltage for
switching
∆VCLK =V
CLK −VCLKN;
AC mode; DC voltage
level = 2.5 V
(tbf) 1.5 (tbf) V
Riinput resistance fCLK = 105 Msps −(tbf) −MΩ
Ciinput
capacitance fCLK = 105 Msps −(tbf) −pF
2003 Dec 09 8
Philips Semiconductors Objective specification
12-bit, 60/80/105 Msps Analog-to-Digital Converter
(ADC) Nyquist/high IF sampling TDA8769
TIMING
fclk(min) minimum clock
frequency VTH =V
CCD −− 9 Msps
fclk(max) maximum clock
frequency
TDA8769HW/6
60 −−MHz/
Msps
maximum clock
frequency
TDA8769HW/8
80 −−MHz/
Msps
maximum clock
frequency
TDA8769HW/10
105 −−MHz/
Msps
tCLKH clock HIGH
pulse width fi= 21.4 MHz (tbf) −−ns
tCLKL clockLOWpulse
width fi= 21.4 MHz (tbf) −−ns
Analog inputs: pins IN and INN
IIL LOW-level input
current VVREF =V
CCA3 −1.75 V;
VTH = HIGH −10 −µA
IIH HIGH-level input
current VVREF =V
CCA3 −1.75 V;
VTH = HIGH −10 −µA
Riinput resistance D −8.4 −MΩ
Ciinput
capacitance D−250 500 fF
Vi(CM) common mode
input voltage VIN =V
INN;
output code = 2047 DV
CCA3 −1.2 VCCA3 −1.6 VCCA3 −1.7 V
Digital inputs: pins OTC, SH, DEL1, DEL0 and CEN
VIL LOW-level input
voltage DGND −0.3VCCD V
VIH HIGH-level input
voltage 0.7VCCD −VCCD V
IIL LOW-level input
current VIL = 0.3VCCD (tbf) −µA
IIH HIGH-level input
current VIH = 0.7VCCD −− (tbf) µA
Voltage controlled regulator output: pin CMADC
Vo(CM) common mode
output voltage −VCCA3 −1.6 −V
IL(CM) load current −12mA
SYMBOL PARAMETER CONDITIONS TEST(1) MIN. TYP. MAX. UNIT
2003 Dec 09 9
Philips Semiconductors Objective specification
12-bit, 60/80/105 Msps Analog-to-Digital Converter
(ADC) Nyquist/high IF sampling TDA8769
Reference voltage input: pin VREF; note 3
Vref(FS) full-scale fixed
voltage fi= 25 MHz;
fCLK = 105 Msps −VCCA3 −1.75 −V
Vi(p-p) input voltage
(peak-to-peak
value)
Vi=V
IN −VINN;
VVREF =V
CCA3 −1.75 V;
Vi(CM) =V
CCA3 −1.6 V
−1.9 −V
Iref input current −0.3 10 µA
Full-scale voltage controlled regulator output: pin FSREF
Vo(FS) 1.9 V full-scale
output voltage −VCCA3 −1.75 −V
IL(FS) load current −12mA
Digital outputs: pins D11 to D0 and IR
OUTPUT LEVELS
VOL LOW-level
output voltage IOL = 2 mA DGND −DGND + 0.5 V
VOH HIGH-level
output voltage IOH =−0.4 mA VCCO −0.5 −VCCO V
IOZ output current in
3-state output level between
0.5 V and VCCO
−20 −+20 µA
TIMING; see Fig. 3
td(s) sampling delay CL= 10 pF; note 4 −(tbf) (tbf) ns
th(o) output hold time CL= 10 pF (tbf) 3.7 −ns
td(o) output delay CL=10pF −4.6 (tbf) ns
3-STATE OUTPUT DELAY
tdZH enable to HIGH
state −2.8 −ns
tdZL enable to LOW
state −7.5 −ns
tdHZ disable from
HIGH state −7.2 −ns
tdLZ disable from
LOW state −2.9 −ns
Timing complete conversion signal: pin CCS
td(CCS) complete
conversion
signal delay
CL= 10 pF; see Table 4
and Fig 4
DEL0 = LOW;
DEL1 = HIGH −0−ns
DEL0 = HIGH;
DEL1 = LOW −1.2 −ns
DEL0 = HIGH;
DEL1 = HIGH −2.2 −ns
SYMBOL PARAMETER CONDITIONS TEST(1) MIN. TYP. MAX. UNIT
2003 Dec 09 10
Philips Semiconductors Objective specification
12-bit, 60/80/105 Msps Analog-to-Digital Converter
(ADC) Nyquist/high IF sampling TDA8769
Analog signal processing (50% clock duty factor)
INL integral
non-linearity fCLK = 20 Msps;
fi= 400 kHz −±1.7 (tbf) LSB
DNL differential
non-linearity fCLK = 20 Msps;
fi= 400 kHz; no missing
code guaranteed
−±0.4 (tbf) LSB
Eoffset offset error VCCA =V
CCD =5V;
VCCO = 3.0 V;
Tamb =25°C;
output code = 2047
−−5−mV
EGgain error
amplitude
(spread from
device to device)
VCCA =V
CCD =5V;
VCCO = 3.0 V;
Tamb =25°C
(tbf) −(tbf) %FS
B analog
bandwidth fCLK = 105 Msps; −3 dB;
full-scale input; note 5 D−330 −MHz
THD total harmonic
distortion
TDA8769HW/6
B = Nyquist; note 6
fi= 21.4 MHz −−74 −dBc
total harmonic
distortion
TDA8769HW8
B = Nyquist; note 6
fi= 21.4 MHz −−74 −dBc
fi= 50 MHz −−68 −dBc
total harmonic
distortion
TDA8769HW/10
B = Nyquist; note 6
fi= 21.4 MHz −−67 −dBc
fi= 78 MHz −−63 −dBc
Nth(rms) thermal noise
(RMS value) shorted input;
VTH =V
CCD;
fclk = 105 Msps
−(tbf) −LSB
SNR signal-to-noise
ratio
TDA8769HW/6
fi= 21.4 MHz; note 7
B = Nyquist −66 −dBc
signal-to-noise
ratio
TDA8769HW/8
fi= 21.4 MHz; note 7
B = Nyquist −66 −dBc
fi= 50 MHz; note 7
B = Nyquist −66 −dBc
B = 5 MHz −72.4 −dBc
signal-to-noise
ratio
TDA8769HW/10
fi= 21.4 MHz; note 7
B = Nyquist −64 −dBc
fi= 78 MHz; note 7
B = Nyquist −62 −dBc
B = 5 MHz −72 −dBc
SYMBOL PARAMETER CONDITIONS TEST(1) MIN. TYP. MAX. UNIT
2003 Dec 09 11
Philips Semiconductors Objective specification
12-bit, 60/80/105 Msps Analog-to-Digital Converter
(ADC) Nyquist/high IF sampling TDA8769
Notes
1. Explanation tests:
a) D = guaranteed by design
b) C = guaranteed by characterization
c) I = industrially tested for 100%.
SFDR spurious free
dynamic range
TDA8769HW/6
fi= 21.4 MHz
B = Nyquist −77 −dBc
spurious free
dynamic range
TDA8769HW/8
fi= 21.4 MHz
B = Nyquist −77 −dBc
fi= 50 MHz
B = Nyquist −70 −dBc
B = 5 MHz −80.8 −dBc
spurious free
dynamic range
TDA8769HW/10
fi= 21.4 MHz
B = Nyquist −68 −dBc
fi= 78 MHz
B = Nyquist −67 −dBc
B = 5 MHz −84 −dBc
ENOB effective number
of bits
TDA8769HW/6
fi= 21.4 MHz; note 8
B = Nyquist −10.6 −bit
effective number
of bits
TDA8769HW/8
fi= 21.4 MHz; note 8
B = Nyquist −10.6 −bit
fi= 50 MHz; note 8
B = Nyquist −10.3 −bit
B = 5 MHz −11.7 −bit
effective number
of bits
TDA8769HW/10
fi= 21.4 MHz; note 8
B = Nyquist −10 −bit
fi= 78 MHz; note 8
B = Nyquist −9.6 −bit
B = 5 MHz −11.8 −bit
IM2 second order
intermodulation
distortion
fi1 = 15 MHz and
fi2 = 18 MHz; note 10
fclk= 80 Msps −(tbf) −dBFS
IM3 third order
intermodulation
distortion
fi1 = 15 MHz and
fi2 = 18 MHz; note 10
fclk= 80 Msps −82 −dBFS
BER bit error rate fi= 25 MHz;
VIN = 16LSB at code
2047; fclk = 105 Msps
−(tbf) −
SYMBOL PARAMETER CONDITIONS TEST(1) MIN. TYP. MAX. UNIT
2003 Dec 09 12
Philips Semiconductors Objective specification
12-bit, 60/80/105 Msps Analog-to-Digital Converter
(ADC) Nyquist/high IF sampling TDA8769
2. The circuit has two clock inputs: CLK and CLKN. There are 5 modes of operation:
a) PECL mode 1: (DC level varies proportionally with VCCD) CLK and CLKN inputs are at differential PECL levels.
b) PECL mode 2: (DC level varies proportionally with VCCD) CLK input is at PECL level and sampling is taken on
the falling edge of the clock input signal. A DC level of 3.65 V has to be applied on CLKN decoupled to GND via
a 100 nF capacitor.
c) PECL mode 3: (DC level varies proportionally with VCCD) CLKN input is at PECL level and sampling is taken on
the rising edge of the clock input signal. A DC level of 3.65 V has to be applied on CLK decoupled to GND via a
100 nF capacitor.
d) Differential AC driving mode 4: When driving the CLK input directly and with any AC signal of minimum 1 V (p-p)
and with a DC level of 2.5 V, the sampling takes place at the falling edge of the clock signal. When driving the
CLKN input with the same signal, sampling takes place at the rising edge of the clock signal. It is recommended
to decouple the CLKN or CLK input to DGND via a 100 nF capacitor.
e) TTL mode 5: CLK input is at TTL level and sampling is taken on the falling edge of the clock input signal. In that
case CLKN pin has to be connected to the ground.
3. The ADC input range can be adjusted with an external reference connected to pin VREF. This voltage has to be
referenced to VCCA.
4. Output data acquisition: the output data is available after the maximum delay of td(s).
5. The −3 dB analog bandwidth is determined by the 3 dB reduction in the reconstructed output, the input being a
full-scale sine wave.
6. The total harmonic distortion is obtained with the addition of the first five harmonics.
7. The signal-to-noise ratio takes into account all harmonics above five and noise up to Nyquist frequency.
8. The effective number of bits, or ENOB, are obtained via a Fast Fourier Transform (FFT). The calculation takes into
account all harmonics and noise up to half of the clock frequency (Nyquist frequency). Conversion to signal-to-noise
and distortion, or SINAD, is given by SINAD = ENOB ×6.02 + 1.76 dB.
9. Intermodulation measured relative to either tone with analog input frequencies of (tbf) and (tbf) MHz. The two input
signals have the same amplitude and the total amplitude of both signals provides full-scale input to the converter
(−6 dB below full-scale for each input signal).
10. IM2is theratio ofthe RMSvalue ofeither inputtone tothe RMSvalue of the worst case second order intermodulation
product. IM3 is the ratio of the RMS value of either input tone to the RMS value of the worst case third order
intermodulation product.
2003 Dec 09 13
Philips Semiconductors Objective specification
12-bit,60/80/105 MspsAnalog-to-DigitalConverter
(ADC) Nyquist/high IF sampling TDA8769
handbook, full pagewidth
VI
CKP
0.5 V
n
D0 to D11 VCCO − 0.5 V
50%
data
n − 1data
ndata
n + 1
td(o)
tds(i)
th(o)
MDB034
sample
nsample
n + 1 sample
n + 2 sample
n + 3 sample
n + 4
Fig.3 Output timing diagram.
handbook, full pagewidth
MBL874
D0 to D11
CCS
td(CCS)
Fig.4 Complete conversion signal timing diagram.
2003 Dec 09 14
Philips Semiconductors Objective specification
12-bit, 60/80/105 Msps Analog-to-Digital Converter
(ADC) Nyquist/high IF sampling TDA8769
11 APPLICATION INFORMATION
11.1 Output coding and control signals
Table 1 Output coding with differential inputs (typical values to AGND); VIN(p−p) −VINN(p−p) = 1.9 V −0.5 dBFS;
VVREF =V
CCA3 −1.75 V
Table 2 Mode selection
Table 3 Track-and-hold selection
Table 4 Complete conversion signal selection
11.2 TDA8769 in 3G radio receivers
TDA8769 has been proven in many 3G receivers with various operating conditions regarding input frequency, signal
input frequency bandwidth and sampling frequency. TDA8769 provides a maximum analog input frequency of 250 MHz.
It allows a significant cost reduction of the RF front-end, from two mixers to only one, even in multicarrier architecture.
Table 5 shows possible applications with the TDA8769 in High IF sampling mode.
CODE VIN(p-p) VINN(p-p) IR BINARY OUTPUTS
(D11 TO D0) TWO’S COMPLEMENT
OUTPUTS (D11 TO D0)
Underflow <2.925 >3.875 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0
0 2.925 3.875 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0
1−− 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1
::: : :
2047 3.4 3.4 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
::: : :
4094 −− 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 0
4095 3.875 2.925 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1
Overflow >3.875 <2.925 0 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1
CONTROL INPUT TWO’S
COMPLEMENT OUTPUT
(OTC)
CHIP ENABLE NOT
(CEN) OUTPUT DATA (D0 TO D11 AND IR)
0 0 binary; active
1 0 two’s complement; active
don’t care 1 high impedance
CONTROL INPUT TRACK-AND-HOLD (TH) MODE
1 active
0 inactive; tracking
DEL1 DEL0 OUTPUT SIGNAL
0 0 inactive
0 1 active (for timing values, see Chapter 10)
10
11
2003 Dec 09 15
Philips Semiconductors Objective specification
12-bit, 60/80/105 Msps Analog-to-Digital Converter
(ADC) Nyquist/high IF sampling TDA8769
Table 5 Examples of possible fi, fclk and fibandwidth combinations supported
For a dual carrier W_CDMA receiver, the most important parameters are the sensitivity and Adjacent Channel Selectivity
(ACS). In W-CDMA, it can be far below the noise floor, is defined by the Sensitivity to Noise Ratio (SENR). Its value is
negative due to the gain processing. The Adjacent Channel Power Ratio (ACPR) is the difference between the peak and
noise floor. It represents the ratio of the adjacent channel power and the average power of the channel. The ACS is
defined by the sum of SENR and ACPR. Figure 5 illustrates the relation between these parameters.
On a typical application with the TDA8769 device, the ACS obtained is 80 dB with an ACPR of 70 dB and a SENR of
10 dB. Moreover, the Noise Figure (NF) of the TDA8769 is 31.5 dB.
fi (MHz) fclk (MHz) fiBW (MHz) SNR (dB) SFDR (dBc)
250 9.60 0.20 66.5 79.9
243.95 9.60 0.20 62.6 68.5
243.95 19.20 0.20 68.4 77.2
243.95 52.00 0.20 65.7 80.0
190 40.00 1.25 72.0 80.0
106 76.80 5.00 70.8 83.6
86 76.80 5.00 72.2 87.1
80 61.44 10.00 (tbf) (tbf)
70 40.00 5.00 70 70
69.99 58.98 1.25 (tbf) (tbf)
27 51.2 3.5 (tbf) (tbf)
10.8 32.5 0.30 84.3 83.0
handbook, full pagewidth
MBL875
ACPR
NF
interfering
channel wanted
channel
ACS
noise floor
sensitivity
thermal noise
SENR
Fig.5 Adjacent channel selectivity and analog-to-digital converter sensitivity.
2003 Dec 09 16
Philips Semiconductors Objective specification
12-bit, 60/80/105 Msps Analog-to-Digital Converter
(ADC) Nyquist/high IF sampling TDA8769
11.3 Application diagrams
MDB035
Q
Q
D
TTL
270 Ω270 Ω
50 Ω
TDA8769
CLKNCLK
Fig.6 TTL to PECL translator application.
MDB036
TDA8769
CLKNCLK
TTL
Fig.7 TTL single-ended clock application.
2003 Dec 09 17
Philips Semiconductors Objective specification
12-bit, 60/80/105 Msps Analog-to-Digital Converter
(ADC) Nyquist/high IF sampling TDA8769
Fig.8 Application diagram.
tbf
2003 Dec 09 18
Philips Semiconductors Objective specification
12-bit, 60/80/105 Msps Analog-to-Digital Converter
(ADC) Nyquist/high IF sampling TDA8769
11.4 Demonstration board
handbook, full pagewidth
MBL876
2
1
3
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A19
A18
A20
A21
A22
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B19
B18
B20
B21
B22
J1
36
TDA8769HW
35
CCS
VCCO
34 D0
33 D1
32 D2
31 D3
30 D4
29 D5
28 D6
27 D7
26 D8
25 D9
37
OGND
38
CLKN
39
CLK
40
VCCD1
41
DGND1
42
TH
43
AGND4
44
VCCA4
45
n.c.
46
IN
47
INN
48
AGND1
4
AGND3
5
DEC
6
n.c.
7
n.c.
8
n.c.
9
n.c.
10
n.c.
11
VREF
12
n.c.
242322212019181716151413
D10
D11
IR
n.c.
CEN
OTC
DGND2
VCCD2
DEL0
DEL1
n.c.
FSREF
IC1
VCCA (44)
C2
330
nF
C3
100
nF
FL1
470D_0D0_S
C18
10
nF
(2/3)
C19
10
nF
VCCD1 (40)
C13
330
nF
C15
100
nF
FL3
470D_0D0_S
C17
10
nF
VCCD2 (17)
C11
330
nF
C6
100
nF
FL2
470D_0D0_S
FL4
HF70A08S
C20
10
nF TM2
TM3
OUTOUT
ADJ
IN 32
1
VCCO (35)
C10
1µF
C16
10
nF
LM317D2T
GND
IN 13
2
MC7805D2T
R8
R7 330
Ω
240
Ω
R6
750 Ω
TM1
C9
470
nF
D2
PWR
LGT679_C0
C8
4.7
µF
16 V
C7
22
µF
20 V
D1
BYD17G
J5 112 V
J5 2GND
MSTBA2.5_20_5D8 IC3
IC2
D0
CSS
PCN12A_44P_2.54DS
S4
VCCD2
ON
DEL1
S8
VCCD2
ON
DEL0
VCCD2
S6
1K2
VCCD2
ON
OTC
S7
1K2
VCCD2
OFF
CEN
R125680
J3 TRIG
R9
50 Ω
VCCO
C12
10
nF
VCC GND
2
35
4
IC4
R10
150 Ω
VCCO
IR
D3
LS6T670
R11
150 Ω14
23
74AHC1GUO4GW
R125680
J2
R2
50 Ω
VCCD1
ON
1K2 TH
S1
VCCA
S3
EXT 1K2
VCCA
R4
2.4 kΩ
P2
1 kΩ
R5
1.2 kΩ
C5
100 nF
C1
220 nF
VCCA
VCCA
1
2
CMADC
VCCA1
3
VCCA3
C4
100
nF
VCCA
TB2
S2
EXT 1K2
VCCA
P1
5 kΩ
CMADC
C14
330
nF
TB1 VCCA R3
100 Ω
R1
100 Ω
TR1
T1_6T_KK81
IN
R125680
J1
CLK
4
6
5
50 Ω
AGND
AGND
AGND AGND AGND DGND
VCCD1
DGND
DGND
DGND
AGND
AGND AGND
DGND
VCCO
AGND
DGND
AGND
AGND
AGND
DGND DGND DGND
DGND DGND
DGND DGND
DGND DGND
DGND
TP1
DGND
DGND
DGND DGND
AGNDDGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND DGND
DGND
AGND
AGND AGND
Fig.9 Demonstration board schematic.
2003 Dec 09 19
Philips Semiconductors Objective specification
12-bit, 60/80/105 Msps Analog-to-Digital Converter
(ADC) Nyquist/high IF sampling TDA8769
MBL877
R2
TM2
C1
J1
S1
S2
P1
1TB1
R1
TR1
IC1
R3
C3
C2
FL1
IC2
J5
21
D1
C7
TM3
J3
TM1
R5
D2 R6
C8
IC3
C10
TP1 C11
C12
R11
R10
P2
R7
R8
C9
C5
R4
D3
FL2
S3 S4
S5
S6
S7
R9
TB2
J4
J2
C4
C5
1
Fig.10 Component placement, top view.
MBL878
IC4
C20
FL3
C13
C15
FL4
C18
C14
C19
C17
C16
Fig.11 Component placement, bottom view.
2003 Dec 09 20
Philips Semiconductors Objective specification
12-bit,60/80/105 MspsAnalog-to-DigitalConverter
(ADC) Nyquist/high IF sampling TDA8769
MBL879
Fig.12 Printed-circuit board tracks, layout 1.
MBL880
Fig.13 Printed-circuit board tracks, layout 2.
MBL881
Fig.14 Printed-circuit board tracks, layout 3.
2003 Dec 09 21
Philips Semiconductors Objective specification
12-bit,60/80/105 MspsAnalog-to-DigitalConverter
(ADC) Nyquist/high IF sampling TDA8769
11.5 Definitions
11.5.1 STATIC PARAMETERS
11.5.1.1 Integral non-linearity (INL)
INL is defined as the deviation of the transfer function from
a best fit straight line (linear regression computation). The
INL of code i is obtained from the following equation:
where:
i = code value
Vin = input voltage for code i
S = slope of the ideal straight line (code width).
11.5.1.2 Differential non-linearity (DNL)
DNL is the deviation in code width from the value of one
LSB. The DNL of code i is obtained from the following
equation:
where:
i=0to2
n−2
Vin = input voltage for code i
S = slope of the ideal straight line.
11.5.2 DYNAMIC PARAMETERS
Figure 15 shows the spectrum of a single tone full-scale
input sine wave with frequency ft, conforming to coherent
sampling and digitized by the ADC under test. Coherent
sampling means that , where M is the number of
cycles, N the number of samples and both M and N being
a relative prime.
Remark: The parameter Pnoise used in the following
equations includes the power of the random noise,
non-linearities, sampling time errors and quantization
noise.
INL i() Vin i() Vin ideal()–S
----------------------------------------------
=
DNL i() Vin i1+()Vin i()–
S
---------------------------------------------
=
ft
fs
----M
N
-----
=
handbook, full pagewidth
MBL882
0
0
measured output range (MHz)
2.5
magnitude
−20
−40
−60
−80
−100
−120
−160 5 7.5 10 12.5 15 17.5 20 22.5 25 27
−140
IMD3
Fig.15 Spectrum of a full-scale input sine wave with frequency ft.
2003 Dec 09 22
Philips Semiconductors Objective specification
12-bit, 60/80/105 Msps Analog-to-Digital Converter
(ADC) Nyquist/high IF sampling TDA8769
11.5.2.1 Signal-to-noise and distortion (SINAD)
SINAD is the ratio of the signal power to the noise plus
distortion power, excluding the DC component, at a given
sample rate and input frequency:
dB.
11.5.2.2 Effective number of bits (ENOB)
ENOB is derived from SINAD and gives the theoretical
resolution an ideal ADC would require to obtain the same
SINAD measured on the actual ADC. A good
approximation is:
11.5.2.3 Total harmonic distortion (THD)
THDis theratio of thepower ofthe harmonics tothe power
of the signal frequency. The equation for k −1 harmonics
is:
dB
where:
As usual the value of k = 6 (i.e. the calculation of THD is
done with the first 5 harmonics).
11.5.2.4 Signal-to-noise ratio (SNR)
SNR is the ratio of the signal power to the noise power,
excluding the harmonics and DC component of the signal:
dB
11.5.2.5 Spurious free dynamic range (SFDR)
The SFDR specifies the available signal range as the
spectral distance between the amplitude of the
fundamental and the amplitude of the largest spurious
signal, harmonic and non-harmonic, excluding the
DC component.
dB
11.5.2.6 Intermodulation distortion (IMD2 and IMD3)
Figure 16 shows the spectral analysis of a dual tone sine
wave input, at frequencies ft1 and ft2, meeting the
coherence criterion.
The2nd and3rd orderintermodulation distortionproducts,
IMD2 and IMD3 respectively, are defined with a dual tone
input. IMD2 is defined as the ratio of the RMS value of
either tone to the RMS value of the second order
intermodulation product, IMD3 with the third order
intermodulation product. The IMD is given by:
dB
SINAD 10log10 Psignal
Pnoise + distortion
--------------------------------------
=
ENOB SINAD 1.76–
6.02
-------------------------------------
=
THD 10log10 Pharmonics
Psignal
-------------------------
=
Pharmonics a22a32... ak2
+++=
Psignal a12
=
SNR 10log10 Psignal
Pnoise
----------------
=
SFDR 10log10 a1
max s()
--------------------
=
IMD 10log10 Pintermod
Psignal
---------------------
=
2003 Dec 09 23
Philips Semiconductors Objective specification
12-bit, 60/80/105 Msps Analog-to-Digital Converter
(ADC) Nyquist/high IF sampling TDA8769
where:
.
is the power of the intermodulation component at ft.
Pintermod a2im ft1 ft2–()
a2im ft1 ft2+()
–a2im ft1 2ft2–()
a2im ft1 2ft2+()
…a2im 2ft1 ft2–()
a2im f2t1 ft2+()
+++++=
Psignal a2ft1 a2ft2
+=
a2im ft()
handbook, full pagewidth
MBL883
measured output range (MHz)
magnitude SFDR
a2a3ak
a1
Fig.16 Spectral analysis with dual tone.
2003 Dec 09 24
Philips Semiconductors Objective specification
12-bit, 60/80/105 Msps Analog-to-Digital Converter
(ADC) Nyquist/high IF sampling TDA8769
12 PACKAGE OUTLINE
UNIT A
max. A1A2A3bpHDHELpZD
(1)
ZE
(1)
ceLywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 1.2 0.15
0.05 1.05
0.95 0.25 0.27
0.17 0.20
0.09 7.1
6.9 0.5 9.1
8.9 0.89
0.61 7°
0°
0.08 0.080.21
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
0.75
0.45
SOT545-2 99-08-04
03-04-07
D
(1)
E
(1)
7.1
6.9 9.1
8.9
DhEh
4.6
4.4
4.6
4.4 0.89
0.61
b
p
e
θ
EA
1
A
L
p
detail X
L
B
121
48
37
D
H
b
p
E
HA
2
v
M
B
D
ZD
A
c
ZE
e
v
M
A
X
2536
24
13
y
pin 1 index
w
M
w
M
0 2.5 5 mm
scale
HTQFP48: plastic thermal enhanced thin quad flat package; 48 leads;
body 7 x 7 x 1 mm; exposed die pad SOT545-2
Dh
Eh
exposed die pad side
(A )
3
2003 Dec 09 25
Philips Semiconductors Objective specification
12-bit, 60/80/105 Msps Analog-to-Digital Converter
(ADC) Nyquist/high IF sampling TDA8769
13 SOLDERING
13.1 Introduction to soldering surface mount
packages
Thistextgivesa very briefinsighttoacomplex technology.
A more in-depth account of soldering ICs can be found in
our
“Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering can still be used for
certainsurfacemountICs,butit is not suitableforfinepitch
SMDs. In these situations reflow soldering is
recommended.
13.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
tothe printed-circuit boardby screenprinting,stencilling or
pressure-syringe dispensing before package placement.
Driven by legislation and environmental forces the
worldwide use of lead-free solder pastes is increasing.
Several methods exist for reflowing; for example,
convection or convection/infrared heating in a conveyor
type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending
on heating method.
Typical reflow peak temperatures range from
215 to 270 °C depending on solder paste material. The
top-surface temperature of the packages should
preferably be kept:
•below 225 °C (SnPb process) or below 245 °C (Pb-free
process)
– for all BGA, HTSSON-T and SSOP-T packages
– for packages with a thickness ≥2.5 mm
– for packages with a thickness < 2.5 mm and a
volume ≥350 mm3 so called thick/large packages.
•below 240 °C (SnPb process) or below 260 °C (Pb-free
process) for packages with a thickness < 2.5 mm and a
volume < 350 mm3 so called small/thin packages.
Moisture sensitivity precautions, as indicated on packing,
must be respected at all times.
13.3 Wave soldering
Conventional single wave soldering is not recommended
forsurfacemountdevices(SMDs)or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
To overcome these problems the double-wave soldering
method was specifically developed.
If wave soldering is used the following conditions must be
observed for optimal results:
•Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
•For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The footprint must incorporate solder thieves at the
downstream end.
•Forpackageswithleadsonfour sides, the footprintmust
be placed at a 45°angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical dwell time of the leads in the wave ranges from
3 to 4 seconds at 250 °C or 265 °C, depending on solder
material applied, SnPb or Pb-free respectively.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
13.4 Manual soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
2003 Dec 09 26
Philips Semiconductors Objective specification
12-bit, 60/80/105 Msps Analog-to-Digital Converter
(ADC) Nyquist/high IF sampling TDA8769
13.5 Suitability of surface mount IC packages for wave and reflow soldering methods
Notes
1. Formore detailed informationonthe BGApackagesrefer tothe
“(LF)BGAApplication Note
”(AN01026); order acopy
from your Philips Semiconductors sales office.
2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the
“Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”
.
3. These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account
be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature
exceeding 217 °C±10 °C measured in the atmosphere of the reflow oven. The package body peak temperature
must be kept as low as possible.
4. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder
cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side,
the solder might be deposited on the heatsink surface.
5. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
6. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not
suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
7. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than
0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
8. Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted
on flex foil. However, the image sensor package can be mounted by the client on a flex foil by using a hot bar
soldering process. The appropriate soldering profile can be provided on request.
9. Hot bar or manual soldering is suitable for PMFP packages.
PACKAGE(1) SOLDERING METHOD
WAVE REFLOW(2)
BGA, HTSSON..T(3), LBGA, LFBGA, SQFP, SSOP..T(3), TFBGA,
USON, VFBGA not suitable suitable
DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON,
HTQFP, HTSSOP, HVQFN, HVSON, SMS not suitable(4) suitable
PLCC(5), SO, SOJ suitable suitable
LQFP, QFP, TQFP not recommended(5)(6) suitable
SSOP, TSSOP, VSO, VSSOP not recommended(7) suitable
CWQCCN..L(8), PMFP(9), WQCCN..L(8) not suitable not suitable
2003 Dec 09 27
Philips Semiconductors Objective specification
12-bit,60/80/105 MspsAnalog-to-DigitalConverter
(ADC) Nyquist/high IF sampling TDA8769
14 DATA SHEET STATUS
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
LEVEL DATA SHEET
STATUS(1) PRODUCT
STATUS(2)(3) DEFINITION
I Objective data Development This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
II Preliminary data Qualification This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
III Product data Production This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Relevant changes will
be communicated via a Customer Product/Process Change Notification
(CPCN).
15 DEFINITIONS
Short-form specification The data in a short-form
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
Limiting values definition Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
attheseor at anyotherconditionsabove thosegiveninthe
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Application information Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
norepresentationorwarrantythatsuchapplicationswillbe
suitable for the specified use without further testing or
modification.
16 DISCLAIMERS
Life support applications These products are not
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductorscustomersusingorsellingtheseproducts
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Right to make changes Philips Semiconductors
reserves the right to make changes in the products -
including circuits, standard cells, and/or software -
described or contained herein in order to improve design
and/or performance. When the product is in full production
(status ‘Production’), relevant changes will be
communicated via a Customer Product/Process Change
Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these
products, conveys no licence or title under any patent,
copyright, or mask work right to these products, and
makes no representations or warranties that these
products are free from patent, copyright, or mask work
right infringement, unless otherwise specified.
© Koninklijke Philips Electronics N.V. 2003 SCA75
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Philips Semiconductors – a w orldwide compan y
Contact information
For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
Printed in The Netherlands R78/02/pp28 Date of release: 2003 Dec 09 Document order number: 9397 750 11706
