Dual Channel Line Receiver
Hermetically Sealed
Optocoupler
Technical Data HCPL-1930
HCPL-1931
HCPL-193K
5962-89572
CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to
prevent damage and/or degradation which may be induced by ESD.
Description
The HCPL-193X devices are dual
channel, hermetically sealed,
high CMR, line receiver optocoup-
lers. The products are capable of
operation and storage over the
full military temperature range
and can be purchased as either a
standard product or with full
MIL-PRF-38534 Class Level H or
K testing, or from the DSCC
Standard Microcircuit Drawing
(SMD) 5962-89572. This is a
sixteen pin DIP which may be
purchased with a variety of lead
bend and plating options. See
selection guide table for details.
Standard Microcircuit Drawing
(SMD) parts are available for each
lead style.
Functional DiagramTruth Table
Features
• Dual Marked with Device
Part Number and DSCC
Standard Microcircuit
Drawing
• Manufactured and Tested on
a MIL-PRF-38534 Certified
Line
• QML-38534, Class H and
Class K
• Hermetically Sealed 16-pin
Dual In-Line Package
• Performance Guaranteed
Over -55°C to +125°C
• High Speed – 10 Mb/s
• Accepts a Broad Range of
Drive Conditions
• Adaptive Line Termination
Included
• Internal Shield Provides
Excellent Common Mode
Rejection
• External Base Lead Allows
"LED Peaking" and LED
Current Adjustment
• 1500 Vdc Withstand Test
Voltage
• High Radiation Immunity
• HCPL-2602 Function
Compatibility
• Reliability Data Available
Applications
• Military and Space
• High Reliability Systems
• Isolated Line Receiver
• Simplex/Multiplex Data
Transmission
• Computer-Peripheral
Interface
• Microprocessor System
Interface
• Harsh Environmental
Environments
• Digital Isolation for A/D,
D/A Conversion
• Current Sensing
• Instrument Input/Output
Isolation
• Ground Loop Elimination
• Pulse Transformer
Replacement
The connection of a 0.1
µ
F bypass capacitor between pins 15 and 10 is recommended.
2
DC specifications are compatible
with TTL logic and are guaranteed
from -55°C to +125°C allowing
trouble-free interfacing with
digital logic circuits. An input
current of 10 mA will sink a six
gate fan-out (TTL) at the output
with a typical propagation delay
from input to output of only
45 nsec.
All devices are manufactured and
tested on a MIL-PRF-38534
certified line and are included in
the DSCC Qualified Manufac-
turers List QML-38534 for Hybrid
Microcircuits.
Each unit contains two indepen-
dent channels, consisting of a
GaAsP light emitting diode, an
input current regulator, and an
integrated high gain photon
detector. The input regulator
serves as a line termination for
line receiver applications. It
clamps the line voltage and
regulates the LED current so line
reflections do not interfere with
circuit performance. The regulator
allows a typical LED current of
12.5 mA before it starts to shunt
excess current. The output of the
detector IC is an open collector
Schottky clamped transistor. An
enable input gates the detector.
The internal detector shield
provides a guaranteed common
mode transient immunity specifi-
cation of +1000 V/µsec.
Selection Guide–Package Styles and Lead
Configuration Options
Agilent Part # and Options
Commercial HCPL-1930
MIL-PRF-38534 Class H HCPL-1931
MIL-PRF-38534 Class K HCPL-193K
Standard Lead Finish Gold
Solder Dipped Option #200
Butt Joint/Gold Plate Option #100
Gull Wing/Soldered Option #300
Crew Cut/Gold Plate Option #600
Class H SMD Part #
Prescript for all below 5962-
Either Gold or Soldered 8957201EX
Gold Plate 8957201EC
Solder Dipped 8957201EA
Butt Joint/Gold Plate 8957201YC
Butt Joint/Soldered 8957201YA
Gull Wing/Soldered 8957201XA
Crew Cut/Gold Plate Available
Crew Cut/Soldered Available
Class K SMD Part #
Prescript for all below 5962-
Either Gold or Soldered 8957202KEX
Gold Plate 8957202KEC
Solder Dipped 8957202KEA
Butt Joint/Gold Plate 8957202KYC
Butt Joint/Soldered 8957202KYA
Gull Wing/Soldered 8957202KXA
3
Outline Drawings
16 Pin DIP Through Hole, 2 Channels
Device Marking
4.45 (0.175)
MAX.
20.06 (0.790)
20.83 (0.820)
0.51 (0.020)
MAX.
2.29 (0.090)
2.79 (0.110)
0.51 (0.020)
MIN.
0.89 (0.035)
1.65 (0.065)
8.13 (0.320)
MAX.
7.36 (0.290)
7.87 (0.310)
0.20 (0.008)
0.33 (0.013)
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
3.81 (0.150)
MIN.
COMPLIANCE INDICATOR,*
DATE CODE, SUFFIX (IF NEEDED)
A QYYWWZ
XXXXXX
XXXXXXX
XXX XXX
50434 COUNTRY OF MFR.
Agilent CAGE CODE*
Agilent DESIGNATOR
DSCC SMD*
PIN ONE/
ESD IDENT
Agilent P/N
DSCC SMD*
* QUALIFIED PARTS ONLY
4
Option Description
Hermetic Optocoupler Options
100 Surface mountable hermetic optocoupler with leads trimmed for butt joint assembly. This option
is available on commercial and hi-rel product.
200 Lead finish is solder dipped rather than gold plated. This option is available on commercial and
hi-rel product. DSCC Drawing part numbers contain provisions for lead finish.
300 Surface mountable hermetic optocoupler with leads cut and bent for gull wing assembly. This
option is available on commercial and hi-rel product. This option has solder dipped leads.
600 Surface mountable hermetic optocoupler with leads trimmed for butt joint assembly. This option
is available on commercial and hi-rel product. Contact factory for the availability of this option
on DSCC part types.
Note: Dimensions in millimeters (inches).
3.81 (0.150)
MIN.
1.14 (0.045)
1.25 (0.049)
2.29 (0.090)
2.79 (0.110)
0.51 (0.020)
MIN. 7.36 (0.290)
7.87 (0.310)
0.20 (0.008)
0.33 (0.013)
1.14 (0.045)
1.40 (0.055)
4.32 (0.170)
MAX.
0.51 (0.020)
MAX.
2.29 (0.090)
2.79 (0.110)
0.51 (0.020)
MIN. 7.36 (0.290)
7.87 (0.310)
0.20 (0.008)
0.33 (0.013)
1.40 (0.055)
1.65 (0.065)
4.57 (0.180)
MAX.
0.51 (0.020)
MAX.
2.29 (0.090)
2.79 (0.110)
0.51 (0.020)
MIN. 9.65 (0.380)
9.91 (0.390)
0.20 (0.008)
0.33 (0.013)
5° MAX.
4.57 (0.180)
MAX.
5
Absolute Maximum Ratings
Storage Temperature ................................................. -65°C to +150°C
Operating Temperature ............................................... -55°C to +125°C
Lead Solder Temperature ................................................ 260°C for 10 s
1.6 mm below seating plane
Forward Input Current – II (each channel) ................................. 60 mA2
Reverse Input Current ................................................................. 60 mA
Supply Voltage – VCC .......................................7 V (1 Minute Maximum)
Enable Input Voltage – VE (each channel) ......................................5.5 V
Not to exceed VCC by more than 500 mV
Output Collector Current – IO (each channel) ............................. 25 mA
Output Collector Power Dissipation (each channel) ................... 40 mW
Output Collector Voltage – VO (each channel) ...................................7 V
Total Package Power Dissipation ..............................................564 mW
Input Power Dissipation (each channel)................................... 168 mW
Parameter Symbol Min. Max. Units
Input Current, Low Level IIL 0 250 µA
Input Current, High Level* IIH 12.5 60 mA
Supply Voltage, Output VCC 4.5 5.5 V
High Level Enable Voltage VEH 2.0 VCC V
Low Level Enable Voltage VEL 0 0.8 V
Fan Out (@ RL = 4 kΩ) N 5 TTL
Loads
Operating Temperature TA-55 125 °C
*12.5 mA condition permits at least 20% guardband for optical coupling variation. Initial
switching threshold is 10 mA or less.
Recommended Operating Conditions
ESD Classification
(MIL-STD-883, Method 3015) .............................................. (∆), Class 1
Schematic
A 0.1 µF BYPASS CAPACITOR
MUST BE CONNECTED BETWEEN
PINS 10 AND 15 (SEE NOTE 1).
6
Group A Limits
Sub-
Parameter Symbol Test Conditions groups Min. Typ.* Max. Units Fig. Note
High Level Output IOH VCC = 5.5 V, VO = 5.5 V 1, 2, 3 20 250 µA3 3
Current II = 250 µA, VE = 2.0 V
Low Level VOL VCC = 5.5 V; II = 10 mA
Output Voltage VE = 2.0 V, 1, 2, 3 0.3 0.6 V 1 3
IOL (Sinking) = 10 mA
II = 10 mA 2.2 2.6
Input Voltage VI1, 2, 3 V 2 3
II = 60 mA 2.35 2.75
Input Reverse VRIR = 10 mA 1, 2, 3 0.8 1.10 V 3
Voltage
Low Level Enable IEL VCC = 5.5 V, VE = 0.5 V 1, 2, 3 -1.45 -2.0 mA 3
Current
High Level Enable VEH 1, 2, 3 2.0 V 3, 12
Voltage
Low Level Enable VEL 1, 2, 3 0.8 V 3
Voltage
High Level ICCH VCC = 5.5 V; II = 0, 1, 2, 3 21 28 mA
Supply Current VE = 0.5 V both channels
Low Level ICCL VCC = 5.5 V; II = 60 mA, 1, 2, 3 27 36 mA
Supply Current VE = 0.5 V both channels
Input-Output Relative Humidity = 45%
Insulation II-O t = 5 s, 1 1 µA4
Leakage Current VI-O = 1500 Vdc
Propagation Delay 9 55 100
Time to High tPLH RL = 510 Ω; CL = 50 pF, ns 4, 5 3, 5
Output Level II = 13 mA,VCC = 5.0 V 10, 11 140
Propagation Delay 9 60 100
Time to Low tPHL RL = 510 Ω; CL = 50 pF, ns 4, 5 3, 6
Output Level II = 13 mA, VCC = 5.0 V 10, 11 120
Common Mode VCM = 50 V (peak),
Transient |CMH|V
O
(min.) = 2 V, 9, 10, 11 1000 10,000 V/µs 8, 9 3, 9,
Immunity at RL = 510 Ω; II = 0 mA, 14
High Output Level VCC = 5.0 V
Common Mode VCM = 50 V (peak),
Transient |CML|V
O
(max.) = 0.8 V, 9, 10, 11 1000 10,000 V/µs 8, 9 3, 10,
Immunity at RL = 510 Ω; II = 10 mA, 14
Low Output Level VCC = 5.0 V
*All typical values are at VCC = 5 V, TA = 25°C.
Electrical Specifications TA = -55°C to 125°C unless otherwise stated. See note 15.
7
Parameter Symbol Typ. Units Test Conditions Fig. Note
Resistance (Input-Output) RI-O 1012 ΩVI-O = 500 V dc 3, 13
Capacitance (Input-Output) CI-O 1.7 pF f = 1 MHz 3, 13
Input-Input Insulation II-I 0.5 nA 45% Relative Humidity, 11
Leakage Current VI-I = 500 Vdc, t = 5 s
Resistance (Input-Input) RI-I 1012 ΩVI-I = 500 Vdc 11
Capacitance (Input-Input) CI-I 0.55 pF f = 1 MHz 11
Propagation Delay Time of Enable tELH 35 ns 6, 7 3, 7
from VEH to VEL RL = 510 Ω, CL = 15 pF,
Propagation Delay Time of Enable tEHL 35 ns II = 13 mA, VEH = 3 V, VEL = 0 V 6, 7 3, 8
from VEL to VEH
Output Rise Time (10-90%) tr30 ns 3
RL = 510 Ω, CL = 15 pF, II = 13 mA
Output Fall Time (90-10%) tf24 ns 3
Input Capacitance CI60 pF f = 1 MHz, VI = 0, 3
PINS 1 to 2 or 5 to 6
Typical Specifications
TA = 25°C, VCC = 5 V
Notes:
1. Bypassing of the power supply line is required, with a 0.1 µF ceramic disc capacitor adjacent to each isolator. The power supply bus
for the isolators should be separate from the bus for any active loads, otherwise additional bypass capacitance may be needed to
suppress regenerative feedback via the power supply.
2. Derate linearly at 1.2 mA/°C above TA = 100°C.
3. Each channel.
4. Device considered a two terminal device: pins 1 through 8 are shorted together, and pins 9 through 16 are shorted together.
5. The tPLH propagation delay is measured form the 6.5 mA point on the trailing edge of the input pulse to the 1.5 V point on the trailing
edge of the output pulse.
6. The tPHL propagation delay is measured from the 6.5 mA point on the leading edge of the input pulse to the 1.5 V point on the leading
edge of the output pulse.
7. The tELH enable propagation delay is measured from the 1.5 V point on the trailing edge of the enable input pulse to the 1.5 V point
on the trailing edge of the output pulse.
8. The tEHL enable propagation delay is measured from the 1.5 V point on the leading edge of the enable input pulse to the 1.5 V point
on the leading edge of the output pulse.
9. CMH is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state, i.e.
VOUT > 2.0 V.
10. CML is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state, i.e.
VOUT < 0.8 V.
11. Measured between adjacent input leads shorted together, i.e. between 1, 2 and 4 shorted together and pins 5, 6 and 8 shorted
together.
12. No external pull up is required for a high logic state on the enable input.
13. Measured between pins 1 and 2 or 5 and 6 shorted together, and pins 10 through 15 shorted together.
14. Parameters shall be tested as part of device initial characterization and after process changes. Parameters shall be guaranteed to the
limits specified for all lots not specifically tested.
15. Standard parts receive 100% testing at 25°C (Subgroups 1 and 9). Hi-Rel and SMD parts receive 100% testing at 25, 125, and -55°C
(Subgroups 1 and 9, 2 and 10, 3 and 11, respectively).
8
Figure 3. High Level Output Current
vs. Temperature.
Figure 2. Input Characteristics.
Figure 1. Input-Output
Characteristics.
Figure 4. Propagation Delay vs.
Temperature. Figure 5. Test Circuit for tPHL and tPLH.
Figure 6. Enable Propagation Delay vs.
Temperature. Figure 7. Test Circuit for tEHL and tELH.
9
1
3
2
4510 Ω
5
6
7
8
16
14
15
13
12
11
10
9
GND
V
CC
5 V
OUTPUT V
O
MONITORING
NODE
0.01 µF
BYPASS
V
CM
PULSE GEN.
–+
V
IN
I
IN
A
B
Figure 10. Burn In Circuit.
100 Ω
100 Ω
200 Ω
200 Ω
V
IN
+5.0 V
0.01 µF
V
CC
+5.5 V V
OUT
+2.6 V
T
A
= +125 °C
–
+
CONDITIONS: I
I
= 30 mA
I
O
= 10 mA
V
CC
= 5.5 V
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Figure 9. Test Circuit for Common
Mode Transient Immunity and Typical
Waveforms.
Figure 8. Typical Common Mode
Transient Immunity.
10
Application Circuits*
Figure A1. Polarity Non-Reversing.
Figure A2. Polarity Reversing, Split Phase.
HCPL-193X
HCPL-193X
11
MIL-PRF-38534 Class H,
Class K, and DSCC SMD
Test Program
Agilent Technologies’ Hi-Rel
Optocouplers are in compliance
with MIL-PRF-38534 Class H and
K. Class H and Class K devices
are also in compliance with DSCC
drawing 5962-89572.
Testing consists of 100% screen-
ing and quality conformance
inspection to MIL-PRF-38534.
Figure A3. Flop-Flop Configurations.
www.semiconductor.agilent.com
Data subject to change.
Copyright © 2000 Agilent Technologies
Obsoletes 5967-5809E
5968-9401E (4/00)
