K7D163674BHC33000 - SAMSUNG - Datasheet.Directory

Rev 1.1

512Kx36 & 1Mx18 SRAM

- 1 - Jan. 2005

K7D161874B

K7D163674B

Document Title

16M DDR SYNCHRONOUS SRAM

Revision History

The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the

right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters

of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or cortact Headquarters.

Rev No.

Rev. 0.0

Rev. 0.1

Rev. 0.2

Rev. 0.3

Rev. 1.0

Rev. 1.1

Remark

Advance

Preliminary

Final

History

Initial document.

Change JTAG DC OPERATING CONDITONS/AC TEST CONDITIONS

-to support 1.8~2.5V VDD, change some items.

Change DC CHARACTERISTICS (Stop Clock Standby Current)

-ISB1 : 100 -> 150

Change JTAG Instruction Cording

- For Reserved

Change DC CHARACTERISTICS (Increase Operating Current)

- x36 : add 40mA, x18 : add 60mA

Add DC CHARACTERISTICS

- VIN-CLK, VDIF-CLK, VCM-CLK

Add AC INPUT CHARACTERISTICS

Add INPUT DEFINITION

Draft Data

Oct. 2003

Nov. 2003

Feb. 2004

Mar. 2004

Jan. 2004

Rev 1.1

512Kx36 & 1Mx18 SRAM

- 2 - Jan. 2005

K7D161874B

K7D163674B

ORDERING INFORMATION

Part Number Organization Maximum

Frequency

K7D163674B-HC37

512Kx36

375MHz

K7D163674B-HC33 333MHz

K7D163674B-HC30 300MHz

K7D163674B-HC27 275MHz

K7D161874B-HC37

1Mx18

375MHz

K7D161874B-HC33 333MHz

K7D161874B-HC30 300MHz

K7D161874B-HC27 275MHz

GENERAL DESCRIPTION

The K7D163674B and K7D161874B are 18,874,368 bit Synchronous Pipeline Burst Mode SRAM devices. They are organized as

524,288 words by 36 bits for K7D163674B and 1,048,576 words by 18 bits for K7D161874B, fabricated using Samsung's advanced

CMOS technology.

Single differential HSTL level clock, K and K are used to initiate the read/write operation and all internal operations are self-timed. At

the rising edge of K clock, all addresses and burst control inputs are registered internally. Data inputs are registered one cycle after

write addresses are asserted(Late Write), at the rising edge of K clock for single data rate (SDR) write operations and at rising and

falling edge of K clock for a double data rate (DDR) write operations.

Data outputs are updated from output registers off the rising edges of K clock for SDR read operations and off the rising and falling

edges of K clock for DDR read operations. Free running echo clocks are supported which are representive of data output access

time for all SDR and DDR operations.

The chip is operated with a single +2.5V power supply and is compatible with Extended HSTL input and output. The package is

9x17(153) Ball Grid Array balls on a 1.27mm pitch.

FEATURES

• 512Kx36 or 1Mx18 Organizations.

• 1.8~2.5V VDD/1.5V VDDQ.(1.9V max VDDQ)

• HSTL Input and Outputs.

• Single Differential HSTL Clock.

• Synchronous Pipeline Mode of Operation with Self-Timed

Late Write.

• Free Running Active High and Active Low Echo Clock Output

Pin.

• Asynchronous Output Enable.

• Registered Addresses, Burst Control and Data Inputs.

• Registered Outputs.

• Double and Single Data Rate Burst Read and Write.

• Burst Count Controllable With Max Burst Length of 4

• Interleved and Linear Burst mode support

• Bypass Operation Support

• Programmable Impedance Output Drivers.

• JTAG Boundary Scan (subset of IEEE std. 1149.1)

• 153(9x17) Pin Ball Grid Array Package(14mmx22mm)

Rev 1.1

512Kx36 & 1Mx18 SRAM

- 3 - Jan. 2005

K7D161874B

K7D163674B

FUNCTIONAL BLOCK DIAGRAM

K,K

Memory Array

512Kx36

Data Out Data In

Advance

Control

SD/DD

Clock

Synchronous

Buffer

Internal

Clock

Generator

R/W

LD Data Output Strobe

Data Output Enable

State Machine

Strobe_out

S/A Array

2 : 1 MUX

Data In

Write Buffer

W/D

Array

Echo Clock

Output

36(or 18)x2

36(or18)x2

XDIN

CQ,CQ

36(or 18)

Select

R/W control

Output

Buffer

Write

Burst

Counter

Address

Comparator

2:1

MUX Dec.

19(or 20) 17(or 18)

17(or 18)19(or 20)

(Burst Write

SA[0:18]( or SA[0:19])

(1Mx18)

(2 stage)

(Burst Address)

Address)

PIN DESCRIPTION

Pin Name Pin Description Pin Name Pin Description

K, K Differential Clocks ZQ Output Driver Impedance Control Input

SA Synchronous Address Input TCK JTAG Test Clock

SA0, SA1 Synchronous Burst Address Input (SA0 = LSB) TMS JTAG Test Mode Select

DQ Synchronous Data I/O TDI JTAG Test Data Input

CQ, CQ Differential Output Echo Clocks TDO JTAG Test Data Output

B1 Load External Address VREF HSTL Input Reference Voltage

B2 Burst R/W Enable VDD Power Supply

B3 Single/Double Data Selection VDDQ Output Power Supply

G Asynchronous Output Enable VSS GND

LBO Linear Burst Order NC No Connection

Rev 1.1

512Kx36 & 1Mx18 SRAM

- 4 - Jan. 2005

K7D161874B

K7D163674B

PACKAGE PIN CONFIGURATIONS(TOP VIEW)

K7D163674B(512Kx36)

* Mode Pin(6L) is a internally NC.

123456789

AVSS VDDQ SA SA ZQ SA SA VDDQ VSS

BDQ DQ SA VSS B1VSS SA DQ DQ

CVSS VDDQ SA SA G SA SA VDDQ VSS

DDQ DQ SA VSS VDD VSS SA DQ DQ

EVSS VDDQ VSS VDD VREF VDD VSS VDDQ VSS

FDQ CQ1DQ VDD VDD VDD DQ CQ2DQ

GVSS VDDQ VSS VSS KVSS VSS VDDQ VSS

HDQ DQ DQ VDD K VDD DQ DQ DQ

JVSS VDDQ VSS VDD VDD VDD VSS VDDQ VSS

KDQ DQ DQ VSS B2VSS DQ DQ DQ

LVSS VDDQ VSS LBO B3MODE VSS VDDQ VSS

MDQ CQ1DQ VDD VDD VDD DQ CQ2DQ

NVSS VDDQ VSS VDD VREF VDD VSS VDDQ VSS

PDQ DQ NC VSS VDD VSS SA DQ DQ

RVSS VDDQ VDD SA SA1SA VDD VDDQ VSS

TDQ DQ SA VSS SA0VSS SA DQ DQ

UVSS VDDQ TMS TDI TCK TDO NC VDDQ VSS

K7D161874B(1Mx18)

* Mode Pin(6L)is a internally NC.

123456789

AVSS VDDQ SA SA ZQ SA SA VDDQ VSS

BNC DQ SA VSS B1VSS SA NC DQ

CVSS VDDQ SA SA G SA SA VDDQ VSS

DDQ NC SA VSS VDD VSS SA DQ NC

EVSS VDDQ VSS VDD VREF VDD VSS VDDQ VSS

FNC CQ1NC VDD VDD VDD DQ NC DQ

GVSS VDDQ VSS VSS KVSS VSS VDDQ VSS

HDQ NC DQ VDD K VDD NC DQ NC

JVSS VDDQ VSS VDD VDD VDD VSS VDDQ VSS

KNC DQ NC VSS B2VSS DQ NC DQ

LVSS VDDQ VSS LBO B3MODE VSS VDDQ VSS

MDQ NC DQ VDD VDD VDD NC CQ1NC

NVSS VDDQ VSS VDD VREF VDD VSS VDDQ VSS

PNC DQ SA VSS VDD VSS SA NC DQ

RVSS VDDQ VDD SA SA1SA VDD VDDQ VSS

TDQ NC SA VSS SA0VSS SA DQ NC

UVSS VDDQ TMS TDI TCK TDO NC VDDQ VSS

Rev 1.1

512Kx36 & 1Mx18 SRAM

- 5 - Jan. 2005

K7D161874B

K7D163674B

Read Operation(Single and Double)

During SDR read operations, addresses and controls are registered at the first rising edge of K clock and then the internal array is

read between first and second rising edges of K clock. Data outputs are updated from output registers off the second rising edge of

K clock. During DDR read operations, addresses and controls are registered at the first rising edge of K clock, and then the internal

array is read twice between first and second rising edges of K clock. Data outputs are updated from output registers sequentially by

burst order off the second rising and falling edge of K clock.

Interleave and linear burst operation is controlled by LBO pin and the burst count is controllable with the maximum burst length of 4.

To avoid data contention,at least one NOP operations are required between the last read and the first write operation.

Write Operation(Late Write)

During SDR write operations, addresses and controls are registered at the first rising edge of K clock and data inputs are registered

at the following rising edge of K clock. During DDR write operations, addresses and controls are registered at the first rising edge of

K clock and data inputs are registered twice at the following rising and falling edge of K clock. Write addresses and data inputs are

stored in the data in registers until the next write operation, and only at the next write opeation are data inputs fully written into SRAM

array.

Echo clock operation

Free running type of Echo clocks are generated from K clock regardless of read, write and NOP operations. They will stop operation

only when K clock is in the stop mode.

Echo clocks are designed to represent data output access time and this allows the echo clocks to be used as reference to capture

data outputs outputs.

Bypass Read Operation

Bypass read operation occurs when the last write operation is followed by a read operation where write and read addresses are

identical. For this case, data outputs are from the data in registers instead of SRAM array.

Programmable Impedance Output Driver

The data output and echo clock driver impedance are adjusted by an external resistor, RQ, connected between ZQ pin and VSS, and

are equal to RQ/5. For example, 250Ω resistor will give an output impedance of 50Ω. Output driver impedance tolerance is 15% by

test(10% by design) and is periodically readjusted to reflect the changes in supply voltage and temperature. Impedance updates

occur early in cycles that do not activate the outputs, such as deselect cycles. They may also occur in cycles initiated with G high. In

all cases impedance updates are transparent to the user and do not produce access time "push-outs" or other anomalous behavior

in the SRAM. Impedance updates occur no more often than every 32 clock cycles. Clock cycles are counted whether the SRAM is

selected or not and proceed regardless of the type of cycle being executed. Therefore, the user can be assured that after 33 contin-

uous read cycles have occurred, an impedance update will occur the next time G are high at a rising edge of the K clock. There are

no power up requirements for the SRAM. However, to guarantee optimum output driver impedance after power up, the SRAM needs

1024 non-read cycles.

Power-Up/Power-Down Supply Voltage Sequencing

The following power-up supply voltage application is recommended: VSS, VDD, VDDQ, VREF, then VIN. VDD and VDDQ can be applied

simultaneously, as long as VDDQ does not exceed VDD by more than 0.5V during power-up. The following power-down supply voltage

removal sequence is recommended: VIN, VREF, VDDQ, VDD, VSS. VDD and VDDQ can be removed simultaneously, as long as VDDQ

does not exceed VDD by more than 0.5V during power-down.

Rev 1.1

512Kx36 & 1Mx18 SRAM

- 6 - Jan. 2005

K7D161874B

K7D163674B

TRUTH TABLE

NOTE : - B(Both) is DIN in write cycle and DOUT in read cycle. Byte write function is not supported. X means "Don't Care".

- K & K are complementary.

K G B1 B2 B3 DQ Operation

LXXXXHi-Z Clock Stop

↑X H L X Hi-Z No Operation, Pipeline High-Z

↑L L H H DOUT Load Address, Single Read

↑L L H L DOUT Load Address, Double Read

↑X L L H DIN Load Address, Single Write

↑X L L L DIN Load Address, Double Write

↑X H H X B Increment Address, Continue

4 Burst Operation for Interleaved Burst (LBO = VDDQ)

NOTE : - For Interleave Burst LBO = VDDQ is recommended. If LBO = VDD, it must not exceed 2.63V.

Interleaved Burst Case 1 Case 2 Case 3 Case 4

A1A0A1A0A1A0A1A0

First Address

Fourth Address

BURST SEQUENCE TABLE

4 Burst Operation for Linear Burst (LBO = VSS)

Linear Burst Mode Case 1 Case 2 Case 3 Case 4

A1A0A1A0A1A0A1A0

First Address

Fourth Address

Rev 1.1

512Kx36 & 1Mx18 SRAM

- 7 - Jan. 2005

K7D161874B

K7D163674B

NOTE :

1. State transitions ; B1 =(Load Address), B1=(Increment Address, Continue)

B2 =(Read), B2 =(Write)

B3 =(Single Data Rate), B3 =(Double Data Rate)

BUS CYCLE STATE DIAGRAM

LOAD

NEW ADDRESS

INCREMENT

ADDRESS

INCREMENT

ADDRESS

INCREMENT

ADDRESS

INCREMENT

ADDRESS

READ

SDR

WRITE

SDR

READ

DDR

WRITE

DDR

, B

B1, B2

NO OP

POWER

, B

B1, B2

Rev 1.1

512Kx36 & 1Mx18 SRAM

- 8 - Jan. 2005

K7D161874B

K7D163674B

RECOMMENDED DC OPERATING CONDITIONS

NOTE :1. These are DC test criteria. DC design criteria is VREF±50mV. The AC VIH/VIL levels are defined separately for measuring

timing parameters.

2. VIH (Max)DC=VDDQ+0.3, VIH (Max)AC=2.6V (2.1V for DQs) (pulse width ≤ 20% of cycle time).

3. VIL (Min)DC=-0.3V, VIL (Min)AC=-1.0V (-0.5V for DQs) (pulse width ≤ 20% of cycle time).

4. VIN-CLK specifies the maximum allowable DC level for the differential clock. i.e VIL-CLK and VIH-CLK.

5. VDIF-CLK specifies the minimum Clock differential voltage required for switching. i.e DC voltage difference between VIL-CLK and VIH-CLK.

6. VCM-CLK specifies the Clock crossing point for the differential clock or the allowable common clock level for a single ended clock.

Parameter Symbol Min Typ Max Unit Note

Core Power Supply Voltage VDD 1.7 2.5 2.63 V

Output Power Supply Voltage VDDQ 1.4 1.5 1.9 V

Input High Level Voltage VIH VREF+0.1 - VDDQ+0.3 V 1, 2

Input Low Level Voltage VIL -0.3 - VREF-0.1 V 1, 3

Input Reference Voltage VREF 0.68 0.75 0.95 V

Clock Input Signal Voltage VIN-CLK -0.3 - VDDQ+0.3 V 1, 4

Clock Input Differential Voltage VDIF-CLK 0.1 - VDDQ+0.6 V 1, 5

Clock Input Common Mode Voltage VCM-CLK 0.68 0.75 0.9 V 1, 6

ABSOLUTE MAXIMUM RATINGS

NOTE : Power Dissipation Capability will be dependent upon package characteristics and use environment. See enclosed thermal impedance data.

Stresses greater than those listed under " Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only

and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not

implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Parameter Symbol Value Unit

Core Supply Voltage Relative to VSS VDD -0.5 to 3.13 V

Output Supply Voltage Relative to VSS VDDQ -0.5 to 2.3 V

Voltage on any pin Relative to VSS VIN -0.5 to VDDQ+0.5 (2.3V MAX)V

Output Short-Circuit Current(per I/O) IOUT 25 mA

Storage Temperature TSTR -55 to 125 °C

DC CHARACTERISTICS

NOTE :1. Minimum cycle. IOUT=0mA.

2. 50% read cycles.

3. |IOH|=(VDDQ/2)/(RQ/5)±15% @VOH=VDDQ/2 for 175Ω ≤ RQ ≤ 350Ω.

4. |IOL|=(VDDQ/2)/(RQ/5)±15% @VOL=VDDQ/2 for 175Ω ≤ RQ ≤ 350Ω.

5. Minimum Impedance Mode when ZQ pin is connected to VSS.

Parameter Symbol Min Max Unit Note

Average Power Supply Operating Current(x36)

(Cycle time = tKHKH min)

IDD37

IDD33

IDD30

IDD27

540

490

440

420

mA 1,2

Average Power Supply Operating Current(x18)

(Cycle time = tKHKH min)

IDD37

IDD33

IDD30

IDD27

510

460

410

390

mA 1,2

Stop Clock Standby Current

(VIN=VDD-0.2V or 0.2V fixed, K=Low, K=High) ISB1 - 150 mA 1

Input Leakage Current

(VIN=VSS or VDDQ)ILI -1 1 µA

Output Leakage Current

(VOUT=VSS or VDDQ)ILO -1 1 µA

Output High Voltage(Programmable Impedance Mode) VOH1 VDDQ/2 VDDQ V3

Output Low Voltage(Programmable Impedance Mode) VOL1 VSS VDDQ/2 V 4

Output High Voltage(IOH=-0.1mA) VOH2 VDDQ-0.2 VDDQ V5

Output Low Voltage(IOL=0.1mA) VOL2 VSS 0.2 V 5

Rev 1.1

512Kx36 & 1Mx18 SRAM

- 9 - Jan. 2005

K7D161874B

K7D163674B

PIN CAPACITANCE

NOTE : Periodically sampled and not 100% tested.(TA=25°C, f=1MHz)

Parameter Symbol Test Condition TYP Max Unit

Input Capacitance CIN VIN=0V - 4 pF

Data Output Capacitance COUT VOUT=0V - 5 pF

AC TEST CONDITIONS(TA=0 to 70°C, VDD=1.7 -2.63V, VDDQ=1.5V)

Parameter Symbol Value Unit Note

Input High/Low Level VIH/VIL 1.25/0.25 V -

Input Reference Level VREF 0.75 V -

Input Rise/Fall Time TR/TF0.5/0.5 ns -

Output Timing Reference Level 0.75 V -

Clock Input Timing Reference Level Cross Point V -

Output Load See Below -

AC INPUT CHARACTERISTICS

Parameter Symbol Min Max Unit Note

AC Input Logic High VIH (AC) VREF + 0.4 V -

AC Input Logic Low VIL (AC) VREF - 0.4 V -

Clock Input Differential Voltage VDIF (AC) 0.8 V -

VREF Peak-to-Peak AC Voltage VREF (AC) 5% VREF (DC) V -

VIH(AC)

VREF

VIL(AC)

AC INPUT DEFINITION

Setup

Time

Hold

Time

DIF

(AC)

Rev 1.1

512Kx36 & 1Mx18 SRAM

- 10 Jan. 2005

K7D161874B

K7D163674B

AC TIMING CHARACTERISTICS

Notes: 1. The maximum cycle time must be limited to guarantee AC timing specification.

2. This parameter is guaranteed by design, and may not be tested at values shown in the table.

3. This parameter refers to CQ and CQ rising and falling edges.

4. This parameter is only for 16Mb density

5. K and K Clocks must be used differencitally to meet AC timing specifications.

PARAMETER SYMBOL -37 -33 -30 -27 UNITS NOTES

Min Max Min Max Min Max Min Max

Clock

Clock Cycle Time tKHKH 2.66 - 3.0 - 3.3 - 3.63 - ns 1

Clock High Pulse Width tKHKL 1.3 - 1.3 - 1.5 - 1.7 - ns

Clock Low Pulse Width tKLKH 1.3 - 1.3 - 1.5 - 1.7 - ns

Setup Times

Address Setup Time tAVKH 0.4 - 0.4 - 0.4 - 0.5 - ns

Control(B1,B2,B3) Setup Time tBVKH 0.4 - 0.4 - 0.4 - 0.5 - ns

Data Setup Time tDVKX 0.25 - 0.3 - 0.3 - 0.4 - ns 2

Hold Times

Address Hold Time tKHAX 0.4 - 0.4 - 0.4 - 0.5 - ns

Control(B1,B2,B3) Hold Time tKHBX 0.4 - 0.4 - 0.4 - 0.5 - ns

Data Hold Time tKXDX 0.25 - 0.3 - 0.3 - 0.4 - ns 2

Output Times

Echo Clock High Pulse Width tCHCL tKHKL-0.1 tKHKL+0.1 tKHKL-0.1 tKHKL+0.1 tKHKL-0.1 tKHKL+0.1 tKHKL-0.1 tKHKL+0.1 ns 2

Echo Clock Low Pulse Width tCLCH tKLKH-0.1 tKLKH+0.1 tKLKH-0.1 tKLKH+0.1 tKLKH-0.1 tKLKH+0.1 tKLKH-0.1 tKLKH+0.1 ns 2

Clock Crossing to Echo Clock tCXCH 0.5 2.3 0.5 2.3 0.5 2.3 0.5 2.3 ns 3

Clock Crossing to Echo Clock tCXCL 0.5 2.3 0.5 2.3 0.5 2.3 0.5 2.3 ns 3

Echo Clock High to Output Vaild tCHQV -0.20 0.20 -0.20 0.20 -0.20 0.20 -0.20 0.20 ns

Echo Clock Low to Output Valid tCLQV -0.20 0.20 -0.20 0.20 -0.20 0.20 -0.20 0.20 ns

Echo Clock High to Output Hold tCHQX -0.20 -0.20 -0.20 -0.20 ns

Echo Clock Low to Output Hold tCLQX -0.20 -0.20 -0.20 -0.20 ns

Echo Clock High to Output High-Z tCHQZ 0.20 0.20 0.20 0.20 ns

Echo Clock High to Output Low-Z tCHLZ -0.20 -0.20 -0.20 -0.20 ns

G Low to Output Valid tGLQV - 1.7 - 1.7 - 1.9 - 2.0 ns 4

G High to Output Low-Z tGHQX 0.5 0.5 0.5 0.5 ns 4

G High to Output High-Z tGHQZ - 1.7 - 1.7 - 1.9 - 2.0 ns 4

50Ω

AC TEST OUTPUT LOAD

25Ω5pF

0.75V

5pF

0.75V

50Ω

0.75V

Rev 1.1

512Kx36 & 1Mx18 SRAM

- 11 Jan. 2005

K7D161874B

K7D163674B

NOP CONTINUE

AVKH

KHAX

NOP

12 3456781012

READ

(burst of 4)

READ

(burst of 2)

READ

(burst of 4)

NOP WRITE

CONTINUE

WRITE

(burst of 4)

READ

CONTINUE

READ

(burst of 4)

CONTINUE

READ

BVKH

KHBX

CHQZ

KXCV

GHQZ

DVKH

KHDX

GLQX

GLQV

KHKH

GHQX

UNDEFINED

DON’T CARE

NOTE

1. Q01 refers to output from address A. Q02 refers to output from the next internal burst address following A, etc.

2. Outputs are disabled(High-Z) one clock cycle after NOP detected or after no pending data requests are present.

3. Doing more than one Read Continue or Write Continue will cause the address to wrap around.

TIMING WAVEFORMS FOR DOUBLE DATA RATE CYCLES

(Burst Length=4, 2)

KHKL

KLKH

CHCL

CLCH

CHLZ

CHQV

CHQX

CLQV

KXCL

Rev 1.1

512Kx36 & 1Mx18 SRAM

- 12 Jan. 2005

K7D161874B

K7D163674B

TIMING WAVEFORMS FOR SINGLE DATA RATE CYCLES

NOTE :

1. Q01 refers to output from address A0. Q02 refers to output from the next internal burst address following A0, etc.

2. Outputs are disabled(High-Z) one clock cycle after NOP detected or after no pending data requests are present.

3. This devices supports cycle lengths of 1, 2, 4. Continue(B1=HIGH, B2=HIGH, B3=X) up to three times following a B1 operation. Any further

Continue assertions constitute invalid operations.

4. This device will have an address wraparound if further Continues are applied.

NOP CONTINUE

KHKH

AVKH

KHAX

NOP

1 2 3 4 5 6 7 8 10 1211

READ

(burst of 2)

READ

(burst of 4)

NOP WRITE

CONTINUE

WRITE

(burst of 2)

READ

CONTINUE

READ

CONTINUE

READ

CONTINUE

READ

BVKH

KHBX

CHQZ

KXCV

GHQZ

GHQX

DVKH

KHDX

GLQX

GLQV

KLKH

UNDEFINED

DON’T CARE

KHKL

(Burst Length=4, 2, 1)

(burst of 1)

CHCL

CLCH

KXCL

CHLZ

CHQV

CHQX

Rev 1.1

512Kx36 & 1Mx18 SRAM

- 13 Jan. 2005

K7D161874B

K7D163674B

IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG

TAP Controller State Diagram

JTAG Block Diagram

SRAM

CORE

BYPASS Reg.

Identification Reg.

Instruction Reg.

Control Signals

TAP Controller

TDO

TDI

TMS

TCK

Test Logic Reset

Run Test Idle

Select DR

Capture DR

Shift DR

Exit1 DR

Pause DR

Exit2 DR

Update DR

Select IR

Capture IR

Shift IR

Exit1 IR

Pause IR

Exit2 IR

Update IR

The SRAM provides a limited set of IEEE standard 1149.1 JTAG functions. This is to test the connectivity during manufacturing

between SRAM, printed circuit board and other components. Internal data is not driven out of SRAM under JTAG control. In conform-

ance with IEEE 1149.1, the SRAM contains a TAP controller, Instruction Register, Bypass Register and ID register. The TAP control-

ler has a standard 16-state machine that resets internally upon power-up, therefore, TRST signal is not required. It is possible to use

this device without utilizing the TAP. To disable the TAP controller without interfacing with normal operation of the SRAM, TCK must

be tied to VSS to preclude mid level input. TMS and TDI are designed so an undriven input will produce a response identical to the

application of a logic 1, and therefore can be left unconnected. But they may also be tied to VDD through a resistor. TDO should be left

unconnected.

JTAG Instruction Coding

NOTE :

1. Places DQs in Hi-Z in order to sample all input data regardless of other

SRAM inputs. This instruction is not IEEE 1149.1 compliant.

2. Places DQs in Hi-Z in order to sample all input data regardless of other

SRAM inputs.

3. TDI is sampled as an input to the first ID register to allow for the serial shift

of the external TDI data.

4. Bypass register is initiated to VSS when BYPASS instruction is invoked. The

Bypass Register also holds serially loaded TDI when exiting the Shift DR

states.

5. SAMPLE instruction dose not places DQs in Hi-Z.

6. This instruction is reserved for future use.

IR2 IR1 IR0 Instruction TDO Output Notes

0 0 0 EXTEST Boundary Scan Register 1

0 0 1 IDCODE Identification Register 3

0 1 0 SAMPLE-Z Boundary Scan Register 2

0 1 1 RESERVED Do Not Use 6

1 0 0 SAMPLE Boundary Scan Register 5

1 0 1 RESERVED Do Not Use 6

1 1 0 RESERVED Do Not Use 6

1 1 1 BYPASS Bypass Register 4

Rev 1.1

512Kx36 & 1Mx18 SRAM

- 14 Jan. 2005

K7D161874B

K7D163674B

BOUNDARY SCAN EXIT ORDER(x36)

* Reserved for Mode Pin

36 4A SA SA 6A 35

37 4C SA SA 6C 34

38 3A SA SA 7A 33

39 3B SA SA 7B 32

40 3C SA SA 7C 31

41 3D SA SA 7D 30

42 2B DQ DQ 8B 29

43 1B DQ DQ 9B 28

44 2D DQ DQ 8D 27

45 3F DQ DQ 7F 26

46 1D DQ DQ 9D 25

47 2F CQ CQ 8F 24

48 1F DQ DQ 9F 23

49 3H DQ DQ 7H 22

50 2H DQ DQ 8H 21

51 1H DQ DQ 9H 20

52 5A ZQ G5C 19

53 5B B1K5G18

54 5K B2K5H 17

55 5L B3MODE 6L 16

56 4L LBO DQ 9K 15

57 1K DQ DQ 8K 14

58 2K DQ DQ 7K 13

59 3K DQ DQ 9M 12

60 1M DQ CQ 8M 11

61 2M CQ DQ 9P 10

62 1P DQ DQ 7M 9

63 3M DQ DQ 8P 8

64 2P DQ DQ 9T 7

65 1T DQ DQ 8T 6

66 2T DQ SA 7P 5

67 3T SA SA 7T 4

68 4R SA SA 6R 3

SA 5T 2

SA 5R 1

BOUNDARY SCAN EXIT ORDER(x18)

* Reserved for Mode Pin

26 4A SA SA 6A 25

27 4C SA SA 6C 24

28 3A SA SA 7A 23

29 3B SA SA 7B 22

30 3C SA SA 7C 21

31 3D SA SA 7D 20

32 2B DQ

DQ 9B 19

DQ 8D 18

DQ 7F 17

33 1D DQ

34 2F CQ

DQ 9F 16

35 3H DQ

DQ 8H 15

36 1H DQ

37 5A ZQ G5C 14

38 5B B1K5G13

39 5K B2K5H 12

40 5L B3MODE 6L 11

41 4L LBO DQ 9K 10

42 2K DQ DQ 7K 9

43 1M DQ CQ 8M 8

DQ 9P 7

44 3M DQ

45 2P DQ

46 1T DQ DQ 8T 6

SA 7P 5

47 3P SA SA 7T 4

48 3T SA SA 6R 3

49 4R SA SA 5T 2

SA 5R 1

ID REGISTER DEFINITION

Part Revision Number

(31:28)

Part Configuration

(27:18)

Vendor Definition

(17:12)

Samsung JEDEC Code

(11: 1)

Start Bit

(0)

512Kx36 0000 00111 00100 XXXXXX 00001001110 1

1M x 18 0000 01000 00011 XXXXXX 00001001110 1

SCAN REGISTER DEFINITION

Part Instruction Register Bypass Register ID Register Boundary Scan

512Kx36 3 bits 1 bits 32 bits 68 bits

1M x 18 3 bits 1 bits 32 bits 49 bits

Rev 1.1

512Kx36 & 1Mx18 SRAM

- 15 Jan. 2005

K7D161874B

K7D163674B

JTAG DC OPERATING CONDITIONS

NOTE : 1. The input level of SRAM pin is to follow the SRAM DC specification.

Parameter Symbol Min Typ Max Unit Note

Power Supply Voltage VDD 1.7 2.5 2.6 V

Input High Level VIH 0.7*VDD -VDD+0.3 V

Input Low Level VIL -0.3 - 0.3*VDD V

Output High Voltage(IOH=-2mA) VOH 0.75*VDD -VDD V

Output Low Voltage(IOL=2mA) VOL VSS - 0.25*VDD V

JTAG AC Characteristics

Parameter Symbol Min Max Unit Note

TCK Cycle Time tCHCH 50 - ns

TCK High Pulse Width tCHCL 20 - ns

TCK Low Pulse Width tCLCH 20 - ns

TMS Input Setup Time tMVCH 5-ns

TMS Input Hold Time tCHMX 5-ns

TDI Input Setup Time tDVCH 5-ns

TDI Input Hold Time tCHDX 5-ns

Clock Low to Output Valid tCLQV 010ns

JTAG AC TEST CONDITIONS

NOTE : 1. See SRAM AC test output load on page 5.

Parameter Symbol Min Unit Note

Input High/Low Level VIH/VIL VDD/0.0 V

Input Rise/Fall Time TR/TF 1.0/1.0 ns

Input and Output Timing Reference Level VDD/2 V 1

JTAG TIMING DIAGRAM

TCK

TMS

TDI

TDO

tCHCH tCHCL tCLCH

tMVCH tCHMX

tDVCH tCHDX

tCLQV

Rev 1.1

512Kx36 & 1Mx18 SRAM

- 16 Jan. 2005

K7D161874B

K7D163674B

153 BGA PACKAGE THERMAL CHARACTERISTICS

NOTE : 1. Junction temperature can be calculated by : TJ = TA + PD x Theta_JA.

Parameter Symbol Thermal Resistance Unit Note

Junction to Ambient(at still air) Theta_JA TBD °C/W

Junction to Case Theta_JC TBD °C/W

Junction to Board Theta_JB TBD °C/W

NOTE :

1. All Dimensions are in Millimeters.

2. Solder Ball to PCS Offset : 0.10 MAX.

3. PCB to Cavity Offset : 0.10 MAX.

153 BGA PACKAGE DIMENSIONS

1.27

7654321

0.050

BCDEFGHJKLMNPRTUA

1.27

0.050

∅

BOTTOM VIEW

0.3/0.012MAX 153-∅0.030 ±0.006

14.00 ±0.10

0.551 ±0.004

22.00 ±0.10

0.866 ±0.004

12.50 ±0.10

0.492 ±0.004

0.60 ±0.10

0.024 ±0.004

20.50 ±0.10

0.807 ±0.004

0.56 ±0.04

0.022 ±0.002

0.90 ±0.10

0.035 ±0.004

2.21

0.087

TOP VIEW

0.006

0.15 MAX

0.75 ±0.15

MAX