Integrated Device Technology, Inc. CMOS DUAL-PORT RAM 32K (4K x 8-BIT) IDT7134SA IDT7134LA FEATURES: High-speed access Military: 25/35/45/55/70ns (max.) Commercial: 20/25/35/45/55/70ns (max.) * Low-power operation 1IDT7134SA Active: 500mW (typ.) Standby: 5mW (typ.) IDT7134LA Active: 500mW (typ.) Standby: imW (typ.) Fully asynchronous operation from either port Battery backup operation2V data retention TTL-compatible; single 5V (410%) power supply Available in several popular hermetic and plastic packages Military product compliant to MIL-STD-883, Class B Industrial temperature range (40C to +85C) is available, tested to military electrical specifications DESCRIPTION: The IDT7134 is an extremely high-speed 4K x 8 Dual-Port Static RAM designed to be used in systems where on-chip hardware port arbitration is not needed. This part lends itself to those systems which cannot tolerate wait states or are designed to be able to externally arbitrate or withstand contention when both sides simultaneously access the same Dual-Port RAM location. The IDT7134 provides two independent ports with separate control, address, and W/O pins that permit independent, asynchronous access for reads or writes to any location in memory. It is the user's responsibility to ensure data integrity when simultaneously accessing the same memory location from both ports. An automatic power down feature, controlled by CE, permits the on-chip circuitry of each portto enter a very low standby power mode. Fabricated using IDTs CMOS high-performance technology, these Dual-Port typically on only 500mW of power. Low-power (LA) versions offer battery backup data retention capability, with each port typically consuming 200nW from a 2V battery. The 1DT7134 is packaged on either a sidebraze or plastic 48-pin DIP, 48-pin LCC, 52-pin PLCC and 48-pin Ceramic Flatpack. Military grade productis manufactured in compliance with the latest revision of MIL-STD-883, Class B, making it ideally suited to military temperature applications demanding the highest level of performance and reliability. FUNCTIONAL BLOCK DIAGRAM RM CEL OEL y COLUMN vO VOoL- 1/O7L <q A y COLUMN vO ++ |/Oor- 1/O7R ADDRESS O PIGDRE SS . MEMORY AoL- A11L *| "DECODE > ARRAY DECODE [* Aor- A1iR LOGIC LOGIC The IDT logo is a registered trademark ol Intagrated Davica Technology, Inc. MILITARY AND COMMERCIAL TEMPERATURE RANGES 1996 integrated Davice Technology. Inc. 6.04 2720 drw 01 DECEMBER 1995 bpc-a72073iDT7134SA/LA CMOS DUAL-PORT RAM 32K (4K x 8-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES PIN CONFIGURATIONS = WF a ce. O1 48(J vec ge sifu gh ges RW C2 47L)CER INDEX Zo <ez222@6 S62 24% An.Q3 461] RWa t, tes tree Ato. 4 45C] Air 6 52 51 48 47 mos | SoBe ok om A Au G7 4210 Aor Aare Aon Aa C8 4iC Air ASL AIR Ast C9 40(] Aer Aa AzR Aa. 10 39(7 Aar ASL AGA As.j11 1077134 380 Asr AeL IDT7134 Ae. 12 P48-1 37LJAsr J52-1 An An 13 & 36(] Aer Ar ASR Asa 414 C48-2 350 A7R AaL pLec Aen Ao (jis DIP = 340 Aar AL TOP VIEW AvA VOo.f]16 TOP VIEW 33[] Aor v0 yvouOl17 320] Vom ot Agr vOal] 18 3110 /O6A Vor Agr vOaLE] 19 3010 /Osa VOat NIC vOal 20 29(] 1/04 VOL VOrR VO stC] 21 281 1/O3A 22 23 24 25 26 27 28 29 30 31 32 33 UO sl 22 37H Oar Pururvrvrirvevrireieiey 7 1A gaoeoe zr OOtCtancrcrerekaee GND 24 25 I/Oonr $86225588S88 2720 drw 02 2720 dew 03 ABSOLUTE MAXIMUM RATINGS") Symbol Rating Coml. Mil. Unit VrenmM4 Terminal Voltage | -0.5to+7.0 | -0.5to+7.0] V with Respect to Ground INDEX Ta Operating 0 to +70 -55 to +125] C Temperature Teias =| Temperature -55 to +125 | -65to +135] C Awl 27 1 420 J Aor Under Bias AxwEia AIR TstG [Storage -55 to +125 | -65to +150} C Ax fI9 A2R Temperature Aa [310 A3R Pr) | Power Dissipation 1.5 1.5 w As fit 1DT7134 Aar r 7 L48-1 lout DC Output Current 50 50 mA Ast p= 12 & Aer An. [313 F4B-1 Asr 2720 tol 01 Aa a4 (1) A NOTE: Lb 7A 1. Stresses greater than those listed under ABSOLUTE MAXIMUMRATINGS Ax 715 Locmlatpack AsA may cause permanent damage to the device. This is a stress rating only vOo. E216 TOP VIEW Aga and functional operation of the device at these or any other conditions 10 a above those indicated in the operational sections of this specification is not WOUE 17 VO7A implied. Exposure to absolute maximum rating conditions tor extended VOa[ 318 VOc6A periods may affect reliability. 19 20 21 22 23 24 25 26 27 28 29 30 2. VTERM must not exceed Vcc + 0.5V for more than 25%of the cycle time or He eeneeTernreenet 10 ns maximum, and is limited to < 20mA for the period of VTeaM > Vcc azeugrFOReceagce |& +0.5V. 8S8SSs5SoSSss CAPACITANCE" (Ta = +25C, f = 1.0MHz) vimana Symbol Parameter Conditions | Max. | Unit CIN Input Capacitance VIN = 3dv?) 9 pF NOTE: . / / 1. This text does not indicate orientation of actual part-marking. Cout Output Capacitance | Vout = 3dv?)| 10 pF 2720 tbl 02 NOTES: 1. This parameter is determined by device characterization but is not production tested. 2. 3dv references the interpolated capacitance when the input and output signals switch from OV to 3V and from 3V to OV. 6.04 2IDT7134SA/LA CMOS DUAL-PORT RAM 32K (4K x 8-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES RECOMMENDED OPERATING RECOMMENDED DC OPERATING CONDITIONS TEMPERATURE AND SUPPLY VOLTAGE Symbol Parameter Min. | Typ. | Max. | Unit Ambient Vec Supply Voltage 4.5 5.0 5.5 Vv Grade Temperature GND Vec GND Ground 0 0 0 V Military -55C to +125C OV 5.0V + 10% Vin Input High Voltage 2.2 [602] v i o, O, Oy Commercial OC to +70C ov 5.0V t 10% VIL Input Low Voltage 5], 08 Vv 2720 101 03 NOTES: 2720 tbl 04 1. Vit (min.) > 1.5V for pulse width less than 10ns. 2. VTERM must not exceed Vcc + 0.5V. DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE (Vcc = 5V + 10%) 10T7134SA IOT7134LA Symbol Parameter Test Conditions Min. Max. Min. Max. Unit hut Input Leakage Current") | Vcc = 5.5V, VIN = OV to Voc 10 _ 5 pA IILol Output Leakage Current CE = VIH, VouT = OV to Vcc _ 10 _ 5 BA VoL Output Low Voitage lo. = 6MA _ 0.4 _ 0.4 Vv loL = BMA = 0.5 = 0.5 Vv VOH Output High Voltage loH = -4mA 2.4 _ 2.4 _ Vv 1. At Vcc < 2.0V input leakages are undefined. 2720 toi Ob DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE" (vcc = 5.0V + 10%) 7134X200) 7134X25 7134X35 7134X45 7134X55 7134X70 Symbol Parameter Teat Conditions | Version | Typ.) Max.| Typ.) Max. Typ. Max. Typ.)Max.| Typ. | Max. Typ.) Max. Unit Ice Dynamic Operating |CE = ViL MiL. S| J] | 160 | 3107150 | 300] 140 |] 280] 140] 270| 140 [270 | mA Current Outputs Open Lt} | 160 | 260] 150 | 250] 140 | 240] 140 | 220] 140 [220 (Both Ports Active) |f = fuax(? COM'L.S| 170 ] 280] 160 | 280] 150 | 260/140 | 240] 140] 240] 140 [240 L] 170 | 240] 160 | 220] 150 | 210] 140 | 200] 140] 200] 140 |200 Isax | Standby Current C& andCE&a=Vin |MIL. S| | | 25 | 100] 25 | 75] 25 | 70] 25 | 70] 25 170 | ma (Both PortsTTL f = fmax?) Ly] _ 25 80 | 25 55 |] 25 50 25 | 50 25 | 50 Level Inputs) COM'L.S] 25 | 110] 25 80 | 25 75 | 25 70 25 | 70 25 170 L] 25 80 25 50 | 25 45 | 25 40 25 | 40 25 | 40 Isa2 Standby Current CE,.= V,, and MIL. S| 95 | 210] 85 200| 75 190} 75 1180] 75 [180 | mA (One PonTTL |TE,.=V,, L| | ] 95 | 1t70| 85 | 160} 75 | 150] 75 | 150] 75 |150 Level Inputs) Active Port Outputs |COM'L.S | 105 | 180] 95 | 180] 85 1701 75 460] 75 | 160] 75 1160 Open, f = fax!) L] 105 | 150] 95 ] 140] 85 |130} 75 | 130] 75 | 130] 75 |130 Iss3__| Full Standby Current] Both Ports CE: and|MIL. S| | | 1.0 | 30] 1.0 | 30] 1.0 | 30] 1.0] 30] 1.0 ]30 | ma (Both PortsAll CER 2 Vcc - 0.2V L] | 0.2 | 10 | 0.2 10 | 0.2 10 0.2 | 10] 02 | 10 CMOS Level Inputs) | Vin 2 Voc -0.2Vor JCOML.S| 10] 15] 1.0] 15] 1.0 | 15] 1.0 | 18] 1.0] 15] 1.0 | 15 Vin s 0.2V, f= 08) L}] 0.2] 45| 02] 40]02 | 40/02 | 40] 02440] 02 |40 Isea Full Standby Current|One Port CE,.or |MIL. S| | ] 95 | 210] a8 | 190] 75 | 180) 75 ] 170] 75 1170 | mA (One PortAll CcE.,. 2 Vcc - 0.2V L}| = 95 | 150] 85 130] 75 120] 75 | 120] 75 [120 CMOS Level Inputs) | Vin 2 Vcc -0.2V or }COM'L.S] 105 | 170] 95 | 170] 85 160] 75 150} 75 | 150] 75 /150 Vin s 0.2V L] 105 | 130] 95 | 120] 85 110] 75 100] 75 |] 100] 75 |100 Active Port Outputs Open, f = fax NOTES: 2720 tbl 0 1. X in part number indicates power rating (SA or LA). 2, Vcc = 5V, Ta = +25C for typical, and parameters are not production tested. 3. fMax = t/tac = All inputs cycling at f = 1/tac (except Output Enable). f = O means no address or control linas change. Applies only to inputs at CMOS level standby tsB3. 4. (Commercial only) 0C to +70C temperature range. 6.04IDT7134SA/LA CMOS DUAL-PORT RAM 32K (4K x 8-BIT) DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES (LA Version Only) Vic = 0.2V, VHc = Vcc - 0.2V MILITARY AND COMMERCIAL TEMPERATURE RANGES Symbol Parameter Test Condition Min. Typ.) Max. Unit VoR VCC for Data Retention Vec = 2V 2.0 _ Vv Iccor Data Retention Current CE > Vic MIL. 100 4000 | pA VIN 2 VHC or < VLC COM'L. 100 1500 tcor) Chip Deselect to Data Retention Time ta) Operation Recovery Time 0 _ ns tac!) _ ns NOTES: 1, Vcc = 2V, Ta = +25C, and are not production tested. 2. trac = Read Cycle Time. 3. This parameter is guaranteed by device characterization, but not production tested. DATA RETENTION WAVEFORM l DATA RETENTION MODE Vec 4.5 Vor > 2V 4.5V {rR CE VLLLLLLLLLL/ ViqoN Von AC TEST CONDITIONS Input Pulse Levels GND to 3.0V Input Rise/Fall Times 5ns Input Timing Reference Levels 1.5V Output Reference Levels 1.5V Output Load See Figures 1 and 2 2720 thi 08 +5V 12500 DATAouTt Ss * 780% 30pF + 2720 drw 06 DATAouTt < 77508 { VIH +5V 12500 SpF* 2720 th! 07 2720 dew 05 2720 drw 07 Figure 1. AC Output Test Load Figure 2, Output Test Load (for tiz, tz, twz, tow) Including scope and jig 6.04IDT7134SA/LA CMOS DUAL-PORT RAM 32K (4K x 8-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE) 7134X20) 7134X25 7134X35 Symbol Parameter Min. | Max. Min. Max. | Min. Max. Unit READ CYCLE tRC Read Cycle Time 20 _ 25 - 35 _ ns taA Address Access Time _ 20 _ 25 _ 35 ns {ACE Chip Enable Access Time _ 20 _ 25 _ 35 ns {AOE Output Enable Access Time _ 15 _ 15 _ 20 ns tOH Output Hold from Address Change 3 _ 0 _ 0 _ ns tlz Output Low-Z Time": 2) 3 _ ) ~ 0 ns tHz Output High-Z Time" 2) _ 15 15 20 ns teu Chip Enable to Power Up Time) 0 _ 0 _ 0 _ ns tp Chip Disable to Power Down Time? 20 25 _ 35 ns AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE") (CONT'D) 7134X45 7134X55 7134X70 Symbol Parameter Min. | Max. | Min. | Max. | Min. | Max. | Unit READ CYCLE tr Read Cycle Time 45 _ 55 _ 70 _ ns taA Address Access Time _ 45 _ 55 _ 70 ns tace Chip Enable Access Time _ 45 _ 55 _ 70 ns tAOE Output Enable Access Time 25 - 30 _ 40 ns tOH Output Hold from Address Change Q _ 0 _ 0 _ ns {Lz Output Low-Z Time! 2) 5 _~ 5 _ 5 _ ns tHz Output High-Z Time" 2) _ 20 25 _ 30 ns teu Chip Enable to Power Up Time) 0 = 0 _ 0 ns {PD Chip Disable to Power Down Time) _ 45 _ 50 _ 50 ns NOTES: 2720 tbl 09 1. Transition is measured +500mV fromLow or High impedance voltage with the Output Test Load (Figures 1 and 2). 2. This parameter is guaranteed by device characterization, but is not production tested. 3. (Commercial only) 0C to +70C temperature range only. 4. X in part number indicates power rating (SA or LA). TIMING WAVEFORM OF READ CYCLE NO. 1, EITHER SIDE: 2:4 + {RC | ADDRESS K tAA toH_> tOH DATAouT PREVIOUS DATA VALID KKKXK DATA VALID 2720 drw 08IOT7134SA/LA CMOS DUAL-PORT RAM 32K (4K x 8-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES TIMING WAVEFORM OF READ CYCLE NO. 2, EITHER SIDE" 9) {ACE CE OE DATAout teu tpD Icc | CURRENT py 50% 50% IsB VALID DATA 2720 drw 09 NOTES: 1. Timing depends on which signal is asserted last, OF or CE. 2. Timing depends on which signal is de-asserted first, OE or CE. 3. RW = V,, and OF = V_, untess otherwise noted. 4. Start of valid data depends on which timing becomes effective , tAOE, tACE or tAA 5. taa for RAM Address Access and tsaa for Semaphore Address Access. AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE) 7134x20") 7134X25 7134X35 Symbol Parameter Min. Max. Min. Max. Min. Max. Unit WRITE CYCLE two Write Cycle Time 20 _ 25 _ 35 _ ns tEw Chip Enable to End-of-Write 15 _ 20 _ 30 _ ns taw Address Valid to End-of-Write 15 _ 20 _ 30 _ ns tas Address Set-up Time 0 _ 0 _ 0 _ ns twp Write Pulse Width 15 _ 20 _ 25 _~ ns twrR Write RecoveryTime 0 _ 0 _ 0 - ns tbw Data Valid to End-of-Write 15 _ 15 _- 20 _ ns tHZ Output High-Z Time": 2) 15 _ 15 _ 20 ns {DH Data Hold Time) 0 - 0 3 ns twz Write Enabled to Output in High-Z"': 2) _ 15 _ 16 _ 20 ns tow Output Active from End-of-Write': 29) 3 _ 3 _ 3 _ ns iwoD Write Pulse to Data Delay) _ 40 _ 50 _ 60 ns topp Write Data Valid to Read Data Delay? _ 30 ~ 30 _ 35 ns NOTES: 2720 tbl 10 1. Transition is measured +500mV fromLow orHigh impedance voltage with Output Test Load (Figures 1 and 2). 2. This parameter is guaranteed by device characterization, but is not production tested. 3. The specification for toy must be met by the device supplying write data to the RAM under alli operating conditions. Although tox and tow values will vary over voltage and temperature, the actual toH will always be smaller than the actual tow. 4. Port-to-port delay through RAM cells from writing port to reading port, refer to Timing Waveform of Write with Port - to - Port Read. . {Commercial only), 0C to +70C temperature range . . X" in part number indicates power rating (SA or LA). . tbd0 = 35ns for military temperature range. NO 6.04 6IOT7134SA/LA CMOS DUAL-PORT RAM 32K (4K x 8-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE (CONT'D) 7134X45 7134X55 7134X70 Symbol Parameter Min. | Max. Min. | Max. Min. | Max. Unit WRITE CYCLE two Write Cycle Time 45 _ 55 _ 70 - ns {ew Chip Enable to End-of-Write 40 _ 50 60 _ ns taw Address Valid to End-of-Write 40 _ 50 _ 60 _ ns tas Address Set-up Time 0 _ 0 _ 0 _ ns twe Write Pulse Width 40 _ 50 60 _ ns twR Write RecoveryTime 0 _ 0 _ 0 _ ns tow Data Valid to End-of-Write 20 _ 25 _ 30 _ ns tHz Output High-Z Time!" #) ~ 20 25 30 ns tDH Data Hold Time) 3 _ 3 _ 3 _ ns twz Write Enabled to Output in High-2- ?) 20 25 _ 30 ns tow Output Active from End-of-Write! 2: 9) 3 _ 3 3 ns twoo Write Pulse to Data Delay _ 70 _ 80 _ 90 ns topb Write Data Valid to Read Data Delay _ 45 _ 55 _ 70 ns NOTES: 2720 thi 10 1. Transition is measured t500mV framLow orHigh impedance voltage with Output Test Load (Figures 1 and 2). 2. This parameter is guaranteed by device characterization, but is not production tested. 3. The specification for to must be met by the device supplying write data to the RAM under ail operating conditions. Although tox and tow values will vary 4. 5. 6. over voltage and temperature, the actual tb# will always be smaller than the actual tow. Pont-to-port delay through RAM cells from writing port to reading port, refer to Timing Waveform of Write with Port - to - Port Read. . (Commercial only), 0C to +70C temperature range . "X in part number indicates power rating (SA or LA). TIMING WAVEFORM OF WRITE WITH PORT - TO - PORT READ ") N 1. 2 3 ~ twe - ADDR a' MATCH < }<~_______ twp taw Rian NN + tow DATAINA' x VALID x ADDA se x MATCH twoD DATAout 8 XK vAuo OTE: - me enone 10 Write cycle parameters should be adhered to, in order to ensure proper writing. . CEt=CER = Vit. OFB = Vit. . PortA" may be either teft or right port. Port B" is the opposite from port A".IDT7134SA/LA CMOS DUAL-PORT RAM 32K (4K x 8-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES TIMING WAVEFORM OF WRITE CYCLE NO. 1, RW CONTROLLED TIMING" 5. 8) TIMING WAVEFORM OF WRITE CYCLE NO. 2, CE CONTROLLED TIMING": ) + two ADDRESS x > < _ pt tA (6) -m yy OE J + taw twR@)~ Ce * twe 2 ~ eee RAV 5 eo 7 7) tz twz HZ) tow sal DATAouT (4) (4) tow (DH DATAIN 2720 drw 10 a two ADDRESS x xK + taw CE } YY CE 7 etaS (6) t tew(2) ht tWR(3) >] RAW \ f - tow e +e 10H -_ > DATAIN 2720 dew 11 NOTES: @ . RW or CE must be High during all address transitions. . . Awrite occurs during the overlap (tew or twe) of a CE =Vit and AWe Va. . twA is measured from the earlier of CE or RAW going high to the end-of-write cycle. During this period, the I/O pins are in the output state, and input signals must not be applied. If the CE low transition occurs simultaneously with or after the R/W low transition, the outputs remain in the high impedance state. .. Timing depends on which enable signal ( CE or R/W )is asserted last. . This parameter is guaranteed by device characterization, but is not production tested. Transition is measured + 500mV from steady state with the Output Test Load (Figure 2). . If OE is tow during a R/W controlled write cycle, the write pulse width must be the larger of twp or (twz + tow) to allow the I/O drivers to tum off data to be placed on the bus for the required tow. If OE is high during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified twp. 6.04 8IDT7134SA/LA CMOS DUAL-PORT RAM 32K (4K x 8-BIT) MILITARY ANO COMMERCIAL TEMPERATURE RANGES FUNCTIONAL DESCRIPTION TABLE | - READ/WRITE CONTROL The 1DT7134 provides two ports with separate control, Left or Right Port! address, and 1/0 pins that permit independent access for RW |CE1OE Do7 Funetion reads or writes to any location in memory. These devices have - - an automatic power down feature controlled by CE. The CE xX | H |X Zz Port Disabled and in Power controls on-chip power down circuitry that permits the Down Mode, Isa2 oF |se4 respective port to go into standby mode when not selected Xx H | Xx Zz CER = CEL = H, Power Down (CE high). When a port is enabled, access to the entire Mode, !sB1 or IsB3 memory array is permitted. Each port has its own Output L L | X | DATA | Data on port written into Enable control (OE). In the read mode, the ports OE turns on memory the output drivers when set LOW. Non-contention READ/ H L L_ | DATAouT | Data in memory output on port WRITE conditions are illustrated in the table below. X X Z High impedance outputs 2720 tol.11 NOTE: 1. Aoi - AriL # Aor: Ari H" = HIGH, L = LOW, X" = Don't Care, and Z = High impedance ORDERING INFORMATION |IOT XXXX A 999 A A Device Type Power Speed Package Process/ Temperature Range Blank Commercial (0C to +70C) Military (-55C to +125C) Compfiant to MIL-STD-883, Class B 48-pin Plastic DiP (P48-1) 48-pin Ceramic DIP (C48-2) 52-pin PLCC (J52-1) 48-pin LCC (L48-1) 48-pin Ceramic Flatpack (F48-1) Commercial Only Speed in nanoseconds Low Power Standard Power 32K (4K x 8-Bit) Dua!l-Port RAM 2720 drw 13 6.04