LTC6946
1
6946fb
For more information www.linear.com/LTC6946
Typical applicaTion
FeaTures DescripTion
Ultralow Noise and Spurious
0.37GHz to 6.39GHz Integer-N
Synthesizer with Integrated VCO
The LT C
®
6946 is a high performance, low noise, 6.39GHz
phase-locked loop (PLL) with a fully integrated VCO,
including a reference divider, phase-frequency detector
(PFD) with phase-lock indicator, ultralow noise charge
pump, integer feedback divider, and VCO output divider.
The charge pump contains selectable high and low voltage
clamps useful for VCO monitoring.
The integrated low noise VCO uses no external components.
It is internally calibrated to the correct output frequency
with no external system support.
The part features a buffered, programmable VCO output
divider with a range of 1 through 6, providing a wide
frequency range.
LTC6946-3 PLL Phase Noise
applicaTions
n Low Noise Integer-N PLL with Integrated VCO
n –226dBc/Hz Normalized In-Band Phase Noise Floor
n –274dBc/Hz Normalized In-Band 1/f Noise
n –157dBc/Hz Wideband Output Phase Noise Floor
n Excellent Spurious Performance
n Output Divider (1 to 6, 50% Duty Cycle)
n Output Buffer Muting
n Low Noise Reference Buffer
n Charge Pump Current Adjustable from 250µA to
11.2mA
n Configurable Status Output
n SPI Compatible Serial Port Control
n PLLWizard™ Software Design Tool Support
n Wireless Base Stations (LTE, WiMAX, W-CDMA, PCS)
n Broadband Wireless Access
n Military and Secure Radio
n Test and Measurement
L, LT , LT C , LT M , Linear Technology and the Linear logo are registered trademarks and
PLLWizard is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners.
OFFSET FREQUENCY (Hz)
–140
PHASE NOISE (dBc/Hz)
–130
–110
–90
–80
100 10k 100k 10M
40M
6946 TA01b
–150
1k 1M
–100
–120
–160
RMS NOISE = 0.61°
RMS JITTER = 296fs
fRF = 5.7GHz
fPFD = 10MHz
BW = 85kHz
GND
VCP+
CP
VREF+
REF+
REF–
BB
VRF+
RF+
RF–
GND
MUTE
VREFO+
REFO
STAT
CS
SCLK
SDI
SDO
VD+
VVCO+
GND
CMA
CMB
CMC
GND
TB
TUNE
LTC6946-3
0.01µF
0.01µF 2.2µF
0.01µF
100pF
0.01µF
68nH 68nH
1µF
3.3V
3.3V
4.7nF
57nF
100pF
UNUSED OUTPUT
IS AVAILABLE
FOR OTHER USE
RF INPUT
SIGNAL
TO IF
PROCESSING
LO IF
RF
0.01µF
1µF
0.1µF 0.1µF
3.3V
6946 TA01a
3.3V
3.3V
+
1µF
51.1Ω
50Ω
SPI BUS
10MHz
15Ω 97.6Ω
5V
Frequency Coverage Options
LTC6946-1 LTC6946-2 LTC6946-3 LTC6946-4
O DIV=1 2.240 to 3.740 3.080 to 4.910 3.840 to 5.790 4.200 to 6.390
O DIV=2 1.120 to 1.870 1.540 to 2.455 1.920 to 2.895 2.100 to 3.195
0 DIV=3 0.747 to 1.247 1.027 to 1.637 1.280 to 1.930 1.400 to 2.130
O DIV=4 0.560 to 0.935 0.770 to 1.228 0.960 to 1.448 1.050 to 1.598
O DIV=5 0.448 to 0.748 0.616 to 0.982 0.768 to 1.158 0.840 to 1.278
O DIV=6 0.373 to 0.623 0.513 to 0.818 0.640 to 0.965 0.700 to 1.065
5.7GHz Wideband Receiver
LTC6946
2
6946fb
For more information www.linear.com/LTC6946
pin conFiguraTionabsoluTe MaxiMuM raTings
Supply Voltages
V+ (VREF+, VREFO+, VRF+, VD+) to GND ..................3.6V
VCP+, VVCO+ to GND .............................................5.5V
Voltage on CP Pin .................GND – 0.3V to VCP+ + 0.3V
Voltage on All Other Pins ..........GND – 0.3V to V+ + 0.3V
Operating Junction Temperature Range, TJ (Note 2)
LTC6946I ............................................... –40°C to 105°C
Junction Temperature, TJMAX ................................ 125°C
Storage Temperature Range .................. –65°C to 150°C
(Note 1)
9 10
TOP VIEW
29
GND
UFD PACKAGE
28-LEAD (4mm × 5mm) PLASTIC QFN
11 12 13
28 27 26 25 24
14
23
6
5
4
3
2
1
VREFO+
REFO
STAT
CS
SCLK
SDI
SDO
VD+
VVCO+
GND
CMA
CMB
CMC
GND
TB
TUNE
REF–
REF+
VREF+
CP
VCP+
GND
MUTE
GND
RF–
RF+
VRF+
BB
7
17
18
19
20
21
22
16
815
TJMAX = 125°C, θJCbottom = 3°C/W, θJCtop = 26°C/W
EXPOSED PAD (PIN 29) IS GND, MUST BE SOLDERED TO PCB
orDer inForMaTion
LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION JUNCTION TEMPERATURE RANGE
LTC6946IUFD-1#PBF LTC6946IUFD-1#TRPBF 69461 28-Lead (4mm × 5mm) Plastic QFN –40°C to 105°C
LTC6946IUFD-2#PBF LTC6946IUFD-2#TRPBF 69462 28-Lead (4mm × 5mm) Plastic QFN –40°C to 105°C
LTC6946IUFD-3#PBF LTC6946IUFD-3#TRPBF 69463 28-Lead (4mm × 5mm) Plastic QFN –40°C to 105°C
LTC6946IUFD-4#PBF LTC6946IUFD-4#TRPBF 69464 28-Lead (4mm × 5mm) Plastic QFN –40°C to 105°C
Consult LT C Marketing for parts specified with wider operating temperature ranges.
Consult LT C Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
available opTions
VCO FREQUENCY
RANGE (GHz)
PACKAGE STYLE OUTPUT FREQUENCY RANGE vs OUTPUT DIVIDER SETTING (GHz)
QFN-28 (UFD28) 0 DIV = 6 0 DIV = 5 0 DIV = 4 0 DIV = 3 0 DIV = 2 0 DIV = 1
2.240 to 3.740 LTC6946IUFD-1 0.373 to 0.623 0.448 to 0.748 0.560 to 0.935 0.747 to 1.247 1.120 to 1.870 2.240 to 3.740
3.080 to 4.910 LTC6946IUFD-2 0.513 to 0.818 0.616 to 0.982 0.770 to 1.228 1.027 to 1.637 1.540 to 2.455 3.080 to 4.910
3.840 to 5.790 LTC6946IUFD-3 0.640 to 0.965 0.768 to 1.158 0.960 to 1.448 1.280 to 1.930 1.920 to 2.895 3.840 to 5.790
4.200 to 6.390 LTC6946IUFD-4 0.700 to 1.065 0.840 to 1.278 1.050 to 1.598 1.400 to 2.130 2.100 to 3.195 4.200 to 6.390
Overlapping Frequency Bands
LTC6946
3
6946fb
For more information www.linear.com/LTC6946
elecTrical characTerisTics
The l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at TA = 25°C. VREF+ = VREF0+ = VD+ = VRF+ = 3.3V, VCP+ = VVCO+ = 5V unless
otherwise specified (Note 2). All voltages are with respect to GND.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Reference Inputs (REF+, REF–)
fREF Input Frequency l10 250 MHz
VREF Input Signal Level Single Ended, 1µF AC-Coupling Capacitors l0.5 2 2.7 VP-P
Input Slew Rate l20 V/µs
Input Duty Cycle 50 %
Self-Bias Voltage l1.65 1.85 2.25 V
Input Resistance Differential l6.2 8.4 11.6 kΩ
Input Capacitance Differential 3 pF
Reference Output (REFO)
fREFO Output Frequency l10 250 MHz
PREFO Output Power fREFO = 10MHz, RLOAD = 50Ω l–0.2 3.2 dBm
Output Impedance, Disabled 800 Ω
VCO
fVCO Frequency Range LTC6946-1 (Note 3)
LTC6946-2 (Note 3)
LTC6946-3 (Note 3)
LTC6946-4 (Note 3)
l
l
l
l
2.24
3.08
3.84
4.20
3.74
4.91
5.79
6.39
GHz
GHz
GHz
GHz
KVCO Tuning Sensitivity LTC6946-1 (Notes 3, 4)
LTC6946-2 (Notes 3, 4)
LTC6946-3 (Notes 3, 4)
LTC6946-4 (Notes 3, 4)
4.7 to 7.2
4.7 to 7.0
4.0 to 6.0
4.5 to 6.5
%Hz/V
%Hz/V
%Hz/V
%Hz/V
RF Output (RF+, RF–)
fRF Output Frequency l0.373 6.39 GHz
O Output Divider Range All Integers Included l1 6
Output Duty Cycle 50 %
Output Resistance Single Ended, Each Output to VRF+l111 136 159 Ω
Output Common Mode Voltage l2.4 VRF+V
PRF(SE) Output Power, Single Ended,
fRF = 900MHz
RFO[1:0] = 0, RZ = 50Ω, LC Match
RFO[1:0] = 1, RZ = 50Ω, LC Match
RFO[1:0] = 2, RZ = 50Ω, LC Match
RFO[1:0] = 3, RZ = 50Ω, LC Match
l
l
l
l
–9.7
–6.8
–3.9
–1.2
–6.0
–3.6
–0.4
2.3
dBm
dBm
dBm
dBm
Output Power, Muted RZ = 50Ω, Single Ended, fRF = 900MHz,
O = 2 to 6
l–60 dBm
Mute Enable Time l110 ns
Mute Disable Time l170 ns
Phase/Frequency Detector
fPFD Input Frequency l100 MHz
Lock Indicator, Available on the STAT Pin and via the SPI-Accessible Status Register
tLWW Lock Window Width LKWIN[1:0] = 0
LKWIN[1:0] = 1
LKWIN[1:0] = 2
LKWIN[1:0] = 3
3.0
10.0
30.0
90.0
ns
ns
ns
ns
tLWHYS Lock Window Hysteresis Increase in tLWW Moving from Locked State to
Unlocked State
22 %
LTC6946
4
6946fb
For more information www.linear.com/LTC6946
elecTrical characTerisTics
The l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at TA = 25°C. VREF+ = VREF0+ = VD+ = VRF+ = 3.3V, VCP+ = VVCO+ = 5V unless
otherwise specified (Note 2). All voltages are with respect to GND.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Charge Pump
ICP Output Current Range 12 Settings (See Table 5) 0.25 11.2 mA
Output Current Source/Sink Accuracy All Settings VCP = VCP+/2 ±6 %
Output Current Source/Sink Matching ICP = 250µA to 1.4mA, VCP = VCP+/2
ICP = 2.0mA to 11.2mA, VCP = VCP+/2
±3.5
±2
%
%
Output Current vs Output Voltage Sensitivity (Note 5) l0.1 1.0 %/V
Output Current vs Temperature VCP = VCP+/2 l170 ppm/°C
Output Hi-Z Leakage Current ICP = 700µA, CPCLO = CPCHI = 0 (Note 5)
ICP = 11.2mA, CPCLO = CPCHI = 0 (Note 5)
0.5
5
nA
nA
VCLMP(LO) Low Clamp Voltage CPCLO = 1 0.84 V
VCLMP(HI) High Clamp Voltage CPCHI = 1, Referred to VCP+–0.96 V
VMID Mid-Supply Output Bias Ratio Referred to (VCP+ – GND) 0.48 V/V
Reference (R) Divider
R Divide Range All Integers Included l1 1023 counts
VCO (N) Divider
N Divide Range All Integers Included l32 65535 counts
Digital Pin Specifications
VIH High Level Input Voltage MUTE, CS, SDI, SCLK l1.55 V
VIL Low Level Input Voltage MUTE, CS, SDI, SCLK l0.8 V
VIHYS Input Voltage Hysteresis MUTE, CS, SDI, SCLK 250 mV
Input Current MUTE, CS, SDI, SCLK l±1 µA
IOH High Level Output Current SDO and STAT, VOH = VD+ – 400mV l–2.3 – 1.4 mA
IOL Low Level Output Current SDO and STAT, VOL = 400mV l1.8 2.6 mA
SDO Hi-Z Current l±1 µA
Digital Timing Specifications (See Figures 7 and 8)
tCKH SCLK High Time l25 ns
tCKL SCLK Low Time l25 ns
tCSS CS Setup Time l10 ns
tCSH CS High Time l10 ns
tCS SDI to SCLK Setup Time l6 ns
tCH SDI to SCLK Hold Time l6 ns
tDO SCLK to SDO Time To VIH/VIL/Hi-Z with 30pF Load l16 ns
Power Supply Voltages
VREF+ Supply Range l3.15 3.3 3.45 V
VREFO+ Supply Range l3.15 3.3 3.45 V
VD+ Supply Range l3.15 3.3 3.45 V
VRF+ Supply Range l3.15 3.3 3.45 V
VVCO+ Supply Range l4.75 5.0 5.25 V
VCP+ Supply Range l4.0 5.25 V
LTC6946
5
6946fb
For more information www.linear.com/LTC6946
elecTrical characTerisTics
The l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at TA = 25°C. VREF+ = VREF0+ = VD+ = VRF+ = 3.3V, VCP+ = VVCO+ = 5V unless
otherwise specified (Note 2). All voltages are with respect to GND.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Power Supply Currents
IDD VD+ Supply Current Digital Inputs at Supply Levels l500 µA
ICC(5V) Sum VCP+, VVCO+ Supply Currents ICP = 11.2mA
ICP = 1.0mA
PDALL = 1
l
l
l
50
28
405
63
39
660
mA
mA
µA
ICC(REFO) VREFO+ Supply Currents REFO Enabled, RZ = ∞l7.8 9.0 mA
ICC (3.3V) Sum VREF+, VRF+ Supply Currents RF Muted, OD[2:0] = 1
RF Enabled, RFO[1:0] =0, OD[2:0] = 1
RF Enabled, RFO[1:0] = 3, OD[2:0] = 1
RF Enabled, RFO[1:0] =3, OD[2:0] = 2
RF Enabled, RFO[1:0] =3, OD[2:0] = 3
RF Enabled, RFO[1:0] =3, OD[2:0] = 4 to 6
PDALL = 1
l
l
l
l
l
l
l
65
76
85
103
108
113
195
76
86
97
117
123
128
340
mA
mA
mA
mA
mA
mA
µA
Phase Noise and Spurious
LMPhase Noise (LTC6946-1, fVCO = 3.0GHz, fRF
= 3.0GHz, OD[2 :0] = 1 (Note 6))
10kHz Offset
1MHz Offset
40MHz Offset
–80
–130
–157
dBc/Hz
dBc/Hz
dBc/Hz
Phase Noise (LTC6946-2, fVCO = 4.0GHz, fRF
= 4.0GHz, OD[2 :0] = 1 (Note 6))
10kHz Offset
1MHz Offset
40MHz Offset
–77
–127
–156
dBc/Hz
dBc/Hz
dBc/Hz
Phase Noise (LTC6946-3, fVCO = 5.0GHz, fRF
= 5.0GHz, OD[2 :0] = 1 (Note 6))
10kHz Offset
1MHz Offset
40MHz Offset
–75
–126
–155
dBc/Hz
dBc/Hz
dBc/Hz
VCO Phase Noise (LTC6946-4, fVCO =
6.0GHz, fRF = 6.0GHz, OD[2 :0] = 1 (Note 6))
10kHz Offset
1MHz Offset
40MHz Offset
–73
–132
–154
dBc/Hz
dBc/Hz
dBc/Hz
Phase Noise (LTC6946-3, fVCO = 5.0GHz, fRF
= 2.50GHz, OD[2 :0] = 2 (Note 6))
10kHz Offset
1MHz Offset
40MHz Offset
–81
–132
–155
dBc/Hz
dBc/Hz
dBc/Hz
Phase Noise (LTC6946-3, fVCO = 5.0GHz, fRF
= 1.667GHz, OD[2 :0] = 3 (Note 6))
10kHz Offset
1MHz Offset
40MHz Offset
–84
–135
–156
dBc/Hz
dBc/Hz
dBc/Hz
Phase Noise (LTC6946-3, fVCO = 5.0GHz, fRF
= 1.25GHz, OD[2 :0] = 4 (Note 6))
10kHz Offset
1MHz Offset
40MHz Offset
–87
–138
–156
dBc/Hz
dBc/Hz
dBc/Hz
Phase Noise (LTC6946-3, fVCO = 5.0GHz, fRF
= 1.00GHz, OD[2 :0] = 5 (Note 6))
10kHz Offset
1MHz Offset
40MHz Offset
–89
–140
–157
dBc/Hz
dBc/Hz
dBc/Hz
Phase Noise (LTC6946-3, fVCO = 5.0GHz, fRF
= 0.833GHz, OD[2 :0] = 6 (Note 6))
10kHz Offset
1MHz Offset
40MHz Offset
–90
–141
–158
dBc/Hz
dBc/Hz
dBc/Hz
LM(NORM) Normalized In-Band Phase Noise Floor ICP = 11.2mA (Notes 7, 8, 9) –226 dBc/Hz
LM(NORM – 1/f) Normalized In-Band 1/f Phase Noise ICP = 11.2mA (Notes 7, 10) –274 dBc/Hz
LM(IB) In-Band Phase Noise Floor (Notes 7, 8, 9, 11) –99 dBc/Hz
Integrated Phase Noise from
100Hz to 40MHz
(Notes 8, 12) 0.17 °RMS
Spurious fOFFSET = fPFD, PLL Locked (Notes 8, 12, 13) –103 dBc
LTC6946
6
6946fb
For more information www.linear.com/LTC6946
elecTrical characTerisTics
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC6946I is guaranteed to meet specified performance limits
over the full operating junction temperature range of –40°C to 105°C.
Under maximum operating conditions, air flow or heat sinking may
be required to maintain a junction temperature of 105°C or lower. It is
strongly recommended that the exposed pad (Pin 29) be soldered directly
to the ground plane with an array of thermal vias as described in the
Applications Information section.
Note 3: Valid for 1.60V ≤ TUNE ≤ 2.85V with part calibrated after a power
cycle or software power-on-reset (POR).
Note 4: Based on characterization.
Note 5: For 0.9V ≤ VCP ≤ (VCP+ – 0.9V).
Note 6: Measured outside the loop bandwidth, using a narrowband loop,
RFO[1:0] = 3.
Note 7: Measured inside the loop bandwidth with the loop locked.
Note 8: Reference frequency supplied by Wenzel 501-04608A,
fREF = 10MHz, PREF = 13dBm.
Note 9: Output phase noise floor is calculated from normalized phase
noise floor by LM(OUT) = –226 + 10log10 (fPFD) + 20log10 (fRF/fPFD).
Note 10: Output 1/f phase noise is calculated from normalized 1/f phase
noise by LM(OUT – 1/f) = –274 + 20log10 (fRF) – 10log10 (fOFFSET).
Note 11: ICP = 11.2mA, fPFD = 250kHz, FILT[1:0] = 3, Loop BW = 25kHz;
fRF = 900MHz, fVCO = 2.7GHz (LTC6946-1), fVCO = 3.6GHz (LTC6946-2),
fVCO = 4.5GHz (LTC6946-3, LTC6946-4).
Note 12: ICP = 11.2mA, fPFD = 1MHz, FILT[1:0] = 3, Loop BW = 40kHz;
fRF = 900MHz, fVCO = 2.7GHz (LTC6946-1), fVCO = 3.6GHz (LTC6946-2),
fVCO = 4.5GHz (LTC6946-3, LTC6946-4).
Note 13: Measured using DC1705.
LTC6946
7
6946fb
For more information www.linear.com/LTC6946
Typical perForMance characTerisTics
Charge Pump Sink Current Error
vs Voltage, Output Current
Charge Pump Source Current
Error vs Voltage, Temperature
Charge Pump Sink Current Error
vs Voltage, Temperature
RF Output Power vs Frequency
(Single Ended on RF–)
Charge Pump Source Current
Error vs Voltage, Output Current
RF Output HD2 vs Output Divide
(Single Ended on RF–)
REF Input Sensitivity
vs Frequency REF0 Output Power vs Frequency
TA = 25°C, VREF+ = VREFO+ = VD+ = VRF+ = 3.3V, VCP+ = VVCO+ = 5V, RFO[1:0] = 3,unless otherwise noted.
REFO Phase Noise
FREQUENCY (MHz)
0
SENSITIVITY (dBm)
–15
–20
–25
–30
–35
–40
–45
–50
–55
200
6946 G01
50 100 150
250
17525 75 125 225
BST = 1
FILT = 0
TJ = 105°C
TJ = 25°C
TJ = –40°C
FREQUENCY (MHz)
0
P
OUT
(dBm)
4
3
2
1
0
–1
–2
–3
–4
200
6946 G02
50 100 150
250
17525 75 125 225
TJ = 105°C
TJ = 25°C
TJ = –40°C
OFFSET FREQUENCY (Hz)
–155
PHASE NOISE (dBc/Hz)
–150
–145
–140
100 10k 100k 1M
6946 G03
–160
1k
POUT = 1.45dBm
fREF = 10MHz
BST = 1
FILT = 3
NOTE 8
OUTPUT VOLTAGE (V)
0
ERROR (%)
1
3
5
4
6946 G04
–1
–3
0
2
4
–2
–4
–5 10.5 21.5 3 3.5 4.5
2.5
5
250µA
1mA
11.2mA
OUTPUT VOLTAGE (V)
0
ERROR (%)
1
3
5
4
6946 G05
–1
–3
0
2
4
–2
–4
–5 10.5 21.5 3 3.5 4.5
2.5
5
TJ = 105°C
TJ = 25°C
TJ = –40°C
ICP = 11.2mA
OUTPUT VOLTAGE (V)
0
ERROR (%)
1
3
5
4
6946 G06
–1
–3
0
2
4
–2
–4
–5 10.5 21.5 3 3.5 4.5
2.5
5
250µA
1mA
11.2mA
OUTPUT VOLTAGE (V)
0
ERROR (%)
1
3
5
4
6946 G07
–1
–3
0
2
4
–2
–4
–5 10.5 21.5 3 3.5 4.5
2.5
5
TJ = 105°C
TJ = 25°C
TJ = –40°C
ICP = 11.2mA
FREQUENCY (GHz)
0.5
P
OUT
(dBm)
–2.5
0.5
1.0
1.5
1.5 3.53 4 4.5
6946 G08
–3.5
–0.5
–1.5
–3.0
0
–4.0
–1.0
–2.0
12 2.5 5 5.5 6
TJ = 105°C
TJ = 25°C
TJ = –40°C
LTC6946-3
LC = 68nH
CS = 100pF
fVCO (GHz)
3.75
–50
HD2 (dBc)
–45
–40
–35
–30
4.25 4.75 5.25 5.75
6946 G09
–25
–20
4.00 4.50 5.00 5.50
LTC6946-3, fRF = fVCO/O
LC = 68nH, CS = 100pF
O = 3
O = 2
O = 1
O = 6
O = 4
O = 5
LTC6946
8
6946fb
For more information www.linear.com/LTC6946
Typical perForMance characTerisTics
TA = 25°C, VREF+ = VREFO+ = VD+ = VRF+ = 3.3V, VCP+ = VVCO+ = 5V, RFO[1:0] = 3,unless otherwise noted.
LTC6946-1 VCO Tuning Sensitivity LTC6946-2 VCO Tuning Sensitivity LTC6946-3 VCO Tuning Sensitivity
RF Output HD3 vs Output Divide
(Single Ended on RF–)
MUTE Output Power vs fVCO and
Output Divide (Single Ended on RF–)
LTC6946-4 Frequency Step
Transient
LTC6946-1 VCO Phase Noise LTC6946-2 VCO Phase Noise
fVCO (GHz)
3.75
–40
HD3 (dBc)
–35
–30
–25
–20
4.25 4.75 5.25 5.75
6946 G10
–15
–10
–5
4.00 4.50 5.00 5.50
LTC6946-3
LC = 68nH
CS = 100pF
fRF = fVCO/O
O = 6
O = 3
O = 2
O = 1
O = 5O = 4
fVCO (MHz)
3800 4050
OUT
VCO
–70
–60
–50
5300 5550
–80
–90
4300 4550 4800 5050
–100
–110
LTC6946-3, LC = 68nH
CS = 100pF, fRF = fVCO/O
O = 1
O = 4
O = 6
O = 5
O = 2
O = 3
TIME (µs)
–5
0
5
10
15
20
25
30
35
4.5
4.7
4.9
5.1
5.3
5.5
5.7
5.9
FREQUENCY (GHz)
6946 G12
240MHz STEP
f
PFD
=10MHz
f
CAL
=1.25MHz
BW=123kHz
MTCAL = 0
CPCHI, CPCLO = 1
CALIBRATION
TIME
FREQUENCY (MHz)
2100
3.0
K
VCO
(%Hz/V)
3.5
4.5
5.0
5.5
8.0
6.5
2600 3100
6946 G13
4.0
7.0
7.5
6.0
3600
4100
FREQUENCY (MHz)
2800
3.0
K
VCO
(%Hz/V)
3.5
4.5
5.0
5.5
8.0
6.5
3300 3800 4300
6946 G14
4.0
7.0
7.5
6.0
4800
5300
FREQUENCY (MHz)
3500
2.5
K
VCO
(%Hz/V)
3.0
4.0
4.5
5.0
5500
7.0
6946 G15
3.5
4500
4000 6000
5000
6500
5.5
6.0
6.5
OFFSET FREQUENCY (Hz)
1k
–100
PHASE NOISE (dBc/Hz)
–90
–80
–70
–60
100k10k 1M 10M
40M
6946 G17
–110
–130
–150
–120
–140
–160
–50
–40
fVCO = fRF = 3GHz
OFFSET FREQUENCY (Hz)
1k
–100
PHASE NOISE (dBc/Hz)
–90
–80
–70
–60
100k10k 1M 10M
40M
6946 G18
–110
–130
–150
–120
–140
–160
–50
–40
fVCO = fRF = 4GHz
FREQUENCY (MHz)
4200
4600
5000
5400
5800
6200
6600
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
7.0
7.5
K
VCO
(%Hz/V)
6946 G16
LTC6946-4 VCO Tuning Sensitivity
LTC6946
9
6946fb
For more information www.linear.com/LTC6946
LTC6946-1 VCO Phase Noise vs
fVCO, Output Divide (fOFFSET = 1MHz)
LTC6946-1 VCO Phase Noise vs fVCO,
Output Divide (fOFFSET = 10kHz)
LTC6946-2 VCO Phase Noise vs
fVCO, Output Divide (fOFFSET = 10kHz)
LTC6946-2 VCO Phase Noise vs
fVCO, Output Divide (fOFFSET = 1MHz)
LTC6946-3 VCO Phase Noise vs
fVCO, Output Divide (fOFFSET = 10kHz)
LTC6946-3 VCO Phase Noise vs fVCO,
Output Divide (fOFFSET = 1MHz)
Typical perForMance characTerisTics
TA = 25°C, VREF+ = VREFO+ = VD+ = VRF+ = 3.3V, VCP+ = VVCO+ = 5V, RFO[1:0] = 3,unless otherwise noted.
fVCO (MHz)
2200
–105
PHASE NOISE (dBc/Hz)
–100
–95
–90
–85
–75
2450 2700 2950 3200
6946 G21
3450
3700
–80
fRF = fVCO/O O = 1
O = 2
O = 3
O = 6O = 5O = 4
fVCO (MHz)
3000
–100
PHASE NOISE (dBc/Hz)
–95
–90
–85
–80
–70
3250 3500 3750 4000 4250
6946 G22
4500 4750
–75
fRF = fVCO/O
O = 1
O = 2
O = 3
O = 6
O = 5
O = 4
fVCO (MHz)
3800
PHASE NOISE (dBc/Hz)
–80
–75
–70
4550 5050
5800
6946 G23
–85
–90
–95
4050 4300 4800 5300 5550
fRF = fVCO/O
O = 1
O = 2
O = 3
O = 4
O = 6 O = 5
fVCO (MHz)
2200
–150
PHASE NOISE (dBc/Hz)
–145
–140
–135
–125
2450 2700 2950 3200
6946 G25
3450
3700
–130
fRF = fVCO/O
O = 1
O = 2
O = 3
O = 6
O = 4
O = 5
fVCO (MHz)
3000
–150
PHASE NOISE (dBc/Hz)
–145
–140
–135
–125
3250 3500 3750 4000 4250
6946 G26
4500 4750
–130
fRF = fVCO/O
O = 1
O = 2
O = 3
O = 6
O = 5
O = 4
fVCO (MHz)
3800
PHASE NOISE (dBc/Hz)
–130
–125
–120
4550 5050
5800
6946 G27
–135
–140
–145
4050 4300 4800 5300 5550
fRF = fVCO/O
O = 1
O = 2
O = 3
O = 4
O = 6
O = 5
LTC6946-3 VCO Phase Noise
OFFSET FREQUENCY (Hz)
1k
–100
PHASE NOISE (dBc/Hz)
–90
–80
–70
–60
100k10k 1M 10M
40M
6946 G19
–110
–130
–150
–120
–140
–160
–50
–40
fVCO = fRF = 5GHz
OFFSET FREQUENCY (Hz)
1k
10k
100k
1M
10M
40M
–160
–150
–140
–130
–120
–110
–100
–90
–80
–70
–60
–50
–40
PHASE NOISE (dBc / Hz)
6946 G20
f
VCO
= f
RF
= 6GHz
LTC6946-4 VCO Phase Noise
f
VCO
(MHz)
4200
4600
5000
5400
5800
6200
6600
–95
–90
–85
–80
–75
–70
PHASE NOISE (dBc/Hz)
6946 G24
f
RF
= f
VCO
/O
O = 1
O = 2
O = 3
O = 4
O = 5
O = 6
LTC6946-4 VCO Phase Noise vs
fVCO, Output Divide (fOFFSET = 10kHz)
LTC6946
10
6946fb
For more information www.linear.com/LTC6946
Closed-Loop Phase Noise, Loop
Bandwidth = 40kHz, LTC6946-1
LTC6946-3 Spurious Response
fRF = 900MHz, fREF = 10MHz,
fPFD = 1MHz, Loop BW = 40kHz
LTC6946-3 Spurious Response
fRF = 2200MHz, fREF = 10MHz,
fPFD = 0.4MHz, Loop BW = 28kHz
LTC6946-3 Spurious Response
fRF = 5700MHz, fREF = 100MHz,
fPFD = 1MHz, Loop BW = 33kHz
Closed-Loop Phase Noise, Loop
Bandwidth = 25kHz, LTC6946-3
LTC6946-2 Supply Current
vs Temperature
Typical perForMance characTerisTics
TA = 25°C, VREF+ = VREFO+ = VD+ = VRF+ = 3.3V, VCP+ = VVCO+ = 5V, RFO[1:0] = 3,unless otherwise noted.
OFFSET FREQUENCY (Hz)
–140
PHASE NOISE (dBc/Hz)
–130
–110
–90
100 10k 100k 10M
40M
6946 G29
–150
1k 1M
–100
–120
–160
RMS NOISE = 0.169°
fRF = 900MHz
fPFD = 1MHz
OD = 3
fSTEP = 333.3kHz
NOTE 12
OFFSET FREQUENCY (Hz)
–140
PHASE NOISE (dBc/Hz)
–130
–110
–90
100 10k 100k 10M
40M
6946 G30
–150
1k 1M
–100
–120
–160
RMS NOISE = 0.276°
fRF = 900MHz
fPFD = 250kHz
OD = 5
fSTEP = 50kHz
NOTE 11
TJ (°C)
–40
80
3.3V CURRENT (mA)
5V CURRENT (mA)
82
84
86
–20 020 40
6946 G31
60
88
90
81
83
85
87
89
45
47
49
51
53
55
46
48
50
52
54
80 100
PDREFO = 1
O = 1
RFO = 3
MUTE = 0
ICP = 11.2mA
FREQUENCY OFFSET (MHz IN 10kHz SEGMENTS)
–10
–105dBc –103dBc
–111dBc –109dBc
–3
–140
POUT (dBm)
–120
–100
–80
123
0
6946 G32
–2 –1 0 10
–60
–40
–20
RBW = 1Hz
VBW = 1Hz
NOTES 8, 13
FREQUENCY OFFSET (MHz IN 10kHz SEGMENTS)
–10
–93dBc –94dBc
–86dBc –88dBc
–1.2
–140
POUT (dBm)
–120
–100
–80
0.4 0.8 1.2
0
6946 G33
–0.8 –0.4 0 10
–60
–40
–20
RBW = 1Hz
VBW = 1Hz
NOTES 8, 13
FREQUENCY OFFSET (MHz IN 10kHz SEGMENTS)
–100
–101dBc –113dBc
–96dBc –92dBc
–3
–140
POUT (dBm)
–120
–100
–80
123
0
6946 G34
–2 –1 0 100
–60
–40
–20
RBW = 1Hz
VBW = 1Hz
NOTE 13
f
VCO
(MHz)
4200
4600
5000
5400
5800
6200
6600
–145
–140
–135
–130
–125
–120
PHASE NOISE (dBc/Hz)
6946 G28
f
RF
= f
VCO
/O
O = 1
O = 2
O = 3
O = 4
O = 5
O = 6
LTC6946-4 VCO Phase Noise vs
fVCO, Output Divide (fOFFSET = 1MHz)
LTC6946
11
6946fb
For more information www.linear.com/LTC6946
pin FuncTions
VREFO+ (Pin 1): 3.15V to 3.45V Positive Supply Pin for
REFO Circuitry. This pin should be bypassed directly to
the ground plane using a 0.1µF ceramic capacitor as close
to the pin as possible.
REFO (Pin 2): Reference Frequency Output. This produces
a low noise square wave, buffered from the REF± differential
inputs. The output is self-biased and must be AC-coupled
with a 22nF capacitor.
STAT (Pin 3): Status Output. This signal is a configurable
logical OR combination of the UNLOCK, LOCK, ALCHI,
ALCLO, THI and TLO status bits, programmable via the
STATUS register. See the Operation section for more details.
CS (Pin 4): Serial Port Chip Select. This CMOS input initi-
ates a serial port communication burst when driven low,
ending the burst when driven back high. See the Operation
section for more details.
SCLK (Pin 5): Serial Port Clock. This CMOS input clocks
serial port input data on its rising edge. See the Operation
section for more details.
SDI (Pin 6): Serial Port Data Input. The serial port uses
this CMOS input for data. See the Operation section for
more details.
SDO (Pin 7): Serial Port Data Output. This CMOS three-
state output presents data from the serial port during a
read communication burst. Optionally attach a resistor
of >200k to GND to prevent a floating output. See the
Operation section for more details.
VD+ (Pin 8): 3.15V to 3.45V Positive Supply Pin for Serial
Port Circuitry. This pin should be bypassed directly to the
ground plane using a 0.1µF ceramic capacitor as close to
the pin as possible.
MUTE (Pin 9): RF Mute. The CMOS active-low input mutes
the RF± differential outputs while maintaining internal bias
levels for quick response to de-assertion.
GND (Pins 10, 17, 21): Negative Power Supply (Ground).
These pins should be tied directly to the ground plane with
multiple vias for each pin.
RF–, RF+ (Pins 11, 12): RF Output Signals. The VCO
output divider is buffered and presented differentially on
these pins. The outputs are open collector, with 136Ω
(typical) pull-up resistors tied to VRF+ to aid impedance
matching. If used single ended, the unused output should
be terminated to 50Ω. See the Applications Information
section for more details on impedance matching.
VRF+ (Pin 13): 3.15V to 3.45V Positive Supply Pin for
RF Circuitry. This pin should be bypassed directly to the
ground plane using a 0.01µF ceramic capacitor as close
to the pin as possible.
BB (Pin 14): RF Reference Bypass. This output must be
bypassed with a 1.0µF ceramic capacitor to GND. Do not
couple this pin to any other signal.
TUNE (Pin 15): VCO Tuning Input. This frequency control
pin is normally connected to the external loop filter. See
the Applications Information section for more details.
TB (Pin 16): VCO Bypass. This output must be bypassed
with a 2.2µF ceramic capacitor to GND, and is normally
connected to CMA, CMB and CMC with a short trace. Do
not couple this pin to any other signal.
CMC, CMB, CMA (Pins 18, 19, 20): VCO Bias Inputs. These
inputs are normally connected to TB with a short trace
and bypassed with a 2.2µF ceramic capacitor to GND. Do
not couple these pins to any other signal. For best phase
noise performance, do not place a trace between these
pads underneath the package.
VVCO+ (Pin 22): 4.75V to 5.25V Positive Supply Pin for
VCO Circuitry. This pin should be bypassed directly to the
ground plane using both 0.01µF and 1µF ceramic capaci-
tors as close to the pin as possible.
LTC6946
12
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For more information www.linear.com/LTC6946
pin FuncTions
GND (23): Negative Power Supply (Ground). This pin is
attached directly to the die attach paddle (DAP) and should
be tied directly to the ground plane.
VCP+ (Pin 24): 4.0V to 5.25V Positive Supply Pin for Charge
Pump Circuitry. This pin should be bypassed directly to
the ground plane using a 0.1µF ceramic capacitor as close
to the pin as possible.
CP (Pin 25): Charge Pump Output. This bi-directional cur-
rent output is normally connected to the external loop filter.
See the Applications Information section for more details.
VREF+ (Pin 26): 3.15V to 3.45V Positive Supply Pin for
Reference Input Circuitry. This pin should be bypassed
directly to the ground plane using a 0.1µF ceramic capaci-
tor as close to the pin as possible.
REF+, REF– (Pins 27, 28): Reference Input Signals. This
differential input is buffered with a low noise amplifier,
which feeds the reference divider and reference buffer.
They are self-biased and must be AC-coupled with 1µF
capacitors. If used single ended, bypass REF– to GND
with a 1µF capacitor. If the single-ended signal is greater
than 2.7VP-P, bypass REF– to GND with a 47pF capacitor.
GND (Exposed Pad Pin 29): Negative Power Supply
(Ground). The package exposed pad must be soldered
directly to the PCB land. The PCB land pattern should
have multiple thermal vias to the ground plane for both
low ground inductance and also low thermal resistance.
LTC6946
13
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For more information www.linear.com/LTC6946
block DiagraM
RF–
28
2
3
11
GND
10
MUTE
9
RF+
12
VRF+
13
27
REF–
REFO
≤250MHz
≤100MHz
÷1 TO 1023
÷1 TO 6, 50%
÷32 TO 65535
0.373GHz TO
6.39GHz
MUTE
1VREFO+
REF+
26
VREF+
R_DIV
LOCK
PFD
O_DIV
N_DIV
B_DIV
CAL, ALC
CONTROL
2.24GHz TO 3.74GHz (LTC6946-1) OR
3.08GHz TO 4.91GHz (LTC6946-2) OR
3.84GHz TO 5.79GHz (LTC6946-3) OR
4.20GHz TO 6.39GHz (LTC6946-4)
TUNE 15
CP
VVCO+
GND
CMA
CMB
CMC
GND
250µA TO
11.2mA 25
22
21
20
19
18
17
24
VCP+
23
GND
16
TB
6946 BD
14
BB
SERIAL
PORT
STAT
CS
7SDO
SDI
SCLK
8VD+
6
5
4
LTC6946
14
6946fb
For more information www.linear.com/LTC6946
operaTion
The LTC6946 is a high performance PLL complete with
a low noise VCO available in three different frequency
range options. The output frequency range may be further
extended by utilizing the output divider (see Available Op-
tions table, for more details). The device is able to achieve
superior integrated phase noise by the combination of
its extremely low in-band phase noise performance and
excellent VCO noise characteristics.
REFERENCE INPUT BUFFER
The PLL’s reference frequency is applied differentially on
pins REF+ and REF–. These high impedance inputs are
self-biased and must be AC-coupled with 1µF capacitors
(see Figure 1 for a simplified schematic). Alternatively, the
inputs may be used single ended by applying the refer-
ence frequency at REF+ and bypassing REF– to GND with
a 1µF capacitor. If the single-ended signal is greater than
2.7VP-P, then use a 47pF capacitor for the GND bypass.
27
28
4.2k
REF+
REF–
4.2k
6946 F01
1.9V
BST
BIAS
VREF+VREF+
LOWPASS
FILT[1:0]
Figure 1. Simplified REF Interface Schematic
The BST bit should be set based upon the input signal level
to prevent the reference input buffer from saturating. See
Table 2 for recommended settings and the Applications
Information section for programming examples.
Table 1. FILT[1:0] Programming
FILT[1:0] fREF
3 <20MHz
2 NA
1 20MHz to 50MHz
0 >50MHz
Table 2. BST Programming
BST VREF
1 <2.0VP-P
0 ≥2.0VP-P
REFERENCE OUTPUT BUFFER
The reference output buffer produces a low noise square
wave with a noise floor of –155dBc/Hz (typical) at 10MHz.
Its output is low impedance, and produces 0dBm typical
output power into a 50Ω load at 10MHz. Larger output
swings will result if driving larger impedances. The out-
put is self-biased, and must be AC-coupled with a 22nF
capacitor (see Figure 2 for a simplified schematic). The
buffer may be powered down by using bit PDREFO found
in the serial port Power register h02.
2
REFO
VREFO+
800Ω
6946 F02
Figure 2. Simplified REFO Interface Schematic
A high quality signal must be applied to the REF± inputs
as they provide the frequency reference to the entire PLL.
To achieve the part’s in-band phase noise performance,
apply a CW signal of at least 6dBm into 50Ω, or a square
wave of at least 0.5VP-P with slew rate of at least 40V/µs.
Additional options are available through serial port register
h08 to further refine the application. Bits FILT[1:0] control
the reference input buffer’s lowpass filter, and should be
set based upon fREF to limit the reference’s wideband
noise. The FILT[1:0] bits must be set correctly to reach
the LM(NORM) normalized in-band phase noise floor. See
Table 1 for recommended settings.
LTC6946
15
6946fb
For more information www.linear.com/LTC6946
REFERENCE (R) DIVIDER
A 10-bit divider, R_DIV, is used to reduce the frequency
seen at the PFD. Its divide ratio R may be set to any
integer from 1 to 1023, inclusive. Use the RD[9:0] bits
found in registers h03 and h04 to directly program the R
divide ratio. See the Applications Information section for
the relationship between R and the fREF
, fPFD, fVCO and
fRF frequencies.
PHASE/FREQUENCY DETECTOR (PFD)
The phase/frequency detector (PFD), in conjunction with
the charge pump, produces source and sink current pulses
proportional to the phase difference between the outputs
of the R and N dividers. This action provides the necessary
feedback to phase-lock the loop, forcing a phase align-
ment at the PFD’s inputs. The PFD may be disabled with
the CPRST bit which prevents UP and DOWN pulses from
being produced. See Figure 3 for a simplified schematic
of the PFD.
operaTion
D Q
RST
N DIV
D Q
RST
CPRST
UP
DOWN
6946 F03
DELAY
R DIV
Figure 3. Simplified PFD Schematic
The user sets the phase difference lock window time,
tLWW, for a valid LOCK condition with the LKWIN[1:0]
bits. See Table 3 for recommended settings for different
FPFD frequencies and the Applications Information sec-
tion for examples.
Table 3. LKWIN[1:0] Programming
LKWIN[1:0] tLWW fPFD
0 3ns >5MHz
1 10ns ≤5MHz
2 30ns ≤1.7MHz
3 90ns ≤550kHz
The PFD phase difference must be less than tLWW for the
LOKCNT number of successive counts before the lock
indicator asserts the LOCK flag. The LKCNT[1:0] bits found
in register h09 are used to set LOKCNT depending upon
the application. See Table 4 for LKCNT[1:0] programming
and the Applications Information section for examples.
Table 4. LKCNT[1:0] Programming
LKCNT[1:0] COUNTS
0 32
1 128
2 512
3 2048
When the PFD phase difference is greater than tLWW
, the
lock indicator immediately asserts the UNLOCK status
flag and clears the LOCK flag, indicating an out-of-lock
condition. The UNLOCK flag is immediately de-asserted
when the phase difference is less than tLWW
. See Figure 4
for more details.
LOCK INDICATOR
The lock indicator uses internal signals from the PFD to
measure phase coincidence between the R and N divider
output signals. It is enabled by setting the LKEN bit in
the serial port register h07, and produces both LOCK and
UNLOCK status flags, available through both the STAT
output and serial port register h00.
+tLWW
–tLWW
UNLOCK FLAG
LOCK FLAG t = COUNTS/fPFD
6946 F04
0
PHASE
DIFFERENCE
AT PFD
Figure 4. UNLOCK and LOCK Timing
LTC6946
16
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For more information www.linear.com/LTC6946
operaTion
CHARGE PUMP
The charge pump, controlled by the PFD, forces sink
(DOWN) or source (UP) current pulses onto the CP pin,
which should be connected to an appropriate loop filter.
See Figure 5 for a simplified schematic of the charge pump.
The CPINV bit found in register h0A should be set for
applications requiring signal inversion from the PFD,
such as for complex external loops using an inverting op
amp. A passive loop filter as shown in Figure 14 requires
CPINV = 0.
CHARGE PUMP FUNCTIONS
The charge pump contains additional features to aid
in system start-up and monitoring. See Table 6 for a
summary.
Table 6. Charge Pump Function Bit Descriptions
BIT DESCRIPTION
CPCHI Enable High Voltage Output Clamp
CPCLO Enable Low Voltage Output Clamp
CPDN Force Sink Current
CPINV Invert PFD Phase
CPMID Enable Mid-Voltage Bias
CPRST Reset PFD
CPUP Force Source Current
CPWIDE Extend Current Pulse Width
THI High Voltage Clamp Flag
TLO Low Voltage Clamp Flag
The CPCHI and CPCLO bits found in register h0A enable
the high and low voltage clamps, respectively. When
CPCHI is enabled and the CP pin voltage exceeds ap-
proximately VCP+ – 0.9V, the THI status flag is set, and
the charge pump sourcing current is disabled. Alternately,
when CPCLO is enabled and the CP pin voltage is less
than approximately 0.9V, the TLO status flag is set, and
the charge pump sinking current is disabled. See Figure
5 for a simplified schematic.
The CPMID bit also found in register h0A enables a resis-
tive VCP+/2 output bias which may be used to pre-bias
troublesome loop filters into a valid voltage range. When
using CPMID, it is recommended to also assert the CPRST
bit, forcing a PFD reset. Both CPMID and CPRST must be
set to “0” for normal operation.
25
+
–
+
–
CP
THI
0.9V
VCP+
VCP+
TLO
+
–
0.9V
6946 F05
+
–
VCP+/2
CPMID
CPUP
UP
CPDN
DOWN
Figure 5. Simplified Charge Pump Schematic
The output current magnitude ICP may be set from 250µA to
11.2mA using the CP[3:0] bits found in serial port register
h09. A larger ICP can result in lower in-band noise due to
the lower impedance of the loop filter components. See
Table 5 for programming specifics and the Applications
Information section for loop filter examples.
Table 5. CP[3:0] Programming
CP[3:0] ICP
0 250µA
1 350µA
2 500µA
3 700µA
4 1.0mA
5 1.4mA
6 2.0mA
7 2.8mA
8 4.0mA
9 5.6mA
10 8.0mA
11 11.2mA
12 to 15 Invalid
LTC6946
17
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For more information www.linear.com/LTC6946
operaTion
The CPUP and CPDN bits force a constant ICP source or
sink current, respectively, on the CP pin. The CPRST bit
may also be used in conjunction with the CPUP and CPDN
bits, allowing a pre-charge of the loop to a known state,
if required. CPUP, CPDN, and CPRST must be set to “0”
to allow the loop to lock.
The CPWIDE bit extends the charge pump output current
pulse width by increasing the PFD reset path’s delay value
(see Figure 3). CPWIDE is normally set to 0.
VCO
The integrated VCO is available in one of three frequency
ranges. The output frequency range may be further ex-
tended by utilizing the output divider (see Available Options
table, for more details). The wide frequency range of the
VCO, coupled with the output divider capability, allows the
LTC6946 to cover an extremely wide range of continuously
selectable frequencies.
VCO Calibration
The VCO must be calibrated each time its frequency is
changed by either fREF
, the R divider, or N divider, but not
the O divider (see the Applications Information section for
the relationship between R, N, O, and the fREF
, fPFD, fVCO
and fRF frequencies). The output frequency is then stable
over the LTC6946’s entire temperature range, regardless
of the temperature at which it was calibrated, until the
part is reset due to a power cycle or software power-on
reset (POR).
The output of the B divider is used to clock digital calibra-
tion circuitry as shown in the Block Diagram. The B value,
programmed with bits BD[3:0], is determined according
to Equation 1.
B≥
f
PFD
f
CAL-MAX
(1)
The maximum calibration frequency fCAL-MAX for each part
option is shown in Table 7.
Table 7. Maximum Calibration Frequency
PART fCAL-MAX (MHz)
LTC6946-1 1.0
LTC6946-2 1.33
LTC6946-3 1.7
LTC6946-4 1.8
The relationship between bits BD[3:0] and the B value is
shown in Table 8.
Table 8. BD[3:0] Programming
BD[3:0] B DIVIDE VALUE
0 8
1 12
2 16
3 24
4 32
5 48
6 64
7 96
8 128
9 192
10 256
11 384
12 to 15 Invalid
The VCO may be calibrated once the RD[9:0], ND[15:0],
and BD[3:0] bits are written. The reference frequency fREF
must also be present and stable at the REF± inputs.
A calibration cycle is initiated each time the CAL bit is writ-
ten to “1” (the bit is self-clearing). The calibration cycle
takes between 12 and 14 cycles of the B divider output.
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VCO Automatic Level Control (ALC)
The VCO uses an internal automatic level control (ALC)
algorithm to maintain an optimal amplitude on the VCO
resonator, and thus optimal phase noise performance. The
user has several ALC configuration and status reporting
options as seen in Table 9.
Table 9. ALC Bit Descriptions
BIT DESCRIPTION
ALCCAL Auto Enable ALC During CAL Operation
ALCEN Always Enable ALC (Overrides ALCCAL, ALCMON and
ALCULOK)
ALCHI ALC Too High Flag (Resonator Amplitude Too High)
ALCLO ALC Too Low Flag (Resonator Amplitude Too Low)
ALCMON Enable ALC Monitoring for Status Flags Only; Does NOT
Enable Amplitude Control
ALCULOK Auto Enable ALC when PLL Unlocked
Changes in the internal ALC output can cause extremely
small jumps in the VCO frequency. These jumps may be
acceptable in some applications but not in others. Use the
above table to choose when the ALC is active. The ALCHI
and ALCLO flags, valid only when the ALC is active or the
ALCMON bit is set, may be used to monitor the resonator
amplitude.
The ALC must be allowed to operate during or after a
calibration cycle. At least one of the ALCCAL, ALCEN or
ALCULOK bits must be set.
VCO (N) DIVIDER
The 16-bit N divider provides the feedback from the VCO
to the PFD. Its divide ratio N may be set to any integer
from 32 to 65535, inclusive. Use the ND[15:0] bits found
in registers h05 and h06 to directly program the N divide
ratio. See the Applications Information section for the
relationship between N and the fREF
, fPFD, fVCO and fRF
frequencies.
OUTPUT (O) DIVIDER
The 3-bit O divider can reduce the frequency from the VCO
to extend the output frequency range. Its divide ratio O
may be set to any integer from 1 to 6, inclusive, outputting
a 50% duty cycle even with odd divide values. Use the
OD[2:0] bits found in register h08 to directly program the
0 divide ratio. See the Applications Information section
for the relationship between O and the fREF
, fPFD, fVCO and
fRF frequencies.
RF OUTPUT BUFFER
The low noise, differential output buffer produces a dif-
ferential output power of –6dBm to 3dBm, settable with
bits RFO[1:0] according to Table 10. The outputs may be
combined externally, or used individually. Terminate any
unused output with a 50Ω resistor to VRF+.
Table 10. RFO[1:0] Programming
RFO[1:0} PRF (Differential) PRF (Single Ended)
0 –6dBm –9dBm
1 –3dBm –6dBm
2 0dBm –3dBm
3 3dBm 0dBm
Each output is open collector with 136Ω pull-up resistors
to VRF+, easing impedance matching at high frequencies.
See Figure 6 for circuit details and the Applications Infor-
mation section for matching guidelines. The buffer may
be muted with either the OMUTE bit, found in register
h02, or by forcing the MUTE input low.
12
11
6946 F06
VRF
+
VRF
+
RF+
136Ω136Ω
RF–
MUTE
OMUTE
RFO[1:0]
9MUTE
Figure 6. Simplified RF Interface Schematic
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SERIAL PORT
The SPI-compatible serial port provides control and moni-
toring functionality. A configurable status output, STAT,
gives additional instant monitoring.
Communication Sequence
The serial bus is comprised of CS, SCLK, SDI and SDO.
Data transfers to the part are accomplished by the se-
rial bus master device first taking CS low to enable the
LTC6946’s port. Input data applied on SDI is clocked on
the rising edge of SCLK, with all transfers MSB first. The
communication burst is terminated by the serial bus master
returning CS high. See Figure 7 for details.
Data is read from the part during a communication burst
using SDO. Readback may be multidrop (more than one
LTC6946 connected in parallel on the serial bus), as SDO
is three-stated (Hi-Z) when CS = 1, or when data is not
being read from the part. If the LTC6946 is not used in
a multidrop configuration, or if the serial port master is
not capable of setting the SDO line level between read
sequences, it is recommended to attach a high value
resistor of greater than 200k between SDO and GND to
ensure the line returns to a known level during Hi-Z states.
See Figure 8 for details.
Single Byte Transfers
The serial port is arranged as a simple memory map, with
status and control available in 12, byte-wide registers. All
data bursts are comprised of at least two bytes. The 7 most
significant bits of the first byte are the register address,
with an LSB of 1 indicating a read from the part, and LSB
of 0 indicating a write to the part. The subsequent byte,
or bytes, is data from/to the specified register address.
See Figure 9 for an example of a detailed write sequence,
and Figure 10 for a read sequence.
Figure 11 shows an example of two write communication
bursts. The first byte of the first burst sent from the serial
bus master on SDI contains the destination register address
(Addr0) and an LSB of “0” indicating a write. The next byte
is the data intended for the register at address Addr0. CS is
then taken high to terminate the transfer. The first byte of
the second burst contains the destination register address
(Addr1) and an LSB indicating a write. The next byte on
SDI is the data intended for the register at address Addr1.
CS is then taken high to terminate the transfer.
MASTER–CS
MASTER–SCLK
tCSS
tCS tCH
DATA DATA
6946 F07
tCKL tCKH
tCSS
tCSH
MASTER–SDI
MASTER–CS
MASTER–SCLK
LTC6946–SDO Hi-Z Hi-Z
6946 F08
8TH CLOCK
DATA DATA
tDO
tDO
tDO tDO
Figure 7. Serial Port Write Timing Diagram
Figure 8. Serial Port Read Timing Diagram
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Multiple Byte Transfers
More efficient data transfer of multiple bytes is accom-
plished by using the LTC6946’s register address auto-
increment feature as shown in Figure 12. The serial port
master sends the destination register address in the first
byte and its data in the second byte as before, but continues
sending bytes destined for subsequent registers. Byte 1’s
address is Addr0+1, Byte 2’s address is Addr0+2, and so
on. If the resister address pointer attempts to increment
past 11 (h0B), it is automatically reset to 0.
An example of an auto-increment read from the part is
shown in Figure 13. The first byte of the burst sent from
the serial bus master on SDI contains the destination reg-
ister address (Addr0) and an LSB of “1” indicating a read.
Once the LTC6946 detects a read burst, it takes SDO out
of the Hi-Z condition and sends data bytes sequentially,
A6 A5 A4 A3 A2
7-BIT REGISTER ADDRESS
Hi-Z
MASTER–CS
MASTER–SCLK
MASTER–SDI
LTC6946–SD0
A1 A0 0D7 D6 D5 D4 D3 D2 D1 D0
8 BITS OF DATA
0 = WRITE
6946 F09
16 CLOCKS
Addr0 + Wr
Hi-Z
MASTER–CS
MASTER–SDI
LTC6946–SDO
Byte 0 Addr1 + Wr Byte 1
6946 F11
Addr0 + Wr
Hi-Z
MASTER–CS
MASTER–SDI
LTC6946–SDO
Byte 0 Byte 1 Byte 2
6946 F12
Figure 9. Serial Port Write Sequence
Figure 10. Serial Port Read Sequence
Figure 11. Serial Port Single Byte Write
Figure 12. Serial Port Auto-Increment Write
A6 A5 A4 A3 A2
7-BIT REGISTER ADDRESS
Hi-Z Hi-Z
A1 A0 1
D7X D6 D5 D4 D3 D2 D1 D0 DX
8 BITS OF DATA
1 = READ
6946 F10
MASTER–CS
MASTER–SCLK
MASTER–SDI
LTC6946–SDO
16 CLOCKS
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Addr0 + Rd DON’T CARE
Hi-Z Hi-Z
MASTER–CS
MASTER–SDI
LTC6946–SDO
6946 F13
Byte 0 Byte 1 Byte 2
Figure 13. Serial Port Auto-Increment Read
beginning with data from register Addr0. The part ignores
all other data on SDI until the end of the burst.
Multidrop Configuration
Several LTC6946s may share the serial bus. In this mul-
tidrop configuration, SCLK, SDI, and SDO are common
between all parts. The serial bus master must use a separate
CS for each LTC6946 and ensure that only one device has
CS asserted at any time. It is recommended to attach a
high value resistor to SDO to ensure the line returns to a
known level during Hi-Z states.
Serial Port Registers
The memory map of the LTC6946 may be found in Table 11,
with detailed bit descriptions found in Table 12. The register
address shown in hexadecimal format under the ADDR
column is used to specify each register. Each register is
denoted as either read-only (R) or read-write (R/W). The
register’s default value on device power-up or after a reset
is shown at the right.
The read-only register at address h00 is used to determine
different status flags. These flags may be instantly output
on the STAT pin by configuring register h01. See the STAT
Output section for more information.
The read-only register at address h0B is a ROM byte for
device identification.
Table 11. Serial Port Register Contents
ADDR MSB [6] [5] [4] [3] [2] [1] LSB R/W DEFAULT
h00 * * UNLOCK ALCHI ALCLO LOCK THI TLO R
h01 * * x[5] x[4] x[3] x[2] x[1] x[0] R/W h04
h02 PDALL PDPLL PDVCO PDOUT PDREFO MTCAL OMUTE POR R/W h0E
h03 BD[3] BD[2] BD[1] BD[0] * * RD[9] RD[8] R/W h30
h04 RD[7] RD[6] RD[5] RD[4] RD[3] RD[2] RD[1] RD[0] R/W h01
h05 ND[15] ND[14] ND[13] ND[12] ND[11] ND[10] ND[9] ND[8] R/W h00
h06 ND[7] ND[6] ND[5] ND[4] ND[3] ND[2] ND[1] ND[0] R/W hFA
h07 ALCEN ALCMON ALCCAL ALCULOK * * CAL LKEN R/W h21
h08 BST FILT[1] FILT[0] RFO[1] RFO[0] OD[2] OD[1] OD[0] R/W hF9
h09 LKWIN[1] LKWIN[0] LKCT[1] LKCT[0] CP[3] CP[2] CP[1] CP[0] R/W h9B
h0A CPCHI CPCLO CPMID CPINV CPWIDE CPRST CPUP CPDN R/W hE4
h0B REV[2] REV[1] REV[0] PART[4] PART[3] PART[2] PART[1] PART[0] R hxx†
*unused †varies depending on version
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STAT Output
The STAT output pin is configured with the x[5:0] bits
of register h01. These bits are used to bit-wise mask, or
enable, the corresponding status flags of status register
h00, according to Equation 2. The result of this bit-wise
Boolean operation is then output on the STAT pin:
STAT = OR (Reg00[5:0] AND Reg01[5:0]) (2)
or expanded:
STAT = (UNLOCK AND x[5]) OR
(ALCHI AND x[4]) OR
(ALCLO AND x[3]) OR
(LOCK AND x[2]) OR
(THI AND x[1]) OR
(TLO AND x[0])
For example, if the application requires STAT to go high
whenever the ALCHI, ALCLO, or THI flags are set, then
x[4], x[3], and x[1] should be set to “1”, giving a register
value of h1A.
Block Power-Down Control
The LTC6946’s power-down control bits are located in
register h02, described in Table 12. Different portions of
the device may be powered down independently. Care must
be taken with the LSB of the register, the POR (power-on
reset) bit. When written to a “1”, this bit forces a full reset
of the part’s digital circuitry to its power-up default state.
Table 12. Serial Port Register Bit Field Summary
BITS DESCRIPTION DEFAULT
ALCCAL Auto Enable ALC During CAL Operation 1
ALCEN Always Enable ALC (Override) 1
ALCHI ALC Too Hi Flag
ALCLO ALC Too Low Flag
ALCMON Enable ALC Monitor for Status Flags Only 0
ALCULOK Enable ALC When PLL Unlocked 0
BD[3:0] Calibration B Divider Value h3
BST REF Buffer Boost Current 1
CAL Start VCO Calibration (auto clears) 0
CP[3:0] CP Output Current hB
CPCHI CP Enable Hi Voltage Output Clamp 1
CPCLO CP Enable Low Voltage Output Clamp 1
CPDN CP Pump Down Only 0
CPINV CP Invert Phase 0
CPMID CP Bias to Mid-Rail 1
CPRST CP Three-State 1
CPUP CP Pump Up Only 0
CPWIDE CP Extend Pulse Width 0
FILT[1:0] REF Input Buffer Filter h3
LKCT[1:0] PLL Lock Cycle Count h1
LKEN PLL Lock Indicator Enable 1
LKWIN[1:0] PLL Lock Indicator Window h2
LOCK PLL Lock Indicator Flag
MTCAL Mutes Output During Calibration 1
ND[15:0] N Divider Value (ND[15:0] > 31) h00FA
OD[2:0] Output Divider Value (0 < OD[2:0] < 7) h1
OMUTE Mutes RF Output 1
PART[4:0] Part code (h01 for LTC6946-1, h02 for
LTC6946-2, h03 for LTC6946-3, h04 for
LTC6946-4 Version)
h01, h02,
h03, h04
PDALL Full Chip Power Down 0
PDOUT Powers Down O_DIV, RF Output Buffer 0
PDPLL Powers Down REF, REFO, R_DIV, PFD,
CPUMP, N_DIV
0
PDREFO Powers Down REFO 1
PDVCO Powers Down VCO, N_DIV 0
POR Force Power-On Reset 0
RD[9:0] R Divider Value (RD[9:0] > 0) h001
REV[2:0] Rev Code
RFO[1:0] RF Output Power h3
THI CP Clamp High Flag
TLO CP Clamp Low Flag
UNLOCK PLL Unlock Flag
x[5:0] STAT Output OR Mask h04
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INTRODUCTION
A PLL is a complex feedback system that may conceptually
be considered a frequency multiplier. The system multiplies
the frequency input at REF± and outputs a higher frequency
at RF±. The PFD, charge pump, N divider, and external VCO
and loop filter form a feedback loop to accurately control
the output frequency (see Figure 14). The R and O divider
are used to set the output frequency resolution.
Using the above equations, the output frequency resolution
fSTEP produced by a unit change in N is given by Equation 6:
fSTEP =
f
REF
R•O
(6)
LOOP FILTER DESIGN
A stable PLL system requires care in selecting the external
loop filter values. The Linear Technology PLLWizard ap-
plication, available from www.linear.com, aids in design
and simulation of the complete system.
The loop design should use the following algorithm:
1. Determine the output frequency, fRF , and frequency step
size, fSTEP
, based on application requirements. Using
Equations 3, 4, 5 and 6, change fREF
, N, R, and O until
the application frequency constraints are met. Use the
minimum R value that still satisfies the constraints.
Then calculate B using Equation 1 and Table 7.
2. Select the open-loop bandwidth, BW, constrained by
fPFD. A stable loop requires that BW is less than fPFD
by at least a factor of 10.
3. Select loop filter component RZ and charge pump cur-
rent ICP based on BW and the VCO gain factor, KVCO.
BW (in Hz) is approximated by the following equation:
B
W≅
I
CP
•R
Z
•K
VCO
2•π•N
(7)
or
R
Z=
2•
π
•BW •N
ICP •KVCO
where KVCO is in Hz/V, ICP is in Amps, and RZ is in
Ohms.
KVCO is obtained from the VCO tuning sensitivity in the
Electrical Characteristics. Use ICP = 11.2mA to lower in-
band noise unless component values force a lower setting.
R_DIV
N_DIV
÷R
÷N
O_DIV
÷O
fPFD
LTC6946
REF±
(fREF)
fVCO
KPFD
KVCO
25
RF±
(fRF)15
CP
RZ
CI
CP
LOOP FILTER
LF(s)
6946 F14
TUNE
ICP
Figure 14. PLL Loop Diagram
OUTPUT FREQUENCY
When the loop is locked, the frequency fVCO (in Hz)
produced at the output of the VCO is determined by the
reference frequency, fREF
, and the R and N divider values,
given by Equation 3:
fVCO =
f
REF
•N
R
(3)
Here, the PFD frequency fPFD produced is given by the
following equation:
fPFD =
f
REF
R
(4)
and fVCO may be alternatively expressed as:
fVCO = fPFD • N
The output frequency fRF produced at the output of the O
divider is given by Equation 5:
fRF =
f
VCO
O
(5)
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4. Select loop filter components CI and CP based on BW
and RZ. A reliable loop can be achieved by using the
following equations for the loop capacitors (in Farads):
CI=
3.5
2•π•BW •R
Z
(8)
CP=
1
7•π•BW •R
Z
(9)
DESIGN AND PROGRAMMING EXAMPLE
This programming example uses the DC1705A with the
LTC6946-3. Assume the following parameters of interest:
fREF = 20MHz at 7dBm into 50Ω
fSTEP = 125kHz
fRF = 2.4GHz
From the Electrical Characteristics table:
fVCO = 3.840GHz to 5.790GHz
KVCO% = 4.0%Hz/V to 6.0%Hz/V
Determining Divider Values
Following the Loop Filter Design algorithm, first deter-
mine all the divider values. Using Equations 2, 3, 4 and 5
calculate the following values:
O = 2
R = 20MHz/(125kHz • 2) = 80
fPFD = 250kHz
N = 2 • 2.4GHz/250kHz = 19200
fVCO = 4.8GHz
Also, from Equation 1 or Table 7 determine B:
B = 8 and BD[3:0] = 0
The next step in the algorithm is to determine the open-
loop bandwidth. BW should be at least 10× smaller than
fPFD. Wider loop bandwidths could have lower integrated
phase noise, depending on the VCO phase noise signature,
while narrower bandwidths will likely have lower spurious
power. Use a factor of 15 for this design example:
BW =
250kHz
15
=16.7kHz
Loop Filter Component Selection
Now set loop filter resistor, RZ, and charge pump current,
ICP
. Because the KVCO varies over the VCO’s frequency
range, using the KVCO geometric mean gives good results.
Using an ICP of 11.2mA, RZ is determined:
KVCO =4.8 •109•0.04 •0.06 =235MHz / V
RZ=2•π•16.7k •19200
11.2m •235M
RZ=765Ω
Now calculate CI and CP from Equations 7 and 8:
CI=
3.5
2•π•16.7k •765 =44nF
CP=1
7•π•16.7k •765
=3.6nF
Status Output Programming
This example will use the STAT pin to alert the system
whenever the LTC6946 generates a fault condition. Pro-
gram x[5], x[4], x[3], x[1], x[0] = 1 to force the STAT pin
high whenever any of the UNLOCK, ALCHI, ALCLO, THI
or TLO flags asserts:
Reg01 = h3B
Power Register Programming
For correct PLL operation all internal blocks should be
enabled, but PDREFO should be set if the REFO pin is
not being used. OMUTE may remain asserted (or the
MUTE pin held low) until programming is complete. For
PDREFO = 1 and OMUTE = 1:
Reg02 = h0A
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Divider Programming
Program registers Reg03 to Reg06 with the previously
determined B, R and N divider values.
Reg03 = h00
Reg04 = h50
Reg05 = h4B
Reg06 = h00
VCO ALC and Calibration Programming
Now that all the divider registers are programmed, and
assuming that the reference frequency is stable at REF±,
calibrate the VCO. Set the ALC options (ALCMON = 1,
ALCCAL = 1) and the lock enable bit (LKEN = 1) at the
same time:
Reg07 = h63
The LTC6946 will now calibrate its VCO. The ALC will only
be active during the calibration cycle, but the ALCHI and
ALCLO status conditions will be monitored.
Reference Input Settings and Output Divider
Programming
From Table 1, FILT = 1 for a 20MHz reference frequency.
Next, convert 7dBm into VP-P
. For a CW tone, use the
following equation with R = 50:
V
P-P ≅R•10
(dBm –21)/20
(10)
This gives VP-P = 1.41V, and, according to Table 2, set
BST = 1.
Now program Reg08, assuming maximum RF± output
power (RFO[1:0] = 3 according to Table 9) and OD[2:0] = 2:
Reg08 = hBA
Lock Detect and Charge Pump Current Programming
Next, determine the lock indicator window from fPFD.
From Table 3, LKWIN[1:0] = 3 for a tLWW of 90ns. The
LTC6946 will consider the loop “locked” as long as the
phase coincidence at the PFD is within 8°, as calculated:
phase = 360° • tLWW • fPFD = 360 • 90n • 250k ≅ 8°
LKWIN[1:0] may be set to a smaller value to be more
conservative. However, the inherent phase noise of the
loop could cause false “unlocks” for too small a value.
Choosing the correct LOKCNT depends upon the ratio of
the bandwidth of the loop to the PFD frequency (BW/fPFD).
Smaller ratios dictate larger LOKCNT values. A LOKCNT
value of 128 will work for our ratio of 1/15. From Table 4,
LKCNT[1:0] = 1 for 128 counts.
Using Table 5 with the previously selected ICP of 11.2mA,
gives CP[3:0] = 11 (hB). This is enough information to
program Reg09:
Reg09 = hDB
Charge Pump Function Programming
This example uses the additional voltage clamp features to
allow us to monitor fault conditions by setting CPCHI = 1
and CPCLO = 1. If something occurs and the system can
no longer lock to its intended frequency, the charge pump
output will move toward either GND or VCP+, thereby setting
either the TLO or THI status flags, respectively. Disable all
the other charge pump functions (CPMID, CPINV, CPRST,
CPUP and CPDN) to allow the loop to lock:
Reg0A = hC0
The loop should now lock. Now unmute the output by
setting OMUTE = 0 (assumes the MUTE pin is high):
Reg02 = h08
REFERENCE SOURCE CONSIDERATIONS
A high quality signal must be applied to the REF± inputs as
they provide the frequency reference to the entire PLL. As
mentioned previously, to achieve the part’s in-band phase
noise performance, apply a CW signal of at least 6dBm
into 50Ω, or a square wave of at least 0.5VP-P with slew
rate of at least 40V/µs.
The LTC6946 may be driven single ended to CMOS levels
(greater than 2.7VP-P ). Apply the reference signal directly
without a DC-blocking capacitor at REF+, and bypass REF–
to GND with a 47pF capacitor. The BST bit must also be
set to “0”, according to guidelines given in Table 2.
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The LTC6946 achieves an in-band normalized phase noise
floor of –226dBc/Hz (typical). To calculate its equiva-
lent input phase noise floor LM(IN), use the following
Equation 11:
LM(IN) = –226 + 10 • log10(fREF) (11)
For example, using a 10MHz reference frequency gives
an input phase noise floor of –156dBc/Hz. The reference
frequency source’s phase noise must be at least 3dB better
than this to prevent limiting the overall system performance.
IN-BAND OUTPUT PHASE NOISE
The in-band phase noise produced at fRF may be calcu-
lated by using Equation 12.
LM(OUT) =–226 +10 •log10 fPFD
( )
+20 •log10
fRF
fPFD
or
LM(OUT) =–226 +10 •log10 fPFD
( )
+20 •log10
N
O
(12)
As can be seen, for a given PFD frequency fPFD, the output
in-band phase noise increases at a 20dB-per-decade rate
with the N divider count. So, for a given output frequency
fRF, fPFD should be as large as possible (or N should be as
small as possible) while still satisfying the application’s
frequency step size requirements.
OUTPUT PHASE NOISE DUE TO 1/f NOISE
In-band phase noise at very low offset frequencies may
be influenced by the LTC6946’s 1/f noise, depending upon
fPFD. Use the normalized in-band 1/f noise of –274dBc/
Hz with Equation 13 to approximate the output 1/f phase
noise at a given frequency offset fOFFSET.
LM(OUT-1/f) f
OFFSET
( )
=–274+20 •log10 f
RF
( )
–10 •log10 f
OFFSET
( )
(13)
Unlike the in-band noise floor LM(OUT), the 1/f noise
LM(OUT 1/f) does not change with fPFD, and is not constant
over offset frequency. See Figure 15 for an example of
in-band phase noise for fPFD equal to 3MHz and 100MHz.
The total phase noise will be the summation of LM(OUT)
and LM(OUT 1/f).
Figure 15. Theoretical In-Band Phase Noise, fRF = 2500MHz
OFFSET FREQUENCY (Hz)
10
PHASE NOISE (dBc/Hz)
–110
–100
100k
6945 F15
–120
–130 100 1k 10k
–90
TOTAL NOISE
fPFD = 3MHz
TOTAL NOISE
fPFD = 100MHz
1/f NOISE
CONTRIBUTION
RF OUTPUT MATCHING
The RF± outputs may be used in either single-ended or dif-
ferential configurations.
Using both RF outputs differentially
will result in approximately 3dB more output power than
single ended. Impedance matching to an external load in
both cases requires external chokes tied to VRF+. Measured
RF± s-parameters are shown below in Table13 to aid in
the design of impedance matching networks.
Table 13. Single-Ended RF Output Impedance
FREQUENCY (MHZ) IMPEDANCE (Ohms) S11 (dB)
500 102.8 – j49.7 –6.90
1000 70.2 – j60.1 –6.53
1500 52.4 – j56.2 –6.35
2000 43.6 – j49.2 –6.58
2500 37.9 – j39.6 –7.34
3000 32.7 – j28.2 –8.44
3500 27.9 – j17.8 –8.99
4000 24.3 – j9.4 –8.72
4500 22.2 – j3.3 –8.26
5000 21.6 + j1.9 –8.02
5500 21.8 + j6.6 –7.91
6000 23.1 + j11.4 –8.09
6500 25.7 + j16.9 –8.38
7000 29.3 + j23.0 –8.53
7500 33.5 + j28.4 –8.56
8000 37.9 + j32.6 –8.64
LTC6946
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applicaTions inForMaTion
Single-ended impedance matching is accomplished
using the circuit of Figure 16, with component values
found in Table 14. Using smaller inductances than
recommended can cause phase noise degradation,
especially at lower center frequencies.
Table 14. Suggested Single-Ended Matching Component Values
fRF (MHz) LC (nH) CS (pF)
350 to 1500 180 270
1000 to 5800 68 100
Return loss measured on the DC1705 using the above
component values is shown in Figure 17. A broadband
match is achieved using an (LC, CS) of either (68nH, 100pF)
or (180nH, 270pF). However, for maximum output power
and best phase noise performance, use the recommended
component values of Table 13. LC should be a wirewound
inductor selected for maximum Q factor and SRF, such
as the Coilcraft HP series of chip inductors.
The LTC6946’s differential RF± outputs may be combined
using an external balun to drive a single-ended load. The
advantages are approximately 3dB more output power than
each output individually and better 2nd order harmonic
performance.
For lower frequencies, transmission line (TL) baluns such
as the M/A-COM MABACT0065 and the TOKO #617DB-
1673 provide good results. At higher frequencies, surface
mount (SMT) baluns such as those produced by TDK,
Anaren, and Johanson Technology, can be attractive
alternatives. See Table 15 for recommended balun part
numbers versus frequency range.
Figure 17. Single-Ended Return Loss
Figure 16. Single-Ended Output Matching Schematic
RF+(–)
LC
CS
50Ω
TO 50Ω
LOAD
VRF
+
RF–(+)
LC
CS
6946 F16
VRF+
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5
6
FREQUENCY (GHz)
S11 (dB)
–6
–4
–2
6946 F17
–10
–16
0
–8
–12
–14
68nH, 100pF
180nH, 270pF
The listed SMT baluns contain internal chokes to bias RF±
and also provide input-to-output DC isolation. The pin
denoted as GND or DC FEED should be connected to the
VRF+ voltage. Figure 18 shows a surface mount balun’s
connections with a DC FEED pin.
Table 15. Suggested Baluns
fRF (MHz) PART NUMBER MANUFACTURER TYPE
350 to 900 #617DB-1673 TOKO TL
400 to 600 HHM1589B1 TDK SMT
600 to 1400 BD0810J50200 Anaren SMT
600 to 3000 MABACT0065 M/A-COM TL
1000 to 2000 HHM1518A3 TDK SMT
1400 to 2000 HHM1541E1 TDK SMT
1900 to 2300 2450BL15B100E Johanson SMT
2000 to 2700 HHM1526 TDK SMT
3700 to 5100 HHM1583B1 TDK SMT
4000 to 6000 HHM1570B1 TDK SMT
The listed TL baluns do not provide input-to-output DC
isolation and must be AC coupled at the output. Figure18
displays RF± connections using these baluns.
LTC6946
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Figure 18. Example SMT Balun Connection
Figure 19. Example TL Balun Connection
applicaTions inForMaTion
SUPPLY BYPASSING AND PCB LAYOUT GUIDELINES
Care must be taken when creating a PCB layout to mini-
mize power supply decoupling and ground inductances.
All power supply V+ pins should be bypassed directly to
the ground plane using a 0.1µF ceramic capacitor as close
to the pin as possible. Multiple vias to the ground plane
should be used for all ground connections, including to
the power supply decoupling capacitors.
The package’s exposed pad is a ground connection, and
must be soldered directly to the PCB land. The PCB land
pattern should have multiple thermal vias to the ground
plane for both low ground inductance and also low thermal
resistance (see Figure 20 for an example). See QFN Pack-
age Users Guide, page 8, on Linear Technology website’s
Packaging Information page for specific recommendations
concerning land patterns and land via solder masks. A link
is provided below.
http://www.linear.com/designtools/packaging
Figure 20. Example Exposed Pad Land Pattern
REFERENCE SIGNAL ROUTING, SPURIOUS AND
PHASE NOISE
The charge pump operates at the PFD’s comparison
frequency fPFD. The resultant output spurious energy is
small and is further reduced by the loop filter before it
modulates the VCO frequency.
However,
improper PCB layout can degrade the LTC6946’s
inherent spurious performance. Care must be taken to
prevent the reference signal fREF from coupling onto the
VCO’s tune line, or into other loop filter signals. Example
suggestions are the following.
1. Do not share power supply decoupling capacitors
between same voltage power supply pins.
2. Use separate ground vias for each power supply decou-
pling capacitor, especially those connected to VREF+,
VCP+, and VVCO+.
3. Physically separate the reference frequency signal from
the loop filter and VCO.
4. Do not place a trace between the CMA, CMB and CMC
pads underneath the package as worse phase noise
could result.
LTC6946
VRF+
RF–
RF+
TO 50Ω
LOAD
6946 F18
12
BALUN
23 1
54 6
11
BALUN PIN CONFIGURATION
1
2
3
4
5
6
UNBALANCED PORT
GND OR DC FEED
BALANCED PORT
BALANCED PORT
GND
NC
LTC6946
VRF
+
RF–
RF+
TO 50Ω
LOAD
PRI
SEC
6946 F19
12
11
6946 F20
LTC6946
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For more information www.linear.com/LTC6946
applicaTions inForMaTion
LTC6946-2 Driving a Modulator
MUTE
GND
RF–
RF+
VRF+
BB
REF–
REF+
VREF+
CP
VCP+
GND
VREFO+
REFO
STAT
CS
SCLK
SDI
SDO
VD+
VVCO+
GND
CMA
CMB
CMC
GND
TB
TUNE
LTC6946-2
SPI BUS
3.3V
1µF
51.1Ω
+15Ω
5V
RZ
1µF
3.3V
LOOP COMPENSATION
COMPONENT VALUES ARE
APPLICATION SPECIFIC
DEPENDING ON THE LO
FREQUENCY RANGE AND
STEP SIZE AND THE PHASE
NOISE OF THE REFERENCE
CI
0.01µF
0.1µF
3.3V
3.3V
1µF
0.01µF
0.01µF
2.2µF
CP
0.01µF
1µF
10MHz
REFERENCE
3.3V3.3V
THE UNUSED RF– OUTPUT
IS AVAILABLE TO DRIVE
ANOTHER 50Ω LOAD
68nH
LOM
LO = 1950MHz
TOKO
4DFB-1950L-10
3.3V
VCC2
RF
GNDRF
BBPI
BBMI
BBPQ
BBMQ
LOP
GND LINOPT 6946 TA02
LTC5588-1 VCC1
1nF
68nH
0.1µF
4.7µF
3.3V
1nF
50Ω 1Ω
1.3Ω
1nF
50Ω
10nF
1810MHz
140MHz
VGA
1nF
4.7µF
0°
90°
BASEBAND
GENERATOR
EN EN
I-DAC
Q-DAC
LTC2630
PA
RF FREQUENCY (MHz)
1802.5
–120
POWER IN 30kHz BW (dBm)
–90
–90
–80
–70
–60
–50
1807.5 1812.5
6946 TA02b
–40
–30
MEASURED SIGNAL
MEASUREMENT NOISE FLOOR
–110
1817.5
≈–80dBc
Measured W-CDMA ACPR
(3.84MHz Bandwidth)
LTC6946-2 Modulator Application
Phase Noise
OFFSET FREQUENCY (Hz)
–130
–140
PHASE NOISE (dBc/Hz)
–110
–90
–150
–120
–100
100 10k 100k 1M 10M
6946 TA02c
–160
1k
RMS NOISE = 0.281°
fRF = 1950MHz
fPFD = 2MHz
OD = 2
fSTEP = 1MHz
LTC6946
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For more information www.linear.com/LTC6946
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
package DescripTion
UFD Package
28-Lead Plastic QFN (4mm × 5mm)
(Reference LTC DWG # 05-08-1712 Rev B)
4.00 ± 0.10
(2 SIDES)
2.50 REF
5.00 ± 0.10
(2 SIDES)
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X).
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
PIN 1
TOP MARK
(NOTE 6)
0.40 ± 0.10
27 28
1
2
BOTTOM VIEW—EXPOSED PAD
3.50 REF
0.75 ± 0.05 R = 0.115
TYP
R = 0.05
TYP
PIN 1 NOTCH
R = 0.20 OR 0.35
× 45° CHAMFER
0.25 ± 0.05
0.50 BSC
0.200 REF
0.00 – 0.05
(UFD28) QFN 0506 REV B
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.70 ±0.05
0.25 ±0.05
0.50 BSC
2.50 REF
3.50 REF
4.10 ± 0.05
5.50 ± 0.05
2.65 ± 0.05
3.10 ± 0.05
4.50 ± 0.05
PACKAGE OUTLINE
2.65 ± 0.10
3.65 ± 0.10
3.65 ± 0.05
LTC6946
31
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For more information www.linear.com/LTC6946
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
revision hisTory
REV DATE DESCRIPTION PAGE NUMBER
A 11/11 Add IOL and remove Max value, remove Max value for IOH
Revise values on Block Diagram
4
11
B 03/15 Added LTC6946-4.
Changed operating core temperature to operating junction temperature.
Updated power supply currents.
Updated VCO calibration.
All pages
2
5
8, 17
LTC6946
32
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For more information www.linear.com/LTC6946
LINEAR TECHNOLOGY CORPORATION 2011
LT 0315 REV B • PRINTED IN USA
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC6946
relaTeD parTs
Typical applicaTion
LTC6946-2 Driving a Passive Downconverting Mixer
RF BLOCKER POWER (dBm)
–20
9
SSB NOISE FIGURE (dB)
10
12
13
14
–10 05
18
6946 TA03b
11
–15 –5
15
16
17
RF = 1982MHz
BLOCKER = 2082MHz
LO = LTC6946-2
LO = CLEAN LAB SOURCE
LTC5541 Noise Figure vs Blocker
Power and LO Signal Source
LTC6946-2 Mixer Application
Phase Noise
OFFSET FREQUENCY (Hz)
–130
–140
PHASE NOISE (dBc/Hz)
–110
–90
–150
–120
–100
100 10k 100k 1M 10M
6946 TA03c
–160
1k
RMS NOISE = 0.270°
fRF = 1842MHz
fPFD = 2MHz
OD = 2
fSTEP = 1MHz
PART NUMBER DESCRIPTION COMMENTS
LTC6945 Ultralow Noise and Spurious Integer-N Synthesizer 350MHz to 6GHz, –226dBc/Hz Normalized In-Band Phase Noise Floor
LTC6947 Ultralow Noise and Spurious Fractional-N Synthesizer 350MHz to 6GHz, –226dBc/Hz Normalized In-Band Phase Noise Floor
LTC6948 Ultralow Noise and Spurious Frac-N Synthesizer with VCO 370MHz to 6.39GHz, –226dBc/Hz Normalized In-Band Phase Noise Floor
LTC6950 Low Phase Noise and Spurious Integer-N PLL Core with Five
Output Clock Distribution and EZSync
1.4GHz Max VCO Frequency, Additive Jitter <20fsRMS, –226dBc/Hz
Normalized In-Band Phase Noise Floor
LTC6957 Low Phase Noise, Dual Output Buffer/Driver/Logic Converter Optimized Conversion of Sine Waves to Logic Levels, LVPECL/LVDS/CMOS
LTC2000 16-/14-/11-Bit 2.5Gsps DAC Superior 80dBc SFDR at 70MHz Output, 40mA Nominal Drive and High
Linearity
LTC5569 Broadband Dual Mixer 300MHz to 4GHz, 26.8dBm IIP3, 2dB Gain, 11.7dB NF, 600mW Power
LTC5588-1 Ultrahigh OIP3 I/Q Modulator 200MHz to 6GHz, 31dBm OIP3, –160.6dBm/Hz Noise Floor
LT
®
5575 Direct Conversion I/Q Demodulator 800MHz to 2.7GHz, 22.6dBm IIP3, 60dBm IIP2, 12.7dB NF
MUTE
GND
RF–
RF+
VRF+
BB
REF–
REF+
VREF+
CP
VCP+
GND
VREFO+
REFO
STAT
CS
SCLK
SDI
SDO
VD+
VVCO+
GND
CMA
CMB
CMC
GND
TB
TUNE
LTC6946-2
SPI BUS
3.3V
1µF
51.1Ω
+15Ω
5V
RZ
1µF
3.3V
LOOP COMPENSATION
COMPONENT VALUES ARE
APPLICATION SPECIFIC
DEPENDING ON THE LO
FREQUENCY RANGE AND
STEP SIZE AND THE PHASE
NOISE OF THE REFERENCE
CI
0.01µF
0.1µF
3.3V
3.3V
1µF
0.01µF
0.01µF
2.2µF
CP
0.01µF
BALUN TDK HHM1525
3.3V
LO2 LO1
LOBIAS
LOSEL
VCC3
IFBIAS
IFGND
SHDN
GNDGND GND
LTC5541
GND GND
VCC2
CT
RF
VCC1
1µF
3.3V 30nH
IF+
150nH
IF–
1µF
10MHz
REFERENCE
TOKO
4DFB-1842N-10
22pF
22pF 1µF
3.3V
3.3V
LO = 1842MHz
0.1µF
ADC
150nH 1nF 140MHz
SAW
140MHz
BPF
1.5pF
2.2pF
LNA
IMAGE
BPF
RF IN
1952MHz
TO 2012MHZ
3.3V
22pF
1nF
6946 TA03