0
10
20
30
40
50
0 10 20 30 40 50 60
Input Voltage (V)
IQ (µA)
− 40°C
+ 25°C
+ 85°C
+ 105°C
+ 125°C
IOUT = 0mA
TPS7A16
OUT
GND
CIN
IN
EN
VIN
VOUT
VEN
RPG
DELAY
CDELAY
PG
COUT
VPG
µC1
IO1
IO2
IO3
µC2
EN
VCC
12 V
60 V
t
VIN
Product
Folder
Sample &
Buy
Technical
Documents
Tools &
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Support &
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Reference
Design
TPS7A16
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TPS7A16 60-V, 5-µA I
Q
, 100-mA, Low-Dropout Voltage Regulator
With Enable and Power-Good
1 Features 3 Description
The TPS7A16 family of ultralow power, low-dropout
1• Wide Input Voltage Range: 3 V to 60 V (LDO) voltage regulators offers the benefits of ultra-
• Ultralow Quiescent Current: 5 µA low quiescent current, high input voltage and
• Quiescent Current at Shutdown: 1 µA miniaturized, high thermal-performance packaging.
• Output Current: 100 mA The TPS7A16 family is designed for continuous or
• Low Dropout Voltage: 60 mV at 20 mA sporadic (power backup) battery-powered
applications where ultralow quiescent current is
• Accuracy: 2% critical to extending system battery life.
• Available in: The TPS7A16 family offers an enable pin (EN)
– Fixed Output Voltage: 3.3 V, 5 V compatible with standard CMOS logic and an
– Adjustable Version from 1.2 V to 18.5 V integrated open drain active-high power good output
• Power-Good With Programmable Delay (PG) with a user-programmable delay. These pins are
intended for use in microcontroller-based, battery-
• Current Limit and Thermal Shutdown Protections powered applications where power-rail sequencing is
• Stable with Ceramic Output Capacitors: required.
≥2.2 µF In addition, the TPS7A16 is ideal for generating a
• Packages: High Thermal Performance MSOP-8 low-voltage supply from multicell solutions ranging
and SON-8 PowerPAD™ from high cell-count power-tool packs to automotive
• Operating Temperature Range: applications; not only can this device supply a well-
–40°C to 125°C regulated voltage rail, but it can also withstand and
maintain regulation during voltage transients. These
2 Applications features translate to simpler and more cost-effective,
electrical surge-protection circuitry.
• Power Supplies for Notebook PCs, Digital TVs,
and Private LAN Systems Device Information(1)
• High Cell-Count Battery Packs for Power Tools PART NUMBER PACKAGE BODY SIZE (NOM)
and other Battery-Powered Microprocessor and HVSSOP (8) 3.00 mm × 3.00 mm
Microcontroller Systems TPS7A16 VSON (8) 3.00 mm × 3.00 mm
• Car Audio, Navigation, Infotainment, and Other (1) For all available packages, see the package option addendum
Automotive Systems at the end of the data sheet.
• Smoke and CO2Detectors and Battery-Powered
Alarm and Security Systems
Typical Application Schematic Quiescent Current vs Input Voltage
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS7A16
SBVS171F –DECEMBER 2011–REVISED OCTOBER 2015
www.ti.com
Table of Contents
1 Features.................................................................. 18 Application and Implementation ........................ 13
8.1 Application Information............................................ 13
2 Applications ........................................................... 18.2 Typical Applications ................................................ 13
3 Description............................................................. 19 Power Supply Recommendations...................... 19
4 Revision History..................................................... 210 Layout................................................................... 19
5 Pin Configuration and Functions......................... 410.1 Layout Guidelines ................................................. 19
6 Specifications......................................................... 510.2 Layout Example .................................................... 19
6.1 Absolute Maximum Ratings ..................................... 510.3 Power Dissipation ................................................. 21
6.2 ESD Ratings.............................................................. 510.4 Thermal Considerations........................................ 21
6.3 Recommended Operating Conditions....................... 511 Device and Documentation Support................. 22
6.4 Thermal Information.................................................. 611.1 Documentation Support ........................................ 22
6.5 Electrical Characteristics........................................... 611.2 Community Resources.......................................... 22
6.6 Typical Characteristics.............................................. 711.3 Trademarks........................................................... 22
7 Detailed Description............................................ 10 11.4 Electrostatic Discharge Caution............................ 22
7.1 Overview................................................................. 10 11.5 Glossary................................................................ 22
7.2 Functional Block Diagram....................................... 10 12 Mechanical, Packaging, and Orderable
7.3 Feature Description................................................. 11 Information........................................................... 22
7.4 Device Functional Modes........................................ 12
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (August 2015) to Revision F Page
• Changed ψJB value in Thermal Information table from 141.2 to 11.2 (typo) ......................................................................... 6
Changes from Revision D (January 2014) to Revision E Page
• Added ESD Ratings table, Feature Description section, Device Functional Modes,Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
• Changed MIN value of Regulated output from 1.2 to 1.169 .................................................................................................. 5
• Changed MAX value of Regulated output from 18 to 18.5 ................................................................................................... 5
• Changed MAX value of Operating junction temperature from 150 to 125 ............................................................................ 5
• Changed value in Power-Good section from 5.5-V to 5-V................................................................................................... 11
Changes from Revision C (November 2013) to Revision D Page
• Changed Feedback Current min, typ, and max values from –1.0, 0.0, and 1.0 to –0.1, –0.01, and 0.1, respectively.......... 6
• Changed Enable Current typ value from 0.01 to –0.01.......................................................................................................... 6
Changes from Revision B (April 2013) to Revision C Page
• Changed DRB package from product preview to production data......................................................................................... 1
• Added DRB package to thermal information.......................................................................................................................... 6
• Changed Figure 4 Y-axis unit from V to mV (typo) ................................................................................................................ 7
Changes from Revision A (December 2011) to Revision B Page
• Added preview DRB package to data sheet........................................................................................................................... 1
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Changes from Original (December 2011) to Revision A Page
• Changed data sheet to from product preview to production data.......................................................................................... 1
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OUT
FB/DNC
PG
GND
DELAY
EN
1
2
3
4
8
7
6
5
GND
IN
NC
IN
DELAY
NC
EN
OUT
FB/DNC
PG
GND
1
2
3
4
8
7
6
5
TPS7A16
SBVS171F –DECEMBER 2011–REVISED OCTOBER 2015
www.ti.com
5 Pin Configuration and Functions
DGN Package DRB Package
8-Pin HVSSOP 8-Pin VSON
Top View Top View
Pin Functions
PIN I/O DESCRIPTION
NAME NO.
Delay pin. Connect a capacitor to GND to adjust the PG delay time; leave open if the reset function is
DELAY 7 O not needed.
Enable pin. This pin turns the regulator on or off.
If VEN ≥VEN_HI, the regulator is enabled.
EN 5 I If VEN ≤VEN_LO, the regulator is disabled.
If not used, the EN pin can be connected to IN. Make sure that VEN ≤VIN at all times.
For the adjustable version (TPS7A1601), the feedback pin is the input to the control-loop error
amplifier. This pin is used to set the output voltage of the device when the regulator output voltage is
FB/DNC 2 I set by external resistors.
For the fixed voltage versions: Do not connect to this pin. Do not route this pin to any electrical net,
not even GND or IN.
GND 4 GND Ground pin.
Regulator input supply pin. A capacitor ≥0.1 µF must be tied from this pin to ground to assure stability.
TI recommends connecting a 10-µF ceramic capacitor from IN to GND (as close to the device as
IN 8 IN possible) to reduce circuit sensitivity to printed-circuit-board (PCB) layout, especially when long input
traces or high source impedances are encountered.
NC 6 — This pin can be left open or tied to any voltage between GND and IN.
Regulator output pin. A capacitor ≥2.2 µF must be tied from this pin to ground to assure stability. TI
OUT 1 O recommends connecting a 10-µF ceramic capacitor from OUT to GND (as close to the device as
possible) to maximize AC performance.
Power-good pin. Open collector output; leave open or connect to GND if the power-good function is
PG 3 O not needed.
Solder to printed-circuit-board (PCB) to enhance thermal performance. Although it can be left floating,
PowerPAD — — TI highly recommends connecting the PowerPAD to the GND plane.
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6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range –40°C ≤TJ≤125°C (unless otherwise noted).(1)
MIN MAX UNIT
IN pin to GND pin –0.3 62
OUT pin to GND pin –0.3 20
OUT pin to IN pin –62 0.3
FB pin to GND pin –0.3 3
Voltage FB pin to IN pin –62 0.3 V
EN pin to IN pin –62 0.3
EN pin to GND pin –0.3 62
PG pin to GND pin –0.3 5.5
DELAY pin to GND pin –0.3 5.5
Current Peak output Internally limited
Operating virtual junction, TJ–40 150
Temperature °C
Storage, Tstg –65 150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings VALUE UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000
V(ESD) Electrostatic discharge V
Charged device model (CDM), per JEDEC specification JESD22-C101, all ±500
pins(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT
VIN Unregulated input 3 60 V
VOUT Regulated output 1.169 18.5 V
EN 0 40 V
DELAY 0 5 V
PG 0 5 V
TJOperating junction temperature range –40 125 °C
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6.4 Thermal Information TPS7A1601
THERMAL METRIC(1) DGN (HVSSOP) DRB (VSON) UNIT
8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 66.2 44.5 °C/W
RθJC(top) Junction-to-case(top) thermal resistance 45.9 49.5 °C/W
RθJB Junction-to-board thermal resistance 34.6 11.3 °C/W
ψJT Junction-to-top characterization parameter 1.9 0.7 °C/W
ψJB Junction-to-board characterization parameter 34.3 11.2 °C/W
RθJC(bot) Junction-to-case(bottom) thermal resistance 14.9 4.7 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics
At TJ= –40°C to 125°C, VIN = VOUT(NOM) + 0.5 V or VIN = 3 V (whichever is greater), VEN = VIN, IOUT = 10 µA, CIN = 1 μF, COUT = 2.2 μF, and
FB tied to OUT, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN Input voltage range 3 60 V
VREF Internal reference TJ= 25°C, VFB = VREF, VIN = 3 V, IOUT = 10 μA 1.169 1.193 1.217 V
VUVLO Undervoltage lockout threshold 2.7 V
Output voltage range VIN ≥VOUT(NOM) + 0.5 V VREF 18.5 V
Nominal accuracy TJ= 25°C, VIN = 3 V, IOUT = 10 μA –2% 2% VOUT
VOUT VOUT(NOM) + 0.5 V ≤VIN ≤60 V(1)
Overall accuracy –2% 2% VOUT
10 µA ≤IOUT ≤100 mA
ΔVO(ΔVI) Line regulation 3 V ≤VIN ≤60 V ±1% VOUT
ΔVO(ΔIO) Load regulation 10 µA ≤IOUT ≤100 mA ±1% VOUT
VIN = 4.5 V, VOUT(NOM) = 5 V, IOUT = 20 mA 60 mV
VDO Dropout voltage VIN = 4.5 V, VOUT(NOM) = 5 V, IOUT = 100 mA 265 500 mV
ILIM Current limit VOUT = 90% VOUT(NOM), VIN = 3 V 101 225 400 mA
3 V ≤VIN ≤60 V, IOUT = 10 µA 5 15 μA
IGND Ground current IOUT = 100 mA 5 μA
ISHDN Shutdown supply current VEN = 0.4 V 0.59 5 μA
IFB Feedback current(2) –0.1 –0.01 0.1 µA
IEN Enable current 3 V ≤VIN ≤12 V, VIN = VEN –1 –0.01 1 μA
VEN_HI Enable high-level voltage 1.2 V
VEN_LO Enable low- level voltage 0.3 V
OUT pin floating, VFB increasing, VIN ≥VIN_MIN 85% 95% VOUT
VIT PG trip threshold OUT pin floating, VFB decreasing, VIN ≥VIN_MIN 83% 93% VOUT
VHYS PG trip hysteresis 2.3% 4% VOUT
VPG, LO PG output low voltage OUT pin floating, VFB = 80% VREF, IPG= 1mA 0.4 V
IPG, LKG PG leakage current VPG= VOUT(NOM) –1 1 μA
IDELAY DELAY pin current 1 2 μA
VIN = 3 V, VOUT(NOM) = VREF, COUT = 10 μF,
PSRR Power-supply rejection ratio 50 dB
f = 100 Hz
Shutdown, temperature increasing 170 °C
TSD Thermal shutdown temperature Reset, temperature decreasing 150 °C
Operating junction temperature
TJ–40 125 °C
range
(1) Maximum input voltage is limited to 24 V because of the package power dissipation limitations at full load (P ≈(VIN – VOUT) × IOUT =
(24 V – VREF) × 50 mA ≈1.14 W). The device is capable of sourcing a maximum current of 50 mA at higher input voltages as long as
the power dissipated is within the thermal limits of the package plus any external heatsinking.
(2) IFB > 0 flows out of the device.
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0
100
200
300
400
500
600
700
800
900
1000
0
Output Current (mA)
VDROP (mV)
− 40°C
+ 25°C
+ 85°C
+ 105°C
+ 125°C
20 40 60 80 100
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SBVS171F –DECEMBER 2011–REVISED OCTOBER 2015
6.6 Typical Characteristics
At TJ= –40°C to 125°C, VIN = VOUT(NOM) + 0.5 V or VIN = 3 V (whichever is greater), VEN = VIN, IOUT = 10 µA, CIN = 1 μF, COUT
= 2.2 μF, and FB tied to OUT, unless otherwise noted.
Figure 1. Quiescent Current vs Input Voltage Figure 2. Shutdown Current vs Input Voltage
Figure 3. Ground Current vs Output Current Figure 4. Dropout Voltage vs Output Current
Figure 5. Feedback Voltage vs Input Voltage Figure 6. Line Regulation
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PG Falling
PG Rising
ON−TO−OFF
OFF−TO−ON
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Typical Characteristics (continued)
At TJ= –40°C to 125°C, VIN = VOUT(NOM) + 0.5 V or VIN = 3 V (whichever is greater), VEN = VIN, IOUT = 10 µA, CIN = 1 μF, COUT
= 2.2 μF, and FB tied to OUT, unless otherwise noted.
Figure 7. Load Regulation Figure 8. Current Limit vs Input Voltage
Figure 9. Power-Good Threshold Voltage vs Temperature Figure 10. Enable Threshold Voltage vs Temperature
Figure 11. Power-Supply Rejection Ratio Figure 12. Output Spectral Noise Density
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V = 1 V 6.5 V
I = 1 mA
®
IN
OUT
C = 10 F
C = 0 nF
OUT
FF
m
Time (5 ms/div)
V (2 V/div)
IN
V (2 V/div)
PG
V (1 V/div)
OUT
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SBVS171F –DECEMBER 2011–REVISED OCTOBER 2015
Typical Characteristics (continued)
At TJ= –40°C to 125°C, VIN = VOUT(NOM) + 0.5 V or VIN = 3 V (whichever is greater), VEN = VIN, IOUT = 10 µA, CIN = 1 μF, COUT
= 2.2 μF, and FB tied to OUT, unless otherwise noted.
Figure 13. Power-Good Delay
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UVLO
Thermal
Shutdown
Current
Limit
Enable Error
Amp
IN
EN
OUT
FB
Pass
Device
Power
Good
Control
DELAY
PG
TPS7A16
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7 Detailed Description
7.1 Overview
The TPS7A16 family of devices are ultralow power, low-dropout (LDO) voltage regulators that offer the benefits
of ultralow quiescent current, high input voltage, and miniaturized, high thermal-performance packaging. The
TPS7A16 family also offers an enable pin (EN) and integrated open-drain active-high power-good output (PG)
with a user-programmable delay.
7.2 Functional Block Diagram
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7.3 Feature Description
7.3.1 Enable (EN)
The enable terminal is a high-voltage-tolerant terminal. A high input on EN actives the device and turns on the
regulator. For self-bias applications, connect this input to the VIN terminal.
7.3.2 Regulated Output (VOUT)
The VOUT terminal is the regulated output based on the required voltage. The output has current limitation. During
initial power up, the regulator has a soft start incorporated to control the initial current through the pass element.
In the event that the regulator drops out of regulation, the output tracks the input minus a drop based on the load
current. When the input voltage drops below the UVLO threshold, the regulator shuts down until the input voltage
recovers above the minimum start-up level.
7.3.3 Power-Good
The power-good (PG) pin is an open-drain output and can be connected to any 5-V or lower rail through an
external pull-up resistor. When no CDELAY is used, the PG output is high-impedance when VOUT is greater than
the PG trip threshold (VIT). If VOUT drops below VIT, the open-drain output turns on and pulls the PG output low. If
output voltage monitoring is not needed, the PG pin can be left floating or connected to GND.
The power-good feature functionality is only guaranteed when VIN ≥3 V (VIN_(MIN))
7.3.4 PG Delay Timer (DELAY)
The power-good delay time (tDELAY) is defined as the time period from when VOUT exceeds the PG trip threshold
voltage (VIT) to when the PG output is high. This power-good delay time is set by an external capacitor (CDELAY)
connected from the DELAY pin to GND; this capacitor is charged from 0 V to approximately 1.8 V by the DELAY
pin current (IDELAY) once VOUT exceeds the PG trip threshold (VIT).
When CDELAY is used, the PG output is high-impedance when VOUT exceeds VIT, and VDELAY exceeds VREF.
The power-good delay time can be calculated using: tDELAY = (CDELAY × VREF)/IDELAY. For example, when CDELAY
= 10 nF, the PG delay time is approximately 12 ms; that is, (10 nF × 1.193 V) / 1 µA = 11.93 ms.
7.3.5 Internal Current Limit
The fixed internal current limit of the TPS7A16 family helps protect the regulator during fault conditions. The
maximum amount of current the device can source is the current limit (225 mA, typical), and is largely
independent of output voltage. For reliable operation, do not operate the device in current limit for extended
periods of time.
7.3.6 Thermal Protection
Thermal protection disables the output when the junction temperature rises to approximately 170°C, allowing the
device to cool. When the junction temperature cools to approximately 150°C, the output circuitry is enabled.
Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may
cycle ON and OFF. This cycling limits the dissipation of the regulator, protecting it from damage as a result of
overheating.
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7.4 Device Functional Modes
7.4.1 Normal Operation
The device regulates to the nominal output voltage under the following conditions:
• The input voltage is at least as high as VIN(MIN).
• The input voltage is greater than the nominal output voltage added to the dropout voltage.
• The enable voltage has previously exceeded the enable rising threshold voltage and has not decreased
below the enable falling threshold.
• The output current is less than the current limit.
• The device junction temperature is less than the maximum specified junction temperature.
7.4.2 Dropout Operation
If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other
conditions are met for normal operation, the device operates in dropout mode. In this mode of operation, the
output voltage is the same as the input voltage minus the dropout voltage. The transient performance of the
device is significantly degraded because the pass device (such as a bipolar junction transistor, or BJT) is in
saturation and no longer controls the current through the LDO. Line or load transients in dropout can result in
large output voltage deviations.
7.4.3 Disabled
The device is disabled under the following conditions:
• The enable voltage is less than the enable falling threshold voltage or has not yet exceeded the enable rising
threshold.
• The device junction temperature is greater than the thermal shutdown temperature.
Table 1 lists the conditions that lead to the different modes of operation.
Table 1. Device Functional Mode Comparison
PARAMETER
OPERATING MODE VIN VEN IOUT TJ
VIN > VOUT(NOM) + VDO
Normal mode VEN > VEN_HI IOUT < ILIM TJ< 125°C
and VIN > VIN(MIN)
Dropout mode VIN < VOUT(NOM) + VDO VEN > VEN_HI — TJ< 125°C
Disabled mode (any true
condition disables the — VEN < VEN_HI — TJ> 170°C
device
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TPS7A1601
OUT
GND
CIN
IN
EN
VIN VOUT
VEN
DELAY PG
COUT
FB
VPG
RPG
CFF R1
R2
CDELAY
VOUT
VREF
-1R = R
1 2
Where:
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SBVS171F –DECEMBER 2011–REVISED OCTOBER 2015
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS7A16 family of ultralow power voltage regulators offers the benefit of ultralow quiescent current, high
input voltage, and miniaturized, high thermal-performance packaging.
The TPS7A16 family is designed for continuous or sporadic (power backup) battery-operated applications where
ultralow quiescent current is critical to extending system battery life.
8.2 Typical Applications
8.2.1 TPS7A1601 Circuit as an Adjustable Regulator
Figure 14. TPS7A1601 Circuit as an Adjustable Regulator Schematic
8.2.1.1 Design Requirements
Table 2 lists the design parameters.
Table 2. Design Parameters
DESIGN PARAMETER EXAMPLE VALUE
Input voltage range 5.5 V to 40 V
Output voltage 5 V
Output current rating 100 mA
Output capacitor range 2.2 μF to 100 μF
Delay capacitor range 100 pF to 100 nF
8.2.1.2 Detailed Design Procedure
8.2.1.2.1 Adjustable Voltage Operation
The TPS7A1601 has an output voltage range from 1.194 V to 20 V. The nominal output of the device is set by
two external resistors, as shown in Figure 15:
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VOUT
VREF
-1
R =R
1 2
IN
EN
DELAY
GND
C
0.1 Fm
IN
C
0.1 Fm
DELAY
VIN PG
OUT
FB
R
1.07 MW
2
R
3.4 MW
1
R
1 MW
PG
C
2.2 Fm
OUT
V
5 V
OUT
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Figure 15. Adjustable Operation
R1and R2can be calculated for any output voltage range using the formula shown in Equation 1:
(1)
8.2.1.2.1.1 Resistor Selection
TI recommends using resistors in the order of MΩto keep the overall quiescent current of the system as low as
possible (by making the current used by the resistor divider negligible compared to the device’s quiescent
current).
If greater voltage accuracy is required, consider the voltage offset contributions as a result of feedback current
and use of 0.1% tolerance resistors.
Table 3 shows the resistor combination to achieve a few of the most common rails using commercially available
0.1% tolerance resistors to maximize nominal voltage accuracy, while abiding to the formula shown in
Equation 1.
Table 3. Selected Resistor Combinations
VOUT R1R2VOUT/(R1+ R2) « IQNOMINAL ACCURACY
1.194 V 0 Ω ∞ 0 µA ±2%
1.8 V 1.18 MΩ2.32 MΩ514 nA ±(2% + 0.14%)
2..5 V 1.5 MΩ1.37 MΩ871 nA ±(2% + 0.16%)
3.3 V 2 MΩ1.13 MΩ1056 nA ±(2% + 0.35%)
5 V 3.4 MΩ1.07 MΩ1115 nA ±(2% + 0.39%)
10 V 7.87 MΩ1.07 MΩ1115 nA ±(2% + 0.42%)
12 V 14.3 MΩ1.58 MΩ755 nA ±(2% + 0.18%)
15 V 42.2 MΩ3.65 MΩ327 nA ±(2% + 0.19%)
18 V 16.2 MΩ1.15 MΩ1038 nA ±(2% + 0.26%)
Close attention must be paid to board contamination when using high-value resistors; board contaminants may
significantly impact voltage accuracy. If board cleaning measures cannot be ensured, consider using a fixed-
voltage version of the TPS7A16 or using resistors in the order of hundreds or tens of kΩ.
8.2.1.2.1.2 Capacitor Recommendations
Low equivalent series resistance (ESR) capacitors should be used for the input, output, and feed-forward
capacitors. Ceramic capacitors with X7R and X5R dielectrics are preferred. These dielectrics offer more stable
characteristics. Ceramic X7R capacitors offer improved overtemperature performance, while ceramic X5R
capacitors are the most cost-effective and are available in higher values.
High ESR capacitors may degrade PSRR.
14 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: TPS7A16
TPS7A16
www.ti.com
SBVS171F –DECEMBER 2011–REVISED OCTOBER 2015
8.2.1.2.1.3 Input and Output Capacitor Requirements
The TPS7A16 family of ultralow power, high-voltage linear regulators achieves stability with a minimum input
capacitance of 0.1 µF and output capacitance of 2.2 µF; however, TI recommends using 10-µF ceramic
capacitors to maximize AC performance.
8.2.1.2.1.4 Feed-Forward Capacitor
Although a feed-forward capacitor (CFF) from OUT to FB is not needed to achieve stability, TI recommends using
a 0.01-µF feed-forward capacitor to maximize AC performance.
8.2.1.2.1.5 Transient Response
As with any regulator, increasing the size of the output capacitor reduces overshoot and undershoot magnitude
but increases the duration of the transient response.
8.2.1.3 Application Curves
Figure 16. CH1 is VOUT, CH2 is PG, CH3 is EN, CH4 is Figure 17. CH1 is VOUT, CH2 is PG, CH3 is EN, CH4 is
lOUT, VIN is 12 V and Ready Before EN lOUT, VIN is 12 V Connected to EN
Copyright © 2011–2015, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: TPS7A16
TPS7A16
OUT
GND
CIN
IN
EN
VIN
VOUT
VEN
RPG
DELAY
CDELAY
PG
COUT
VPG
µC1
IO1
IO2
IO3
µC2
EN
VCC
12 V
60 V
t
VIN
TPS7A16
SBVS171F –DECEMBER 2011–REVISED OCTOBER 2015
www.ti.com
8.2.2 Automotive Applications
The TPS7A16 family maximum input voltage of 60 V makes it ideal for use in automotive applications where
high-voltage transients are present.
Events such as load-dump overvoltage (where the battery is disconnected while the alternator is providing
current to a load) may cause voltage spikes from 25 V to 60 V. To prevent any damage to sensitive circuitry,
local transient voltage suppressors can be used to cap voltage spikes to lower, more manageable voltages.
The TPS7A16 family can be used to simplify and lower costs in such cases. The TPS7A16 very high voltage
range allows this regulator to not only withstand the voltages coming out of these local transient voltage
suppressors, but even replace them, thus lowering system cost and complexity.
Figure 18. Low-Power Microcontroller Rail Sequencing in Automotive Applications Subjected to Load-
Dump Transients
8.2.2.1 Design Requirements
Table 4 lists the design parameters.
Table 4. Design Parameters
DESIGN PARAMETER EXAMPLE VALUE
Input voltage range 5.5 V to 60 V
Output voltage 5 V
Output current rating 100 mA
Output capacitor range 2.2 μF to 100 μF
Delay capacitor range 100 pF to 100 nF
8.2.2.2 Detailed Design Procedure
See Capacitor Recommendations and Input and Output Capacitor Requirements.
8.2.2.2.1 Device Recommendations
The output is 5 V, so choose either the fixed output version TPS7A1650 or the adjustable output version
TPS7A1601, and set the resistor divider appropriately. See Resistor Selection for more details.
8.2.2.3 Application Curves
See Figure 16 and Figure 17.
16 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: TPS7A16
Cell
Balance
Voltage
Sensing
TPS7A16
Comparator
Microcontroller
Sensing
+
-
UART
Up To 42 V
TPS7A16
www.ti.com
SBVS171F –DECEMBER 2011–REVISED OCTOBER 2015
8.2.3 Multicell Battery Packs
Currently, battery packs can employ up to a dozen cells in series that, when fully charged, may have voltages of
up to 55 V. Internal circuitry in these battery packs is used to prevent overcurrent and overvoltage conditions that
may degrade battery life or even pose a safety risk; this internal circuitry is often managed by a low-power
microcontroller, such as TI’s MSP430.
The microcontroller continuously monitors the battery itself, whether the battery is in use or not. Although this
microcontroller could be powered by an intermediate voltage taken from the multicell array, this approach
unbalances the battery pack itself, degrading its life or adding cost to implement more complex cell balancing
topologies.
The best approach to power this microcontroller is to regulate down the voltage from the entire array to discharge
every cell equally and prevent any balancing issues. This approach reduces system complexity and cost.
TPS7A16 is the ideal regulator for this application because it can handle very high voltages (from the entire
multicell array) and has very low quiescent current (to maximize battery life).
Figure 19. Protection Based on Low-Power Microcontroller Power from Multicell Battery Packs
8.2.3.1 Design Requirements
Table 5 lists the design parameters.
Table 5. Device Parameters
DESIGN PARAMETER EXAMPLE VALUE
Input voltage range 5.5 V to 55 V
Output voltage 5 V
Output current rating 100 mA
Output capacitor range 2.2 μF to 100 μF
Delay capacitor range 100 pF to 100 nF
8.2.3.2 Detailed Design Procedure
See Device Recommendations,Capacitor Recommendations, and Input and Output Capacitor Requirements.
8.2.3.3 Application Curves
See Figure 16 and Figure 17.
Copyright © 2011–2015, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links: TPS7A16
100 W
0.47 Fm
Optional
Filter
First
Cell
Last
Cell
Second
Cell
LDO
MSP430
Microcontroller
PWM
Transient
M
TPS7A16
SBVS171F –DECEMBER 2011–REVISED OCTOBER 2015
www.ti.com
8.2.4 Battery-Operated Power Tools
High voltage multicell battery packs support high-power applications, such as power tools, with high current drain
when in use, highly intermittent use cycles, and physical separation between battery and motor.
In these applications, a microcontroller or microprocessor controls the motor. This microcontroller must be
powered with a low-voltage rail coming from the high-voltage, multicell battery pack; as mentioned previously,
powering this microcontroller or microprocessor from an intermediate voltage from the multicell array causes
battery-pack life degradation or added system complexity because of cell balancing issues. In addition, this
microcontroller or microprocessor must be protected from the high-voltage transients due to the motor
inductance.
The TPS7A16 can be used to power the motor-controlled microcontroller or microprocessor; its low quiescent
current maximizes battery shelf life and its very high-voltage capabilities simplify system complexity by replacing
voltage suppression filters, thus lowering system cost.
Figure 20. Low Power Microcontroller Power From Multicell Battery Packs In Power Tools
8.2.4.1 Design Requirements
Table 6 lists the design parameters.
Table 6. Design Parameters
DESIGN PARAMETER EXAMPLE VALUE
Input voltage range 5.5 V to 60 V
Output voltage 5 V
Output current rating 100 mA
Output capacitor range 2.2 μF to 100 μF
Delay capacitor range 100 pF to 100 nF
8.2.4.2 Detailed Design Procedure
See Device Recommendations,Capacitor Recommendations, and Input and Output Capacitor Requirements.
8.2.4.3 Application Curves
See Figure 16 and Figure 17.
18 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: TPS7A16
TPS7A16
www.ti.com
SBVS171F –DECEMBER 2011–REVISED OCTOBER 2015
9 Power Supply Recommendations
The device is designed to operate from an input voltage supply with a range between 3 V and 60 V. This input
supply must be well regulated. The TPS7A16 family of ultralow-power, high-voltage linear regulators achieve
stability with a minimum input capacitance of 0.1 μF and output capacitance of 2.2 μF; however, TI recommends
using 10-μF ceramic capacitors to maximize ac performance.
10 Layout
10.1 Layout Guidelines
To improve AC performance such as PSRR, output noise, and transient response, it is recommended that the
board be designed with separate ground planes for IN and OUT, with each ground plane connected only at the
GND pin of the device. In addition, the ground connection for the output capacitor should connect directly to the
GND pin of the device.
Equivalent series inductance (ESL) and ESR must be minimized in order to maximize performance and ensure
stability. Every capacitor must be placed as close as possible to the device and on the same side of the PCB as
the regulator itself.
Do not place any of the capacitors on the opposite side of the PCB from where the regulator is installed. The use
of vias and long traces is strongly discouraged because they may impact system performance negatively and
even cause instability.
If possible, and to ensure the maximum performance denoted in this product data sheet, use the same layout
pattern used for TPS7A16 evaluation board, available at www.ti.com.
10.1.1 Additional Layout Considerations
The high impedance of the FB pin makes the regulator sensitive to parasitic capacitances that may couple
undesirable signals from near-by components (specially from logic and digital ICs, such as microcontrollers and
microprocessors); these capacitively-coupled signals may produce undesirable output voltage transients. In these
cases, TI recommends using a fixed-voltage version of the TPS7A16, or isolate the FB node by flooding the local
PCB area with ground-plane copper to minimize any undesirable signal coupling.
10.2 Layout Example
Layout is a critical part of good power-supply design. There are several signal paths that conduct fast-changing
currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade
the power-supply performance. To help eliminate these problems, the IN pin should be bypassed to ground with
a low ESR ceramic bypass capacitor with a X5R or X7R dielectric.
It may be possible to obtain acceptable performance with alternative PCB layouts; however, the layout and the
schematic have been shown to produce good results and are meant as a guideline.
Figure 21 shows the schematic for the suggested layout. Figure 22 and Figure 23 show the top and bottom
printed-circuit-board (PCB) layers for the suggested layout.
Copyright © 2011–2015, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Links: TPS7A16
1300 mil
2200 mil
``
1
2
3
4
8
7
6
5
OUT
FB
PG
GND
IN
DELAY
NC
EN
CDELAY
Input GND Plane
Output GND Plane
Vin
Notes: Cin and Cout are 1208 packages
CNR, R1, and R2 are 0402 packages
Thermal
Pad
Cout
R2
Sense Line
Vout Cin
R1
Denotes a via to a connection made on another layer
TPS7A16
SBVS171F –DECEMBER 2011–REVISED OCTOBER 2015
www.ti.com
Layout Example (continued)
Figure 21. Schematic for Suggested Layout
Figure 22. Suggested Layout: Top Layer
20 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: TPS7A16
P =(V V )I-
D IN OUT OUT
1300 mil
2200 mil
TPS7A16
www.ti.com
SBVS171F –DECEMBER 2011–REVISED OCTOBER 2015
Layout Example (continued)
Figure 23. Suggested Layout: Bottom Layer
10.3 Power Dissipation
The ability to remove heat from the die is different for each package type, presenting different considerations in
the PCB layout. The PCB area around the device that is free of other components moves the heat from the
device to the ambient air. Using heavier copper increases the effectiveness in removing heat from the device.
The addition of plated through-holes to heat dissipating layers also improves the heatsink effectiveness.
Power dissipation depends on input voltage and load conditions. Power dissipation (PD) is equal to the product of
the output current times the voltage drop across the output pass element, as shown in Equation 2:
(2)
10.4 Thermal Considerations
Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate
heat spreading area. For reliable operation, junction temperature should be limited to a maximum of +125°C at
the worst case ambient temperature for a given application. To estimate the margin of safety in a complete
design (including the copper heat-spreading area), increase the ambient temperature until the thermal protection
is triggered; use worst-case loads and signal conditions. For good reliability, thermal protection should trigger at
least +45°C above the maximum expected ambient condition of the particular application. This configuration
produces a worst-case junction temperature of +125°C at the highest expected ambient temperature and worst-
case load.
The internal protection circuitry of the TPS7A16 has been designed to protect against overload conditions. It was
not intended to replace proper heatsinking. Continuously running the TPS7A16 into thermal shutdown degrades
device reliability.
Copyright © 2011–2015, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Links: TPS7A16
TPS7A16
SBVS171F –DECEMBER 2011–REVISED OCTOBER 2015
www.ti.com
11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
•Pros and Cons of Using a Feedforward Capacitor with a Low-Dropout Regulator,SBVA042
•Using New Thermal Metrics,SBVA025
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.5 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
22 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: TPS7A16
PACKAGE OPTION ADDENDUM
www.ti.com 30-Sep-2015
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
TPS7A1601DGNR ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PTYQ
TPS7A1601DGNT ACTIVE MSOP-
PowerPAD DGN 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PTYQ
TPS7A1601DRBR ACTIVE SON DRB 8 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PA5M
TPS7A1601DRBT ACTIVE SON DRB 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PA5M
TPS7A1633DGNR ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PPNQ
TPS7A1633DGNT ACTIVE MSOP-
PowerPAD DGN 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PPNQ
TPS7A1633DRBR ACTIVE SON DRB 8 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PPNQ
TPS7A1633DRBT ACTIVE SON DRB 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PPNQ
TPS7A1650DGNR ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PPOQ
TPS7A1650DGNT ACTIVE MSOP-
PowerPAD DGN 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PPOQ
TPS7A1650DRBR ACTIVE SON DRB 8 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PPOQ
TPS7A1650DRBT ACTIVE SON DRB 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PPOQ
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
PACKAGE OPTION ADDENDUM
www.ti.com 30-Sep-2015
Addendum-Page 2
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS7A1601DGNR MSOP-
Power
PAD
DGN 8 2500 330.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1
TPS7A1601DGNT MSOP-
Power
PAD
DGN 8 250 180.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1
TPS7A1601DRBR SON DRB 8 3000 330.0 12.4 3.3 3.3 1.0 8.0 12.0 Q2
TPS7A1601DRBT SON DRB 8 250 180.0 12.4 3.3 3.3 1.0 8.0 12.0 Q2
TPS7A1633DGNR MSOP-
Power
PAD
DGN 8 2500 330.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1
TPS7A1633DGNT MSOP-
Power
PAD
DGN 8 250 180.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1
TPS7A1633DRBR SON DRB 8 3000 330.0 12.4 3.3 3.3 1.0 8.0 12.0 Q2
TPS7A1633DRBT SON DRB 8 250 180.0 12.4 3.3 3.3 1.0 8.0 12.0 Q2
TPS7A1650DGNR MSOP-
Power
PAD
DGN 8 2500 330.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1
TPS7A1650DGNT MSOP-
Power
PAD
DGN 8 250 180.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Aug-2017
Pack Materials-Page 1
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS7A1650DRBR SON DRB 8 3000 330.0 12.4 3.3 3.3 1.0 8.0 12.0 Q2
TPS7A1650DRBT SON DRB 8 250 180.0 12.4 3.3 3.3 1.0 8.0 12.0 Q2
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS7A1601DGNR MSOP-PowerPAD DGN 8 2500 370.0 355.0 55.0
TPS7A1601DGNT MSOP-PowerPAD DGN 8 250 195.0 200.0 45.0
TPS7A1601DRBR SON DRB 8 3000 370.0 355.0 55.0
TPS7A1601DRBT SON DRB 8 250 220.0 205.0 50.0
TPS7A1633DGNR MSOP-PowerPAD DGN 8 2500 370.0 355.0 55.0
TPS7A1633DGNT MSOP-PowerPAD DGN 8 250 195.0 200.0 45.0
TPS7A1633DRBR SON DRB 8 3000 370.0 355.0 55.0
TPS7A1633DRBT SON DRB 8 250 220.0 205.0 50.0
TPS7A1650DGNR MSOP-PowerPAD DGN 8 2500 370.0 355.0 55.0
TPS7A1650DGNT MSOP-PowerPAD DGN 8 250 195.0 200.0 45.0
TPS7A1650DRBR SON DRB 8 3000 370.0 355.0 55.0
TPS7A1650DRBT SON DRB 8 250 220.0 205.0 50.0
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Aug-2017
Pack Materials-Page 2
www.ti.com
PACKAGE OUTLINE
C
8X 0.35
0.25
2.4 0.05
2X
1.95
1.65 0.05
6X 0.65
1 MAX
8X 0.5
0.3
0.05
0.00
A3.1
2.9 B
3.1
2.9
(0.2) TYP
VSON - 1 mm max heightDRB0008B
PLASTIC SMALL OUTLINE - NO LEAD
4218876/A 12/2017
PIN 1 INDEX AREA
SEATING PLANE
0.08 C
1
45
8
(OPTIONAL)
PIN 1 ID 0.1 C A B
0.05 C
THERMAL PAD
EXPOSED
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
SCALE 4.000
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
8X (0.3)
(2.4)
(2.8)
6X (0.65)
(1.65)
( 0.2) VIA
TYP
(0.575)
(0.95)
8X (0.6)
(R0.05) TYP
VSON - 1 mm max heightDRB0008B
PLASTIC SMALL OUTLINE - NO LEAD
4218876/A 12/2017
SYMM
1
45
8
LAND PATTERN EXAMPLE
SCALE:20X
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
SOLDER MASK
OPENING
SOLDER MASK
METAL UNDER
SOLDER MASK
DEFINED
METAL
SOLDER MASK
OPENING
SOLDER MASK DETAILS
NON SOLDER MASK
DEFINED
(PREFERRED)
www.ti.com
EXAMPLE STENCIL DESIGN
(R0.05) TYP
8X (0.3)
8X (0.6)
(1.47)
(1.06)
(2.8)
(0.63)
6X (0.65)
VSON - 1 mm max heightDRB0008B
PLASTIC SMALL OUTLINE - NO LEAD
4218876/A 12/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
81% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
SYMM
1
45
8
METAL
TYP
SYMM
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products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards
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Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life
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TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product).
Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications
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Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s non-
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