UPD44165084AF5-E50-EQ2-A - Renesas Electronics

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MOS INTEGRATED CIRCUIT

PD44165084A-A, 44165094A-A, 44165184A-A, 44165364A-A

18M-BIT QDRTMII SRAM

4-WORD BURST OPERATION

Document No. M19870EJ1V0DS00 (1st edition)

Date Published July 2009

Printed in Japan

DATA SHEET

2009

Description

The

PD44165084A-A is a 2,097,152-word by 8-bit, the

PD44165094A-A is a 2,097,152-word by 9-bit, the

PD44165184A-A is a 1,048,576-word by 18-bit and the

PD44165364A-A is a 524,288-word by 36-bit synchronous quad

data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell.

The

PD44165084A-A,

PD44165094A-A,

PD44165184A-A and

PD44165364A-A integrate unique synchronous

peripheral circuitry and a burst counter. All input registers controlled by an input clock pair (K and K#) are latched on

the positive edge of K and K#.

These products are suitable for application which require synchronous operation, high speed, low voltage, high density

and wide bit configuration.

These products are packaged in 165-pin PLASTIC BGA.

Features

• 1.8 ± 0.1 V power supply

• 165-pin PLASTIC BGA (13 x 15)

• HSTL interface

• PLL circuitry for wide output data valid window and future frequency scaling

• Separate independent read and write data ports with concurrent transactions

• 100% bus utilization DDR READ and WRITE operation

• Four-tick burst for reduced address frequency

• Two input clocks (K and K#) for precise DDR timing at clock rising edges only

• Two output clocks (C and C#) for precise flight time

and clock skew matching-clock and data delivered together to receiving device

• Internally self-timed write control

• Clock-stop capability. Normal operation is restored in 1,024 cycles after clock is resumed.

• User programmable impedance output

• Fast clock cycle time : 3.3 ns (300 MHz) , 3.7 ns (270 MHz) , 4.0 ns (250 MHz) , 5.0 ns (200 MHz)

• Simple control logic for easy depth expansion

• JTAG boundary scan

• Operating ambient temperature : Commercial TA = 0 to +70°C (-E33, -E40, -E50)

Industrial TA = –40 to +85°C (-E37Y, -E40Y, -E50Y)

2 Data Sheet M19870EJ1V0DS

PD44165084A-A, 44165094A-A, 44165184A-A, 44165364A-A

Ordering Information

(1) Operating Ambient Temperature TA = 0 to +70°C

Part number Cycle Clock Organization Package Operating

Time Frequency (word x bit) Ambient

ns MHz Temperature

PD44165084AF5-E33-EQ2-A

3.3 300 2M x 8-bit 165-pin PLASTIC Commercial

PD44165084AF5-E40-EQ2-A 4.0 250 BGA (13 x 15) (TA = 0 to +70°C)

PD44165084AF5-E50-EQ2-A 5.0 200

PD44165094AF5-E33-EQ2-A

3.3 300 2M x 9-bit Lead-free

PD44165094AF5-E40-EQ2-A 4.0 250

PD44165094AF5-E50-EQ2-A 5.0 200

PD44165184AF5-E33-EQ2-A

3.3 300 1M x 18-bit

PD44165184AF5-E40-EQ2-A 4.0 250

PD44165184AF5-E50-EQ2-A 5.0 200

PD44165364AF5-E33-EQ2-A

3.3 300 512K x 36-bit

PD44165364AF5-E40-EQ2-A 4.0 250

PD44165364AF5-E50-EQ2-A 5.0 200

Remarks 1. QDR Consortium standard package size is 13 x 15 and 15 x 17.

The footprint is commonly used.

2. Products with -A at the end of the part number are lead-free products.

3 Data Sheet M19870EJ1V0DS

PD44165084A-A, 44165094A-A, 44165184A-A, 44165364A-A

(2) Operating Ambient Temperature TA = –40 to +85°C

Part number Cycle Clock Organization Package Operating

Time Frequency (word x bit) Ambient

ns MHz Temperature

PD44165084AF5-E37Y-EQ2-A 3.7 270 2M x 8-bit 165-pin PLASTIC Industrial

PD44165084AF5-E40Y-EQ2-A 4.0 250 BGA (13 x 15) (TA = –40 to +85°C)

PD44165084AF5-E50Y-EQ2-A 5.0 200

PD44165094AF5-E37Y-EQ2-A 3.7 270 2M x 9-bit Lead-free

PD44165094AF5-E40Y-EQ2-A 4.0 250

PD44165094AF5-E50Y-EQ2-A 5.0 200

PD44165184AF5-E37Y-EQ2-A 3.7 270 1M x 18-bit

PD44165184AF5-E40Y-EQ2-A 4.0 250

PD44165184AF5-E50Y-EQ2-A 5.0 200

Remarks 1. QDR Consortium standard package size is 13 x 15 and 15 x 17.

The footprint is commonly used.

2. Products with -A at the end of the part number are lead-free products.

4 Data Sheet M19870EJ1V0DS

PD44165084A-A, 44165094A-A, 44165184A-A, 44165364A-A

Pin Configurations

165-pin PLASTIC BGA (13 x 15)

(Top View)

[

PD44165084A-A]

2M x 8-bit

1 2 3 4 5 6 7 8 9 10 11

A CQ# VSS A W# NW1# K# NC R# A VSS CQ

B NC NC NC A NC K NW0# A NC NC Q3

C NC NC NC VSS A NC A VSS NC NC D3

D NC D4 NC VSS VSS VSS VSS VSS NC NC NC

E NC NC Q4 VDDQ VSS VSS VSS VDDQ NC D2 Q2

F NC NC NC VDDQ VDD VSS VDD VDDQ NC NC NC

G NC D5 Q5 VDDQ VDD VSS VDD VDDQ NC NC NC

H DLL# VREF VDDQ VDDQ VDD VSS VDD VDDQVDDQVREF ZQ

J NC NC NC VDDQ VDD VSS VDD VDDQ NC Q1 D1

K NC NC NC VDDQ VDD VSS VDD VDDQ NC NC NC

L NC Q6 D6 VDDQ VSS VSS VSS VDDQ NC NC Q0

M NC NC NC VSS VSS VSS VSS VSS NC NC D0

N NC D7 NC VSS A A A VSS NC NC NC

P NC NC Q7 A A C A A NC NC NC

R TDO TCK A A A C# A A A TMS TDI

A : Address inputs DLL# : DLL/PLL disable

D0 to D7 : Data inputs TMS : IEEE 1149.1 Test input

Q0 to Q7 : Data outputs TDI : IEEE 1149.1 Test input

R# : Read input TCK : IEEE 1149.1 Clock input

W# : Write input TDO : IEEE 1149.1 Test output

NW0#, NW1# : Nibble Write data select VREF : HSTL input reference input

K, K# : Input clock VDD : Power Supply

C, C# : Output clock VDDQ : Power Supply

CQ, CQ# : Echo clock VSS : Ground

ZQ : Output impedance matching NC : No connection

Remarks 1. ×××# indicates active LOW signal.

2. Refer to Package Drawing for the index mark.

3. 2A, 7A and 10A are expansion addresses: 10A for 36Mb, 2A for 72Mb and 7A for 144Mb.

2A and 10A of this product can also be used as NC.

5 Data Sheet M19870EJ1V0DS

PD44165084A-A, 44165094A-A, 44165184A-A, 44165364A-A

165-pin PLASTIC BGA (13 x 15)

(Top View)

[

PD44165094A-A]

2M x 9-bit

1 2 3 4 5 6 7 8 9 10 11

A CQ# VSS A W# NC K# NC R# A VSS CQ

B NC NC NC A NC K BW0# A NC NC Q4

C NC NC NC VSS A NC A VSS NC NC D4

D NC D5 NC VSS VSS VSS VSS VSS NC NC NC

E NC NC Q5 VDDQ VSS VSS VSS VDDQ NC D3 Q3

F NC NC NC VDDQ VDD VSS VDD VDDQ NC NC NC

G NC D6 Q6 VDDQ VDD VSS VDD VDDQ NC NC NC

H DLL# VREF VDDQ VDDQ VDD VSS VDD VDDQVDDQVREF ZQ

J NC NC NC VDDQ VDD VSS VDD VDDQ NC Q2 D2

K NC NC NC VDDQ VDD VSS VDD VDDQ NC NC NC

L NC Q7 D7 VDDQ VSS VSS VSS VDDQ NC NC Q1

M NC NC NC VSS VSS VSS VSS VSS NC NC D1

N NC D8 NC VSS A A A VSS NC NC NC

P NC NC Q8 A A C A A NC D0 Q0

R TDO TCK A A A C# A A A TMS TDI

A : Address inputs DLL# : DLL/PLL disable

D0 to D8 : Data inputs TMS : IEEE 1149.1 Test input

Q0 to Q8 : Data outputs TDI : IEEE 1149.1 Test input

R# : Read input TCK : IEEE 1149.1 Clock input

W# : Write input TDO : IEEE 1149.1 Test output

BW0# : Byte Write data select VREF : HSTL input reference input

K, K# : Input clock VDD : Power Supply

C, C# : Output clock VDDQ : Power Supply

CQ, CQ# : Echo clock VSS : Ground

ZQ : Output impedance matching NC : No connection

Remarks 1. ×××# indicates active LOW signal.

2. Refer to Package Drawing for the index mark.

3. 2A, 7A and 10A are expansion addresses: 10A for 36Mb, 2A for 72Mb and 7A for 144Mb.

2A and 10A of this product can also be used as NC.

6 Data Sheet M19870EJ1V0DS

PD44165084A-A, 44165094A-A, 44165184A-A, 44165364A-A

165-pin PLASTIC BGA (13 x 15)

(Top View)

[

PD44165184A-A]

1M x 18-bit

1 2 3 4 5 6 7 8 9 10 11

A CQ# VSS NC W# BW1# K# NC R# A VSS CQ

B NC Q9 D9 A NC K BW0# A NC NC Q8

C NC NC D10 VSS A NC A VSS NC Q7 D8

D NC D11 Q10 VSS VSS VSS VSS VSS NC NC D7

E NC NC Q11 VDDQ VSS VSS VSS VDDQ NC D6 Q6

F NC Q12 D12 VDDQ VDD VSS VDD VDDQ NC NC Q5

G NC D13 Q13 VDDQ VDD VSS VDD VDDQ NC NC D5

H DLL# VREF VDDQ VDDQ VDD VSS VDD VDDQVDDQVREF ZQ

J NC NC D14 VDDQ VDD VSS VDD VDDQ NC Q4 D4

K NC NC Q14 VDDQ VDD VSS VDD VDDQ NC D3 Q3

L NC Q15 D15 VDDQ VSS VSS VSS VDDQ NC NC Q2

M NC NC D16 VSS VSS VSS VSS VSS NC Q1 D2

N NC D17 Q16 VSS A A A VSS NC NC D1

P NC NC Q17 A A C A A NC D0 Q0

R TDO TCK A A A C# A A A TMS TDI

A : Address inputs DLL# : DLL/PLL disable

D0 to D17 : Data inputs TMS : IEEE 1149.1 Test input

Q0 to Q17 : Data outputs TDI : IEEE 1149.1 Test input

R# : Read input TCK : IEEE 1149.1 Clock input

W# : Write input TDO : IEEE 1149.1 Test output

BW0#, BW1# : Byte Write data select VREF : HSTL input reference input

K, K# : Input clock VDD : Power Supply

C, C# : Output clock VDDQ : Power Supply

CQ, CQ# : Echo clock VSS : Ground

ZQ : Output impedance matching NC : No connection

Remarks 1. ×××# indicates active LOW signal.

2. Refer to Package Drawing for the index mark.

3. 2A, 3A and 10A are expansion addresses: 3A for 36Mb, 10A for 72Mb and 2A for 144Mb.

2A and 10A of this product can also be used as NC.

7 Data Sheet M19870EJ1V0DS

PD44165084A-A, 44165094A-A, 44165184A-A, 44165364A-A

165-pin PLASTIC BGA (13 x 15)

(Top View)

[

PD44165364A-A]

512K x 36-bit

1 2 3 4 5 6 7 8 9 10 11

A CQ# VSS NC W# BW2# K# BW1# R# NC VSS CQ

B Q27 Q18 D18 A BW3# K BW0# A D17 Q17 Q8

C D27 Q28 D19 VSS A NC A VSS D16 Q7 D8

D D28 D20 Q19 VSS VSS VSS VSS VSS Q16 D15 D7

E Q29 D29 Q20 VDDQ VSS VSS VSS VDDQ Q15 D6 Q6

F Q30 Q21 D21 VDDQ VDD VSS VDD VDDQ D14 Q14 Q5

G D30 D22 Q22 VDDQ VDD VSS VDD VDDQ Q13 D13 D5

H DLL# VREF VDDQ VDDQ VDD VSS VDD VDDQVDDQVREF ZQ

J D31 Q31 D23 VDDQ VDD VSS VDD VDDQ D12 Q4 D4

K Q32 D32 Q23 VDDQ VDD VSS VDD VDDQ Q12 D3 Q3

L Q33 Q24 D24 VDDQ VSS VSS VSS VDDQ D11 Q11 Q2

M D33 Q34 D25 VSS VSS VSS VSS VSS D10 Q1 D2

N D34 D26 Q25 VSS A A A VSS Q10 D9 D1

P Q35 D35 Q26 A A C A A Q9 D0 Q0

R TDO TCK A A A C# A A A TMS TDI

A : Address inputs DLL# : DLL/PLL disable

D0 to D35 : Data inputs TMS : IEEE 1149.1 Test input

Q0 to Q35 : Data outputs TDI : IEEE 1149.1 Test input

R# : Read input TCK : IEEE 1149.1 Clock input

W# : Write input TDO : IEEE 1149.1 Test output

BW0# to BW3# : Byte Write data select VREF : HSTL input reference input

K, K# : Input clock VDD : Power Supply

C, C# : Output clock VDDQ : Power Supply

CQ, CQ# : Echo clock VSS : Ground

ZQ : Output impedance matching NC : No connection

Remarks 1. ×××# indicates active LOW signal.

2. Refer to Package Drawing for the index mark.

3. 3A, 9A and 10A are expansion addresses: 9A for 36Mb, 3A for 72Mb and 10A for 144Mb.

2A and 10A of this product can also be used as NC.

8 Data Sheet M19870EJ1V0DS

PD44165084A-A, 44165094A-A, 44165184A-A, 44165364A-A

Pin Identification (1/2)

Symbol Description

A Synchronous Address Inputs: These inputs are registered and must meet the setup and hold times around the

rising edge of K. All transactions operate on a burst of four words (two clock periods of bus activity). These

inputs are ignored when device is deselected, i.e., NOP (R# = W# = HIGH).

D0 to Dxx Synchronous Data Inputs: Input data must meet setup and hold times around the rising edges of K and K#

during WRITE operations. See Pin Configurations for ball site location of individual signals.

x8 device uses D0 to D7.

x9 device uses D0 to D8.

x18 device uses D0 to D17.

x36 device uses D0 to D35.

Q0 to Qxx Synchronous Data Outputs: Output data is synchronized to the respective C and C# or to K and K# rising edges

if C and C# are tied HIGH. Data is output in synchronization with C and C# (or K and K#), depending on the R#

command. See Pin Configurations for ball site location of individual signals.

x8 device uses Q0 to Q7.

x9 device uses Q0 to Q8.

x18 device uses Q0 to Q17.

x36 device uses Q0 to Q35.

R# Synchronous Read: When LOW this input causes the address inputs to be registered and a READ cycle to be

initiated. This input must meet setup and hold times around the rising edge of K. If a READ command (R# =

LOW) is input, an input of R# on the subsequent rising edge of K is ignored.

W# Synchronous Write: When LOW this input causes the address inputs to be registered and a WRITE cycle to be

initiated. This input must meet setup and hold times around the rising edge of K. If a WRITE command (W# =

LOW) is input, an input of W# on the subsequent rising edge of K is ignored.

BWx#

NWx#

Synchronous Byte Writes (Nibble Writes on x8): When LOW these inputs cause their respective byte or nibble

to be registered and written during WRITE cycles. These signals must meet setup and hold times around the

rising edges of K and K# for each of the two rising edges comprising the WRITE cycle. See Pin

Configurations for signal to data relationships.

x8 device uses NW0#, NW1#.

x9 device uses BW0#.

x18 device uses BW0#, BW1#.

x36 device uses BW0# to BW3#.

See Byte Write Operation for relation between BWx#, NWx# and Dxx.

K, K# Input Clock: This input clock pair registers address and control inputs on the rising edge of K, and registers data

on the rising edge of K and the rising edge of K#. K# is ideally 180 degrees out of phase with K. All

synchronous inputs must meet setup and hold times around the clock rising edges.

C, C# Output Clock: This clock pair provides a user controlled means of tuning device output data. The rising edge of

C# is used as the output timing reference for first and third output data. The rising edge of C is used as the

output reference for second and fourth output data. Ideally, C# is 180 degrees out of phase with C. When use of

K and K# as the reference instead of C and C#, then fixed C and C# to HIGH. Operation cannot be guaranteed

unless C and C# are fixed to HIGH (i.e. toggle of C and C#).

9 Data Sheet M19870EJ1V0DS

PD44165084A-A, 44165094A-A, 44165184A-A, 44165364A-A

(2/2)

Symbol Description

CQ, CQ# Synchronous Echo Clock Outputs. The rising edges of these outputs are tightly matched to the synchronous

data outputs and can be used as a data valid indication. These signals run freely and do not stop when Q

tristates. If C and C# are stopped (if K and K# are stopped in the single clock mode), CQ and CQ# will also

stop.

ZQ Output Impedance Matching Input: This input is used to tune the device outputs to the system data bus

impedance. Q, CQ and CQ# output impedance are set to 0.2 x RQ, where RQ is a resistor from this bump to

ground. The output impedance can be minimized by directly connect ZQ to VDDQ. This pin cannot be connected

directly to GND or left unconnected. The output impedance is adjusted every 1,024 cycles upon power-up to

account for drifts in supply voltage and temperature. After replacement for a resistor, the new output impedance

is reset by implementing power-on sequence.

DLL# DLL/PLL Disable: When debugging the system or board, the operation can be performed at a clock frequency

slower than TKHKH (MAX.) without the DLL/PLL circuit being used, if DLL# = LOW. The AC/DC characteristics

cannot be guaranteed. For normal operation, DLL# must be HIGH and it can be connected to VDDQ through a

10 kΩ or less resistor.

TMS

TDI

IEEE 1149.1 Test Inputs: 1.8 V I/O level. These balls may be left Not Connected if the JTAG function is not

used in the circuit.

TCK IEEE 1149.1 Clock Input: 1.8 V I/O level. This pin must be tied to VSS if the JTAG function is not used in the

circuit.

TDO IEEE 1149.1 Test Output: 1.8 V I/O level.

VREF HSTL Input Reference Voltage: Nominally VDDQ/2. Provides a reference voltage for the input buffers.

VDD Power Supply: 1.8 V nominal. See Recommended DC Operating Conditions and DC Characteristics for

range.

VDDQ Power Supply: Isolated Output Buffer Supply. Nominally 1.5 V. 1.8 V is also permissible. See Recommended DC

Operating Conditions and DC Characteristics for range.

VSS Power Supply: Ground

NC No Connect: These signals are not connected internally.

10 Data Sheet M19870EJ1V0DS

PD44165084A-A, 44165094A-A, 44165184A-A, 44165364A-A

Block Diagram

[

PD44165084A-A]

DATA

REGISTRY

& LOGIC

OUTPUT

NW0#

NW1#

K# K

ADDRESS 19

D0 to D7 8

OUTPUT

SELECT

OUTPUT

BUFFER

MUX

ADDRESS

REGISTRY

& LOGIC

219x 32

MEMORY

ARRAY

WRITE

DRIVER

SENSE

AMPS

WRITE

Q0 to Q7

C, C#

K, K#

CQ,

CQ#

[

PD44165094A-A]

DATA

REGISTRY

& LOGIC

OUTPUT

BW0#

K# K

ADDRESS 19

D0 to D8 9

OUTPUT

SELECT

OUTPUT

BUFFER

MUX

ADDRESS

REGISTRY

& LOGIC

219x 36

MEMORY

ARRAY

WRITE

DRIVER

SENSE

AMPS

WRITE

Q0 to Q8

C, C#

K, K#

CQ,

CQ#

11 Data Sheet M19870EJ1V0DS

PD44165084A-A, 44165094A-A, 44165184A-A, 44165364A-A

[

PD44165184A-A]

DATA

REGISTRY

& LOGIC

OUTPUT

BW0#

BW1#

K# K

DDRESS 18

D0 to D17 18

OUTPUT

SELECT

OUTPUT

BUFFER

36 36

MUX

ADDRESS

REGISTRY

& LOGIC

x 72

MEMORY

ARRAY

WRITE

DRIVER

SENSE

AMPS

WRITE

Q0 to Q1

C, C#

K, K#

CQ,

CQ#

[

PD44165364A-A]

DATA

REGISTRY

& LOGIC

OUTPUT

BW0#

BW1#

K# K

ADDRESS 17

D0 to D35 36

OUTPUT

SELECT

OUTPUT

BUFFER

72 72

144

MUX

ADDRESS

REGISTRY

& LOGIC

217x 144

MEMORY

ARRAY

WRITE

DRIVER

SENSE

AMPS

WRITE

Q0 to Q35

C, C#

K, K#

CQ,

CQ#

BW2#

BW3#

12 Data Sheet M19870EJ1V0DS

PD44165084A-A, 44165094A-A, 44165184A-A, 44165364A-A

Power-on Sequence

The following timing charts show the recommended power-on sequence, i.e., when starting the clock after VDD/VDDQ

stable and when starting the clock before VDD/VDDQ stable.

1. Clock starts after VDD/VDDQ stable

The clock is supplied from a controller.

(a)

Q Stable (< ±0.1 V DC per 50 ns)

DLL#

Clock Start Normal Operation

Start

Clock

Fix HIGH (or tied to V

20 ns (MIN.)

1,024 cycles or more

Stable Clock

Note

Note Input a stable clock from the start.

(b)

VDD/VDDQ

DLL# Switched to HIGH after Clock is stable.

Unstable Clock

(level, frequency)

VDD/VDDQ Stable (< ±0.1 V DC per 50 ns)

Clock

Clock Start

Normal Operation

Start

1,024 cycles or more

Stable Clock

(c)

DLL#

30 ns. (MIN.)

Clock Stop

Q Stable (< ±0.1 V DC per 50 ns)

Fix HIGH (or tied to V

Unstable Clock

(level, frequency)

Clock

Clock Start

Normal Operation

Start

1,024 cycles or more

Stable Clock

13 Data Sheet M19870EJ1V0DS

PD44165084A-A, 44165094A-A, 44165184A-A, 44165364A-A

2. Clock starts before VDD/VDDQ stable

The clock is supplied from a clock generator.

(a)

DLL#

30 ns. (MIN.)

Clock Stop

Q Stable (< ±0.1 V DC per 50 ns)

Fix HIGH (or tied to V

Unstable Clock

(level, frequency)

Clock

Clock Start

Normal Operation Start1,024 cycles or more

Stable Clock

(b)

DLL#

Clock keep running

Switched to HIGH after Clock is stable.

HIGH or LOW

30 ns (MIN.)

DLL# LOW

Q Stable (< ±0.1 V DC per 50 ns)

Normal

Operation

Start

1,024 cycles or more

Stable Clock

Unstable Clock

(level, frequency)

Clock

Clock Start

14 Data Sheet M19870EJ1V0DS

PD44165084A-A, 44165094A-A, 44165184A-A, 44165364A-A

Truth Table

Operation CLK R# W# D or Q

WRITE cycle L → H H L Data in

Load address, input write data on two Input data DA(A+0) DA(A+1) DA(A+2) DA(A+3)

consecutive K and K# rising edge Input clock K(t+1) ↑K#(t+1) ↑ K(t+2) ↑K#(t+2) ↑

READ cycle L → H L X Data out

Load address, read data on two Output data QA(A+0) QA(A+1) QA(A+2) QA(A+3)

consecutive C and C# rising edge Output clock C#(t+1) ↑C(t+2) ↑ C#(t+2) ↑C(t+3) ↑

NOP (No operation) L → H H H D = X, Q = High-Z

Clock stop Stopped X X Previous state

Remarks 1. H : HIGH, L : LOW, × : don’t care, ↑ : rising edge.

2. Data inputs are registered at K and K# rising edges. Data outputs are delivered at C and C# rising edges

except if C and C# are HIGH then data outputs are delivered at K and K# rising edges.

3. R# and W# must meet setup/hold times around the rising edge (LOW to HIGH) of K and are registered at

the rising edge of K.

4. This device contains circuitry that ensure the outputs to be in high impedance during power-up.

5. Refer to state diagram and timing diagrams for clarification.

6. It is recommended that K = K# = C = C# when clock is stopped. This is not essential but permits most

rapid restart by overcoming transmission line charging symmetrically.

7. If R# was LOW to initiate the previous cycle, this signal becomes a don't care for this WRITE operation

however it is strongly recommended that this signal is brought HIGH as shown in the truth table.

8. W# during write cycle and R# during read cycle were HIGH on previous K clock rising edge. Initiating

consecutive READ or WRITE operations on consecutive K clock rising edges is not permitted. The

device will ignore the second request.

15 Data Sheet M19870EJ1V0DS

PD44165084A-A, 44165094A-A, 44165184A-A, 44165364A-A

Byte Write Operation

[

PD44165084A-A]

Operation K K# NW0# NW1#

Write D0 to D7 L → H – 0 0

– L → H 0 0

Write D0 to D3 L → H – 0 1

– L → H 0 1

Write D4 to D7 L → H – 1 0

– L → H 1 0

Write nothing L → H – 1 1

– L → H 1 1

Remarks 1. H : HIGH, L : LOW, → : rising edge.

2. Assumes a WRITE cycle was initiated. NW0# and NW1# can be altered for any portion of the BURST

WRITE operation provided that the setup and hold requirements are satisfied.

[

PD44165094A-A]

Operation K K# BW0#

Write D0 to D8 L → H – 0

– L → H 0

Write nothing L → H – 1

– L → H 1

Remarks 1. H : HIGH, L : LOW, → : rising edge.

2. Assumes a WRITE cycle was initiated. BW0# can be altered for any portion of the BURST WRITE

operation provided that the setup and hold requirements are satisfied.

[

PD44165184A-A]

Operation K K# BW0# BW1#

Write D0 to D17 L → H – 0 0

– L → H 0 0

Write D0 to D8 L → H – 0 1

– L → H 0 1

Write D9 to D17 L → H – 1 0

– L → H 1 0

Write nothing L → H – 1 1

– L → H 1 1

Remarks 1. H : HIGH, L : LOW, → : rising edge.

2. Assumes a WRITE cycle was initiated. BW0# and BW1# can be altered for any portion of the BURST

WRITE operation provided that the setup and hold requirements are satisfied.

16 Data Sheet M19870EJ1V0DS

PD44165084A-A, 44165094A-A, 44165184A-A, 44165364A-A

[

PD44165364A-A]

Operation K K# BW0# BW1# BW2# BW3#

Write D0 to D35 L → H – 0 0 0 0

– L → H 0 0 0 0

Write D0 to D8 L → H – 0 1 1 1

– L → H 0 1 1 1

Write D9 to D17 L → H – 1 0 1 1

– L → H 1 0 1 1

Write D18 to D26 L → H – 1 1 0 1

– L → H 1 1 0 1

Write D27 to D35 L → H – 1 1 1 0

– L → H 1 1 1 0

Write nothing L → H – 1 1 1 1

– L → H 1 1 1 1

Remarks 1. H : HIGH, L : LOW, → : rising edge.

2. Assumes a WRITE cycle was initiated. BW0# to BW3# can be altered for any portion of the BURST

WRITE operation provided that the setup and hold requirements are satisfied.

17 Data Sheet M19870EJ1V0DS

PD44165084A-A, 44165094A-A, 44165184A-A, 44165364A-A

Bus Cycle State Diagram

READ DOUBLE;

R_Count = R_Count+2

WRITE DOUBLE;

W_Count = W_Count+2

Power UP

Always

R# = HIGH

Supply voltage

provided

LOAD NEW

READ ADDRESS;

R_Count = 0;

R_Init = 1

READ PORT NOP

R_Init = 0

R# = LOW & R_Count = 4

W# = HIGH

WRITE PORT NOP

LOAD NEW

WRITE ADDRESS;

W_Count = 0

Always W# = LOW & W_Count = 4

W# = LOW

R_Init = 0 R# = LOW

Supply voltage

provided

INCREMENT READ

ADDRESS BY TWO

R_Init = 0

INCREMENT WRITE

ADDRESS BY TWO

W_Count = 2 R_Count = 2 AlwaysAlways

W# = HIGH

& W_Count = 4

R# = HIGH

& R_Count = 4

Remarks 1. The address is concatenated with two additional internal LSBs to facilitate burst operation.

The address order is always fixed as: xxx...xxx+0, xxx...xxx+1, xxx...xxx+2, xxx...xxx+3.

Bus cycle is terminated at the end of this sequence (burst count = 4).

2. Read and write state machines can be active simultaneously.

Read and write cannot be simultaneously initiated. Read takes precedence.

3. State machine control timing is controlled by K.

18 Data Sheet M19870EJ1V0DS

PD44165084A-A, 44165094A-A, 44165184A-A, 44165364A-A

Electrical Specifications

Absolute Maximum Ratings

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Supply voltage VDD –0.5 +2.5 V

Output supply voltage VDDQ –0.5 VDD V

Input voltage VIN –0.5 VDD + 0.5 (2.5 V MAX.) V

Input / Output voltage VI/O –0.5 VDDQ + 0.5 (2.5 V MAX.) V

Operating ambient temperature TA Commercial 0 +70 °C

Industrial –40 +85

Storage temperature Tstg –55 +125 °C

Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause

permanent damage. The device is not meant to be operated under conditions outside the limits

described in the operational section of this specification. Exposure to Absolute Maximum Rating

conditions for extended periods may affect device reliability.

Recommended DC Operating Conditions

Parameter Symbol Conditions MIN. TYP. MAX. Unit Note

Supply voltage VDD 1.7 1.9 V

Output supply voltage VDDQ 1.4 VDD V 1

Input HIGH voltage VIH (DC) VREF + 0.1 VDDQ + 0.3 V 1, 2

Input LOW voltage VIL (DC) –0.3 VREF – 0.1 V 1, 2

Clock input voltage VIN –0.3 VDDQ + 0.3 V 1, 2

Reference voltage VREF 0.68 0.95 V

Notes 1. During normal operation, VDDQ must not exceed VDD.

2. Power-up: VIH ≤ VDDQ + 0.3 V and VDD ≤ 1.7 V and VDDQ ≤ 1.4 V for t ≤ 200 ms

Recommended AC Operating Conditions

Parameter Symbol Conditions MIN. TYP. MAX. Unit Note

Input HIGH voltage VIH (AC) VREF + 0.2 – V 1

Input LOW voltage VIL (AC) – VREF – 0.2 V 1

Note 1. Overshoot: VIH (AC) ≤ VDD + 0.7 V (2.5 V MAX.) for t ≤ TKHKH/2

Undershoot: VIL (AC) ≥ – 0.5 V for t ≤ TKHKH/2

Control input signals may not have pulse widths less than TKHKL (MIN.) or operate at cycle rates less than

TKHKH (MIN.).

19 Data Sheet M19870EJ1V0DS

PD44165084A-A, 44165094A-A, 44165184A-A, 44165364A-A

DC Characteristics (VDD = 1.8 ± 0.1 V)

Parameter Symbol Test condition MIN. TYP. MAX. Unit Note

x8, x9 x18 x36

Input leakage current ILI –2 – +2

I/O leakage current ILO –2 – +2

Operating supply IDD Note1 Commercial -E33 520 610 790 mA

current (TA = 0 to +70°C) -E40 460 530 680

(Read cycle/ -E50 410 460 580

Write cycle) Industrial -E37Y 500 580 –

(TA = –40 to +85°C) -E40Y 480 550 –

-E50Y 430 480 –

Standby supply ISB1 Note1 Commercial -E33 300 300 300 mA

current (TA = 0 to +70°C) -E40 280 280 280

(NOP) -E50 260 260 260

Industrial -E37Y 310 310 –

(TA = –40 to +85°C) -E40Y 300 300 –

-E50Y 280 280 –

Output HIGH voltage VOH(Low) |IOH| ≤ 0.1 mA VDDQ – 0.2 – VDDQ V 4, 5

VOH Note2 VDDQ/2–0.12 – VDDQ/2+0.12 4, 5

Output LOW voltage VOL(Low) IOL ≤ 0.1 mA VSS – 0.2 V 4, 5

VOL Note3 VDDQ/2–0.12 – VDDQ/2+0.12 4, 5

Notes 1. VIN ≤ VIL or VIN ≥ VIH, II/O = 0 mA, Cycle = MAX.

2. Outputs are impedance-controlled. | IOH | = (VDDQ/2)/(RQ/5) ±15% for values of 175 Ω ≤ RQ ≤ 350 Ω.

3. Outputs are impedance-controlled. IOL = (VDDQ/2)/(RQ/5) ±15% for values of 175 Ω ≤ RQ ≤ 350 Ω.

4. AC load current is higher than the shown DC values.

5. HSTL outputs meet JEDEC HSTL Class I standards.

Capacitance (TA = 25°C, f = 1 MHz)

Parameter Symbol Test conditions MIN. TYP. MAX. Unit

Input capacitance (Address, Control) CIN VIN = 0 V 4 5 pF

Input / Output capacitance CI/O VI/O = 0 V 6 7 pF

(D, Q, CQ, CQ#)

Clock Input capacitance Cclk Vclk = 0 V 5 6 pF

Remark These parameters are periodically sampled and not 100% tested.

Thermal Resistance

Parameter Symbol Test conditions MIN. TYP. MAX. Unit

Thermal resistance

j-a 25.1 °C/W

(junction – ambient)

Thermal resistance

j-c 2.8 °C/W

(junction – case)

Remark These parameters are simulated under the condition of air flow velocity = 1 m/s.

20 Data Sheet M19870EJ1V0DS

PD44165084A-A, 44165094A-A, 44165184A-A, 44165364A-A

AC Characteristics (VDD = 1.8 ± 0.1 V)

AC Test Conditions (VDD = 1.8 ± 0.1 V, VDDQ = 1.4 V to VDD)

Input waveform (Rise / Fall time ≤ 0.3 ns)

0.75 V 0.75 V

Test Points

1.25 V

0.25 V

Output waveform

Q / 2 V

Q / 2

Test Points

Output load condition

Figure 1. External load at test

Q / 2

0.75 V 50 Ω

= 50 Ω

250 Ω

SRAM

REF

21 Data Sheet M19870EJ1V0DS

PD44165084A-A, 44165094A-A, 44165184A-A, 44165364A-A

Read and Write Cycle

Parameter Symbol

-E33 -E37Y

-E40, -E40Y -E50, -E50Y Unit Note

(300 MHz) (270 MHz) (250 MHz) (200 MHz)

MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.

Clock

Average Clock cycle time (K, K#, C, C#) TKHKH 3.3 8.4 3.7 8.4 4.0 8.4 5.0 8.4 ns 1

Clock phase jitter (K, K#, C, C#) TKC var – 0.2 − 0.2 – 0.2 – 0.2

ns 2

Clock HIGH time (K, K#, C, C#) TKHKL 1.32 – 1.5 − 1.6 – 2.0 – ns

Clock LOW time (K, K#, C, C#) TKLKH 1.32 – 1.5 − 1.6 – 2.0 – ns

Clock HIGH to Clock# HIGH

(K→K#, C→C#)

TKHK#H 1.49 – 1.7 − 1.8 – 2.2 – ns

Clock# HIGH to Clock HIGH

(K#→K, C#→C)

TK#HKH 1.49 – 1.7 − 1.8 – 2.2 – ns

Clock to data clock 270 to 300 MHz TKHCH 0 1.45 – – – – – –

(K→C, K#→C#) 250 to 270 MHz 0 1.65 0 1.65 – – – –

200 to 250 MHz 0 1.8 0 1.8 0 1.8 – –

167 to 200 MHz 0 2.3 0 2.3 0 2.3 0 2.3

133 to 167 MHz 0 2.8 0 2.8 0 2.8 0 2.8

< 133 MHz 0 3.55 0 3.55 0 3.55 0 3.55

DLL/PLL lock time (K, C) TKC lock 1,024 – 1,024 − 1,024 – 1,024 – Cycle 3

K static to DLL/PLL reset TKC reset 30 – 30 − 30 – 30 – ns 4

Output Times

C, C# HIGH to output valid TCHQV – 0.45 − 0.45 – 0.45 – 0.45

C, C# HIGH to output hold TCHQX – 0.45 – −0.45 − – 0.45 – – 0.45 – ns

C, C# HIGH to echo clock valid TCHCQV – 0.45 − 0.45 – 0.45 – 0.45

C, C# HIGH to echo clock hold TCHCQX – 0.45 – −0.45 − – 0.45 – – 0.45 – ns

CQ, CQ# HIGH to output valid TCQHQV – 0.27 − 0.3 – 0.3 – 0.35

ns 5

CQ, CQ# HIGH to output hold TCQHQX – 0.27 – – 0.3 − – 0.3 – – 0.35 – ns 5

C HIGH to output High-Z TCHQZ – 0.45 − 0.45 – 0.45 – 0.45

C HIGH to output Low-Z TCHQX1 – 0.45 – −0.45 − – 0.45 – – 0.45 – ns

Setup Times

Address valid to K rising edge TAVKH 0.4 – 0.5 − 0.5 – 0.6 – ns 6

Control inputs (R#, W#) valid to K rising

edge

TIVKH 0.4 – 0.5 − 0.5 – 0.6 – ns 6

Data inputs and write data select TDVKH 0.3 –

0.35 − 0.35 – 0.4 – ns 6

inputs (BWx#, NWx#) valid to K, K#

rising edge

Hold Times

K rising edge to address hold TKHAX 0.4 – 0.5 − 0.5 – 0.6 – ns 6

K rising edge to control inputs (R#, W#)

hold

TKHIX 0.4 – 0.5 − 0.5 – 0.6 – ns 6

K, K# rising edge to data inputs and TKHDX 0.3 –

0.35 − 0.35 – 0.4 – ns 6

write data select inputs (BWx#, NWx#)

hold

22 Data Sheet M19870EJ1V0DS

PD44165084A-A, 44165094A-A, 44165184A-A, 44165364A-A

Notes 1. When debugging the system or board, these products can operate at a clock frequency slower than TKHKH

(MAX.) without the DLL/PLL circuit being used, if DLL# = LOW. Read latency (RL) is changed to 1.5 clock in

this operation. The AC/DC characteristics cannot be guaranteed, however.

2. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge. TKC var

(MAX.) indicates a peak-to-peak value.

3. V

DD slew rate must be less than 0.1 V DC per 50 ns for DLL/PLL lock retention.

DLL/PLL lock time begins once VDD and input clock are stable.

It is recommended that the device is kept NOP (R# = W# = HIGH) during these cycles.

4. K input is monitored for this operation. See below for the timing.

TKC reset

5. Echo clock is very tightly controlled to data valid / data hold. By design, there is a ± 0.1 ns variation from

echo clock to data. The data sheet parameters reflect tester guardbands and test setup variations.

6. This is a synchronous device. All addresses, data and control lines must meet the specified setup

and hold times for all latching clock edges.

Remarks 1. This parameter is sampled.

2. Test conditions as specified with the output loading as shown in AC Test Conditions

unless otherwise noted.

3. Control input signals may not be operated with pulse widths less than TKHKL (MIN.).

4. If C, C# are tied HIGH, K, K# become the references for C, C# timing parameters.

5. VDDQ is 1.5 V DC.

23 Data Sheet M19870EJ1V0DS

PD44165084A-A, 44165094A-A, 44165184A-A, 44165364A-A

Read and Write Timing

Address

Data in

24613 5 7

TKHK#H TK#HKH

TKHCH

NOP READ READ

TKHKL TKLKH

Q00 Q02

Data out

Q01 Q03

TKHKL TKLKH

TCHQX1 TCHQX TCHQZ

D10 D12D11 D13

TDVKH TKHDX

TKHKH

TIVKH TKHIX

TAVKH TKHAX

CQ#

TCHQV

TCHCQX

TCHCQV

TCHCQX

TCHCQV

WRITE NOP

Qx3

TCHQX

TCHQV

WRITE

TIVKH TKHIX

A0 A1 A2 A3

D30 D32D31 D33

Q20 Q22Q21 Q23

Qx2

TKHK#H TK#HKH

TKHCH

TKHKH

TCQHQV

TCQHQX

Remarks 1. Q00 refers to output from address A0+0.

Q01 refers to output from the next internal burst address following A0,i.e.,A0+1.

2. Outputs are disabled (high impedance) 3.5 clocks after the last READ (R# = LOW) is input in the

sequences of [READ]-[NOP]-[NOP], [READ]-[WRITE]-[NOP] and [READ]-[NOP]-[WRITE].

3. In this example, if address A2 = A1, data Q20 = D10, Q21 = D11, Q22 = D12 and Q23 = D13.

Write data is forwarded immediately as read results.

24 Data Sheet M19870EJ1V0DS

PD44165084A-A, 44165094A-A, 44165184A-A, 44165364A-A

Application Example

SRAM

Controller

Data In

Data Out

Address

BW#

SRAM#1 CQ/CQ#

SRAM#4 CQ/CQ#

Source CLK/CLK#

Return CLK/CLK#

CQ#

SRAM#4

A R# W# BWx# C/C# K/K#

RVt

R =

250 ΩR =

250 Ω

CQ#

SRAM#1

A R# W# BWx# C/C# K/K#

R = 50 Ω Vt = Vref

. . .

Remark AC specifications are defined at the condition of SRAM outputs, CQ, CQ# and Q with termination.

25 Data Sheet M19870EJ1V0DS

PD44165084A-A, 44165094A-A, 44165184A-A, 44165364A-A

JTAG Specification

These products support a limited set of JTAG functions as in IEEE standard 1149.1.

Test Access Port (TAP) Pins

Pin name Pin assignments Description

TCK 2R Test Clock Input. All input are captured on the rising edge of TCK and all outputs

propagate from the falling edge of TCK.

TMS 10R Test Mode Select. This is the command input for the TAP controller state machine.

TDI 11R Test Data Input. This is the input side of the serial registers placed between TDI and

TDO. The register placed between TDI and TDO is determined by the state of the TAP

controller state machine and the instruction that is currently loaded in the TAP instruction.

TDO 1R Test Data Output. This is the output side of the serial registers placed between TDI and

TDO. Output changes in response to the falling edge of TCK.

Remark The device does not have TRST (TAP reset). The Test-Logic Reset state is entered while TMS is held HIGH

for five rising edges of TCK. The TAP controller state is also reset on the SRAM POWER-UP.

JTAG DC Characteristics (VDD = 1.8 ± 0.1 V, unless otherwise noted)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

JTAG Input leakage current ILI 0 V ≤ VIN ≤ VDD –5.0 – +5.0

JTAG I/O leakage current ILO 0 V ≤ VIN ≤ VDDQ , –5.0 – +5.0

Outputs disabled

JTAG input HIGH voltage VIH 1.3 – VDD+0.3 V

JTAG input LOW voltage VIL –0.3 – +0.5 V

JTAG output HIGH voltage VOH1 | IOHC | = 100

A 1.6 – – V

VOH2 | IOHT | = 2 mA 1.4 – – V

JTAG output LOW voltage VOL1 IOLC = 100

A – – 0.2 V

VOL2 IOLT = 2 mA – – 0.4 V

26 Data Sheet M19870EJ1V0DS

PD44165084A-A, 44165094A-A, 44165184A-A, 44165364A-A

JTAG AC Test Conditions

Input waveform (Rise / Fall time ≤ 1 ns)

0.9 V 0.9 V

Test Points

1.8 V

0 V

Output waveform

0.9 V 0.9 V

Test Points

Output load

Figure 2. External load at test

TDO Z

= 50 Ω

= 0.9 V

20 pF

50 Ω

27 Data Sheet M19870EJ1V0DS

PD44165084A-A, 44165094A-A, 44165184A-A, 44165364A-A

JTAG AC Characteristics

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Clock

Clock cycle time tTHTH 50 – – ns

Clock frequency fTF – – 20 MHz

Clock HIGH time tTHTL 20 – – ns

Clock LOW time tTLTH 20 – – ns

Output time

TCK LOW to TDO unknown tTLOX 0 – – ns

TCK LOW to TDO valid tTLOV – – 10 ns

Setup time

TMS setup time tMVTH 5 – – ns

TDI valid to TCK HIGH tDVTH 5 – – ns

Capture setup time tCS 5 – – ns

Hold time

TMS hold time tTHMX 5 – – ns

TCK HIGH to TDI invalid tTHDX 5 – – ns

Capture hold time tCH 5 – – ns

JTAG Timing Diagram

THTH

TLOV

TLTH

THTL

MVTH

THDX

DVTH

THMX

TCK

TMS

TDI

TDO

TLOX

28 Data Sheet M19870EJ1V0DS

PD44165084A-A, 44165094A-A, 44165184A-A, 44165364A-A

Scan Register Definition (1)

Instruction register The instruction register holds the instructions that are executed by the TAP controller when it is

moved into the run-test/idle or the various data register state. The register can be loaded when it is

placed between the TDI and TDO pins. The instruction register is automatically preloaded with the

IDCODE instruction at power-up whenever the controller is placed in test-logic-reset state.

Bypass register The bypass register is a single bit register that can be placed between TDI and TDO. It allows serial

test data to be passed through the RAMs TAP to another device in the scan chain with as little delay

as possible.

ID register The ID Register is a 32 bit register that is loaded with a device and vendor specific 32 bit code when

the controller is put in capture-DR state with the IDCODE command loaded in the instruction register.

The register is then placed between the TDI and TDO pins when the controller is moved into shift-DR

state.

Boundary register The boundary register, under the control of the TAP controller, is loaded with the contents of the

RAMs I/O ring when the controller is in capture-DR state and then is placed between the TDI and

TDO pins when the controller is moved to shift-DR state. Several TAP instructions can be used to

activate the boundary register.

The Scan Exit Order tables describe which device bump connects to each boundary register

location. The first column defines the bit’s position in the boundary register. The second column is

the name of the input or I/O at the bump and the third column is the bump number.

Scan Register Definition (2)

Instruction register 3 bit

Bypass register 1 bit

ID register 32 bit

Boundary register 107 bit

ID Register Definition

Part number Organization ID [31:28] vendor revision no. ID [27:12] part no. ID [11:1] vendor ID no. ID [0] fix bit

PD44165084A-A 2M x 8 XXXX 0000 0000 0000 1111 00000010000 1

PD44165094A-A 2M x 9 XXXX 0000 0000 0101 0010 00000010000 1

PD44165184A-A 1M x 18 XXXX 0000 0000 0001 0000 00000010000 1

PD44165364A-A 512K x 36 XXXX 0000 0000 0001 0001 00000010000 1

29 Data Sheet M19870EJ1V0DS

PD44165084A-A, 44165094A-A, 44165184A-A, 44165364A-A

SCAN Exit Order

Bit Signal name Bump Bit Signal name Bump Bit Signal name Bump

no. x8 x9 x18 x36 ID no. x8 x9 x18 x36 ID no. x8 x9 x18 x36 ID

1 C# 6R 37 NC NC NC D15 10D 73 NC NC NC Q28 2C

2 C 6P 38 NC NC NC Q15 9E 74 Q4 Q5 Q11 Q20 3E

3 A 6N 39 NC NC Q7 Q7 10C 75 D4 D5 D11 D20 2D

4 A 7P 40 NC NC D7 D7 11D 76 NC NC NC D29 2E

5 A 7N 41 NC NC NC D16 9C 77 NC NC NC Q29 1E

6 A 7R 42 NC NC NC Q16 9D 78 NC NC Q12 Q21 2F

7 A 8R 43 Q3 Q4 Q8 Q8 11B 79 NC NC D12 D21 3F

8 A 8P 44 D3 D4 D8 D8 11C 80 NC NC NC D30 1G

9 A 9R 45 NC NC NC D17 9B 81 NC NC NC Q30 1F

10 NC Q0 Q0 Q0 11P 46 NC NC NC Q17 10B 82 Q5 Q6 Q13 Q22 3G

11 NC D0 D0 D0 10P 47 CQ 11A 83 D5 D6 D13 D22 2G

12 NC NC NC D9 10N 48 – Internal 84 NC NC NC D31 1J

13 NC NC NC Q9 9P 49 A A A NC 9A 85 NC NC NC Q31 2J

14 NC NC Q1 Q1 10M 50 A 8B 86 NC NC Q14 Q23 3K

15 NC NC D1 D1 11N 51 A 7C 87 NC NC D14 D23 3J

16 NC NC NC D10 9M 52 NC 6C 88 NC NC NC D32 2K

17 NC NC NC Q10 9N 53 R# 8A 89 NC NC NC Q32 1K

18 Q0 Q1 Q2 Q2 11L 54 NC NC NC BW1# 7A 90 Q6 Q7 Q15 Q24 2L

19 D0 D1 D2 D2 11M 55 NW0# BW0# BW0# BW0# 7B 91 D6 D7 D15 D24 3L

20 NC NC NC D11 9L 56 K 6B 92 NC NC NC D33 1M

21 NC NC NC Q11 10L 57 K# 6A 93 NC NC NC Q33 1L

22 NC NC Q3 Q3 11K 58 NC NC NC BW3# 5B 94 NC NC Q16 Q25 3N

23 NC NC D3 D3 10K 59 NW1# NC BW1# BW2# 5A 95 NC NC D16 D25 3M

24 NC NC NC D12 9J 60 W# 4A 96 NC NC NC D34 1N

25 NC NC NC Q12 9K 61 A 5C 97 NC NC NC Q34 2M

26 Q1 Q2 Q4 Q4 10J 62 A 4B 98 Q7 Q8 Q17 Q26 3P

27 D1 D2 D4 D4 11J 63 A A NC NC 3A 99 D7 D8 D17 D26 2N

28 ZQ 11H 64 DLL# 1H 100 NC NC NC D35 2P

29 NC NC NC D13 10G 65 CQ# 1A 101 NC NC NC Q35 1P

30 NC NC NC Q13 9G 66 NC NC Q9 Q18 2B 102 A 3R

31 NC NC Q5 Q5 11F 67 NC NC D9 D18 3B 103 A 4R

32 NC NC D5 D5 11G 68 NC NC NC D27 1C 104 A 4P

33 NC NC NC D14 9F 69 NC NC NC Q27 1B 105 A 5P

34 NC NC NC Q14 10F 70 NC NC Q10 Q19 3D 106 A 5N

35 Q2 Q3 Q6 Q6 11E 71 NC NC D10 D19 3C 107 A 5R

36 D2 D3 D6 D6 10E 72 NC NC NC D28 1D

30 Data Sheet M19870EJ1V0DS

PD44165084A-A, 44165094A-A, 44165184A-A, 44165364A-A

JTAG Instructions

Instructions Description

EXTEST The EXTEST instruction allows circuitry external to the component package to be tested. Boundary-

scan register cells at output pins are used to apply test vectors, while those at input pins capture test

results. Typically, the first test vector to be applied using the EXTEST instruction will be shifted into the

boundary scan register using the PRELOAD instruction. Thus, during the update-IR state of EXTEST,

the output drive is turned on and the PRELOAD data is driven onto the output pins.

IDCODE The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in

capture-DR mode and places the ID register between the TDI and TDO pins in shift-DR mode. The

IDCODE instruction is the default instruction loaded in at power up and any time the controller is

placed in the test-logic-reset state.

BYPASS When the BYPASS instruction is loaded in the instruction register, the bypass register is placed

between TDI and TDO. This occurs when the TAP controller is moved to the shift-DR state. This

allows the board level scan path to be shortened to facilitate testing of other devices in the scan path.

SAMPLE / PRELOAD SAMPLE / PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE /

PRELOAD instruction is loaded in the instruction register, moving the TAP controller into the capture-

DR state loads the data in the RAMs input and Q pins into the boundary scan register. Because the

RAM clock(s) are independent from the TAP clock (TCK) it is possible for the TAP to attempt to

capture the I/O ring contents while the input buffers are in transition (i.e., in a metastable state).

Although allowing the TAP to sample metastable input will not harm the device, repeatable results

cannot be expected. RAM input signals must be stabilized for long enough to meet the TAPs input

data capture setup plus hold time (tCS plus tCH). The RAMs clock inputs need not be paused for any

other TAP operation except capturing the I/O ring contents into the boundary scan register. Moving

the controller to shift-DR state then places the boundary scan register between the TDI and TDO pins.

SAMPLE-Z If the SAMPLE-Z instruction is loaded in the instruction register, all RAM Q pins are forced to an

inactive drive state (high impedance) and the boundary register is connected between TDI and TDO

when the TAP controller is moved to the shift-DR state.

JTAG Instruction Coding

IR2 IR1 IR0 Instruction Note

0 0 0 EXTEST

0 0 1 IDCODE

0 1 0 SAMPLE-Z 1

0 1 1 RESERVED 2

1 0 0 SAMPLE / PRELOAD

1 0 1 RESERVED 2

1 1 0 RESERVED 2

1 1 1 BYPASS

Notes 1. TRISTATE all Q pins and CAPTURE the pad values into a SERIAL SCAN LATCH.

2. Do not use this instruction code because the vendor uses it to evaluate this product.

31 Data Sheet M19870EJ1V0DS

PD44165084A-A, 44165094A-A, 44165184A-A, 44165364A-A

Output Pin States of CQ, CQ# and Q

Instructions Control-Register Status Output Pin Status

CQ, CQ# Q

EXTEST 0 Update High-Z

1 Update Update

IDCODE 0 SRAM SRAM

1 SRAM SRAM

SAMPLE-Z 0 High-Z High-Z

1 High-Z High-Z

SAMPLE 0 SRAM SRAM

1 SRAM SRAM

BYPASS 0 SRAM SRAM

1 SRAM SRAM

Remark The output pin statuses during each instruction vary according

to the Control-Register status (value of Boundary Scan

There are three statuses:

Update : Contents of the “Update Register” are output to

the output pin (QDR Pad).

SRAM : Contents of the SRAM internal output “SRAM

Output” are output to the output pin (QDR Pad).

High-Z : The output pin (QDR Pad) becomes high

impedance by controlling of the “High-Z JTAG ctrl”.

The Control-Register status is set during Update-DR at the

EXTEST or SAMPLE instruction.

SRAM

CAPTURE

Boundary Scan

Update

QDR

Pad

SRAM

Output

Driver

High-Z

JTAG ctrl

High-Z

Update

SRAM

Output

32 Data Sheet M19870EJ1V0DS

PD44165084A-A, 44165094A-A, 44165184A-A, 44165364A-A

Boundary Scan Register Status of Output Pins CQ, CQ# and Q

Instructions SRAM Status Boundary Scan Register Status Note

CQ, CQ# Q

EXTEST READ (Low-Z) Pad Pad

NOP (High-Z) Pad Pad

IDCODE READ (Low-Z) – – No definition

NOP (High-Z) – –

SAMPLE-Z READ (Low-Z) Pad Pad

NOP (High-Z) Pad Pad

SAMPLE READ (Low-Z) Internal Internal

NOP (High-Z) Internal Pad

BYPASS READ (Low-Z) – – No definition

NOP (High-Z) – –

Remark The Boundary Scan Register statuses during execution each

instruction vary according to the instruction code and SRAM

operation mode.

There are two statuses:

Pad : Contents of the output pin (QDR Pad) are captured

in the “CAPTURE Register” in the Boundary Scan

Internal : Contents of the SRAM internal output “SRAM

Output” are captured in the “CAPTURE Register”

in the Boundary Scan Register.

Pad

Internal

SRAM

Output

Driver

Update

QDR

Pad

High-Z

JTAG ctrl

CAPTURE

SRAM

Output

Boundary Scan

33 Data Sheet M19870EJ1V0DS

PD44165084A-A, 44165094A-A, 44165184A-A, 44165364A-A

TAP Controller State Diagram

Test-Logic-Reset

Run-Test / Idle Select-DR-Scan

Capture-DR Capture-IR

Shift-DR

Exit1-DR

Pause-DR

Exit2-DR

Update-DR Update-IR

Exit2-IR

Pause-IR

Exit1-IR

Shift-IR

Select-IR-Scan

10 10

11 1

Disabling the Test Access Port

It is possible to use this device without utilizing the TAP. To disable the TAP Controller without interfering with normal

operation of the device, TCK must be tied to VSS to preclude mid level inputs. TDI and TMS may be left open but fix

them to VDD via a resistor of about 1 kΩ when the TAP controller is not used. TDO should be left unconnected also

when the TAP controller is not used.

34 Data Sheet M19870EJ1V0DS

PD44165084A-A, 44165094A-A, 44165184A-A, 44165364A-A

Test Logic Operation (Instruction Scan)

TCK

Controller

state

TDI

TMS

TDO

Test-Logic-Reset

Run-Test/Idle

Select-DR-Scan

Select-IR-Scan

Capture-IR

Shift-IR

Exit1-IR

Pause-IR

Exit2-IR

Shift-IR

Exit1-IR

Update-IR

Run-Test/Idle

IDCODE

Instruction

Output Inactive

35 Data Sheet M19870EJ1V0DS

PD44165084A-A, 44165094A-A, 44165184A-A, 44165364A-A

Test Logic (Data Scan)

Controller

state

TDI

TMS

TDO

Run-Test/Idle

Select-DR-Scan

Capture-DR

Shift-DR

Exit1-DR

Pause-DR

Exit2-DR

Shift-DR

Exit1-DR

Update-DR

Test-Logic-Reset

Instruction

Run-Test/Idle

Select-DR-Scan

Select-IR-Scan

Output Inactive

TCK

36 Data Sheet M19870EJ1V0DS

PD44165084A-A, 44165094A-A, 44165184A-A, 44165364A-A

Package Drawing

165-PIN PLASTIC BGA (13x15)

ITEM DIMENSIONS

13.00±0.10

15.00±0.10

0.15

0.40±0.05

1.00

1.40±0.11

1.00

0.50±0.05

(UNIT:mm)

0.08

0.10

0.20

1.50

0.50

P165F5-100-EQ2

INDEX MARK

ZD B

SwB

SwA

y1 S

SxbA

φφ

RPNMLKJHGFEDCBA

37 Data Sheet M19870EJ1V0DS

PD44165084A-A, 44165094A-A, 44165184A-A, 44165364A-A

Recommended Soldering Condition

Please consult with our sales offices for soldering conditions of these products.

Types of Surface Mount Devices

PD44165084AF5-EQ2-A : 165-pin PLASTIC BGA (13 x 15)

PD44165094AF5-EQ2-A : 165-pin PLASTIC BGA (13 x 15)

PD44165184AF5-EQ2-A : 165-pin PLASTIC BGA (13 x 15)

PD44165364AF5-EQ2-A : 165-pin PLASTIC BGA (13 x 15)

Quality Grade

• A quality grade of the products is “Standard”.

• Anti-radioactive design is not implemented in the products.

• Semiconductor devices have the possibility of unexpected defects by affection of cosmic ray that reach to the

ground and so forth.

38 Data Sheet M19870EJ1V0DS

PD44165084A-A, 44165094A-A, 44165184A-A, 44165364A-A

[ MEMO ]

39 Data Sheet M19870EJ1V0DS

PD44165084A-A, 44165094A-A, 44165184A-A, 44165364A-A

VOLTAGE APPLICATION WAVEFORM AT INPUT PIN

Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the

CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may

malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,

and also in the transition period when the input level passes through the area between VIL (MAX) and

VIH (MIN).

HANDLING OF UNUSED INPUT PINS

Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is

possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS

devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed

high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND

via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must

be judged separately for each device and according to related specifications governing the device.

PRECAUTION AGAINST ESD

A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and

ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as

much as possible, and quickly dissipate it when it has occurred. Environmental control must be

adequate. When it is dr y, a humidifier should be used. It is recommended to avoid using insulators that

easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static

container, static shielding bag or conductive material. All test and measurement tools including work

benches and floors should be grounded. The operator should be grounded using a wrist strap.

Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for

PW boards with mounted semiconductor devices.

STATUS BEFORE INITIALIZATION

Power-on does not necessarily define the initial status of a MOS device. Immediately after the power

source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does

not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the

reset signal is received. A reset operation must be executed immediately after power-on for devices

with reset functions.

POWER ON/OFF SEQUENCE

In the case of a device that uses different power supplies for the internal operation and external

interface, as a rule, switch on the external power supply after switching on the internal power supply.

When switching the power supply off, as a rule, switch off the external power supply and then the

internal power supply. Use of the reverse power on/off sequences may result in the application of an

overvoltage to the internal elements of the device, causing malfunction and degradation of internal

elements due to the passage of an abnormal current.

The correct power on/off sequence must be judged separately for each device and according to related

specifications governing the device.

INPUT OF SIGNAL DURING POWER OFF STATE

Do not input signals or an I/O pull-up power supply while the device is not powered. The current

injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and

the abnormal current that passes in the device at this time may cause degradation of internal elements.

Input of signals during the power off state must be judged separately for each device and according to

related specifications governing the device.

NOTES FOR CMOS DEVICES

PD44165084A-A, 44165094A-A, 44165184A-A, 44165364A-A

QDR RAMs and Quad Data Rate RAMs comprise a new series of products developed by Cypress Semiconductor,

Renesas, IDT, NEC Electronics, and Samsung.

The information in this document is current as of July, 2009. The information is subject to change

without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets,

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No part of this document may be copied or reproduced in any form or by any means without the prior

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(Note)

•

M8E0904E

(1)

(2)

"NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its

majority-owned subsidiaries.

"NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as

defined above).

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"Standard":

"Special":

"Specific":