PDU13F 3-BIT PROGRAMMABLE DELAY LINE (SERIES PDU13F) data Ly delay \G evicesy inc. FEATURES PACKAGES * Digitally programmable in 8 delay steps nn O14400 vee in C Monotonic delayversusaddress variation * Two separate outputs: inverting & non-inverting Nic Y2 13H) NC NIC Precise and stable delays NC O3 ia No NCO e = Input & outputs fully TTL interfaced & buffered OUT 4 i100 NCO NCO 10TL fan-out capability OUT) (5 10] Ao OUT O Fits standard 14-pin DIP socket EN/ [6 gm] At ouT/ O Auto-nsertable GND o 7 8d A? EN/ o PDU13F-xx DIP GND PDU13F-xxA2 Gull-Wing PDU13F-xxB2 J-Lead PDU13F-xxM Military DIP voc NYG NYG NAG NG AO Al A2 PDU13F-xxMC3 Military Gull-Wing FUNCTIONAL DESCRIPTION The PDU13F-series device is a 3bit cigitally programmable delay line. The delay, TD, from the input pin (IN) te the output pins (OUT, OUT/) depends on the address code (A2A0) according to the following formula: TDs = TDo + Tinc * A where A is the address code, Tic is the incremental delay of the device, and TDp is the inherent delay of the device. The incremental delay is specitied by the dash number of the device and can range from 0.5ns through 50ns, inclusively. The enable pin (EN/) is held LOW during normal cperation. When this signal is brought HIGH, OUT and OUT/ are forced into LOW and HIGH slates, respectively. The address is not latched and must remain asserted during normal operation. PIN DESCRIPTIONS IN Delay Line Input OUT OUT/ A2 Al AO EN/ oc GND Non-inverted Output Inverted Output Acdress Bit 2 Acdress Bit 1 Address Bit 0 Qutput Enable +5 Volts Ground SERIES SPECIFICATIONS Total programmed delay tolerance: 5% or ins, whichever is greater Inherent delay (TDz): 6ns typical (OUT) 5.5ns typical (OUT/) * Setup time and propagation delay: Address to input setup (Tas): 6ns Disable to output delay (Tpiso): Gns typ. (OUT) Operating temperature: 0 to 70 C Temperature coefficient: 100PPM/C (excludes TD) Supply voltage Veco: 5VDC + 5% Supply current: Iecy = 45ma loa. = 20ma * Minimum pulse width: 20% of total delay DASH NUMBER SPECIFICATIONS Part Incremental Delay | Total Delay Number Per Step (ns) Change (ns) PDUI3F-.5 5+.3 3.5210 PDU13F-1 1+.4 721.0 PDU13F-2 a+.4 1421.0 PDU13F-3 32.5 2i+i1.1 PDU13F-5 5+.6 35+ 1.8 PDUi3F-10 10+1.0 70+ 3.5 PDU13F-15 15+1.3 105+ 5.3 PDU13F-20 20+1.5 140+ 7.0 PDU13F-40 4042.0 280 + 14.0 PDU13F-50 50+2.5 350+ 17.5 NOTE: Any dash number between .5 and 50 not shown is also available. 1997 Data Delay Devices Doc #97001 1/10/97 DATA DELAY DEVICES, INC. 3 Mt. Prospect Ave. Clifton, NJ 07013PDU13F APPLICATION NOTES ADDRESS UPDATE The PDU13F is a memory device. As such, special precautions must be taken when changing the delay address in order to prevent spurious output signals. The timing restrictions are shown in Figure 1. After the last signal edge to be delayed has appeared on the OUT pin, a minimum time, Toax, Is required before the address lines can change. This time is given by the following relation: Toax = max { (Ai - A) * Tinc , 0} where Aj,_, and A; are the old and new address codes, respectively. Violation of this constraint may, depending on the history of the input signal, cause spurious signals to appear on the OUT pin. The possibility of spurious signals persists until the required Toa, has elapsed. A similar situation occurs when using the EN/ signal to disable the output while IN is active. In this case, the unit must be held in the disabled state until the device is able to clear itself. This is achieved by holding the EN/ signal high and the IN signal low for a time given by: Tpisu = A * Tine Violation of this constraint may, depending on the history of the input signal, cause spurious signals to appear on the OUT pin. The possibility of spurious signals persists until the required Tpisy has elapsed. INPUT RESTRICTIONS There are three types of restrictions on input pulse width and period listed in the AC Characteristics table. The recommended conditions are those for which the delay tolerance specifications and monotonicity are guaranteed. The suggested conditions are those for which signals will propagate through the unit without significant distortion. The absolute conditions are those for which the unit will produce some type of output for a given input. When operating the unit between the recommended and absolute conditions, the delays may deviate from their values at low frequency. However, these deviations will remain constant from pulse to pulse if the input pulse width and period remain fixed. In other words, the delay of the unit exhibits frequency and pulse width dependence when operated beyond the recommended conditions. Please consult the technical staff at Data Delay Devices if your application has specific high-frequency requirements. Please note that the increment tolerances listed represent a design goal. Although most delay increments will fall within tolerance, they are not guaranteed throughout the address range of the unit. Monotonicity is, however, guaranteed over all addresses. Tals TpisH Tp ISO Figure 1: Timing Diagram Doc #97001 DATA DELAY DEVICES, INC. 2 1/10/97 Tel: 201-773-2299 Fax: 201-773892 hittp:/Wwww.datadelay.comPDU13F DEVICE SPECIFICATIONS TABLE 1: AC CHARACTERISTICS PARAMETER SYMBOL MIN TYP UNITS Total Programmable Delay TDy 7 Tine Inherent Delay TDo 6.0 ns Output Skew Tskew 1.5 ns Disable to Output Low Delay Tpiso 6.0 ns Address to Enable Setup Time TaENS 2.0 ns Address to Input Setup Time Tals 6.0 ns Enable to Input Setup Time Tenis 6.0 ns Output to Address Change Toax See Text Disable Hold Time Toisu See Text Absolute PERw 20 % of TDy Input Period Suggested PER 50 % of TDy Recommended PER 200 % of TDy Absolute PWin 10 % of TDy Input Pulse Width Suggested PWin 25 % of TDy Recommended PWin 100 % of TDy TABLE 2: ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL MIN MAX UNITS | NOTES DC Supply Voltage Voc -0.3 7.0 Vv Input Pin Voltage Vin -0.3 Vpp+0.3 V Storage Temperature Tstre 55 150 Cc Lead Temperature TLEAD 300 Cc 10 sec TABLE 3: DC ELECTRICAL CHARACTERISTICS (OC to 70C, 4.75V to 5.25V) PARAMETER SYMBOL MIN TYP MAX | UNITS NOTES High Level Output Voltage Vou 2.5 3.4 V Vee = MIN, low = MAX Vin = MIN, Vip = MAX Low Level Output Voltage Vo 0.35 0.5 V Veco = MIN, lop = MAX Vin = MIN, Vip = MAX High Level Output Current lou -1.0 mA Low Level Output Current lot 20.0 mA High Level Input Voltage Vid 2.0 Vv Low Level Input Voltage Vit 0.8 V Input Clamp Voltage Vik -1.2 V Voc = MIN, l= Ix Input Current at Maximum NaH 0.1 mA Veco = MAX, V| = 7.0V Input Voltage High Level Input Current hia 20 LA Veco = MAX, V, = 2.7V Low Level Inout Current lie -0.6 mA Vcc = MAX, Vi = 0.5V Shortcircuit Output Current log -60 -150 mA Veco = MAX Output High Fanout 25 Unit Qutput Low Fan-out 12.5 Load Doc #97001 1/10/97 DATA DELAY DEVICES, INC. 3 Mt. Prospect Ave. Clifton, NJ 07013PDU13F PACKAGE DIMENSIONS +H 020 TYP + 040 010 TYP-# AAA AAR A R Ve. fe | 4 1312 11 109=~8 * 1413 12 11 10 8 8 270 430 oom. TYP. TP. Lead Material: @i 23 5 6 7 + : NickelIron alloy 42 Nete-on WAAAY Ste 100 300 ne 600 MAX. ne #790 MAX. -280 Max Commercial Gull-Wing (PDU13F-xxA2) Ke o20 TYP. +H +040 050 TYP 8 f fh ft fi fy TYP. HTS T2108 8 on 320 .010+.002 . .. TYP. iP Oi Me Ng Tu gt + 600+.010 250, wae a u 6 Equal spaces : 110 - -350 110 each 100010 600 MAX. "| TYP. NonAccu mulative 799 MAX. Commercial DIP (PDU13F-xx) Commercial J-Lead (PDU13F-xxB2) eis ee) 7 A10 TYP. [ HM 920 TYP. + ono o10+002 i AAAAAA AAR TWP ~~ J 16 16 14 13 12 11 10 9 <8 MAX. a 882 710.590 +005 @ie2e3s45 67 eles en eres eooRS - - a +005 MAX. 007 Oo MAX. 005 + * 2 3 5 6 7 8 > r F130 Wy wy Yu y % #030 020 TYP. ooo 100 280 4 il 018 TYP. -100 a ro MAX 050 TYP. 300 -700 . 010 .600 TYP Ve * 880.020 Military DIP (PDU13F-xxM) Military Gull-Wing (PDU13F-xxMC3) DATA DELAY DEVICES, INC. Doc #97001 Tel: 201-773-2299 Fax: 201-773892 hittp:/Wwww.datadelay.com 1/10/97PDU13F DELAY LINE AUTOMATED TESTING TEST CONDITIONS INPUT: OUTPUT: Ambient Temperature: 25C + 3C Load: 1 FAST-TTL Gate Supply Voltage (Vcc): 5.0V1+0.1V Cicada! 5pf + 10% Input Pulse: High = 3.0V +0.1V Threshold: 1.5V (Rising & Falling) Low = 0.0V+0.1V Source Impedance: 500 Max. Rise/Fall Time: 3.0 ns Max. (measured between 0.6V and 2.4V } Pulse Width: PWin = 1.5 x Total Delay Period: PERw = 4.5 x Total Delay NOTE: The above conditions are for test only and do not in any way restrict the operation of the device. COMPUTER 2 PRINTER SYSTEM PULSE OUT IN DEVICE UNDER TIME INTERVAL GENERATOR TRIG TEST (DUT) COUNTER Test Setup A - PER PWin Trise INPUT 2ay Vin aay SIGNAL 06v 0.6V K TDar K TDar OUTPUT Vor SIGNAL 1.5 1.5V Vo Timing Diagram For Testing Dac #97001 DATA DELAY DEVICES, INC. 5 1/10/97 3 Mt. Prospect Ave. Clifton, NJ 07013