www.irf.com 1
07/10/09
IRF7413ZGPbF
HEXFET® Power MOSFET
Notes through are on page 10
Applications
lControl FET for Notebook Processor
Power
lControl and Synchronous Rectifier
MOSFET for Graphics Cards and POL
Converters in Computing, Networking
and Telecommunication Systems
Top View
8
1
2
3
45
6
7
D
D
D
DG
S
A
S
S
A
SO-8
Absolute Maximum Ratin
g
s
Parameter Units
VDS Drain-to-Source Voltage V
VGS Gate-to-Source Voltage
ID @ TA = 25°C Continuous Drain Current, VGS @ 10V
ID @ TA = 70°C Continuous Drain Current, VGS @ 10V A
IDM Pulsed Drain Current
c
PD @TA = 25°C Power Dissipation W
PD @TA = 70°C Power Dissipation
Linear Derating Factor W/°C
TJ Operating Junction and °C
TSTG Storage Temperature Range
Thermal Resistance
Parameter Typ. Max. Units
RθJL Junction-to-Drain Lead ––– 20 °C/W
RθJA Junction-to-Ambient
f
––– 50
-55 to + 150
2.5
0.02
1.6
Max.
13
10
100
± 20
30
VDSS RDS(on) max ID
30V 10m
:
@VGS = 10V 13A
Benefits
lUltra-Low Gate Impedance
lVery Low RDS(on)
lFully Characterized Avalanche Voltage and
Current
l100% Tested for RG
lLead-Free
lHalogen-Free
PD - 96249
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Static @ TJ = 25°C (unless otherwise specified)
Parameter Min. T
y
p. Max. Units
BVDSS Drain-to-Source Breakdown Voltage 30 ––– ––– V
∆ΒVDSS
/
∆TJ Breakdown Voltage Temp. Coefficient ––– 0.025 ––– V/°C
RDS(on) Static Drain-to-Source On-Resistance ––– 8.0 10 mΩ
––– 10.5 13
VGS(th) Gate Threshold Voltage 1.35 1.80 2.25 V
∆VGS(th)
/
∆TJGate Threshold Voltage Coefficient ––– -5.0 ––– mV/°C
IDSS Drain-to-Source Leakage Current ––– ––– 1.0 µA
––– ––– 150
IGSS Gate-to-Source Forward Leakage ––– ––– 100 nA
Gate-to-Source Reverse Leakage ––– ––– -100
gfs Forward Transconductance 62 ––– ––– S
QgTotal Gate Charge ––– 9.5 14
Qgs1 Pre-Vth Gate-to-Source Charge ––– 3.0 –––
Qgs2 Post-Vth Gate-to-Source Charge ––– 1.0 ––– nC
Qgd Gate-to-Drain Charge ––– 3.0 –––
Qgodr Gate Charge Overdrive ––– 2.5 ––– See Fig. 16
Qsw Switch Char
g
e (Qgs2 + Qgd)––– 4.0 –––
Qoss Output Charge ––– 5.6 ––– nC
RGGate Resistance ––– 2.3 4.5 Ω
td(on) Turn-On Delay Time ––– 8.7 –––
trRise Time ––– 6.3 –––
td(off) Turn-Off Delay Time ––– 11 ––– ns
tfFall Time ––– 3.8 –––
Ciss Input Capacitance ––– 1210 –––
Coss Output Capacitance ––– 270 ––– pF
Crss Reverse Transfer Capacitance ––– 140 –––
Avalanche Characteristics
Parameter Units
EAS
Si
n
gl
e
P
u
l
se
A
va
l
anc
h
e
E
ner
gy
d
mJ
IAR
A
va
l
anc
h
e
C
urrent
c
A
Diode Characteristics
Parameter Min. T
y
p. Max. Units
ISContinuous Source Current ––– ––– 3.1
(Body Diode) A
ISM Pulsed Source Current ––– ––– 100
(
Bod
y
Diode
)
c
VSD Diode Forward Voltage ––– ––– 1.0 V
trr Reverse Recovery Time ––– 24 36 ns
Qrr Reverse Recovery Charge ––– 16 24 nC
ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Conditions
Max.
32
10
ƒ = 1.0MHz
Conditions
VGS = 0V, ID = 250µA
Reference to 25°C, ID = 1mA
VGS = 10V, ID = 13A
e
MOSFET symbol
VDS = 15V, VGS = 0V
VDD = 16V, VGS = 4.5V
ID = 10A
VDS = 15V
VGS = 20V
VGS = -20V
VDS = 24V, VGS = 0V
TJ = 25°C, IF = 10A, VDD = 15V
di/dt = 100A/
µ
s
e
TJ = 25°C, IS = 10A, VGS = 0V
e
showing the
integral reverse
p-n junction diode.
VGS = 4.5V, ID = 10A
e
VGS = 4.5V
Typ.
–––
VDS = VGS, ID = 25µA
Clamped Inductive Load
VDS = 15V, ID = 10A
VDS = 24V, VGS = 0V, TJ = 125°C
–––
ID = 10A
VGS = 0V
VDS = 15V
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Fig 4. Normalized On-Resistance
vs. Temperature
Fig 2. Typical Output Characteristics
Fig 1. Typical Output Characteristics
Fig 3. Typical Transfer Characteristics
0.1 110
VDS, Drain-to-Source Voltage (V)
1
10
100
1000
ID, Drain-to-Source Current (A)
2.5V
20µs PULSE WIDTH
Tj = 150°C
VGS
TOP 10V
8.0V
4.5V
4.0V
3.5V
3.0V
2.8V
BOTTOM 2.5V
0.1 110
VDS, Drain-to-Source Voltage (V)
0.1
1
10
100
1000
ID, Drain-to-Source Current (A)
2.5V
20µs PULSE WIDTH
Tj = 25°C
VGS
TOP 10V
8.0V
4.5V
4.0V
3.5V
3.0V
2.8V
BOTTOM 2.5V
2 3 4 5 6
VGS, Gate-to-Source Voltage (V)
1
10
100
1000
ID, Drain-to-Source Current (Α)
TJ = 25°C
TJ = 150°C
VDS = 10V
20µs PULSE WIDTH
-60 -40 -20 020 40 60 80 100 120 140 160
TJ , Junction Temperature (°C)
0.5
1.0
1.5
2.0
RDS(on) , Drain-to-Source On Resistance
(Normalized)
ID = 13A
VGS = 10V
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Fig 8. Maximum Safe Operating Area
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance vs.
Drain-to-Source Voltage
Fig 7. Typical Source-Drain Diode
Forward Voltage
110 100
VDS, Drain-to-Source Voltage (V)
100
1000
10000
C, Capacitance(pF)
VGS = 0V, f = 1 MHZ
Ciss = C gs + Cgd, C ds SHORTED
Crss = Cgd
Coss = Cds + Cgd
Coss
Crss
Ciss
0.2 0.4 0.6 0.8 1.0 1.2 1.4
VSD, Source-to-Drain Voltage (V)
0.10
1.00
10.00
100.00
1000.00
ISD, Reverse Drain Current (A)
TJ = 25°C
TJ = 150°C
VGS = 0V
0 1 10 100 1000
VDS, Drain-to-Source Voltage (V)
0.1
1
10
100
1000
ID, Drain-to-Source Current (A)
1msec
10msec
OPERATION IN THIS AREA
LIMITED BY R DS(on)
100µsec
TA = 25°C
Tj = 150°C
Single Pulse
0481216
QG Total Gate Charge (nC)
0.0
2.0
4.0
6.0
8.0
10.0
12.0
VGS, Gate-to-Source Voltage (V)
VDS= 24V
VDS= 15V
ID= 10A
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Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient
Fig 9. Maximum Drain Current vs.
Ambient Temperature
Fig 10. Threshold Voltage vs. Temperature
-75 -50 -25 025 50 75 100 125 150
TJ , Temperature ( °C )
0.5
1.0
1.5
2.0
2.5
VGS(th) Gate threshold Voltage (V)
ID = 250µA
1E-006 1E-005 0.0001 0.001 0.01 0.1 110 100
t1 , Rectangular Pulse Duration (sec)
0.001
0.01
0.1
1
10
100
Thermal Response ( Z thJA )
0.20
0.10
D = 0.50
0.02
0.01
0.05
SINGLE PULSE
( THERMAL RESPONSE )
Notes:
1. Duty factor D = t / t
2
. Peak
T
= P x Z + T
1 2
JDM thJA A
P
t
t
DM
1
2
τJ
τJ
τ1
τ1τ2
τ2τ3
τ3
R1
R1R2
R2R3
R3
Ci i/Ri
Ci= τi/Ri
τ
τC
τ4
τ4
R4
R4Ri (°C/W) τi (sec)
1.8556 0.000337
2.4927 0.012752
25.570 0.691000
20.340 21.90000
25 50 75 100 125 150
TA , Ambient Temperature (°C)
0
2
4
6
8
10
12
14
ID, Drain Current (A)
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D.U.T. VDS
ID
IG
3mA
VGS
.3µF
50KΩ
.2µF
12V
Current Regulator
Same Type as D.U.T.
Current Sampling Resistors
+
-
Fig 13. Gate Charge Test Circuit
Fig 12b. Unclamped Inductive Waveforms
Fig 12a. Unclamped Inductive Test Circuit
tp
V
(BR)DSS
I
AS
Fig 12c. Maximum Avalanche Energy
vs. Drain Current
R
G
I
AS
0.01
Ω
t
p
D.U.T
L
VDS
+
-V
DD
DRIVER
A
15V
20V
VGS
25 50 75 100 125 150
Starting TJ , Junction Temperature (°C)
0
20
40
60
80
100
120
140
EAS , Single Pulse Avalanche Energy (mJ)
ID
TOP 3.1A
3.9A
BOTTOM 10A
Fig 14a. Switching Time Test Circuit
Fig 14b. Switching Time Waveforms
VGS
VDS
90%
10%
td(on) td(off)
trtf
VGS
Pulse Width < 1µs
Duty Factor < 0.1%
VDD
VDS
LD
D.U.T
+
-
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Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
P.W. Period
di/dt
Diode Recovery
dv/dt
Ripple ≤5%
Body Diode Forward Drop
Re-Applied
Voltage
Reverse
Recovery
Current
Body Diode Forward
Current
V
GS
=10V
V
DD
I
SD
Driver Gate Drive
D.U.T. I
SD
Waveform
D.U.T. V
DS
Waveform
Inductor Curent
D = P. W .
Period
* VGS = 5V for Logic Level Devices
*
+
-
+
+
+
-
-
-
RGVDD
• dv/dt controlled by RG
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
D.U.T
Fig 16. Gate Charge Waveform
Vds
Vgs
Id
Vgs(th)
Qgs1 Qgs2 Qgd Qgodr
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Control FET
Special attention has been given to the power losses
in the switching elements of the circuit - Q1 and Q2.
Power losses in the high side switch Q1, also called
the Control FET, are impacted by the Rds(on) of the
MOSFET, but these conduction losses are only about
one half of the total losses.
Power losses in the control switch Q1 are given
by;
Ploss = Pconduction+ Pswitching+ Pdrive+ Poutput
This can be expanded and approximated by;
P
loss =Irms
2×Rds(on )
()
+I×Qgd
ig
×Vin ×f
⎛
⎝
⎜ ⎞
⎠
⎟ +I×Qgs 2
ig
×V
in ×f
⎛
⎝
⎜ ⎞
⎠
⎟
+Qg×Vg×f
()
+Qoss
2×Vin ×f
⎛
⎝ ⎞
⎠
This simplified loss equation includes the terms Qgs2
and Qoss which are new to Power MOSFET data sheets.
Qgs2 is a sub element of traditional gate-source
charge that is included in all MOSFET data sheets.
The importance of splitting this gate-source charge
into two sub elements, Qgs1 and Qgs2, can be seen from
Fig 16.
Qgs2 indicates the charge that must be supplied by
the gate driver between the time that the threshold
voltage has been reached and the time the drain cur-
rent rises to Idmax at which time the drain voltage be-
gins to change. Minimizing Qgs2 is a critical factor in
reducing switching losses in Q1.
Qoss is the charge that must be supplied to the out-
put capacitance of the MOSFET during every switch-
ing cycle. Figure A shows how Qoss is formed by the
parallel combination of the voltage dependant (non-
linear) capacitances Cds and Cdg when multiplied by
the power supply input buss voltage.
Synchronous FET
The power loss equation for Q2 is approximated
by;
P
loss =P
conduction +P
drive +P
output
*
P
loss =Irms
2×Rds(on)()
+Qg×Vg×f
()
+Qoss
2×Vin ×f
⎛
⎝
⎜ ⎞
⎠ +Qrr ×Vin ×f
(
)
*dissipated primarily in Q1.
For the synchronous MOSFET Q2, Rds(on) is an im-
portant characteristic; however, once again the im-
portance of gate charge must not be overlooked since
it impacts three critical areas. Under light load the
MOSFET must still be turned on and off by the con-
trol IC so the gate drive losses become much more
significant. Secondly, the output charge Qoss and re-
verse recovery charge Qrr both generate losses that
are transfered to Q1 and increase the dissipation in
that device. Thirdly, gate charge will impact the
MOSFETs’ susceptibility to Cdv/dt turn on.
The drain of Q2 is connected to the switching node
of the converter and therefore sees transitions be-
tween ground and Vin. As Q1 turns on and off there is
a rate of change of drain voltage dV/dt which is ca-
pacitively coupled to the gate of Q2 and can induce
a voltage spike on the gate that is sufficient to turn
the MOSFET on, resulting in shoot-through current .
The ratio of Qgd/Qgs1 must be minimized to reduce the
potential for Cdv/dt turn on.
Power MOSFET Selection for Non-Isolated DC/DC Converters
Figure A: Qoss Characteristic
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SO-8 Package Outline(Mosfet & Fetky)
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Dimensions are shown in milimeters (inches)
SO-8 Part Marking Information
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
(;$03/(7+,6,6$1,5)*3%)
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IRF7413ZGPbF
10 www.irf.com
Notes:
Repetitive rating; pulse width limited by max. junction temperature.
Starting TJ = 25°C, L = 0.62mH, RG = 25Ω, IAS = 10A.
Pulse width ≤ 400µs; duty cycle ≤ 2%.
When mounted on 1 inch square copper board.
Data and specifications subject to change without notice.
This product has been designed and qualified for the Consumer market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 07/2009
330.00
(12.992)
MAX.
14.40 ( .566 )
12.40 ( .488 )
NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. OUTLINE CONFORMS TO EIA-481 & EIA-541.
FEED DIRECTION
TERMINAL NUMBER 1
12.3 ( .484 )
11.7 ( .461 )
8.1 ( .318 )
7.9 ( .312 )
NOTES:
1. CONTROLLING DIMENSION : MILLIMETER.
2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS(INCHES).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
SO-8 Tape and Reel
Dimensions are shown in millimeters (inches)
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
