Publication#
16564
Rev:
E
Amendment/
0
Issue Date:
November 1998
COM'L: -25 IND: -15/25
PALCE22V10 and PALCE22V10Z
Families
24-Pin EE CMOS (Zer o Po wer) Versatile PAL De vice
DISTINCTIVE CHARACTERISTICS
◆
As fast as 5-ns propagation delay and 142.8 MHz f
MAX
(external)
◆
Low-power EE CMOS
◆
10 macrocells programmable as registered or combinatorial, and active high or active low to
match application needs
◆
Varied product term distribution allows up to 16 product terms per output for complex
functions
◆
Peripheral Component Interconnect (PCI) compliant (-5/-7/-10)
◆
Global asynchronous reset and synchronous preset for initialization
◆
Power-up reset for initialization and register preload for testability
◆
Extensive third-party software and programmer support
◆
24-pin SKINNY DIP, 24-pin SOIC, and 28-pin PLCC
◆
5-ns and 7.5-ns versions utilize split leadframes for improved performance
GENERAL DESCRIPTION
The PALCE22V10 provides user-programmable logic for replacing conventional SSI/MSI gates and
flip-flops at a reduced chip count.
The PALCE22V10Z is an advanced PAL
®
device built with zero-power, high-speed, electrically-
erasable CMOS technology. It provides user-programmable logic for replacing conventional zero-
power CMOS SSI/MSI gates and flip-flops at a reduced chip count.
The PALCE22V10Z provides zero standby power and high speed. At 30 µA maximum standby
current, the PALCE22V10Z allows battery-powered operation for an extended period.
The PAL device implements the familiar Boolean logic transfer function, the sum of products. The
PAL device is a programmable AND array driving a fixed OR array. The AND array is programmed
to create custom product terms, while the OR array sums selected terms at the outputs.
The product terms are connected to the fixed OR array with a varied distribution from 8 to16 across
the outputs (see Block Diagram). The OR sum of the products feeds the output macrocell. Each
macrocell can be programmed as registered or combinatorial, and active-high or active low. The
output configuration is determined by two bits controlling two multiplexers in each macrocell.
COM'L: H-5/7/10/15/25,Q-10/15/25 IND: H-10/15/20/25
PALCE22V10Z
PALCE22V10
2 PALCE22V10 and PALCE22V10Z Families
BLOCK DIAGRAM
FUNCTIONAL DESCRIPTION
The PALCE22V10 allows the systems engineer to implement the design on-chip, by programming
EE cells to configure AND and OR gates within the device, according to the desired logic function.
Complex interconnections between gates, which previously required time-consuming layout, are
lifted from the PC board and placed on silicon, where they can be easily modified during
prototyping or production.
The P ALCE22V10Z is the zero-power version of the P ALCE22V10. It has all the architectural features
of the PALCE22V10. In addition, the PALCE22V10Z has zero standby power and unused product
term disable.
Product terms with all connections opened assume the logical HIGH state; product terms
connected to both true and complement of any single input assume the logical LOW state.
The P ALCE22V10 has 12 inputs and 10 I/O macrocells. The macrocell (Figure 1) allows one of four
potential output configurations registered output or combinatorial I/O, active high or active low
(see Figure 1). The configuration choice is made according to the user’s design specification and
corresponding programming of the configuration bits S
0
- S
1
. Multiplexer controls are connected
to ground (0) through a programmable bit, selecting the “0” path through the multiplexer . Erasing
the bit disconnects the control line from GND and it is driven to a high level, selecting the “1” path.
The device is produced with an EE cell link at each input to the AND gate array, and connections
may be selectively removed by applying appropriate voltages to the circuit. Utilizing an easily-
implemented programming algorithm, these products can be rapidly programmed to any
customized pattern.
OUTPUT
LOGIC
MACRO
CELL
OUTPUT
LOGIC
MACRO
CELL
OUTPUT
LOGIC
MACRO
CELL
OUTPUT
LOGIC
MACRO
CELL
OUTPUT
LOGIC
MACRO
CELL
OUTPUT
LOGIC
MACRO
CELL
OUTPUT
LOGIC
MACRO
CELL
OUTPUT
LOGIC
MACRO
CELL
OUTPUT
LOGIC
MACRO
CELL
OUTPUT
LOGIC
MACRO
CELL
RESET
PRESET
CLK/I0
1
I1 - I11
11
810121416161412108
I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 I/O9
PROGRAMMABLE
AND ARRAY
(44 x 132)
PALCE22V10 and PALCE22V10Z Families 3
Variable Input/Output Pin Ratio
The PALCE22V10 has twelve dedicated input lines, and each macrocell output can be an I/O pin.
Buffers for device inputs have complementary outputs to provide user-programmable input signal
polarity. Unused input pins should be tied to V
CC
or GND.
Registered Output Configuration
Each macrocell of the PALCE22V10 includes a D-type flip-flop for data storage and
synchronization. The flip-flop is loaded on the LOW-to-HIGH transition of the clock input. In the
registered configuration (S
1
= 0), the array feedback is from Q of the flip-flop.
Combinatorial I/O Configuration
Any macrocell can be configured as combinatorial by selecting the multiplexer path that bypasses
the flip-flop (S
1
= 1). In the combinatorial configuration, the feedback is from the pin.
0 = Programmed EE bit
1 = Erased (charged) EE bit
Figure 1. Output Logic Macrocell Diagram
16564E-004
CLK
S1
10
11
00
01
AR
SP
0
1
I/On
S0
D Q
QS1S0Output Configuration
0 0 Registered/Active Low
0 1 Registered/Active High
1 0 Combinatorial/Active Low
1 1 Combinatorial/Active High
4 PALCE22V10 and PALCE22V10Z Families
Programmable Three-State Outputs
Each output has a three-state output buffer with three-state control. A product term controls the
buffer, allowing enable and disable to be a function of any product of device inputs or output
feedback. The combinatorial output provides a bi-directional I/O pin, and may be configured as
a dedicated input if the buffer is always disabled.
Programmable Output Polarity
The polarity of each macrocell output can be active high or active low, either to match output
signal needs or to reduce product terms. Programmable polarity allows Boolean expressions to be
written in their most compact form (true or inverted), and the output can still be of the desired
polarity. It can also save “DeMorganizing” efforts.
Selection is controlled by programmable bit S
0
in the output macrocell, and affects both registered
and combinatorial outputs. Selection is automatic, based on the design specification and pin
definitions. If the pin definition and output equation have the same polarity, the output is
programmed to be active high (S
0
= 1).
Preset/Reset
For initialization, the PALCE22V10 has preset and reset product terms. These terms are connected
to all registered outputs. When the synchronous preset (SP) product term is asserted high, the
output registers will be loaded with a HIGH on the next LOW-to-HIGH clock transition. When the
asynchronous reset (AR) product term is asserted high, the output registers will be immediately
loaded with a LOW independent of the clock.
Figure 2. Macrocell Configuration Options
DQ
CLK
SP
AR
a. Registered/active low
S0 = 0
S1 = 0
b. Combinatorial/active low
S0 = 0
S1 = 1
DQ
CLK
SP
AR
c. Registered/active high
S0 = 1
S1 = 0
d. Combinatorial/active high
S0 = 1
S1 = 1
16564E-005
Q
Q
PALCE22V10 and PALCE22V10Z Families 5
Note that preset and reset control the flip-flop, not the output pin. The output level is determined
by the output polarity selected.
Power-Up Reset
All flip-flops power up to a logic LOW for predictable system initialization. Outputs of the
PALCE22V10 will depend on the programmed output polarity. The V
CC
rise must be monotonic,
and the reset delay time is 1000ns maximum.
Register Preload
The register on the PALCE22V10 can be preloaded from the output pins to facilitate functional
testing of complex state machine designs. This feature allows direct loading of arbitrary states,
making it unnecessary to cycle through long test vector sequences to reach a desired state. In
addition, transitions from illegal states can be verified by loading illegal states and observing
proper recovery.
Security Bit
After programming and verification, a PALCE22V10 design can be secured by programming the
security EE bit. Once programmed, this bit defeats readback of the internal programmed pattern
by a device programmer, securing proprietary designs from competitors. When the security bit is
programmed, the array will read as if every bit is erased, and preload will be disabled.
The bit can only be erased in conjunction with erasure of the entire pattern.
Programming and Erasing
The PALCE22V10 can be programmed on standard logic programmers. It also may be erased to
reset a previously configured device back to its unprogrammed state. Erasure is automatically
performed by the programming hardware. No special erase operation is required.
Quality and Testability
The PALCE22V10 offers a very high level of built-in quality. The erasability of the device provides
a direct means of verifying performance of all AC and DC parameters. In addition, this verifies
complete programmability and functionality of the device to provide the highest programming
yields and post-programming functional yields in the industry.
Technology
The high-speed PALCE22V10 is fabricated with Vantis’ advanced electrically erasable (EE) CMOS
process. The array connections are formed with proven EE cells. Inputs and outputs are designed
to be compatible with TTL devices. This technology provides strong input clamp diodes, output
slew-rate control, and a grounded substrate for clean switching.
PCI Compliance
The PALCE22V10H devices in the -5/-7/-10 speed grades are fully compliant with the
PCI Local
Bus Specification
published by the PCI Special Interest Group. The PALCE22V10H’s predictable
timing ensures compliance with the PCI AC specifications independent of the design.
Zero-Standby Power Mode
The PALCE22V10Z features a zero-standby power mode. When none of the inputs switch for an
extended period (typically 50 ns), the PALCE22V10Z will go into standby mode, shutting down
6 PALCE22V10 and PALCE22V10Z Families
most of its internal circuitry. The current will go to almost zero (I
CC
< 30 µA). The outputs will
maintain the states held before the device went into the standby mode.
When any input switches, the internal circuitry is fully enabled, and power consumption returns
to normal. This feature results in considerable power savings for operation at low to medium
frequencies. This saving is illustrated in the I
CC
vs. frequency graph.
Product-Term Disable
On a programmed PALCE22V10Z, any product terms that are not used are disabled. Power is cut
off from these product terms so that they do not draw current. As shown in the I
CC
vs. frequency
graph, product-term disabling results in considerable power savings. This saving is greater at the
higher frequencies.
Further hints on minimizing power consumption can be found in a separate document entitled,
Minimizing Power Consumption with Zero-Power PLDs
.
PALCE22V10 and PALCE22V10Z Families 7
LOGIC DIAGRAM
0
1
9
SP
AR
0 34 78 1112151619202324272831323536394043
10
20
21
0 34 78 1112151619202324272831323536394043
CLK/I01
(2)
2
(3)
I1
3
(4)
I2
4
(5)
I3
5
(6)
I4
6
(7)
I5
7
(9)
I6
8
(10)
I7
9
(11)
I8
10
(12)
I9
11
(13)
I10
12
(14)
GND
24
(28) VCC
(16) I13 11
34
33
48
49
65
66
82
83
97
98
110
111
121
122
130
131
I/O9
23
(27)
8
I/O22
(26)
I/O21
(25) 7
I/O20
(24) 6
5
I/O19
(23)
4
I/O
18
(21)
I/O
17
(20) 3
I/O
16
(19) 2
I/O
15
(18) 1
I/O
14
(17) 0
D
SP
ARQ
0
1
10
11
00
01
D
SP
ARQ
0
1
10
11
00
01
D
SP
ARQ
0
1
10
11
00
01
D
SP
ARQ
0
1
10
11
00
01
D
SP
ARQ
0
1
10
11
00
01
D
SP
ARQ
0
1
10
11
00
01
D
SP
ARQ
0
1
10
11
00
01
D
SP
ARQ
0
1
10
11
00
01
D
SP
ARQ
0
1
10
11
00
01
D
SP
ARQ
0
1
10
11
00
01
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
16564E-006
8 PALCE22V10H-5 (Com’l)
ABSOLUTE MAXIMUM RATINGS
Storage Temperature. . . . . . . . . . . . . .-65
°
C to +150
°
C
Ambient Temperature with
Power Applied . . . . . . . . . . . . . . . . . .-55
°
C to +125
°
C
Supply Voltage with
Respect to Ground . . . . . . . . . . . . . . .-0.5 V to +7.0 V
DC Input Voltage . . . . . . . . . . . .-0.5 V to V
CC
+ 1.0 V
DC Output or I/O Pin Voltage . . .-0.5 V to V
CC
+ 1.0 V
Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V
Latchup Current (T
A
= 0
°
C to +75
°
C) . . . . . . . . 100 mA
Stresses above those listed under Absolute Maximum Ratings
may cause permanent device failure. Functionality at or above
these limits is not implied. Exposure to Absolute Maximum
Ratings for extended periods may affect device reliability.
Programming conditions may vary.
OPERATING RANGES
Commercial (C) Devices
Ambient Temperature (T
A
)
Operating in Free Air. . . . . . . . . . . . . . . 0
°
C to +75
°
C
Supply Voltage (V
CC
) with
Respect to Ground. . . . . . . . . . . . . +4.75 V to +5.25 V
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
Notes:
1. These are absolute values with respect to the device ground, and all overshoots due to system and tester noise are included.
2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH).
3. Not more than one output should be tested at a time, and the duration of the short-circuit test should not exceed one second.
V
OUT
= 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
DC CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES
Parameter
Symbol Parameter Description Test Conditions Min Max Unit
V
OH
Output HIGH Voltage IOH = -3.2 mA, VIN = VIH
or VIL, VCC
= Min 2.4 V
V
OL
Output LOW Voltage IOL
= 16 mA, VIN
= VIH or VIL, VCC
= Min 0.4 V
V
IH
Input HIGH Voltage Guaranteed Input Logical HIGH
Voltage for all Inputs (Note 1) 2.0 V
V
IL
Input LOW Voltage Guaranteed Input Logical LOW
Voltage for all Inputs (Note 1) 0.8 V
I
IH
Input HIGH Leakage Current VIN = VCC, VCC = Max (Note 2) 10
µ
A
I
IL
Input LOW Leakage Current VIN = 0 V, VCC = Max (Note 2) -100
µ
A
I
OZH
Off-State Output Leakage
Current HIGH VOUT = VCC, VCC = Max,
VIN
= VIL or VIH (Note 2) 10
µ
A
I
OZL
Off-State Output Leakage
Current LOW VOUT = 0 V, VCC
= Max,
VIN
= VIL or VIH (Note 2) -100
µ
A
I
SC
Output Short-Circuit
Current VOUT
= 0.5 V, VCC = Max (Note 3) -30 -130 mA
I
CC
(Static) Supply Current Outputs Open, (IOUT = 0 mA), VCC = Max 125 mA
I
CC
(Dynamic) Supply Current Outputs Open, (IOUT = 0 mA), V
CC
= Max, f = 25 MHz 140 mA
PALCE22V10H-5 (Com’l) 9
CAPACITANCE
1
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where
capacitance may be affected.
Notes:
1. See “Switching Test Circuit” for test conditions.
2. Skew is measured with all outputs switching in the same direction.
3. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where
frequency may be affected.
4. t
CF
is a calculated value and is not guaranteed. t
CF
can be found using the following equation:
t
CF
= 1/f
MAX
(internal feedback) - t
S
.
Parameter
Symbol Parameter Description Test Conditions Typ Unit
C
IN
Input Capacitance VIN = 2.0 V VCC = 5.0 V
TA = 25
°C
f = 1 MHz
5pF
C
OUT
Output Capacitance VOUT = 2.0 V 8
SWITCHING CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES
1
Parameter
Symbol Parameter Description
-5
UnitMin Max
t
PD
Input or Feedback to Combinatorial Output 5 ns
t
S1
Setup Time from Input or Feedback 3 ns
t
S2
Setup Time from SP to Clock 4 ns
t
H
Hold Time 0 ns
t
CO
Clock to Output 4ns
t
SKEWR
Skew Between Registered Outputs (Note 2) 0.5 ns
t
AR
Asynchronous Reset to Registered Output 7.5 ns
t
ARW
Asynchronous Reset Width 4.5 ns
t
ARR
Asynchronous Reset Recovery Time 4.5 ns
t
SPR
Synchronous Preset Recovery Time 4.5 ns
t
WL
Clock Width LOW 2.5 ns
t
WH
HIGH 2.5 ns
f
MAX
Maximum Frequency (Note 3)
External Feedback 1/(tS + tCO) 142.8 MHz
Internal Feedback (fCNT) 1/(tS + tCF) (Note 4) 150 MHz
No Feedback 1/(tWH + tWL) 200 MHz
t
EA Input to Output Enable Using Product Term Control 6 ns
tER Input to Output Disable Using Product Term Control 5.5 ns
10 PALCE22V10H-7 (Com’l)
ABSOLUTE MAXIMUM RATINGS
Storage Temperature. . . . . . . . . . . . . .-65°C to +150°C
Ambient Temperature with
Power Applied . . . . . . . . . . . . . . . . . .-55°C to +125°C
Supply Voltage with Respect
to Ground . . . . . . . . . . . . . . . . . . . . .-0.5 V to +7.0 V
DC Input Voltage . . . . . . . . . . . .-0.5 V to VCC + 1.0 V
DC Output or I/O Pin Voltage . . .-0.5 V to VCC + 1.0 V
Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V
Latchup Current (TA = 0°C to +75°C) . . . . . . . . 100 mA
Stresses above those listed under Absolute Maximum Ratings
may cause permanent device failure. Functionality at or above
these limits is not implied. Exposure to Absolute Maximum
Ratings for extended periods may affect device reliability.
Programming conditions may vary.
OPERATING RANGES
Commercial (C) Devices
Ambient Temperature (TA)
Operating in Free Air. . . . . . . . . . . . . . . 0°C to +75°C
Supply Voltage (VCC) with
Respect to Ground. . . . . . . . . . . . . +4.75 V to +5.25 V
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
Notes:
1. These are absolute values with respect to the device ground, and all overshoots due to system and tester noise are included.
2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH).
3. Not more than one output should be tested at a time. Duration of the short-circuit test should not exceed one second.
VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
DC CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES
Symbol Parameter Description Test Conditions Min Max Unit
VOH Output HIGH Voltage IOH = -3.2 mA, VIN = VIH or VIL, VCC = Min 2.4 V
VOL Output LOW Voltage IOL = 16 mA, VIN = VIH or VIL, VCC = Min 0.4 V
VIH Input HIGH Voltage Guaranteed Input Logical HIGH
Voltage for all Inputs (Note 1) 2.0 V
VIL Input LOW Voltage Guaranteed Input Logical LOW
Voltage for all Inputs (Note 1) 0.8 V
IIH Input HIGH Leakage Current VIN = VCC, VCC = Max (Note 2) 10 µA
IIL Input LOW Leakage Current VIN = 0 V, VCC = Max (Note 2) -100 µA
IOZH Off-State Output Leakage
Current HIGH VOUT = VCC, VCC = Max, VIN = VIL or VIH (Note 2) 10 µA
IOZL Off-State Output Leakage
Current LOW VOUT = 0 V, VCC = Max, VIN = VIL or VIH (Note 2) -100 µA
ISC Output Short-Circuit
Current VOUT = 0.5 V, VCC = Max
TA = 25°C (Note 3) -30 -130 mA
ICC (Static) Supply Current Outputs Open, (IOUT = 0 mA), VCC = Max 115 mA
ICC (Dynamic) Supply Current Outputs Open, (IOUT = 0 mA), VCC = Max, f = 25 MHz 140 mA
PALCE22V10H-7 (Com’l) 11
CAPACITANCE 1
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where
capacitance may be affected.
Notes:
1. See “Switching Test Circuit” for test conditions.
2. Skew is measured with all outputs switching in the same direction.
3. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where
frequency may be affected.
4. tCF is a calculated value and is not guaranteed. tCF can be found using the following equation:
tCF = 1/fMAX (internal feedback) - tS.
Parameter
Symbol Parameter Description Test Conditions Typ Unit
CIN Input Capacitance VIN = 2.0 V VCC = 5.0 V
TA = 25°C
f = 1 MHz
5pF
COUT Output Capacitance VOUT = 2.0 V 8
SWITCHING CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES 1
Parameter
Symbol Parameter Description
-7
Unit
PDIP PLCC
Min Max Min Max
tPD Input or Feedback to Combinatorial Output 3 7.5 3 7.5 ns
tS1 Setup Time from Input or Feedback 5 4.5 ns
tS2 Setup Time from SP to Clock 6 6 ns
tHHold Time 0 0 ns
tCO Clock to Output 2 5 2 4.5 ns
tSKEWR Skew Between Registered Outputs (Note 2) 1 1 ns
tAR Asynchronous Reset to Registered Output 10 10 ns
tARW Asynchronous Reset Width 7 7 ns
tARR Asynchronous Reset Recovery Time 7 7 ns
tSPR Synchronous Preset Recovery Time 7 7 ns
tWL Clock Width LOW 3.5 3.0 ns
tWH HIGH 3.5 3.0 ns
fMAX Maximum Frequency
(Note 3)
External Feedback 1/(tS + tCO) 100 111 MHz
Internal Feedback
(fCNT)1/(tS + tCF) (Note 4) 125 133 MHz
No Feedback 1/(tWH + tWL) 142.8 166 MHz
tEA Input to Output Enable Using Product Term Control 7.5 7.5 ns
tER Input to Output Disable Using Product Term Control 7.5 7.5 ns
12 PALCE22V10H-10 (Com’l)
ABSOLUTE MAXIMUM RATINGS
Storage Temperature. . . . . . . . . . . . . .-65°C to +150°C
Ambient Temperature with
Power Applied . . . . . . . . . . . . . . . . . .-55°C to +125°C
Supply Voltage with Respect
to Ground . . . . . . . . . . . . . . . . . . . . .-0.5 V to +7.0 V
DC Input Voltage . . . . . . . . . . . .-0.5 V to VCC + 1.0 V
DC Output or I/O Pin Voltage . . .-0.5 V to VCC + 1.0 V
Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V
Latchup Current (TA = 0°C to +75°C) . . . . . . . . 100 mA
Stresses above those listed under Absolute Maximum Ratings
may cause permanent device failure. Functionality at or above
these limits is not implied. Exposure to absolute maximum rat-
ings for extended periods may affect device reliability.
Programming conditions may vary.
OPERATING RANGES
Commercial (C) Devices
Ambient Temperature (TA)
Operating in Free Air. . . . . . . . . . . . . . . 0°C to +75°C
Supply Voltage (VCC) with
Respect to Ground. . . . . . . . . . . . . +4.75 V to +5.25 V
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
Notes:
1. These are absolute values with respect to the device ground, and all overshoots due to system and tester noise are included.
2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH).
3. Not more than one output should be tested at a time. Duration of the short-circuit test should not exceed one second.
VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
DC CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES
Parameter
Symbol Parameter Description Test Conditions Min Max Unit
VOH Output HIGH Voltage IOH = -3.2 mA, VIN = VIH or VIL, VCC = Min 2.4 V
VOL Output LOW Voltage IOL = 16 mA, VIN = VIH or VIL, VCC = Min 0.4 V
VIH Input HIGH Voltage Guaranteed Input Logical HIGH Voltage for all Inputs (Note 1) 2.0 V
VIL Input LOW Voltage Guaranteed Input Logical LOW
Voltage for all Inputs (Note 1) 0.8 V
IIH Input HIGH Leakage Current VIN = VCC, VCC = Max (Note 2) 10 µA
IIL Input LOW Leakage Current VIN = 0 V, VCC = Max (Note 2) -100 µA
IOZH Off-State Output Leakage
Current HIGH VOUT = VCC, VCC = Max, VIN = VIL or VIH (Note 2) 10 µA
IOZL Off-State Output Leakage
Current LOW VOUT = 0 V, VCC = Max
VIN = VIL or VIH (Note 2) -100 µA
ISC Output Short-Circuit
Current VOUT = 0.5 V, VCC = Max
TA = 25°C (Note 3) -30 -130 mA
ICC (Dynamic) Supply Current Outputs Open , (IOUT = 0 mA), VCC = Max, f = 25 MHz 120 mA
PALCE22V10H-10 (Com’l) 13
CAPACITANCE 1
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where
capacitance may be affected.
Notes:
1. See “Switching Test Circuit” for test conditions.
2. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where
frequency may be affected.
3. tCF is a calculated value and is not guaranteed. tCF can be found using the following equation:
tCF = 1/fMAX (internal feedback) - tS.
Parameter
Symbol Parameter Description Test Conditions Typ Unit
CIN Input Capacitance VIN = 2.0 V VCC = 5.0 V
TA = 25°C
f = 1 MHz
5pF
COUT Output Capacitance VOUT = 2.0 V 8
SWITCHING CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES 1
Parameter
Symbol Parameter Description
-10
UnitMin Max
tPD Input or Feedback to Combinatorial Output 10 ns
tS1 Setup Time from Input or Feedback 6 ns
tS2 Setup Time from SP to Clock 7 ns
tHHold Time 0 ns
tCO Clock to Output 6ns
tAR Asynchronous Reset to Registered Output 13 ns
tARW Asynchronous Reset Width 8 ns
tARR Asynchronous Reset Recovery Time 8 ns
tSPR Synchronous Preset Recovery Time 8 ns
tWL Clock Width LOW 4 ns
tWH HIGH 4 ns
fMAX
Maximum
Frequency
(Note 2)
External Feedback 1/(tS + tCO) 83.3 MHz
Internal Feedback (fCNT) 1/(tS + tCF) (Note 3) 110 MHz
No Feedback 1/(tWH + tWL) 125 MHz
tEA Input to Output Enable Using Product Term Control 10 ns
tER Input to Output Disable Using Product Term Control 9 ns
14 PALCE22V10Q-10 (Com’l)
ABSOLUTE MAXIMUM RATINGS
Storage Temperature. . . . . . . . . . . . . .-65°C to +150°C
Ambient Temperature with
Power Applied . . . . . . . . . . . . . . . . . .-55°C to +125°C
Supply Voltage with Respect
to Ground . . . . . . . . . . . . . . . . . . . . .-0.5 V to +7.0 V
DC Input Voltage . . . . . . . . . . . .-0.5 V to VCC + 1.0 V
DC Output or I/O Pin
Voltage . . . . . . . . . . . . . . . . . . .-0.5 V to VCC + 1.0 V
Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V
Latchup Current (TA = 0°C to +75°C) . . . . . . . . 100 mA
Stresses above those listed under Absolute Maximum Ratings
may cause permanent device failure. Functionality at or above
these limits is not implied. Exposure to Absolute Maximum
Ratings for extended periods may affect device reliability.
Programming conditions may vary.
OPERATING RANGES
Commercial (C) Devices
Ambient Temperature (TA)
Operating in Free Air. . . . . . . . . . . . . . . 0°C to +75°C
Supply Voltage (VCC) with
Respect to Ground. . . . . . . . . . . . . +4.75 V to +5.25 V
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
Notes:
1. These are absolute values with respect to the device ground, and all overshoots due to system and tester noise are included.
2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH).
3. Not more than one output should be tested at a time, and the duration of the short-circuit test should not exceed one second.
VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
4. This parameter is guaranteed worst case under test condition. Refer to the ICC vs. frequency graph for typical ICC
characteristics.
DC CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES
Parameter
Symbol Parameter Description Test Conditions Min Max Unit
VOH Output HIGH Voltage IOH = -3.2 mA, VIN = VIH or VIL, VCC = Min 2.4 V
VOL Output LOW Voltage IOL = 16 mA, VIN = VIH or VIL, VCC = Min 0.4 V
VIH Input HIGH Voltage Guaranteed Input Logical HIGH
Voltage for all Inputs (Note 1) 2.0 V
VIL Input LOW Voltage Guaranteed Input Logical LOW
Voltage for all Inputs (Note 1) 0.8 V
IIH Input HIGH Leakage Current VIN = VCC, VCC = Max (Note 2) 10 µA
IIL Input LOW Leakage Current VIN = 0 V, VCC = Max (Note 2) -100 µA
IOZH Off-State Output Leakage
Current HIGH VOUT = VCC, VCC = Max
VIN = VIL or VIH (Note 2) 10 µA
IOZL Off-State Output Leakage
Current LOW VOUT = 0 V, VCC = Max
VIN = VIL or VIH (Note 2) -100 µA
ISC Output Short-Circuit
Current VOUT = 0.5 V, VCC = 5 V
TA = 25°C (Note 3) -30 -130 mA
ICC (Static) Supply Current VIN = 0 V, Outputs Open (IOUT = 0mA),
VCC = Max (Note 4) 55 mA
PALCE22V10Q-10 (Com’l) 15
CAPACITANCE 1
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where
capacitance may be affected.
Notes:
1. See “Switching Test Circuit” for test conditions.
2. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where
frequency may be affected.
3. tCF is a calculated value and is not guaranteed. tCF can be found using the following equation:
tCF = 1/fMAX (internal feedback) - tS.
Parameter
Symbol Parameter Description Test Conditions Typ Unit
CIN Input Capacitance VIN = 2.0 V VCC = 5.0 V
TA = 25°C
f = 1 MHz
5pF
COUT Output Capacitance VOUT = 2.0 V 8
SWITCHING CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES 1
Parameter
Symbol Parameter Description
-10
UnitMin Max
tPD Input or Feedback to Combinatorial Output 10 ns
tSSetup Time from Input, Feedback or SP to Clock 6 ns
tHHold Time 0 ns
tCO Clock to Output 6ns
tAR Asynchronous Reset to Registered Output 13 ns
tARW Asynchronous Reset Width 8 ns
tARR Asynchronous Reset Recovery Time 8 ns
tSPR Synchronous Preset Recovery Time 8 ns
tWL Clock Width LOW 4 ns
tWH HIGH 4 ns
fMAX Maximum Frequency (Note 2)
External Feedback 1/(tS + tCO) 83 MHz
Internal Feedback (fCNT) 1/(tS + tCO) (Note 3) 110 MHz
No Feedback 1/(tWH + tWL) 125 MHz
tEA Input to Output Enable Using Product Term Control 10 ns
tER Input to Output Disable Using Product Term Control 9 ns
16 PALCE22V10H-15/25, Q-15/25 (Com’l)
ABSOLUTE MAXIMUM RATINGS
Storage Temperature. . . . . . . . . . . . . .-65°C to +150°C
Ambient Temperature with
Power Applied . . . . . . . . . . . . . . . . . .-55°C to +125°C
Supply Voltage with Respect
to Ground . . . . . . . . . . . . . . . . . . . . .-0.5 V to +7.0 V
DC Input Voltage . . . . . . . . . . . .-0.5 V to VCC + 0.5 V
DC Output or I/O Pin
Voltage . . . . . . . . . . . . . . . . . . .-0.5 V to VCC + 0.5 V
Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V
Latchup Current (TA = 0°C to +75°C) . . . . . . . . 100 mA
Stresses above those listed under Absolute Maximum Ratings
may cause permanent device failure. Functionality at or above
these limits is not implied. Exposure to Absolute Maximum Rat-
ings for extended periods may affect device reliability.
Programming conditions may vary.
OPERATING RANGES
Commercial (C) Devices
Ambient Temperature (TA)
Operating in Free Air. . . . . . . . . . . . . . . 0°C to +75°C
Supply Voltage (VCC) with
Respect to Ground (H/Q-15) . . . . . +4.75 V to +5.25 V
Supply Voltage (VCC) with
Respect to Ground (H/Q-25) . . . . . . . +4.5 V to +5.5 V
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
Notes:
1. These are absolute values with respect to the device ground, and all overshoots due to system and tester noise are included.
2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH).
3. Not more than one output should be tested at a time, and the duration of the short-circuit test should not exceed one second.
VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
DC CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES
Parameter
Symbol Parameter Description Test Conditions Min Max Unit
VOH Output HIGH Voltage IOH = -3.2 mA, VIN = VIH or VIL, VCC = Min 2.4 V
VOL Output LOW Voltage IOL = 16 mA, VIN = VIH or VIL, VCC = Min 0.4 V
VIH Input HIGH Voltage Guaranteed Input Logical HIGH Voltage for all Inputs
(Note 1) 2.0 V
VIL Input LOW Voltage Guaranteed Input Logical LOW Voltage for all Inputs
(Note 1) 0.8 V
IIH Input HIGH Leakage Current VIN = VCC, VCC = Max (Note 2) 10 µA
IIL Input LOW Leakage Current VIN = 0 V, VCC = Max (Note 2) -100 µA
IOZH Off-State Output Leakage
Current HIGH VOUT = VCC, VCC = Max, VIN = VIL or VIH (Note 2) 10 µA
IOZL Off-State Output Leakage
Current LOW VOUT = 0 V, VCC = Max, VIN = VIL or VIH (Note 2) -100 µA
ISC Output Short-Circuit
Current VOUT = 0.5 V, VCC = 5 V
TA = 25°C (Note 3) -30 -130 mA
ICC Supply Current VIN = 0 V, Outputs Open
(IOUT = 0 mA), VCC = Max H90
mA
Q55
PALCE22V10H-15/25, Q-15/25 (Com’l) 17
CAPACITANCE 1
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where
capacitance may be affected.
Notes:
1. See “Switching Test Circuit” for test conditions.
2. These parameters are not 100% tested, but are evaluated at initial characterization and at any time
the design is modified where frequency may be affected.
3. tCF is a calculated value and is not guaranteed. tCF can be found using the following equation:
tCF = 1/fMAX (internal feedback) - tS.
Parameter
Symbol Parameter Description Test Conditions Typ Unit
CIN Input Capacitance VIN = 2.0 V VCC = 5.0 V
TA = 25°C
f = 1 MHz
5pF
COUT Output Capacitance VOUT = 2.0 V 8
SWITCHING CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES 1
Parameter
Symbol Parameter Description
-15 -25
UnitMin Max Min Max
tPD Input or Feedback to Combinatorial Output 15 25 ns
tSSetup Time from Input, Feedback or SP to Clock 10 15 ns
tHHold Time 0 0 ns
tCO Clock to Output 10 15 ns
tAR Asynchronous Reset to Registered Output 20 25 ns
tARW Asynchronous Reset Width 15 25 ns
tARR Asynchronous Reset Recovery Time 10 25 ns
tSPR Synchronous Preset Recovery Time 10 25 ns
tWL Clock Width LOW 8 13 ns
tWH HIGH 8 13 ns
fMAX Maximum Frequency
(Note 2) External Feedback 1/(tS + tCO) 50 33.3 MHz
Internal Feedback (fCNT) 1/(tS + tCF) (Note 3) 58.8 35.7 MHz
tEA Input to Output Enable Using Product Term Control 15 25 ns
tER Input to Output Disable Using Product Term Control 15 25 ns
18 PALCE22V10H-10/15/20/25 (Ind)
ABSOLUTE MAXIMUM RATINGS
Storage Temperature. . . . . . . . . . . . . .-65°C to +150°C
Ambient Temperature with
Power Applied . . . . . . . . . . . . . . . . . .-55°C to +125°C
Supply Voltage with Respect
to Ground . . . . . . . . . . . . . . . . . . . . .-0.5 V to +7.0 V
DC Input Voltage . . . . . . . . . . . .-0.5 V to VCC + 0.5 V
DC Output or I/O Pin
Voltage . . . . . . . . . . . . . . . . . . .-0.5 V to VCC + 0.5 V
Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V
Latchup Current (TA = -40°C to +85°C) . . . . . . 100 mA
Stresses above those listed under Absolute Maximum Ratings
may cause permanent device failure. Functionality at or above
these limits is not implied. Exposure to Absolute Maximum Rat-
ings for extended periods may affect device reliability.
Programming conditions may vary.
OPERATING RANGES
Industrial (I) Devices
Ambient Temperature (TA)
Operating in Free Air. . . . . . . . . . . . . . -40°C to +85°C
Supply Voltage (VCC) with
Respect to Ground. . . . . . . . . . . . . . . +4.5 V to +5.5 V
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
Notes:
1. These are absolute values with respect to the device ground, and all overshoots due to system and tester noise are included.
2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH).
3. Not more than one output should be tested at a time, and the duration of the short-circuit test should not exceed one second.
VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
DC CHARACTERISTICS OVER INDUSTRIAL OPERATING RANGES
Parameter
Symbol Parameter Description Test Conditions Min Max Unit
VOH Output HIGH Voltage IOH = -3.2 mA, VIN = VIH or VIL, VCC = Min 2.4 V
VOL Output LOW Voltage IOL = 16 mA, VIN = VIH or VIL, VCC = Min 0.4 V
VIH Input HIGH Voltage Guaranteed Input Logical HIGH
Voltage for all Inputs (Note 1) 2.0 V
VIL Input LOW Voltage Guaranteed Input Logical LOW
Voltage for all Inputs (Note 1) 0.8 V
IIH Input HIGH Leakage Current VIN = VCC, VCC = Max (Note 2) 10 µA
IIL Input LOW Leakage Current VIN = 0 V, VCC = Max (Note 2) -100 µA
IOZH Off-State Output Leakage Current HIGH VOUT = VCC, VCC = Max, VIN = VIL or VIH (Note 2) 10 µA
IOZL Off-State Output Leakage Current LOW VOUT = 0 V, VCC = Max, VIN = VIL or VIH (Note 2) -100 µA
ISC Output Short-Circuit Current VOUT = 0.5 V, VCC = 5 V
TA = 25°C (Note 3) -30 -130 mA
ICC (Static) Supply Current H-20/25 VIN = 0 V, Outputs Open
(IOUT = 0 mA), VCC = Max 100 mA
H-10/15 110
ICC (Dynamic) Supply Current VIN = 0 V, Outputs Open
(IOUT = 0 mA), VCC = Max, f = 15 MHz 130 mA
PALCE22V10H-10/15/20/25 (Ind) 19
CAPACITANCE 1
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where
capacitance may be affected.
Notes:
1. See “Switching Test Circuit” for test conditions.
2. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where
frequency may be affected.
3. tCF is a calculated value and is not guaranteed. tCF can be found using the following equation:
tCF = 1/fMAX (internal feedback) - tS.
Parameter
Symbol Parameter Description Test Conditions Typ Unit
CIN Input Capacitance VIN = 2.0 V VCC = 5.0 V
TA = 25°C
f = 1 MHz
5pF
COUT Output Capacitance VOUT = 2.0 V 8
SWITCHING CHARACTERISTICS OVER INDUSTRIAL OPERATING RANGES 1
Parameter
Symbol Parameter Description
-10 -15 -20 -25
UnitMin Max Min Max Min Max Min Max
tPD Input or Feedback to Combinatorial Output 10 15 20 25 ns
tSSetup Time from Input, Feedback or SP to Clock 7 10 12 15 ns
tHHold Time 0000ns
tCO Clock to Output 6 10 12 15 ns
tAR Asynchronous Reset to Registered Output 13 20 25 25 ns
tARW Asynchronous Reset Width 8 15 20 25 ns
tARR Asynchronous Reset Recovery Time 8 10 20 25 ns
tSPR Synchronous Preset Recovery Time 8 10 14 25 ns
tWL Clock Width LOW 4 8 10 13 ns
tWH HIGH 4 8 10 13 ns
fMAX
Maximum
Frequency
(Note 2)
External Feedback 1/(tS + tCO) 83.3 50 41.6 33.3 MHz
Internal Feedback (fCNT) 1/(tS + tCF) (Note 3) 110 58.8 45.4 35.7 MHz
No Feedback 1/(tWH + tWL) 125 83.3 50 38.5 MHz
tEA Input to Output Enable Using Product Term Control 10 15 20 25 ns
tER Input to Output Disable Using Product Term Control 9 15 20 25 ns
20 PALCE22V10Z-15 (Ind)
ABSOLUTE MAXIMUM RATINGS
Storage Temperature. . . . . . . . . . . . . .-65°C to +150°C
Ambient Temperature with
Power Applied . . . . . . . . . . . . . . . . . .-55°C to +125°C
Supply Voltage with Respect
to Ground . . . . . . . . . . . . . . . . . . . . .-0.5 V to +7.0 V
DC Input Voltage . . . . . . . . . . . .-0.5 V to VCC + 0.5 V
DC Output or I/O Pin
Voltage . . . . . . . . . . . . . . . . . . .-0.5 V to VCC + 0.5 V
Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V
Latchup Current (TA = -40°C to +85°C) . . . . . . 100 mA
Stresses above those listed under Absolute Maximum Ratings
may cause permanent device failure. Functionality at or above
these limits is not implied. Exposure to Absolute Maximum Rat-
ings for extended periods may affect device reliability.
Programming conditions may differ.
OPERATING RANGES
Industrial (I) Devices
Ambient Temperature (TA). . . . . . . . . . -40°C to +85°C
Supply Voltage (VCC) with
Respect to Ground. . . . . . . . . . . . . . . +4.5 V to +5.5 V
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
Notes:
1. These are absolute values with respect to device ground, and all overshoots due to system or tester noise are included.
2. Represents the worst case of HC and HCT standards, allowing compatibility with either.
3. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH).
4. Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second.
VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation
DC CHARACTERISTICS OVER INDUSTRIAL OPERATING RANGES
Parameter
Symbol Parameter Description Test Conditions Min Max Unit
VOH Output HIGH Voltage VIN = VIH or VIL
VCC = Min
IOH = -6 mA 3.84 V
IOH = -20 µAV
CC-0.1 V
VOL Output LOW Voltage VIN = VIH or VIL
VCC = Min
IOL = 16 mA 0.5 V
IOL = 6 mA 0.33 V
IOL = 20 µA 0.1 V
VIH Input HIGH Voltage Guaranteed Input Logical HIGH Voltage for all Inputs
(Notes 1, 2) 2.0 V
VIL Input LOW Voltage Guaranteed Input Logical LOW Voltage for all Inputs
(Notes 1, 2) 0.9 V
IIH Input HIGH Leakage Current VIN = VCC, VCC = Max (Note 3) 10 µA
IIL Input LOW Leakage Current VIN = 0 V, VCC = Max (Note 3) -10 µA
IOZH Off-State Output Leakage Current HIGH VOUT = VCC, VCC = Max VIN = VIH or VIL (Note 3) 10 µA
IOZL Off-State Output Leakage Current LOW VOUT = 0 V, VCC = Max VIN = VIH or VIL (Note 3) -10 µA
ISC Output Short-Circuit Current VOUT = 0.5 V, VCC = Max (Note 4) -5 -150 mA
ICC Supply Current Outputs Open (IOUT = 0 mA)
VCC = Max
f = 0 MHz 30 µA
f = 15 MHz 100 mA
PALCE22V10Z-15 (Ind) 21
CAPACITANCE 1
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where
capacitance may be affected.
Notes:
1. See “Switching Test Circuit” for test conditions.
2. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where frequency may be affected.
3. tCF is a calculated value and is not guaranteed. tCF can be found using the following equation:
tCF = 1/fMAX (internal feedback) - tS.
Parameter
Symbol Parameter Description Test Conditions Typ Unit
CIN Input Capacitance VIN = 2.0 V VCC = 5.0 V
TA = 25°C
f = 1 MHz
5pF
COUT Output Capacitance VOUT = 2.0 V 8
SWITCHING CHARACTERISTICS OVER INDUSTRIAL OPERATING RANGES 1
Parameter
Symbol Parameter Description
-15
UnitMin Max
tPD Input or Feedback to Combinatorial Output 15 ns
tSSetup Time from Input, Feedback or SP to Clock 10 ns
tHHold Time 0ns
tCO Clock to Output 10 ns
tAR Asynchronous Reset to Registered Output 20 ns
tARW Asynchronous Reset Width 15 ns
tARR Asynchronous Reset Recovery Time 10 ns
tSPR Synchronous Preset Recovery Time 10 ns
tWL Clock Width LOW 8 ns
tWH HIGH 8 ns
fMAX Maximum Frequency
(Note 2)
External Feedback 1/(tS + tCO) 50 MHz
Internal Feedback (fCNT) 1/(tS + tCF) (Note 3) 58.8 MHz
No Feedback 1/(tWH + tWL) 62.5 MHz
tEA Input to Output Enable Using Product Term Control 15 ns
tER Input to Output Disable Using Product Term Control 15 ns
22 PALCE22V10Z-25 (Com’l, Ind)
ABSOLUTE MAXIMUM RATINGS
Storage Temperature. . . . . . . . . . . . . .-65°C to +150°C
Ambient Temperature with
Power Applied . . . . . . . . . . . . . . . . . .-55°C to +125°C
Supply Voltage with Respect
to Ground . . . . . . . . . . . . . . . . . . . . .-0.5 V to +7.0 V
DC Input Voltage . . . . . . . . . . . .-0.5 V to VCC + 0.5 V
DC Output or I/O Pin
Voltage . . . . . . . . . . . . . . . . . . .-0.5 V to VCC + 0.5 V
Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V
Latchup Current (TA = -40°C to +85°C) . . . . . . 100 mA
Stresses above those listed under Absolute Maximum Ratings
may cause permanent device failure. Functionality at or above
these limits is not implied. Exposure to Absolute Maximum
Ratings for extended periods may affect device reliability.
Programming conditions may differ.
OPERATING RANGES
Commercial (C) Devices
Ambient Temperature (TA). . . . . . . . . . . 0°C to +75°C
Supply Voltage (VCC) with
Respect to Ground. . . . . . . . . . . . . +4.75 V to +5.25 V
Industrial (I) Devices
Ambient Temperature (TA). . . . . . . . . -40°C to +85°C
Supply Voltage (VCC) with
Respect to Ground. . . . . . . . . . . . . . . +4.5 V to +5.5 V
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
Notes:
1. These are absolute values with respect to device ground, and all overshoots due to system or tester noise are included.
2. Represents the worst case of HC and HCT standards, allowing compatibility with either.
3. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH).
4. Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second.
VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
DC CHARACTERISTICS OVER COMMERCIAL AND INDUSTRIAL OPERATING
RANGES
Parameter
Symbol Parameter Description Test Conditions Min Max Unit
VOH Output HIGH Voltage VIN = VIH or VIL
VCC = Min
IOH = -6 mA 3.84 V
IOH = -20 µA VCC-0.1 V
VOL Output LOW Voltage VIN = VIH or VIL
VCC = Min
IOL = 16 mA 0.5 V
IOL = 6 mA 0.33 V
IOL = 20 µA 0.1 V
VIH Input HIGH Voltage Guaranteed Input Logical HIGH Voltage for all Inputs
(Notes 1, 2) 2.0 V
VIL Input LOW Voltage Guaranteed Input Logical LOW Voltage for all Inputs
(Notes 1, 2) 0.9 V
IIH Input HIGH Leakage Current VIN = VCC, VCC = Max (Note 3) 10 µA
IIL Input LOW Leakage Current VIN = 0 V, VCC = Max (Note 3) -10 µA
IOZH Off-State Output Leakage Current HIGH VOUT = VCC, VCC = Max, VIN = VIH or VIL (Note 3) 10 µA
IOZL Off-State Output Leakage Current LOW VOUT = 0 V, VCC = Max, VIN = VIH or VIL (Note 3) -10 µA
ISC Output Short-Circuit Current VOUT = 0.5 V, VCC = Max (Note 4) -5 -150 mA
ICC Supply Current Outputs Open (IOUT = 0 mA)
VCC = Max
f = 0 MHz 30 µA
f = 15 MHz 120 mA
PALCE22V10Z-25 (Com’l, Ind) 23
CAPACITANCE 1
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where
capacitance may be affected.
Notes:
1. See “Switching Test Circuit” for test conditions.
2. This parameter is tested in Standby Mode. When the device is not in Standby Mode, the tPD will typically be 5 ns faster.
3. These parameters are not 100% tested, but are evaluated at initial characterization and at any time
the design is modified where frequency may be affected.
4. tCF is a calculated value and is not guaranteed. tCF can be found using the following equation:
tCF = 1/fMAX (internal feedback) - tS.
Parameter
Symbol Parameter Description Test Conditions Typ Unit
CIN Input Capacitance VIN = 2.0 V VCC = 5.0 V
TA = 25°C
f = 1 MHz
5pF
COUT Output Capacitance VOUT = 2.0 V 8
SWITCHING CHARACTERISTICS OVER COMMERCIAL AND INDUSTRIAL
OPERATING RANGES 1
Parameters
Symbol Parameter Description
-25
UnitMin Max
tPD Input or Feedback to Combinatorial Output (Note 2) 25 ns
tSSetup Time from Input, Feedback or SP to Clock 15 ns
tHHold Time 0 ns
tCO Clock to Output 15 ns
tAR Asynchronous Reset to Registered Output 25 ns
tARW Asynchronous Reset Width 25 ns
tARR Asynchronous Reset Recovery Time 25 ns
tSPR Synchronous Preset Recovery Time 25 ns
tWL Clock Width LOW 10 ns
tWH HIGH 10 ns
fMAX Maximum Frequency
(Notes 3)
External Feedback 1/(tS + tCO) 33.3 MHz
Internal Feedback (fCNT) 1/(tS + tCF) (Note 4) 35.7 MHz
No Feedback 1/(tWH + tWL) 50 MHz
tEA Input to Output Enable Using Product Term Control 25 ns
tER Input to Output Disable Using Product Term Control 25 ns
24 PALCE22V10 and PALCE22V10Z Families
SWITCHING WAVEFORMS
Notes:
1. VT = 1.5 V.
2. Input pulse amplitude 0 V to 3.0 V.
3. Input rise and fall times 2 ns to 5 ns typical.
16564-007 16564-008
a. Combinatorial output b. Registered output
tPD
Input, I/O, or
Feedback
Combinatorial
Output
VT
VT
VT
Input, I/O,
or Feedback
Registered
Output
tS
tCO
VT
tH
VT
Clock
16564-009 16564-010
c. Clock width d. Input to output disable/enable
tWH
Clock
tWL
VT
VT
Input
Output
tER tEA
VOH - 0.5V
VOL + 0.5V
16564-011 16564-012
e. Asynchronous reset f. Synchronous preset
VT
VT
tARW
VT
tAR
Registered
Output
Clock
tARR VT
VT
tSPR
VT
tS
Clock
Registered
Output
Input
Asserting
Synchronous
Preset tH
tCO
Input
Asserting
Asynchronous
Preset
PALCE22V10 and PALCE22V10Z Families 25
KEY TO SWITCHING WAVEFORMS
SWITCHING TEST CIRCUIT
Specification S1CL
Commercial Measured Output
ValueR1R2
tPD, tCO Closed
50 pF
300 Ω
All except H-5/7:
390 Ω
1.5 V
tEA Z → H: Open 1.5 V
Z → L: Closed
tER H → Z: Open 5 pF H-5/7:
300 ΩH → Z: VOH - 0.5 V
L →Z: VOL + 0.5 V
L → Z: Closed
Must be
Steady
May
Change
from H to L
May
Change
from L to H
Does Not
Apply
Don’t Care,
Any Change
Permitted
Will be
Steady
Will be
Changing
from H to L
Will be
Changing
from L to H
Changing,
State
Unknown
Center
Line is High-
Impedance
“Off” State
WAVEFORM INPUTS OUTPUTS
16564E-013
16564-014
CL
Output
R1
R2
S1
Test Point
5 V
26 PALCE22V10 and PALCE22V10Z Families
TYPICAL ICC CHARACTERISTICS
VCC = 5.0 V, TA = 25°C
Frequency (MHz)
ICC (mA)
The selected “typical” pattern utilized 50% of the device resources. Half of the macrocells were programmed as registered,
and the other half were programmed as combinator ial. Half of the available product terms were used for each macrocell. On
any vector, half of the outputs were switching.
By utilizing 50% of the device, a midpoint is defined for ICC., From this midpoint, a designer may scale the ICC graphs up or
down to estimate the ICC requirements for a particular design.
22V10H-7
22V10H-15
22V10H-25
22V10Q-25
ICC vs. Frequency
22V10H-10
22V10H-5
22V10Q-10
16564E-015
150
125
100
75
50
25
0
01020304050
PALCE22V10 and PALCE22V10Z Families 27
TYPICAL ICC CHARACTERISTICS FOR THE PALCE22V10Z-15
VCC = 5.0 V, TA = 25°C
TYPICAL ICC CHARACTERISTICS FOR THE PALCE22V10Z-25
VCC = 5.0 V, TA = 25°C
Frequency (MHz)
100%* 50%*
25%*
0
15
30
45
60
75
110
01530 4560
ICC (mA)
*Percent of product terms used. 16564E-016
ICC vs. Frequency Graph for the PALCE22V10Z-15
Frequency (MHz)
100%*
50%*
25%*
0
20
40
60
80
100
120
0102030
ICC (mA)
*Percent of product terms used.
5 15 25 35 40 45 50
16564E-017
ICC vs. Frequency Graph for the PALCE22V10Z-25
28 PALCE22V10 and PALCE22V10Z Families
ENDURANCE CHARACTERISTICS
The PALCE22V10 is manufactured using V antis’ advanced electrically-erasable (EE) CMOS process.
This technology uses an EE cell to replace the fuse link used in bipolar parts. As a result, the device
can be erased and reprogrammed—a feature which allows 100% testing at the factory.
INPUT/OUTPUT EQUIVALENT SCHEMATICS FOR SELECTED /4 DEVICES*
Symbol Parameter Test Conditions Value Unit
tDR Min Pattern Data Retention Time Max Storage Temperature 10 Years
N Max Reprogramming Cycles Normal Programming Conditions 100 Cycles
Input
Output
Preload
Circuitry
ESD
Protection
Feedback
Input
VCC
VCC
100 kΩ
100 kΩ
VCC
VCC VCC
*
16564E-018
Device Rev Letter
PALCE22V10H-15
HPALCE22V10H-20H
PALCE22V10H-25
PALCE22V10Q-25I I
PALCE22V10 and PALCE22V10Z Families 29
ROBUSTNESS FEATURES
The PALCE22V10X-X/5 devices have some unique features that make them extremely robust,
especially when operating in high-speed design environments. Pull-up resistors on inputs and I/O
pins cause unconnected pins to default to a known state. Input clamping circuitry limits negative
overshoot, eliminating the possibility of false clocking caused by subsequent ringing. A special
noise filter makes the programming circuitry completely insensitive to any positive overshoot that
has a pulse width of less than about 100 ns for the /5 version.
INPUT/OUTPUT EQUIVALENT SCHEMATICS FOR /5 VERSION DEVICES
Typical Input
Typical Output
Preload
Circuitry
ESD
Protection
and
Clamping
Feedback
Input
> 50 kΩ
VCC
Programming
Voltage
Detection
Positive
Overshoot
Filter Programming
Circuitry
Provides ESD
Protection and
Clamping
Programming
Pins only
16564-16
VCC
> 50 kΩ
VCC
VCC
30 PALCE22V10 and PALCE22V10Z Families
INPUT/OUTPUT EQUIVALENT SCHEMATICS FOR PALCE22V10Z
Typical Input
Typical Output
Preload
Circuitry
ESD
Protection
and
Clamping
Feedback
Input
VCC
VCC
Programming
Voltage
Detection
Positive
Overshoot
Filter Programming
Circuitry
Provides ESD
Protection and
Clamping
Programming
Pins only
Input
Transition
Detection
Input
Transition
Detection
16564E-020
PALCE22V10 and PALCE22V10Z Families 31
POWER-UP RESET
The power-up reset feature ensures that all flip-flops will be reset to LOW after the device has been
powered up. The output state will depend on the programmed pattern. This feature is valuable in
simplifying state machine initialization. A timing diagram and parameter table are shown below.
Due to the synchronous operation of the power-up reset and the wide range of ways VCC can rise
to its steady state, two conditions are required to ensure a valid power-up reset. These conditions
are:
◆The VCC rise must be monotonic.
◆Following reset, the clock input must not be driven from LOW to HIGH until all applicable input
and feedback setup times are met.
Parameter
Symbol Parameter Description Max Unit
tPR Power-up Reset Time 1000 ns
tSInput or Feedback Setup Time See Switching
Characteristics
tWL Clock Width LOW
tPR
tWL
tS
4 V VCC
Power
Registered
Active-Low
Output
Clock
Figure 3. Power-Up Reset Waveform
VCC Off
16564E-021
32 PALCE22V10 and PALCE22V10Z Families
TYPICAL THERMAL CHARACTERISTICS
PALCE22V10
Measured at 25°C ambient. These parameters are not tested.
Plastic θjc Considerations
The data listed for plastic
θ
jc ar e for refer ence only and are not r ecommended for use in calculating junction temperatur es. The
heat-flow paths in plastic-encapsulated devices are complex, making the
θ
jc measurement relative to a specific location on the pack-
age surface. Tests indicate this measurement reference point is directly below the die-attach area on the bottom center of the package.
Furthermore,
θ
jc tests on packages ar e performed in a constant-temperature bath, keeping the package surface at a constant tem-
perature. Therefore, the measurements can only be used in a similar environment.
Parameter
Symbol Parameter Description
Typ
UnitSKINNY DIP PLCC
θjc Thermal impedance, junction to case 20 18 °C/W
θja Thermal impedance, junction to ambient 73 55 °C/W
θjma Thermal impedance, junction to ambient with air flow
200 lfpm air 66 48 °C/W
400 lfpm air 61 43 °C/W
600 lfpm air 55 40 °C/W
800 lfpm air 52 37 °C/W
PALCE22V10 and PALCE22V10Z Families 33
CONNECTION DIAGRAMS
Top View
4
5
6
7
8
9
10
11
3 2 1 28 27 26
25
24
23
22
21
20
19
12 13 14 15 16 17 18
I3
I4
I5
NC
I6
I7
I8
I/O7
I/O6
I/O5
GND/NC *
I/O4
I/O3
I/O2
I9
I10
GND
NC
I11
I/O0
I/O1
I2
I1
CLK/I0
NC
VCC
I/O9
I/O8
SKINNYDIP/SOIC
PIN DESIGNATIONS
CLK = Clock
GND = Ground
I = Input
I/O = Input/Output
NC = No Connect
VCC = Supply Voltage
Note:
Pin 1 is marked for orientation.
PLCC
*For -5, this pin must be grounded for guaranteed data sheet performance. If not grounded, AC timing may degrade
by about 10%.
16564E-002 16564E-003
VCC
I1
I3
I5
I7
I9
GND
I/O9
I/O7
I/O5
I/O3
I/O1
I11
I/O8
I/O6
I/O4
I/O2
I/O0
CLK/I0
I2
I4
I6
I8
I10
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
34 PALCE22V10 and PALCE22V10Z Families
ORDERING INFORMATION
Commercial and Industrial Products
L
attice/Vantis programmable logic products for commercial and industrial applications are available with several ordering options.
T
he order number (Valid Combination) is formed by a combination of:
CE
TECHNOLOGY
CE = CMOS Electrically Erasable
Valid Combinations
PAL 22 V 10 -5 J C
FAMILY TYPE
PAL = Programmable Array Logic
NUMBER OF
ARRAY INPUTS
OUTPUT TYPE
V = Versatile
NUMBER OF OUTPUTS
SPEED
-5 = 5 ns tPD
-7 = 7.5 ns tPD
-10 = 10 ns tPD
-15 = 15 ns tPD
-20 = 20 ns tPD
-25 = 25 ns tPD
PACKAGE TYPE
P = 24-Pin 300 mil Plastic
SKINNYDIP (PD3024)
J = 28-Pin Plastic Leaded Chip
Carrier (PL 028)
S = 24-Pin Plastic Gull-Wing
Small Outline Package
(SO 024)
OPERATING CONDITIONS
C = Commercial (0°C to +75°C)
I = Industrial (-40 °C to +85°C)
H
POWER
Q = Quarter Power (90-140 mA ICC)
H = Half Power (90-140 mA ICC)
Z = Zero Power (30 µA ICC standby)
PROGRAMMING DESIGNATOR
Blank = Initial Algorithm
/4 = First Revision
/5 = Second Revision
(Same Algorithm as /4)
/5
Valid Combinations list configurations planned to be
supported in volume for this device. Consult the local
Lattice/Vantis sales office to confirm availability of
specific valid combinations and to check on newly
released combinations.
Valid Combinations
PALCE22V10H-5 JC
/5
PALCE22V10H-7 PC, JC
PALCE22V10H-10 PC, JC, SC, PI, JI
PALCE22V10Q-10 PC, JC
PALCE22V10H-15 PC, JC, PI, JI, SC /4
PALCE22V10Q-15 PC, JC /5
PALCE22V10H-20 PI, JI /4
PALCE22V10H-25 PC, JC, SC, PI, JI /4
PALCE22V10Q-25 PC, JC
PALCE22V10Z-15 PI, JI
PALCE22V10Z-25 PC, JC, SC, PI, JI, SI
