ICS9DB801C
IDTTM/ICSTM Eight Output Differential Buffer for PCI Express (50-200MHz) 9DB801C REV E 01/27/11
Eight Output Differential Buffer for PCI Express (50-200MHz)
DATASHEET
1
STOP
LOGIC
SRC_IN
SRC_IN#
DIF(7:0))
CONTROL
LOGIC
BYPASS#/PLL
S D ATA
SCLK
PD#
SPREAD
COMPATIBLE
PLL
8
IREF
OE_(7:0)
8
LOCK
SRC_STOP#
HIGH_BW#
M
U
X
Description
Output Features
The 9DB801C is a DB800 Version 2.0 Yellow Cover part with
PCI Express support. It can be used in PC or embedded
systems to provide outputs that have low cycle-to-cycle jitter
(50ps), low output-to-output skew (100ps), and are PCI Express
gen 1 compliant. The 9DB801C supports a 1 to 8 output
configuration, taking a spread or non spread differential HCSL
input from a CK410(B) main clock such as 954101 and
932S401, or any other differential HCSL pair. 9DB801C can
generate HCSL or LVDS outputs from 50 to 200MHz in PLL
mode or 0 to 400Mhz in bypass mode. There are two de-jittering
modes available selectable through the HIGH_BW# input pin,
high bandwidth mode provides de-jittering for spread inputs and
low bandwidth mode provides extra de-jittering for non-spread
inputs. The SRC_STOP#, PD#, and individual OE# real-time
input pins provide completely programmable power
management control.
• 8 - 0.7V current-mode differential output pairs
• Supports zero delay buffer mode and fanout mode
• Bandwidth programming available
Funtional Block Diagram
Key Specifications
• Outputs cycle-cycle jitter < 50ps
• Outputs skew: 50ps
• 50 - 200MHz operation
• Extended frequency range in bypass mode to 400 MHz
• PCI Express Gen I compliant
• Real time PLL lock detect output pin
• 48-pin SSOP/TSSOP package
• Available in RoHS compliant packaging
Features/Benefits
• Spread spectrum modulation tolerant, 0 to -0.5% down
spread and +/- 0.25% center spread.
• Supports undriven differential outputs in PD# and
SRC_STOP# modes for power management.
• Supports polarity inversion to the output enables,
SRC_STOP and PD.
Note: Polarities shown for OE_INV = 0.
IDTTM/ICSTM Eight Output Differential Buffer for PCI Express (50-200MHz) 9DB801C REV E 01/27/11
ICS9DB801C
Eight Output Differential Buffer for PCI Express (50-200MHz)
2
Pin Configuration
SRC_DIV# 1 48 VDDA
VDD 2 47 GNDA
GND 3 46 IREF
SRC_IN 4 45 LOCK
SRC_IN# 5 44 OE_7
OE_0 6 43 OE_4
OE_3 7 42 DIF_7
DIF_0 8 41 DIF_7#
DIF_0# 9 40 OE_INV
GND 10 39 VDD
VDD 11 38 DIF_6
DIF_112 37DIF_6#
DIF_1# 13 36 OE_6
OE_1 14 35 OE_5
OE_2 15 34 DIF_5
DIF_216 33DIF_5#
DIF_2# 17 32 GND
GND 18 31 VDD
VDD 19 30 DIF_4
DIF_320 29DIF_4#
DIF_3# 21 28 HIGH_BW#
BYPASS#/PLL 22 27 SRC_STOP#
SCLK 23 26 PD#
SDATA 24 25 GND
OE_INV = 0
ICS9DB801
(Same as ICS9DB108)
SRC_DIV# 1 48 VDDA
VDD 2 47 GNDA
GND 3 46 IREF
SRC_IN 4 45 LOCK
SRC_IN# 5 44 OE7#
OE0# 643
OE4#
OE3# 742DIF_7
DIF_0 8 41 DIF_7#
DIF_0# 9 40 OE_INV
GND 10 39 VDD
VDD 11 38 DIF_6
DIF_1 12 37 DIF_6#
DIF_1# 13 36 OE6#
OE1# 14 35 OE5#
OE2# 15 34 DIF_5
DIF_2 16 33 DIF_5#
DIF_2# 17 32 GND
GND 18 31 VDD
VDD 19 30 DIF_4
DIF_3 20 29 DIF_4#
DIF_3# 21 28 HIGH_BW#
BYPASS#/PLL 22 27 SRC_STOP
SCLK 23 26 PD
SDATA 24 25 GND
OE_INV = 1
ICS9DB801
01
6OE_0 OE0#
7OE_3 OE3#
14 OE_1 OE1#
15 OE_2 OE2#
26 PD# PD
27 DIF_STOP# DIF_STOP
35 OE_5 OE5#
36 OE_6 OE6#
43 OE_4 OE4#
44 OE_7 OE7#
Pins
OE_INV
Polarity Inversion Pin List Table
IDTTM/ICSTM Eight Output Differential Buffer for PCI Express (50-200MHz) 9DB801C REV E 01/27/11
ICS9DB801C
Eight Output Differential Buffer for PCI Express (50-200MHz)
3
Pin Description for OE_INV = 0
PIN # PIN NAME PIN TYPE DESCRIPTION
1 SRC_DIV# INPUT Active low Input for determining SRC output frequency SRC or SRC/2.
0 = SRC/2, 1= SRC
2 VDD POWER Power supply, nominal 3.3V
3 GND POWER Ground pin.
4 SRC_IN INPUT 0.7 V Differential SRC TRUE input
5 SRC_IN# INPUT 0.7 V Differential SRC COMPLEMENTARY input
6 OE_0 INPUT Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
7 OE_3 INPUT Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
8 DIF_0 OUTPUT 0.7V differential true clock outputs
9 DIF_0# OUTPUT 0.7V differential complement clock outputs
10 GND POWER Ground pin.
11 VDD POWER Power supply, nominal 3.3V
12 DIF_1 OUTPUT 0.7V differential true clock outputs
13 DIF_1# OUTPUT 0.7V differential complement clock outputs
14 OE_1 INPUT Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
15 OE_2 INPUT Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
16 DIF_2 OUTPUT 0.7V differential true clock outputs
17 DIF_2# OUTPUT 0.7V differential complement clock outputs
18 GND POWER Ground pin.
19 VDD POWER Power supply, nominal 3.3V
20 DIF_3 OUTPUT 0.7V differential true clock outputs
21 DIF_3# OUTPUT 0.7V differential complement clock outputs
22 BYPASS#/PLL INPUT Input to select Bypass(fan-out) or PLL (ZDB) mode
0 = Bypass mode, 1= PLL mode
23 SCLK INPUT Clock pin of SMBus circuitry, 5V tolerant.
24 SDATA I/O Data pin for SMBus circuitry, 5V tolerant.
IDTTM/ICSTM Eight Output Differential Buffer for PCI Express (50-200MHz) 9DB801C REV E 01/27/11
ICS9DB801C
Eight Output Differential Buffer for PCI Express (50-200MHz)
4
Pin Description for OE_INV = 0
PIN # PIN NAME PIN TYPE DESCRIPTION
25 GND POWER Ground pin.
26 PD# INPUT
Asynchronous active low input pin, with 120Kohm internal pull-
up resistor, used to power down the device. The internal clocks
are disabled and the VCO and the crystal are stopped.
27 SRC_STOP# INPUT Active low input to stop SRC outputs.
28 HIGH_BW# INPUT 3.3V input for selecting PLL Band Width
0 = High, 1= Low
29 DIF_4# OUTPUT 0.7V differential complement clock outputs
30 DIF_4 OUTPUT 0.7V differential true clock outputs
31 VDD POWER Power supply, nominal 3.3V
32 GND POWER Ground pin.
33 DIF_5# OUTPUT 0.7V differential complement clock outputs
34 DIF_5 OUTPUT 0.7V differential true clock outputs
35 OE_5 INPUT Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
36 OE_6 INPUT Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
37 DIF_6# OUTPUT 0.7V differential complement clock outputs
38 DIF_6 OUTPUT 0.7V differential true clock outputs
39 VDD POWER Power supply, nominal 3.3V
40 OE_INV INPUT This latched input selects the polarity of the OE pins.
0 = OE pins active high, 1 = OE pins active low (OE#)
41 DIF_7# OUTPUT 0.7V differential complement clock outputs
42 DIF_7 OUTPUT 0.7V differential true clock outputs
43 OE_4 INPUT Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
44 OE_7 INPUT Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
45 LOCK OUTPUT 3.3V output indicating PLL Lock Status. This pin goes high
when lock is achieved.
46 IREF INPUT
This pin establishes the reference current for the differential
current-mode output pairs. This pin requires a fixed precision
resistor tied to ground in order to establish the appropriate
current. 475 ohms is the standard value.
47 GNDA POWER Ground pin for the PLL core.
48 VDDA POWER 3.3V power for the PLL core.
IDTTM/ICSTM Eight Output Differential Buffer for PCI Express (50-200MHz) 9DB801C REV E 01/27/11
ICS9DB801C
Eight Output Differential Buffer for PCI Express (50-200MHz)
5
Pin Description for OE_INV = 1
PIN # PIN NAME PIN TYPE DESCRIPTION
1 SRC_DIV# INPUT
Active low Input for determining SRC output frequency SRC or
SRC/2.
0 = SRC/2, 1= SRC
2 VDD POWER Power supply, nominal 3.3V
3 GND POWER Ground pin.
4 SRC_IN INPUT 0.7 V Differential SRC TRUE input
5 SRC_IN# INPUT 0.7 V Differential SRC COMPLEMENTARY input
6 OE0# INPUT Active low input for enabling DIF pair 0.
1 = tri-state outputs, 0 = enable outputs
7 OE3# INPUT Active low input for enabling DIF pair 3.
1 = tri-state outputs, 0 = enable outputs
8 DIF_0 OUTPUT 0.7V differential true clock outputs
9 DIF_0# OUTPUT 0.7V differential complement clock outputs
10 GND POWER Ground pin.
11 VDD POWER Power supply, nominal 3.3V
12 DIF_1 OUTPUT 0.7V differential true clock outputs
13 DIF_1# OUTPUT 0.7V differential complement clock outputs
14 OE1# INPUT Active low input for enabling DIF pair 1.
1 = tri-state outputs, 0 = enable outputs
15 OE2# INPUT Active low input for enabling DIF pair 2.
1 = tri-state outputs, 0 = enable outputs
16 DIF_2 OUTPUT 0.7V differential true clock outputs
17 DIF_2# OUTPUT 0.7V differential complement clock outputs
18 GND POWER Ground pin.
19 VDD POWER Power supply, nominal 3.3V
20 DIF_3 OUTPUT 0.7V differential true clock outputs
21 DIF_3# OUTPUT 0.7V differential complement clock outputs
22 BYPASS#/PLL INPUT Input to select Bypass(fan-out) or PLL (ZDB) mode
0 = Bypass mode, 1= PLL mode
23 SCLK INPUT Clock pin of SMBus circuitry, 5V tolerant.
24 SDATA I/O Data pin for SMBus circuitry, 5V tolerant.
IDTTM/ICSTM Eight Output Differential Buffer for PCI Express (50-200MHz) 9DB801C REV E 01/27/11
ICS9DB801C
Eight Output Differential Buffer for PCI Express (50-200MHz)
6
Pin Description for OE_INV = 1
PIN # PIN NAME PIN TYPE DESCRIPTION
25 GND PWR Ground pin.
26 PD IN
Asynchronous active high input pin used to power down the
device. The internal clocks are disabled and the VCO is
stopped.
27 SRC_STOP IN Active high input to stop SRC outputs.
28 HIGH_BW# IN 3.3V input for selecting PLL Band Width
0 = High, 1= Low
29 DIF_4# OUT 0.7V differential complement clock outputs
30 DIF_4 OUT 0.7V differential true clock outputs
31 VDD PWR Power supply, nominal 3.3V
32 GND PWR Ground pin.
33 DIF_5# OUT 0.7V differential complement clock outputs
34 DIF_5 OUT 0.7V differential true clock outputs
35 OE5# IN Active low input for enabling DIF pair 5.
1 = tri-state outputs, 0 = enable outputs
36 OE6# IN Active low input for enabling DIF pair 6.
1 = tri-state outputs, 0 = enable outputs
37 DIF_6# OUT 0.7V differential complement clock outputs
38 DIF_6 OUT 0.7V differential true clock outputs
39 VDD PWR Power supply, nominal 3.3V
40 OE_INV IN This latched input selects the polarity of the OE pins.
0 = OE pins active high, 1 = OE pins active low (OE#)
41 DIF_7# OUT 0.7V differential complement clock outputs
42 DIF_7 OUT 0.7V differential true clock outputs
43 OE4# IN Active low input for enabling DIF pair 4
1 = tri-state outputs, 0 = enable outputs
44 OE7# IN Active low input for enabling DIF pair 7.
1 = tri-state outputs, 0 = enable outputs
45 LOCK OUT 3.3V output indicating PLL Lock Status. This pin goes high
when lock is achieved.
46 IREF IN
This pin establishes the reference current for the differential
current-mode output pairs. This pin requires a fixed precision
resistor tied to ground in order to establish the appropriate
current. 475 ohms is the standard value.
47 GNDA PWR Ground pin for the PLL core.
48 VDDA PWR 3.3V power for the PLL core.
IDTTM/ICSTM Eight Output Differential Buffer for PCI Express (50-200MHz) 9DB801C REV E 01/27/11
ICS9DB801C
Eight Output Differential Buffer for PCI Express (50-200MHz)
7
Symbol Parameter Min Max Units
VDD_A 3.3V Core Supply Voltage 4.6 V
VDD_In 3.3V Logic Supply Voltage 4.6 V
VIL Input Low Voltage GND-0.5 V
VIH Input High Voltage VDD+0.5V V
Ts Storage Temperature -65 150 °C
Tambient Ambient Operating Temp 0 70 °C
Tcase Case Temperature 115 °C
ESD prot
Input ESD protection
human body model 2000 V
Absolute Max
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Input High Voltage VIH 3.3 V +/-5% 2 VDD + 0.3 V
Input Low Voltage VIL 3.3 V +/-5% GND - 0.3 0.8 V
Input High Current IIH VIN = VDD -5 5 uA
IIL1
VIN = 0 V; Inputs with no pull-
up resistors -5 uA
IIL2
VIN = 0 V; Inputs with pull-up
resistors -200 uA
IDD3.3PLL 175 200 mA
IDD3.3B
y
Pass 160 175 mA
all diff pairs driven 50 70 mA
all differential pairs tri-stated 1 4 mA
Input Frequency FiPLL PLL Mode 50 200 MHz
Input Frequency FiBypass
Bypass Mode (Revision
B/REV ID = 1H) 0 333.33 MHz
Input Frequency FiBypass
Bypass Mode (Revision
C/REV ID = 2H) 0400MHz
Pin Inductance1Lpin 7nH1
CIN Logic Inputs 1.5 4 pF 1
COUT Output pin capacitance 4 pF 1
PLL Bandwidth when
PLL_BW=0 2.4 3 3.4 MHz 1
PLL Bandwidth when
PLL_BW=1 0.7 1 1.4 MHz 1
Clk Stabilization1,2 TSTAB
From VDD Power-Up and after
input clock stabilization or de-
assertion of PD# to 1st clock
0.5 1 ms 1,2
Modulation Frequency fMOD Triangular Modulation 30 33 kHz 1
Tdrive_SRC_STOP# DIF output enable after
SRC_Stop# de-assertion 10 15 ns 1,3
Tdrive_PD# DIF output enable after
PD# de-assertion 300 us 1,3
Tfall Fall time of PD# and
SRC_STOP# 5ns1
Trise Rise time of PD# and
SRC_STOP# 5ns2
1Guaranteed by design and characterization, not 100% tested in production.
2See timing diagrams for timing requirements.
IDD3.3PD
3Time from deassertion until out
p
uts are >200 mV
Input Capacitance1
Input Low Current
Powerdown Current
PLL Bandwidth BW
Full Active, CL = Full load; Operating Supply Current
IDTTM/ICSTM Eight Output Differential Buffer for PCI Express (50-200MHz) 9DB801C REV E 01/27/11
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Eight Output Differential Buffer for PCI Express (50-200MHz)
8
Electrical Characteristics - DIF 0.7V Current Mode Differential Pair
T
A
= 0 - 70°C; V
DD
= 3.3 V +/-5%; C
L
=2pF, R
S
=33.2Ω, R
P
=49.9Ω, Ι
REF
= 475Ω
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Current Source Output
Im
p
edance Zo
1
V
O
= V
x
3000 Ω1
Voltage High VHigh 660 850 1,3
Voltage Low VLow -150 150 1,3
Max Volta
g
e Vovs 1150 1
Min Volta
g
e Vuds -300 1
Crossin
g
Volta
g
e
(
abs
)
Vcross
(
abs
)
250 550 mV 1
Crossing Voltage (var) d-Vcross Variation of crossing over all
ed
g
es 140 mV 1
Lon
g
Accurac
y
pp
m see T
p
eriod min-max values 0
pp
m1,2
Rise Time t
r
V
OL
= 0.175V, V
OH
= 0.525V 175 700 ps 1
Fall Time t
f
V
OH
= 0.525V V
OL
= 0.175V 175 700 ps 1
Rise Time Variation d-t
r
125 ps 1
Fall Time Variation d-t
f
125 ps 1
Duty Cycle d
t3
Measurement from differential
wavefrom 45 55 % 1
Skew t
sk3
V
T
= 50% 50 ps 1
PLL mode,
Measurement from differential
wavefrom
50 ps 1
BYPASS mode as additive
j
itter 50
p
s1
1
Guaranteed b
y
desi
g
n and characterization, not 100% tested in
p
roduction.
3
I
REF
= V
DD
/(3xR
R
). For R
R
= 475Ω (1%), I
REF
= 2.32mA. I
OH
= 6 x I
REF
and V
OH
= 0.7V @ Z
O
=50Ω.
Statistical measurement on single
ended signal using oscilloscope
math function.
mV
Measurement on single ended
signal using absolute value. mV
2
All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that the input clock
complies with CK409/CK410 accuracy requirements
Jitter, Cycle to cycle t
jcyc-cyc
Electrical Characteristics - Clock Input Parameters
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER SYMBOL CONDITIONS MIN MAX UNITS NOTES
Differential Input High Voltage VIHDIF
Differential inputs
(single-ended measurement) 600 1150 mV 1
Differential Input Low Voltage VILDIF
Differential inputs
(single-ended measurement) VSS - 300 300 mV 1
Input Slew Rate - DIF_IN dv/dt Measured differentially 0.4 8 V/ns 2
Input Leakage Current IIN VIN = VDD , VIN = GND -5 5 uA 1
Input Duty Cycle dtin
Measurement from differential
wavefrom 45 55 % 1
Input SRC Jitter - Cycle to
Cycle SRCJC2CIn Differential Measurement 125 ps 1
1 Guaranteed by design and characterization, not 100% tested in production.
2Slew rate measured through Vswing centered around differential zero
IDTTM/ICSTM Eight Output Differential Buffer for PCI Express (50-200MHz) 9DB801C REV E 01/27/11
ICS9DB801C
Eight Output Differential Buffer for PCI Express (50-200MHz)
9
Comm on Recom mendat i ons for Differential Rout i ng Dim ension or Val ue Unit Fi gure
L1 l ength, route as non-c oupl ed 50ohm trac e 0. 5 max inch 1
L2 l ength, route as non-c oupl ed 50ohm trac e 0. 2 max inch 1
L3 l ength, route as non-c oupl ed 50ohm trac e 0. 2 max inch 1
Rs 33 ohm 1
Rt 49.9 ohm 1
Down Devi ce Di ffere nti al Rou t i ng
L4 l ength, route as coupl ed m i crostri p 100ohm differential trace 2 m in to 16 m ax i nch 1
L4 l ength, route as coupl ed stripl i ne 100ohm di fferenti al trac e 1. 8 min to 14. 4 m ax inch 1
Different i al Rout i ng to P CI Express Connec tor
L4 l ength, route as coupl ed m i crostri p 100ohm differential trace 0.25 to 14 max inch 2
L4 lengt h, rout e as c oupled s t ri pline 100ohm different ial t rac e 0.225 mi n t o 12.6 m ax inch 2
S RC Ref eren ce Cl o c k
HCSL Output Buff er
L1
L1' Rs
L2
L2'
Rs
L4'
L4
L3L3'
Rt Rt PCI Express
Down Dev ice
REF_CLK Input
Figure 1: Down Dev ice Routing
HCSL Output Buffer
L1
L1' Rs
L2
L2'
Rs
L4'
L4
L3L3'
Rt Rt PCI Express
Add-in Boar d
REF_CLK Input
Figure 2: PCI Express Connector Routing
IDTTM/ICSTM Eight Output Differential Buffer for PCI Express (50-200MHz) 9DB801C REV E 01/27/11
ICS9DB801C
Eight Output Differential Buffer for PCI Express (50-200MHz)
10
Vdiff Vp-p Vcm R1 R2 R3 R4 Note
0.45v 0.22v 1.08 33 150 100 100
0.58 0.28 0.6 33 78.7 137 100
0.80 0.40 0. 6 33 78.7 none 100 ICS874003i -02 i nput compat i bl e
0.60 0.3 1.2 33 174 140 100 St andard LV D S
R1a = R1b = R1
R2a = R2b = R2
Alterna tive Termi nation for LVDS and other Common Di ffe rential Signals (figure 3)
HCSL Output Buff er
L1
L1' R1b
L2
L2'
R1a
L4'
L4
L3
R2a R2b Down Dev ice
REF_CLK Input
Figure 3
L3'
R3 R4
Component Value Note
R5a, R5b 8.2K 5%
R6a, R6b 1K 5%
Cc 0. 1 µF
Vcm 0.350 volts
Ca ble Conne cted AC Couple d Appli ca ti on (fi gure 4)
PC I e De vice
REF_CLK Input
Figure 4
R5a
L4'
L4
3.3 Vol ts
R5b
R6a R6b
Cc
Cc
IDTTM/ICSTM Eight Output Differential Buffer for PCI Express (50-200MHz) 9DB801C REV E 01/27/11
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Eight Output Differential Buffer for PCI Express (50-200MHz)
11
General SMBus serial interface information for the ICS9DB801C
How to Write:
•Controller (host) sends a start bit.
• Controller (host) sends the write address DC (h)
• ICS clock will
acknowledge
• Controller (host) sends the begining byte location = N
• ICS clock will
acknowledge
• Controller (host) sends the data byte count = X
• ICS clock will
acknowledge
• Controller (host) starts sending
Byte N through
Byte N + X -1
• ICS clock will
acknowledge
each byte
one at a time
• Controller (host) sends a Stop bit
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the write address DC (h)
• ICS clock will
acknowledge
• Controller (host) sends the begining byte
location = N
• ICS clock will
acknowledge
• Controller (host) will send a separate start bit.
• Controller (host) sends the read address DD (h)
• ICS clock will
acknowledge
• ICS clock will send the data byte count = X
• ICS clock sends
Byte N + X -1
• ICS clock sends
Byte 0 through byte X (if X
(h)
was written to byte 8)
.
• Controller (host) will need to acknowledge each byte
• Controllor (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
ICS (Slave /Receiver)
T
WR ACK
ACK
ACK
ACK
ACK
PstoP bit
X Byte
Index Block Writ e O peration
S l ave Address DC(h)
B eginni ng B yte = N
WRite
s tarT bit
Control l er (Host)
Byte N + X - 1
Dat a Byt e Count = X
B egi nning B yte N
T starT bit
WR WRite
RT Repeat starT
RD ReaD
B egi nni ng Byte N
Byte N + X - 1
N Not ack nowl edge
PstoP bit
S l ave Address DD(h)
Index Block Read O peration
S l ave Address DC(h)
B eginni ng B yte = N ACK
ACK
Data By te Count = X
ACK
ICS (Slave/Re ce iver)
Control l er (Host)
X Byte
ACK
ACK
IDTTM/ICSTM Eight Output Differential Buffer for PCI Express (50-200MHz) 9DB801C REV E 01/27/11
ICS9DB801C
Eight Output Differential Buffer for PCI Express (50-200MHz)
12
SMBus Table: Frequency Select Register, READ/WRITE ADDRESS (DC/DD)
Pin # Name Control Function T
yp
e0 1PWD
Bit
7
PD_Mode PD# drive mode RW driven Hi-Z 0
Bit
6
STOP_Mode SRC_Stop# drive mode RW driven Hi-Z 0
Bit
5
Reserved Reserved RW X
Bit
4
Reserved Reserved RW X
Bit
3
Reserved Reserved RW X
Bit 2 PLL_BW# Select PLL BW RW High BW Low BW 1
Bit 1 BYPASS# BYPASS#/PLL RW fan-out ZDB 1
Bit 0 SRC_DIV# SRC Divide by 2 Select RW x/2 1x 1
SMBus Table: Output Control Register
Pin # Name Control Function T
yp
e0 1PWD
Bit
7
DIF_7 Output Control RW Disable Enable 1
Bit
6
DIF_6 Output Control RW Disable Enable 1
Bit
5
DIF_5 Output Control RW Disable Enable 1
Bit
4
DIF_4 Output Control RW Disable Enable 1
Bit
3
DIF_3 Output Control RW Disable Enable 1
Bit 2 DIF_2 Output Control RW Disable Enable 1
Bit 1 DIF_1 Output Control RW Disable Enable 1
Bit 0 DIF_0 Output Control RW Disable Enable 1
SMBus Table: Output Control Register
Pin # Name Control Function T
yp
e0 1PWD
Bit
7
DIF_7 Output Control RW Free-run Stoppable 0
Bit
6
DIF_6 Output Control RW Free-run Stoppable 0
Bit
5
DIF_5 Output Control RW Free-run Stoppable 0
Bit
4
DIF_4 Output Control RW Free-run Stoppable 0
Bit
3
DIF_3 Output Control RW Free-run Stoppable 0
Bit 2 DIF_2 Output Control RW Free-run Stoppable 0
Bit 1 DIF_1 Output Control RW Free-run Stoppable 0
Bit 0 DIF_0 Output Control RW Free-run Stoppable 0
SMBus Table: Output Control Register
Pin # Name Control Function T
yp
e0 1PWD
Bit
7
RW X
Bit
6
RW X
Bit
5
RW X
Bit
4
RW X
Bit
3
RW X
Bit 2 RW X
Bit 1 RW X
Bit 0 RW X
Reserved
Reserved Reserved
Reserved Reserved
Reserved Reserved
Reserved Reserved
Reserved Reserved
Reserved Reserved
Reserved Reserved
12,13
8,9
B
y
te 3
Reserved Reserved
34,33
30,29
20,21
16,17
8,9
B
y
te 2
42,41
38,37
30,29
20,21
16,17
12,13
B
y
te 0
-
-
-
-
-
-
-Reserved
-
Reserved
B
y
te 1
42,41
38,37
34,33
IDTTM/ICSTM Eight Output Differential Buffer for PCI Express (50-200MHz) 9DB801C REV E 01/27/11
ICS9DB801C
Eight Output Differential Buffer for PCI Express (50-200MHz)
13
SMBus Table: Vendor & Revision ID Register
Pin # Name Control Function T
yp
e0 1PWD
Bit
7
RID3 R - - X
Bit
6
RID2 R - - X
Bit 5 RID1 R - - X
Bit
4
RID0 R - - X
Bit 3 VID3 R - - 0
Bit 2 VID2 R - - 0
Bit 1 VID1 R - - 0
Bit 0 VID0 R - - 1
SMBus Table: DEVICE ID
Pin # Name Control Function T
yp
e0 1PWD
Bit
7
R1
Bit
6
R0
Bit 5 R0
Bit
4
R0
Bit 3 R0
Bit 2 R0
Bit 1 R0
Bit 0 R1
SMBus Table: Byte Count Register
Pin # Name Control Function T
yp
e0 1PWD
Bit
7
BC7 RW - - 0
Bit
6
BC6 RW - - 0
Bit 5 BC5 RW - - 0
Bit
4
BC4 RW - - 0
Bit 3 BC3 RW - - 0
Bit 2 BC2 RW - - 1
Bit 1 BC1 RW - - 1
Bit 0 BC0 RW - - 1
Device ID 3 Reserved
Device ID 0 Reserved
Device ID 2 Reserved
Device ID 1 Reserved
Device ID 5
Device ID 7 (MSB) Reserved
Reserved
Device ID 4 Reserved
Device ID 6 Reserved
B
y
te 6
-
Writing to this register
configures how many bytes
will be read back.
-
-
-
-
-
-
-
B
y
te 5
-
-
-
-
-
VENDOR ID
-
-
-
-
-
-
-
B
y
te 4
-
REVISION ID
-
-
-
IDTTM/ICSTM Eight Output Differential Buffer for PCI Express (50-200MHz) 9DB801C REV E 01/27/11
ICS9DB801C
Eight Output Differential Buffer for PCI Express (50-200MHz)
14
The PD# pin cleanly shuts off all clocks and places the device into a power saving mode. PD# must be asserted before shutting
off the input clock or power to insure an orderly shutdown. PD is asynchronous active-low input for both powering down the
device and powering up the device. When PD# is asserted, all clocks will be driven high, or tri-stated (depending on the PD#
drive mode and Output control bits) before the PLL is shut down.
PD#, Power Down
When PD# is sampled low by two consecutive rising edges of DIF#, all DIF outputs must be held High, or tri-stated (depending
on the PD# drive mode and Output control bits) on the next High-Low transition of the DIF# outputs. When the PD# drive mode
bit is set to ‘0’, all clock outputs will be held with DIF driven High with 2 x IREF and DIF# tri-stated. If the PD# drive mode bit is
set to ‘1’, both DIF and DIF# are tri-stated.
PD# Assertion
Power-up latency is less than 1 ms. This is the time from de-assertion of the PD# pin, or VDD reaching 3.3V, or the time from
valid SRC_IN clocks until the time that stable clocks are output from the device (PLL Locked). If the PD# drive mode bit is set
to ‘1’, all the DIF outputs must driven to a voltage of >200 mV within 300 us of PD# de-assertion.
PD# De-assertion
PWRDWN#
DIF
DIF#
PWRDWN#
DIF
DIF#
Tstable
<1mS
Tdrive_PwrDwn#
<300uS, >200mV
Note: Polarities in timing diagrams are shown OE_INV = 0. They are similar to OE_INV = 1.
IDTTM/ICSTM Eight Output Differential Buffer for PCI Express (50-200MHz) 9DB801C REV E 01/27/11
ICS9DB801C
Eight Output Differential Buffer for PCI Express (50-200MHz)
15
Asserting SRC_STOP# causes all DIF outputs to stop after their next transition (if the control register settings allow the output
to stop). When the SRC_STOP# drive bit is ‘0’, the final state of all stopped DIF outputs is DIF = High and DIF# = Low. There
is no change in output drive current. DIF is driven with 6xIREF. DIF# is not driven, but pulled low by the termination. When the
SRC_STOP# drive bit is ‘1’, the final state of all DIF output pins is Low. Both DIF and DIF# are not driven.
SRC_STOP# - Assertion
All stopped differential outputs resume normal operation in a glitch-free manner. The de-assertion latency to active outputs is
2-6 DIF clock periods, with all DIF outputs resuming simultaneously. If the SRC_STOP# drive control bit is ‘1’ (tri-state), all
stopped DIF outputs must be driven High (>200 mV) within 10 ns of de-assertion.
SRC_STOP# - De-assertion (transition from '0' to '1')
The SRC_STOP# signal is an active-low asynchronous input that cleanly stops and starts the DIF outputs. A valid clock must
be present on SRC_IN for this input to work properly. The SRC_STOP# signal is de-bounced and must remain stable for two
consecutive rising edges of DIF# to be recognized as a valid assertion or de-assertion.
SRC_STOP#
PWRDWN#
SRC_Stop#
DIF (Free Running)
DIF# (Free Running)
DIF (Stoppable)
DIF# (Stoppable)
1mS
PWRDWN#
SRC_Stop#
DIF (Free Running)
DIF# (Free Running)
DIF (Stoppable)
DIF# (Stoppable)
1mS
SRC_STOP_1 (SRC_Stop = Driven, PD = Driven)
SRC_STOP_2 (SRC_Stop =Tristate, PD = Driven)
IDTTM/ICSTM Eight Output Differential Buffer for PCI Express (50-200MHz) 9DB801C REV E 01/27/11
ICS9DB801C
Eight Output Differential Buffer for PCI Express (50-200MHz)
16
PWRDWN#
SRC_Stop#
DIF (Free Running)
DIF# (Free Running)
DIF (Stoppable)
DIF# (Stoppable)
1mS
PWRDWN#
SRC_Stop#
DIF (Free Running)
DIF# (Free Running)
DIF (Stoppable)
DIF# (Stoppable)
1mS
SRC_STOP_4 (SRC_Stop = Tristate, PD = Tristate)
SRC_STOP_3 (SRC_Stop = Driven, PD = Tristate)
IDTTM/ICSTM Eight Output Differential Buffer for PCI Express (50-200MHz) 9DB801C REV E 01/27/11
ICS9DB801C
Eight Output Differential Buffer for PCI Express (50-200MHz)
17
INDEX
AREA
INDEX
AREA
1 2
N
D
h x 45°
E1 E
α
SEATING
PLANE
SEATING
PLANE
A1
A
e
- C -
b
.10 (.004) C
.10 (.004) C
c
L
MIN MAX MIN MAX
A 2.41 2.80 .095 .110
A1 0.20 0.40 .008 .016
b 0.20 0.34 .008 .0135
c 0.13 0.25 .005 .010
D
E 10.03 10.68 .395 .420
E1 7.40 7.60 .291 .299
e
h 0.38 0.64 .015 .025
L 0.50 1.02 .020 .040
N
α0° 8° 0° 8°
MIN MAX MIN MAX
48 15.75 16.00 .620 .630
10-0034
SYMBOL
In Millimeters In Inches
COMMON DIMENSIONS COMMON DIMENSIONS
SEE VARIATIONS SEE VARIATIONS
0.635 BASIC 0.025 BASIC
Reference Doc.: JEDEC Publication 95, MO-118
VARIATIONS
SEE VARIATIONS SEE VARIATIONS
ND mm. D (inch)
Ordering Information
9DB801CFLFT
Example:
Designation for tape and reel packaging
Lead Free, RoHS Compliant
Package Type
F = SSOP
Revision Designator
Device Type
XXXX C F LF T
IDTTM/ICSTM Eight Output Differential Buffer for PCI Express (50-200MHz) 9DB801C REV E 01/27/11
ICS9DB801C
Eight Output Differential Buffer for PCI Express (50-200MHz)
18
INDEX
AREA
INDEX
AREA
12
1 2
N
D
E1 E
a
SEATING
PLANE
SEATING
PLANE
A1
A
A2
e
-C-
- C -
b
c
L
aaa
C
MIN MAX MIN MAX
A -- 1.20 -- .047
A1 0.05 0.15 .002 .006
A2 0.80 1.05 .032 .041
b 0.17 0.27 .007 .011
c 0.09 0.20 .0035 .008
D
E
E1 6.00 6.20 .236 .244
e
L 0.45 0.75 .018 .030
N
a 0°8°0°8°
aaa -- 0.10 -- .004
VARIATIONS
MIN MAX MIN MAX
48 12.40 12.60 .488 .496
10-0039
Reference Doc.: JEDEC Publication 95, MO-153
In Millimeters In Inches
COMMON DIMENSIONS
0.50 BASIC 0.020 BASIC
8.10 BASIC 0.319 BASIC
ND (inch)
SEE VARIATIONS SEE VARIATIONS
D mm.
48-Lead, 6.10 mm. Body, 0.50 mm. Pitch TSSOP
(240 mil) (20 mil)
SYMBOL
SEE VARIATIONS
COMMON DIMENSIONS
SEE VARIATIONS
Ordering Information
9DB801CGLFT
Example:
Designation for tape and reel packaging
Lead Free, RoHS Compliant
Package Type
G = TSSOP
Revision Designator
Device Type
XXXX C G LF T
ICS9DB801C
Eight Output Differential Buffer for PCI Express (50-200MHz)
19
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www.IDT.com
For Sales
800-345-7015
408-284-8200
Fax: 408-284-2775
For Tech Support
408-284-6578
pcclockhelp@idt.com
Corporate Headquarters
Integrated Device Technology, Inc.
6024 Silver Creek V alley Road
San Jose, CA 95138
United S tates
800 345 7015
+408 284 8200 (outside U.S.)
Asia Pacific and Jap an
Integrated Device Technology
Singapore (1997) Pte. Ltd.
Reg. No. 199707558G
435 Orchard Road
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Singapore 238877
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Europe
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Prime House
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Leatherhead, Surrey
United Kingdom KT22 7DE
+44 1372 363 339
© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated
Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks
or registered trademarks used to identify products or services of their respective owners.
Printed in USA
TM
Revision History
Rev. Issue Date Description Page #
A 4/8/2005 Release to Final
B 9/7/2006
1. Added Polarity Table.
2. Updated Electrical Characteristics.
3. Updated LF Ordering Information from "Annealed Lead Free" to
"RoHS Com
p
liant".
1, 7,
16-17
C 2/29/2008 Added Input Clock Specs 8
D 12/3/2008 Removed ICS prefix from ordering information. 17-18
E 1/27/2011 Updated terminaton Figure 4. 10
