RT7272B
12 DS7272B-07 February 2018www.richtek.com
Copyright 2018 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
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Figure 7. Derating Curve of Maximum Power Dissipation
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
0 25 50 75 100 125
Ambient Tem pera ture (°C)
Power Dissi pation (W )
Copper Area
70mm2
50mm2
30mm2
10mm2
Min.Layout
Four-Layer PCB
The output ripple will be the highest at the maximum input
voltage since ∆IL increases with input voltage. Multiple
capa citors pla ced in parallel may be needed to meet the
ESR and RMS current handling requirement. Higher values,
lower cost cera mic capacitors are now becoming available
in smaller case sizes. Their high ripple current, high voltage
rating and low ESR make them ideal for switching regulator
applications. However, care must be taken when these
ca pa citors are used at input a nd output. When a ceramic
capacitor is used at the input and the power is supplied
by a wall adapter through long wires, a load step at the
output can induce ringing at the input, VIN. At best, this
ringing ca n couple to the output and be mista ken a s loop
instability. At worst, a sudden inrush of current through
the long wires can potentially cause a voltage spike at
VIN large enough to da mage the part.
Thermal Considerations
For continuous operation, do not exceed the maximum
operation junction temperature 125°C. The maximum
power dissipation depends on the thermal resistance of
IC pa ckage, PCB layout, the rate of surroundings airflow
and temperature difference between junction to a mbient.
The maximum power dissipation can be calculated by
following formula :
PD(MAX) = (TJ(MAX) − TA ) / θJA
Where TJ(MAX) is the maximum operation junction
temperature , TA is the a mbient temperature and the θJA is
the junction to ambient thermal resistance.
For recommended operating conditions specification of
RT7272B, the maximum junction temperature is 125°C.
The junction to ambient thermal resistance θJA is layout
dependent. For SOP-8 (Exposed Pad) package, the
thermal resistance θJA is 75°C/W on the standard JEDEC
51-7 four-layers thermal test board. The maximum power
dissipation at TA = 25°C can be calculated by following
formula :
PD(MAX) = (125°C − 25°C) / (75°C/W) = 1.333W
(min.copper area PCB layout)
PD(MAX) = (125°C − 25°C) / (49°C/W) = 2.04W
(70mm2copper area PCB layout)
The thermal resistance θJA of SOP-8 (Exposed Pad) is
determined by the package architecture design and the
PCB layout design. However, the package architecture
design had been designed. If possible, it's useful to
increa se thermal perf ormance by the PCB layout copper
design. The thermal resistance θJA c a n be decre ased by
adding copper area under the exposed pad of SOP-8
(Exposed Pad) pa ckage.
As shown in Figure 6, the a mount of copper area to which
the SOP-8 (Exposed Pad) is mounted affects thermal
performance. When mounted to the standard
SOP-8 (Exposed Pad) pad (Figure 6.a), θJA is 75°C/W.
Adding copper area of pad under the SOP-8 (Exposed
Pad) (Figure 6.b) reduces the θJA to 64°C/W . Even further,
increasing the copper area of pad to 70mm2 (Figure 6.e)
reduces the θJA to 49°C/W.
The maximum power dissipation depends on operating
ambient temperature for fixed TJ(MAX) and thermal
resistance θJA. The Figure 7 of derating curves allows the
designer to see the ef fect of rising ambient temperature
on the maximum power dissipation allowed.