Data Sheet 26180.120 6273 8-BIT LATCHED DMOS POWER DRIVER 20 LOGIC SUPPLY 2 19 IN 8 IN 2 3 18 IN 7 OUT 1 4 17 OUT 8 OUT 2 5 16 OUT 7 OUT 3 6 15 OUT 6 OUT 4 7 14 OUT 5 IN 3 8 13 IN 6 IN 4 9 12 IN 5 GROUND 10 11 STROBE IN 1 VDD LATCHES 1 LATCHES CLEAR The A6273KA and A6273KLW combine eight (positive-edgetriggered D-type) data latches and DMOS outputs for systems requiring relatively high load power. Driver applications include relays, solenoids, and other medium-current or high-voltage peripheral power loads. The CMOS inputs and latches allow direct interfacing with microprocessor-based systems. Use with TTL may require appropriate pull-up resistors to ensure an input logic high. The DMOS output inverts the DATA input. All of the output drivers are disabled (the DMOS sink drivers turned OFF) with the CLEAR input low. The A6273KA/KLW DMOS open-drain outputs are capable of sinking up to 750 mA. Note that the A6273KA (DIP) and the A6273KLW (SOIC) are electrically identical and share a common terminal number assignment. The A6273KA is furnished in a 20-pin dual in-line plastic package. The A6273KLW is furnished in a 20-lead wide-body, small-outline plastic package (SOIC) with gull-wing leads for surface-mount applications. Copper lead frames, reduced supply current requirements, and low on-state resistance allow both devices to sink 150 mA from all outputs continuously, to ambient temperatures over 85C. ABSOLUTE MAXIMUM RATINGS at TA = 25C FEATURES Dwg. PP-015-2A Output Voltage, VO ............................. 50 V Output Drain Current, Continuous, IO ....................... 250 mA* Peak, IOM .............................. 750 mA* Peak, IOM ..................................... 2.0 A Single-Pulse Avalanche Energy, EAS .............................................. 75 mJ Logic Supply Voltage, VDD ................ 7.0 V Input Voltage Range, VI ................................. -0.3 V to +7.0 V Package Power Dissipation, PD ........................................ See Graph Operating Temperature Range, TA .............................. -40C to +125C Storage Temperature Range, TS .............................. -55C to +150C 50 V Minimum Output Clamp Voltage 250 mA Output Current (all outputs simultaneously) 1.3 Typical rDS(on) Low Power Consumption Replacements for TPIC6273N and TPIC6273DW * Each output, all outputs on. Pulse duration 100 s, duty cycle 2%. Caution: These CMOS devices have input static protection (Class 3) but are still susceptible to damage if exposed to extremely high static electrical charges. Always order by complete part number: Part Number Package A6273KA 20-pin DIP A6273KLW 20-lead SOIC RJA 55C/W 70C/W RJC 25C/W 17C/W 6273 8-BIT LATCHED DMOS POWER DRIVER ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS LOGIC SYMBOL 2.5 1 R 11 2.0 SU FF IX 1.5 'A ', R J A = SU FF IX 'LW ', R 1.0 55 C /W JA = 90 C /W 0.5 0 50 75 100 125 AMBIENT TEMPERATURE IN C 25 C1 2 1D 4 3 1D 5 8 1D 6 9 1D 7 12 1D 14 13 1D 15 18 1D 16 19 1D 17 150 Dwg. FP-046-1A Dwg. GS-004B VDD IN OUT Dwg. EP-010-16 Dwg. EP-063 LOGIC INPUTS DMOS POWER DRIVER OUTPUT FUNCTION TABLE CLEAR L H H H Inputs STROBE X L INX OUTX X H L X H L H R L = Low Logic Level H = High Logic Level X = Irrelevant R = Previous State 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 Copyright (c) 2002 Allegro MicroSystems, Inc. 6273 8-BIT LATCHED DMOS POWER DRIVER FUNCTIONAL BLOCK DIAGRAM IN 1 D OUT 1 C1 STROBE CLR IN2 LOGIC SUPPLY IN 3 D OUT 2 C1 V DD CLR D OUT 3 C1 CLR IN 4 D OUT 4 C1 CLR IN5 D OUT 5 C1 CLR IN6 D OUT 6 C1 CLR IN 7 D OUT 7 C1 CLR IN8 D OUT 8 C1 CLEAR CLR GROUND (ACTIVE LOW) Dwg. FP-016-2 www.allegromicro.com 6273 8-BIT LATCHED DMOS POWER DRIVER RECOMMENDED OPERATING CONDITIONS over operating temperature range Logic Supply Voltage Range, VDD ............... 4.5 V to 5.5 V High-Level Input Voltage, VIH ............................ 0.85VDD Low-level input voltage, VIL ................................. 0.15VDD ELECTRICAL CHARACTERISTICS at TA = +25C, VDD = 5 V, tir = tif 10 ns (unless otherwise specified). Limits Characteristic Logic Supply Voltage Symbol Test Conditions Min. Typ. Max. Units VDD Operating 4.5 5.0 5.5 V V(BR)DSX IO = 1 mA 50 -- -- V IDSX VO = 40 V -- 0.05 1.0 A VO = 40 V TA = 125C -- 0.15 5.0 A IO = 250 mA, VDD = 4.5 V -- 1.3 2.0 IO = 250 mA, VDD = 4.5 V, TA = 125C -- 2.0 3.2 IO = 500 mA, VDD = 4.5 V (see note) -- 1.3 2.0 VDS(on) = 0.5 V, TA = 85C -- 250 -- mA IIH VI = VDD = 5.5 V -- -- 1.0 A IIL VI = 0, VDD = 5.5 V -- -- -1.0 A tPLH IO = 250 mA, CL = 30 pF -- 625 -- ns tPHL IO = 250 mA, CL = 30 pF -- 150 -- ns Output Rise Time tr IO = 250 mA, CL = 30 pF -- 675 -- ns Output Fall Time tf IO = 250 mA, CL = 30 pF -- 400 -- ns IDD(off) VDD = 5.5 V, Outputs OFF -- 15 100 A IDD(on) VDD = 5.5 V, Outputs ON -- 150 300 A Output Breakdown Voltage Off-State Output Current Static Drain-Source On-State Resistance Nominal Output Current Logic Input Current Prop. Delay Time Supply Current rDS(on) IO(nom) Typical Data is at VDD = 5 V and is for design information only. NOTE -- Pulse test, duration 100 s, duty cycle 2%. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 6273 8-BIT LATCHED DMOS POWER DRIVER TIMING REQUIREMENTS 50% INx t su(D) 50% t h(D) t su(D) t h(D) 50% STROBE t PLH t PHL 90% OUTPUTx 10% tr tf Dwg. WP-036-1 Input Active Time Before Strobe (Data Set-Up Time), tsu(D) .............................................. 20 ns Input Active Time After Strobe (Data Hold Time), th(D) ................................................... 20 ns Input Pulse Width, tw(D) ...................................................... 40 ns Input Logic High, VIH ................................................ 0.85VDD Input Logic Low, VIL ................................................. 0.15VDD TEST CIRCUIT +15 V 0.11 INPUT 100 mH tav IAS = 1.0 A IO DUT OUT VO V(BR)DSX VO(ON) Dwg. EP-066-1 EAS = IAS x V(BR)DSX x tAV/2 www.allegromicro.com Single-Pulse Avalanche Energy Test Circuit and Waveforms 6273 8-BIT LATCHED DMOS POWER DRIVER TERMINAL DESCRIPTIONS Terminal No. Terminal Name Function 1 CLEAR When (active) LOW, all latches are reset and all outputs go HIGH (turn OFF). 2 IN1 CMOS data input to a latch. When strobed, the output then inverts the data input (IN1 = HIGH, OUT1 = LOW). 3 IN2 CMOS data input to a latch. When strobed, the output then inverts the data input (IN2 = HIGH, OUT2 = LOW). 4 OUT1 Current-sinking, open-drain DMOS output. 5 OUT2 Current-sinking, open-drain DMOS output. 6 OUT3 Current-sinking, open-drain DMOS output. 7 OUT4 Current-sinking, open-drain DMOS output. 8 IN3 CMOS data input to a latch. When strobed, the output then inverts the data input (IN3 = HIGH, OUT3 = LOW). 9 IN4 CMOS data input to a latch. When strobed, the output then inverts the data input (IN4 = HIGH, OUT4 = LOW). 10 GROUND Reference terminal for all voltage measurements. 11 STROBE A CMOS dynamic input to all latches. Data on each INx terminal is loaded into its associated latch on a low-to-high STROBE transition. 12 IN5 CMOS data input to a latch. When strobed, the output then inverts the data input (IN5 = HIGH, OUT5 = LOW). 13 IN6 CMOS data input to a latch. When strobed, the output then inverts the data input (IN6 = HIGH, OUT6 = LOW). 14 OUT5 Current-sinking, open-drain DMOS output. 15 OUT6 Current-sinking, open-drain DMOS output. 16 OUT7 Current-sinking, open-drain DMOS output. 17 OUT8 Current-sinking, open-drain DMOS output. 18 IN7 CMOS data input to a latch. When strobed, the output then inverts the data input (IN7 = HIGH, OUT7 = LOW). 19 IN8 CMOS data input to a latch. When strobed, the output then inverts the data input (IN8 = HIGH, OUT8 = LOW). 20 LOGIC SUPPLY (VDD) The logic supply voltage (typically 5 V). 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 6273 8-BIT LATCHED DMOS POWER DRIVER A6273KA Dimensions in Inches (controlling dimensions) 20 0.014 0.008 11 0.430 MAX 0.280 0.240 0.300 BSC 1 0.070 0.045 0.100 1.060 0.980 10 0.005 BSC MIN 0.210 MAX 0.015 0.150 0.115 MIN 0.022 0.014 Dwg. MA-001-20 in Dimensions in Millimeters (for reference only) 0.355 0.204 11 20 10.92 MAX 7.11 6.10 7.62 BSC 1 1.77 1.15 2.54 26.92 24.89 BSC 10 0.13 MIN 5.33 MAX 3.81 2.93 0.39 MIN 0.558 0.356 NOTES:1. 2. 3. 4. Exact body and lead configuration at vendor's option within limits shown. Lead spacing tolerance is non-cumulative. Lead thickness is measured at seating plane or below. Supplied in standard sticks/tubes of 18 devices. www.allegromicro.com Dwg. MA-001-20 mm 6273 8-BIT LATCHED DMOS POWER DRIVER A6273KLW Dimensions in Inches (for reference only) 20 11 0.0125 0.0091 0.419 0.394 0.2992 0.2914 0.050 0.016 0.020 0.013 1 2 0.050 3 0.5118 0.4961 0 TO 8 BSC 0.0926 0.1043 Dwg. MA-008-20 in 0.0040 MIN. Dimensions in Millimeters (controlling dimensions) 20 11 0.32 0.23 10.65 10.00 7.60 7.40 1.27 0.40 0.51 0.33 1 2 1.27 3 13.00 12.60 BSC 0 TO 8 2.65 2.35 0.10 MIN. Dwg. MA-008-20 mm NOTES:1. Exact body and lead configuration at vendor's option within limits shown. 2. Lead spacing tolerance is non-cumulative. 3. Supplied in standard sticks/tubes of 37 devices or add `TR' to part number for tape and reel. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 6273 8-BIT LATCHED DMOS POWER DRIVER The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro products are not authorized for use as critical components in life-support devices or systems without express written approval. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. www.allegromicro.com 6273 8-BIT LATCHED DMOS POWER DRIVER POWER INTERFACE DRIVERS Function Output Ratings* Part Number SERIAL-INPUT LATCHED DRIVERS 8-Bit (saturated drivers) 8-Bit 8-Bit 8-Bit 8-Bit 8-Bit (constant-current LED driver) 8-Bit (constant-current LED driver) 8-Bit (DMOS drivers) 8-Bit (DMOS drivers) 8-Bit (DMOS drivers) -120 mA 350 mA 350 mA 350 mA 350 mA 75 mA 120 mA 250 mA 350 mA 100 mA 50 V 50 V 80 V 50 V 80 V 17 V 24 V 50 V 50 V 50 V 5895 5821 5822 5841 5842 6275 6277 6595 6A595 6B595 10-Bit (active pull-downs) -25 mA 60 V 5810-F and 6810 12-Bit (active pull-downs) -25 mA 60 V 5811 75 mA 17 V 6276 20-Bit (active pull-downs) -25 mA 60 V 5812-F and 6812 32-Bit (active pull-downs) 32-Bit 32-Bit (saturated drivers) -25 mA 100 mA 100 mA 60 V 30 V 40 V 5818-F and 6818 5833 5832 16-Bit (constant-current LED driver) PARALLEL-INPUT LATCHED DRIVERS 4-Bit 350 mA 50 V 5800 8-Bit 8-Bit 8-Bit (DMOS drivers) 8-Bit (DMOS drivers) -25 mA 350 mA 100 mA 250 mA 60 V 50 V 50 V 50 V 5815 5801 6B273 6273 SPECIAL-PURPOSE DEVICES Unipolar Stepper Motor Translator/Driver Addressable 8-Bit Decoder/DMOS Driver Addressable 8-Bit Decoder/DMOS Driver Addressable 8-Bit Decoder/DMOS Driver Addressable 28-Line Decoder/Driver 1.25 A 250 mA 350 mA 100 mA 450 mA 50 V 50 V 50 V 50 V 30 V 5804 6259 6A259 6B259 6817 * Current is maximum specified test condition, voltage is maximum rating. See specification for sustaining voltage limits. Negative current is defined as coming out of (sourcing) the output. Complete part number includes additional characters to indicate operating temperature range and package style. Internal transient-suppression diodes included for inductive-load protection. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000