ICS84330-02 Integrated Circuit Systems, Inc. 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER GENERAL DESCRIPTION FEATURES The ICS84330-02 is a general purpose, single output high frequency synthesizer and a HiPerClockSTM member of the HiPerClockSTM family of High Perfor mance Clock Solutions from ICS. The VCO operates at a frequency range of 250MHz to 700MHz. The VCO and output frequency can be programmed using the serial or parallel interfaces to the configuration logic. The output can be configured to divide the VCO frequency by 1, 2, 4, and 8. Output frequency steps from 250kHz to 2MHz can be achieved using a 16MHz crystal depending on the output divider setting. * * * * * * BLOCK DIAGRAM PIN ASSIGNMENT ICS * * * * * * Fully integrated PLL, no external loop filter requirements 1 differential 3.3V LVPECL output Crystal oscillator interface: 10MHz to 25MHz Output frequency range: 31.25MHz to 700MHz VCO range: 250MHz to 700MHz Parallel or serial interface for programming M and N dividers during power-up RMS Period jitter: 5ps (maximum) Cycle-to-cycle jitter: 40ps (maximum) 3.3V supply voltage 0C to 70C ambient operating temperature Lead-Free package fully RoHS compliant Industrial temperature information available upon request VEE TEST VCC VEE OSC S_CLOCK 26 S_DATA 27 S_LOAD 28 18 N1 17 N0 16 28-Lead PLCC V Package 1 15 11.6mm x 11.4mm x 4.1mm 14 2 body package 13 3 Top View M8 12 M4 1 XTAL_OUT 0 VCCA / 16 FREF_EXT XTAL_SEL XTAL_SEL XTAL_IN PLL 9 10 11 M7 M6 M5 M3 CONFIGURATION INTERFACE LOGIC 8 M2 0 7 M1 /2 6 M0 /M 5 nP_LOAD VCO FOUT nFOUT 4 OE 1 /2 /4 /8 /1 ICS84330-02 XTAL_OUT PHASE DETECTOR S_LOAD S_DATA S_CLOCK nP_LOAD FOUT XTAL_IN FREF_EXT nFOUT VCC 25 24 23 22 21 20 19 OE TEST M0:M8 N0:N1 84330AV-02 www.icst.com/products/hiperclocks.html 1 REV. A MAY 31, 2005 ICS84330-02 Integrated Circuit Systems, Inc. 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER FUNCTIONAL DESCRIPTION NOTE: The functional description that follows describes operation using a 16MHz crystal. Valid PLL loop divider values for different crystal or input frequencies are defined in the Input Frequency Characteristics, Table 6, NOTE 1. divider. On the LOW-to-HIGH transition of the nP_LOAD input, the data is latched and the M divider remains loaded until the next LOW transition on nP_LOAD or until a serial event occurs. The TEST output is Mode 000 (shift register out) when operating in the parallel input mode. The relationship between the VCO frequency, the crystal frequency and the M divider is defined as follows: fVCO = fxtal x 2M 16 The M value and the required values of M0 through M8 are shown in Table 3B, Programmable VCO Frequency Function Table. Valid M values for which the PLL will achieve lock are defined as 125 M 350. The frequency out is defined as follows: fout fVCO fxtal x 2M = = N N 16 Serial operation occurs when nP_LOAD is HIGH and S_LOAD is LOW. The shift register is loaded by sampling the S_DATA bits with the rising edge of S_CLOCK. The contents of the shift register are loaded into the M divider when S_LOAD transitions from LOW-to-HIGH. The M divide and N output divide values are latched on the HIGH-to-LOW transition of S_LOAD. If S_LOAD is held HIGH, data at the S_DATA input is passed directly to the M divider on each rising edge of S_CLOCK. The serial mode can be used to program the M and N bits and test bits T2:T0. The internal registers T2:T0 determine the state of the TEST output as follows: The ICS84330-02 features a fully integrated PLL and therefore requires no external components for setting the loop bandwidth. A quartz crystal is used as the input to the on-chip oscillator. The output of the oscillator is divided by 16 prior to the phase detector. With a 16MHz crystal this provides a 1MHz reference frequency. The VCO of the PLL operates over a range of 250MHz to 700MHz. The output of the M divider is also applied to the phase detector. The phase detector and the M divider force the VCO output frequency to be 2M times the reference frequency by adjusting the VCO control voltage. Note that for some values of M (either too high or too low), the PLL will not achieve lock. The output of the VCO is scaled by a divider prior to being sent to each of the LVPECL output buffers. The divider provides a 50% output duty cycle. The programmable features of the ICS84330-02 support two input modes to program the M divider and N output divider. The two input operational modes are parallel and serial. Figure 1 shows the timing diagram for each mode. In parallel mode the nP_LOAD input is LOW. The data on inputs M0 through M8 and N0 through N1 is passed directly to the M divider and N output T2 0 0 0 0 1 T1 0 0 1 1 0 T0 0 1 0 1 0 1 1 1 0 1 1 1 0 1 TEST Output Shift Register Out High PLL Reference Xtal / 16 (VCO / M) /2 (non 50% Duty Cycle M divider) fOUT LVCMOS Output Frequency < 200MHz Low (S_CLOCK / M) /2 (non 50% Duty Cycle M divider) fOUT / 4 fOUT fOUT fOUT fOUT fOUT fOUT fOUT S_CLOCK / N divider fOUT SERIAL LOADING S_CLOCK T2 S_DATA t S_LOAD S T1 t T0 N1 N0 M8 M7 M6 M5 M4 M3 M2 M1 M0 H t nP_LOAD S PARALLEL LOADING M0:M8, N0:N1 M, N nP_LOAD t S t H S_LOAD Time FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS NOTE: nP_LOAD is designed to eliminate runt pulses when changing M and N bits. 84330AV-02 www.icst.com/products/hiperclocks.html 2 REV. A MAY 31, 2005 ICS84330-02 Integrated Circuit Systems, Inc. 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER TABLE 1. PIN DESCRIPTIONS Name Type VCCA XTAL_IN, XTALOUT Power XTAL_SEL Input Pullup OE Input Pullup nP_LOAD Input Pullup M0, M1, M2 M3, M4, M5 M6, M7, M8 Input Pullup N0, N1 Input Pullup VEE Power TEST Output VCC Power nFOUT, FOUT nc FREF_EXT Output Unused Input Description Analog supply pin. Crystal oscillator interface. XTAL_IN is an oscillator input. XTAL_OUT is an oscillator output. Selects between the crystal oscillator or FREF_EXT inputs as the PLL reference source. Selects XTAL inputs when HIGH. Selects FREF_EXT when LOW. LVCMOS / LVTTL interface levels. Output enable. LVCMOS / LVTTL interface levels. Parallel load input. Determines when data present at M8:M0 is loaded into M divider, and when data present at N1:N0 sets the N output divide value. LVCMOS / LVTTL interface levels. M divider inputs. Data latched on LOW-to-HIGH transition of nP_LOAD input. LVCMOS / LVTTL interface levels. Determines N output divider value as defined in Table 3C Function Table. LVCMOS / LVTTL interface levels. Negative supply pins. Test output which is used in the serial mode of operation. LVCMOS / LVTTL interface levels. Core supply pins. Differential output for the synthesizer. 3.3V LVPECL interface levels. Do not connect. Pulldown PLL reference input. LVCMOS / LVTTL interface levels. Clocks the serial data present at S_DATA input into the shift register on the S_CLOCK Input Pulldown rising edge of S_CLOCK. LVCMOS / LVTTL interface levels. Shift register serial input. Data sampled on the rising edge of S_CLOCK. S_DATA Input Pulldown LVCMOS / LVTTL interface levels. Controls transition of data from shift register into the M divider. S_LOAD Input Pulldown LVCMOS / LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance Test Conditions Minimum Typical 4 Maximum Units pF RPULLUP Input Pullup Resistor 51 k RPULLDOWN Input Pulldown Resistor 51 k 84330AV-02 www.icst.com/products/hiperclocks.html 3 REV. A MAY 31, 2005 ICS84330-02 Integrated Circuit Systems, Inc. TABLE 3A. PARALLEL AND 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER SERIAL MODE FUNCTION TABLE Inputs nP_LOAD M N S_LOAD S_CLOCK S_DATA L Data Data X X X Data Data L X X H X X L Data H X X L Data H X X L Data H X X L X X H X X H NOTE: L = LOW H = HIGH X = Don't care = Rising edge transition = Falling edge transition Data Conditions Data on M and N inputs passed directly to M divider and N output divider. TEST mode 000. Data is latched into input registers and remains loaded until next LOW transition or until a serial event occurs. Serial input mode. Shift register is loaded with data on S_DATA on each rising edge of S_CLOCK. Contents of the shift register are passed to the M divider and N output divider. M divide and N output divide values are latched. Parallel or serial input do not affect shift registers. S_DATA passed directly to M divider as it is clocked. TABLE 3B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE VCO Frequency (MHz) M Divide 256 128 64 32 16 8 4 2 1 M8 M7 M6 M5 M4 M3 M2 M1 M0 250 125 0 0 1 1 1 1 1 0 1 252 126 0 0 1 1 1 1 1 1 0 254 127 0 0 1 1 1 1 1 1 1 256 128 0 1 0 0 0 0 0 0 0 * * * * * * * * * * * * * * * * * * * * * * 696 348 1 0 1 0 1 1 1 0 0 698 349 1 0 1 0 1 1 1 0 1 700 350 1 0 1 0 1 1 1 1 0 NOTE 1: These M divide values and the resulting frequencies correspond to a crystal frequency of 16MHz. TABLE 3C. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE Inputs N Divider Value Output Frequency (MHz) N1 N0 0 0 2 0 1 4 62. 5 175 1 0 8 31.25 87.5 1 1 1 250 700 84330AV-02 Minimum Maximum 12 5 35 0 www.icst.com/products/hiperclocks.html 4 REV. A MAY 31, 2005 ICS84330-02 Integrated Circuit Systems, Inc. 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC Inputs, VI 4.6V -0.5V to VCC + 0.5 V Outputs, IO Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, JA 37.8C/W (0 lfpm) Storage Temperature, TSTG -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. DC POWER SUPPLY CHARACTERISTICS, VCC = VCCA = 3.3V5%, TA = 0C TO 70C Symbol Parameter Test Conditions Minimum Typical Maximum Units VCC Core Supply Voltage 3.135 3. 3 3.465 V VCCA Analog Supply Voltage 3.135 3.3 3.465 V ICC Power Supply Current 130 mA ICCA Analog Supply Current 15 mA TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = 3.3V5%, TA = 0C TO 70C Symbol Parameter Maximum Units VIH Input High Voltage Test Conditions 2 VCC + 0.3 V VIL Input Low Voltage -0.3 0.8 V VCC = VIN = 3.465V 5 A VCC = VIN = 3.465V 150 A VOH M0-M8, N0, N1, OE, nP_LOAD, XTAL_SEL Input High Current S_LOAD, S_CLOCK FREF_EXT, S_DATA M0-M8, N0, N1, OE, nP_LOAD, XTAL_SEL Input Low Current S_LOAD, S_CLOCK FREF_EXT, S_DATA Output High Voltage; NOTE 1 VOL Output Low Voltage; NOTE 1 IIH IIL Minimum Typical VCC = 3.465V, VIN = 0V -150 A VCC = 3.465V, VIN = 0V -5 A 2.6 V 0.5 V Maximum Units NOTE 1: Outputs terminated with 50 to VCC/2. TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = VCCA = 3.3V5%, TA = 0C TO 70C Symbol Parameter Test Conditions Minimum Typical VOH Output High Voltage; NOTE 1 VCC - 1.4 VCC - 0.9 V V OL Output Low Voltage; NOTE 1 VCC - 2.0 VCC - 1.7 V VSWING Peak-to-Peak Output Voltage Swing 0.6 1.0 V NOTE 1: Outputs terminated with 50 to VCC - 2V. 84330AV-02 www.icst.com/products/hiperclocks.html 5 REV. A MAY 31, 2005 ICS84330-02 Integrated Circuit Systems, Inc. 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER TABLE 5. CRYSTAL CHARACTERISTICS Parameter Test Conditions Minimum Mode of Oscillation Typical Maximum Units Fundamental Frequency 10 25 MHz Equivalent Series Resistance (ESR) 70 Shunt Capacitance 7 pF Drive Level 1 mW TABLE 6. INPUT FREQUENCY CHARACTERISTICS, VCC = VCCA = 3.3V5%, TA = 0C TO 70C Symbol Parameter Test Conditions fIN Input Frequency XTAL; NOTE 1 Minimum Typical 10 S_CLOCK Maximum Units 25 MHz 50 MHz FREF_EXT; NOTE 2 10 25 MHz NOTE 1: For the cr ystal frequency range the M value must be set to achieve the minimum or maximum VCO frequency range of 250MHz to 700MHz. Using the minimum frequency of 10MHz, valid values of M are 200 M 511. Using the maximum frequency of 25MHz, valid values of M are 80 M 224. NOTE 2: Maximum frequency on FREF_EXT is dependent on the internal M counter limitations. See Application Information Section for recommendations on optimizing the performance using the FREF_EXT input. TABLE 7. AC CHARACTERISTICS, VCC = VCCA = 3.3V5%, TA = 0C TO 70C Symbol Parameter Maximum Units FOUT Output Frequency 700 MHz tjit(per) tjit(cc) Period Jitter, RMS; NOTE 1, 2 5 ps Cycle-to-Cycle Jitter; NOTE 1, 2 40 ps tR / tF tnP_LOAD Output Rise/Fall Time Input Parallel Data Load Time Rise Time S_DATA to S_CLOCK 600 ps 50 ns tS Setup Time tH Hold Time tL PLL Lock Time odc Test Conditions 20% to 80% Minimum 200 20% to 80% Typical 20 ns S_CLOCK to S_LOAD 20 ns M, N to nP_LOAD 20 ns S_DATA to S_CLOCK 20 ns M, N to nP_LOAD 20 ns Output Duty Cycle 10 ms N1 45 55 % N = 1, fOUT 250MHz N = 1, 250MHz < fOUT 500MHz 45 55 % 40 60 % See Parameter Measurement Information section. Characterized using a XTAL input. NOTE 1: This parameter is defined in accordance with JEDEC Standard 65 NOTE 2: See Applications section. 84330AV-02 www.icst.com/products/hiperclocks.html 6 REV. A MAY 31, 2005 ICS84330-02 Integrated Circuit Systems, Inc. 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER PARAMETER MEASUREMENT INFORMATION 2V VOH VCC, VCCA SCOPE Qx VREF nQx VEE VOL 1 contains 68.26% of all measurements 2 contains 95.4% of all measurements 3 contains 99.73% of all measurements 4 contains 99.99366% of all measurements 6 contains (100-1.973x10-7)% of all measurements LVPECL Histogram Reference Point Mean Period (Trigger Edge) (First edge after trigger) -1.3V 0.165V PERIOD JITTER 3.3V OUTPUT LOAD AC TEST CIRCUIT nFOUT 80% 80% V FOUT SW I N G tcycle n tcycle n+1 20% 20% Clock Outputs t R t F t jit(cc) = tcycle n -tcycle n+1 1000 Cycles CYCLE-TO-CYCLE JITTER OUTPUT RISE/FALL TIME nFOUT FOUT t PW t odc = PERIOD t PW x 100% t PERIOD OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD 84330AV-02 www.icst.com/products/hiperclocks.html 7 REV. A MAY 31, 2005 ICS84330-02 Integrated Circuit Systems, Inc. 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS84330-02 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC and VCCA should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 2 illustrates how a 10 resistor along with a 10F and a .01F bypass capacitor should be connected to each VCCA pin. TERMINATION FOR 3.3V VCC .01F 10 .01F 10F V CCA FIGURE 2. POWER SUPPLY FILTERING LVPECL OUTPUTS drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to 3.3V Zo = 50 125 FOUT 125 FIN Zo = 50 Zo = 50 FOUT 50 RTT = 1 Z ((VOH + VOL) / (VCC - 2)) - 2 o VCC - 2V Zo = 50 RTT 84 FIGURE 3A. LVPECL OUTPUT TERMINATION 84330AV-02 FIN 50 84 FIGURE 3B. LVPECL OUTPUT TERMINATION www.icst.com/products/hiperclocks.html 8 REV. A MAY 31, 2005 ICS84330-02 Integrated Circuit Systems, Inc. 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER LVCMOS TO XTAL INTERFACE ance trace may be required. The input can function with half swing amplitude. Reducing amplitude from full swing of 3.3V to half swing of about 1.65V can prevent signal interfere with power rail and may reduce noise. Please refer to the LVCMOS driver data sheet and application note for amplitude reduction and termination approach. The XTAL_IN input can accept single ended LVCMOS signal through an AC couple capacitor. A general interface diagram is shown in Figure 4. The XTAL_OUT input can be left floating. The edge rate can be as slow as 10ns. If the incoming signal has sharp edge rate and the signal path is a long trace, proper termination for the driver and controlled characteristic imped- 3.3V C1 XTAL_IN 0.1uF LVCMOS_Driv er XTAL_OUT Cry stal Interf ace Figure 4. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE Cycle-to-Cycle Jitter (ps) 50 40 30 Spec Limit N=1 20 10 0 200 300 400 500 600 700 Output Frequency (MHz) FIGURE 5. CYCLE-TO-CYCLE JITTER 84330AV-02 VS. fOUT (using a 16MHz XTAL) www.icst.com/products/hiperclocks.html 9 REV. A MAY 31, 2005 ICS84330-02 Integrated Circuit Systems, Inc. 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER LAYOUT GUIDELINE The schematic of the ICS84330-02 layout example used in this layout guideline is shown in Figure 6A. The ICS84330-02 recommended PCB board layout for this example is shown in Figure 6B. This layout example is used as a general guide- line. The layout in the actual system will depend on the selected component types, the density of the components, the density of the traces, and the stack up of the P.C. board. SP C1 X1 C2 16MHz, 18pF M3 M2 M1 M0 nPLOAD OE SP S P = S p a ce (i .e . n o t in tsta ll e d ) M [8 :0 ]= 1 1 0 0 1 0 0 0 0 (4 0 0 ) N[1 :0 ] =0 0 (Di vi d e b y 2 ) M4 M5 M6 M7 M8 N0 N1 U1 ICS84330-02 X_IN XTAL_SEL FREF_EXT VCCA S_LOAD S_DATA S_CLOCK 4 3 2 1 28 27 26 VEE TEST VCC VEE nFOUT FOUT VCC V CC=3 .3 V 12 13 14 15 16 17 18 19 20 21 22 23 24 25 M4 M5 M6 M7 M8 N2 N1 M3 M2 M1 M0 nP_LOAD OE X_OUT 11 10 9 8 7 6 5 VCC R7 10 VCCA C11 0.01u C16 10u C3 VCC VCC 0.1uF Zo = 50 Ohm RD0 1K RD1 1K RD7 SP RD8 SP RU10 1K RD9 1K RU11 SP nPLoad RD10 SP RU12 1K Fo u t = 2 0 0 M Hz C4 0.1u + Zo = 50 Ohm OE N0 RU9 SP N1 RU8 1K M8 RU7 1K M7 RU1 SP M1 M0 RU0 SP RD6 1K - R2 50 RD12 SP R1 50 R3 50 FIGURE 6A. SCHEMATIC 84330AV-02 OF RECOMMENDED LAYOUT www.icst.com/products/hiperclocks.html 10 REV. A MAY 31, 2005 ICS84330-02 Integrated Circuit Systems, Inc. 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER The following component footprints are used in this layout example: * The differential 50 output traces should have the same length. All the resistors and capacitors are size 0603. * Avoid sharp angles on the clock trace. Sharp angle turns cause the characteristic impedance to change on the transmission lines. POWER AND GROUNDING Place the decoupling capacitors C3 and C4, as close as possible to the power pins. If space allows, placement of the decoupling capacitor on the component side is preferred. This can reduce unwanted inductance between the decoupling capacitor and the power pin caused by the via. * Keep the clock traces on the same layer. Whenever possible, avoid placing vias on the clock traces. Placement of vias on the traces can affect the trace characteristic impedance and hence degrade signal integrity. Maximize the power and ground pad sizes and number of vias capacitors. This can reduce the inductance between the power and ground planes and the component power and ground pins. * To prevent cross talk, avoid routing other signal traces in parallel with the clock traces. If running parallel traces is unavoidable, allow a separation of at least three trace widths between the differential clock trace and the other signal trace. The RC filter consisting of R7, C11, and C16 should be placed as close to the VCCA pin as possible. * Make sure no other signal traces are routed between the clock trace pair. CLOCK TRACES * The matching termination resistors should be located as close to the receiver input pins as possible. AND TERMINATION Poor signal integrity can degrade the system performance or cause system failure. In synchronous high-speed digital systems, the clock signal is less tolerant to poor signal integrity than other signals. Any ringing on the rising or falling edge or excessive ring back can cause system failure. The shape of the trace and the trace delay might be restricted by the available space on the board and the component location. While routing the traces, the clock signal traces should be routed first and should be locked prior to routing other signal traces. CRYSTAL The crystal X1 should be located as close as possible to the pins 4 (XTAL_IN) and 5 (XTAL_OUT). The trace length between the X1 and U1 should be kept to a minimum to avoid unwanted parasitic inductance and capacitance. Other signal traces should not be routed near the crystal traces. X1 C1 C2 U1 GND VCC PIN 2 C11 C16 PIN 1 VCCA VCCA R7 VIA Signals Traces C3 C4 50 Ohm Traces FIGURE 6B. PCB BOARD LAYOUT 84330AV-02 FOR ICS84330-02 www.icst.com/products/hiperclocks.html 11 REV. A MAY 31, 2005 ICS84330-02 Integrated Circuit Systems, Inc. 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER JITTER REDUCTION FOR FREF_EXT SINGLE END INPUT If the FREF_EXT input is driven by a 3.3V LVCMOS driver, the jitter performance can be improved by reducing the amplitude swing and slowing down the edge rate. Figure 7A shows an amplitude reduction approach for a long trace. The swing will be approximately 0.85V for logic low and 2.5V for logic high (instead of 0V to 3.3V). Figure 7B shows amplitude reduction approach for a short trace. The circuit shown in Figure 7C reduces amplitude swing and also slows down the edge rate by increasing the resistor value. VDD VDD Ro ~ 7 Ohm RS R1 100 Zo = 50 Ohm Td VDD GND 43 R2 100 Driver_LVCMOS FIGURE 7A. AMPLITUDE REDUCTION FOR A TEST_CLK FREF_EXT LONG TRACE VDD VDD R1 200 Ro ~ 7 Ohm VDD RS GND 100 R2 200 Driver_LVCMOS FIGURE 7B. AMPLITUDE REDUCTION FOR A TEST_CLK FREF_EXT SHORT TRACE VDD VDD R1 400 Ro ~ 7 Ohm VDD RS GND 200 R2 400 Driver_LVCMOS FIGURE 7C. EDGE RATE REDUCTION 84330AV-02 BY INCREASING THE www.icst.com/products/hiperclocks.html 12 TEST_CLK FREF_EXT RESISTOR VALUE REV. A MAY 31, 2005 ICS84330-02 Integrated Circuit Systems, Inc. 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS84330-02. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS84330-02 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. * * Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 145mA = 502.4mW Power (outputs)MAX = 30mW/Loaded Output pair Total Power_MAX (3.465V, with all outputs switching) = 502.4mW + 30mW = 532.4mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 31.1C/W per Table 9 below. Therefore, Tj for an ambient temperature of 70C with all outputs switching is: 70C + 0.532W * 31.1C/W = 86.6C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 9. THERMAL RESISTANCE JA FOR 28-PIN PLCC, FORCED CONVECTION JA by Velocity (Linear Feet per Minute) Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 37.8C/W 31.1C/W 28.3C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. 84330AV-02 www.icst.com/products/hiperclocks.html 13 REV. A MAY 31, 2005 ICS84330-02 Integrated Circuit Systems, Inc. 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in the Figure 8. VCC Q1 VOUT RL 50 VCC - 2V FIGURE 8. LVPECL DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V. CC * For logic high, VOUT = VOH_MAX = VCC_MAX - 0.9V (V CC_MAX * -V OH_MAX ) = 0.9V For logic low, VOUT = V OL_MAX (V CC_MAX -V OL_MAX =V CC_MAX - 1.7V ) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V OH_MAX - (V CC_MAX - 2V))/R ] * (V CC_MAX L -V OH_MAX ) = [(2V - (V CC_MAX -V OH_MAX ))/R ] * (V CC_MAX L -V OH_MAX )= [(2V - 0.9V)/50] * 0.9V = 19.8mW Pd_L = [(V OL_MAX - (V CC_MAX - 2V))/R ] * (V L CC_MAX -V OL_MAX ) = [(2V - (V CC_MAX -V OL_MAX ))/R ] * (V L CC_MAX -V OL_MAX )= [(2V - 1.7V)/50] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW 84330AV-02 www.icst.com/products/hiperclocks.html 14 REV. A MAY 31, 2005 ICS84330-02 Integrated Circuit Systems, Inc. 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER RELIABILITY INFORMATION TABLE 10. JAVS. AIR FLOW PLCC TABLE FOR 28 LEAD PLCC JA by Velocity (Linear Feet per Minute) Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 37.8C/W 31.1C/W 28.3C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS84330-02 is: 4442 Pin compatible with the MC12430 84330AV-02 www.icst.com/products/hiperclocks.html 15 REV. A MAY 31, 2005 ICS84330-02 Integrated Circuit Systems, Inc. 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER PACKAGE OUTLINE - V SUFFIX FOR 28 LEAD PLCC TABLE 11. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL MINIMUM MAXIMUM 28 N A 4.19 4.57 A1 2.29 3.05 A2 1.57 2.11 b 0.33 0.53 c 0.19 0.32 D 12.32 12.57 D1 11.43 11.58 D2 4.85 5.56 E 12.32 12.57 E1 11.43 11.58 E2 4.85 5.56 Reference Document: JEDEC Publication 95, MS-018 84330AV-02 www.icst.com/products/hiperclocks.html 16 REV. A MAY 31, 2005 ICS84330-02 Integrated Circuit Systems, Inc. 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER TABLE 12. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS84330AV-02 ICS84330AV-02 28 Lead PLCC tube 0C to 70C ICS84330AV-02T ICS84330AV-02 28 Lead PLCC 500 tape & reel 0C to 70C ICS84330AV-02LF ICS84330AV02L 28 Lead "Lead-Free" PLCC tube 0C to 70C ICS84330AV-02LFT ICS84330AV02L 28 Lead "Lead-Free" PLCC 500 tape & reel 0C to 70C NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 84330AV-02 www.icst.com/products/hiperclocks.html 17 REV. A MAY 31, 2005