- Page ANALOG DEVICES fAX-ON-DEMAND HOTLINE ,. W 1~ ANALOG DEVICES 12-BitSerialInput Multiplying CMOSD/AConverter PM-7543 I I FEATURES GENERAL DESCRIPTION . Fast, Flexible Microprocessor Interface with Serial Data Input The PM-7543isa 12-bitresolution.multiplying, CMOS DtAconverter. which features serial data input and current output. Serial data input reduces pin count and allows the PM- 7543 to be placed in a smaller package. saving PC board space. Improved analog parameters such asdigitalchargeinjection, powersupply rejection. output capacitance, feedthrough error. fast microprocessor interface. and improved ESD protective circuitry make the PM- 7543 a superior pin-compatible second-source to the industry standard AD7543. . . .. Superior Accuracy :t1/2 LSB INLMax :t1 LSB Gain Error Max Low 5ppml"C Max Tempco . Improved ESD Resistance Auto-Insertable DIP Package . Surface Mount SOL Package Superior Direct Replacement for AD7543 -40C to +85C for the Extended Industrial Temperature Range . Available In Die Form The rising orfalling edge (user selected) ofthe strobe inputs are used to clock serial data (present at the SRI pin) into the input shift register. When the shift register's data has been updated. the new data word is transferred to the DAC register with use of the LOAD inputs, Continued APPLICATIONS Process Control and Industrial Automation . PIN CONNECTIONS . ProgrammableAmplifiers ~ Digitally-Controlled Power Supplies, Attenuators, Filters Instrumentation . 5~~:j .!? .!? z a; . Avionics - . Auto-Calibration Systems ORDERING INFORMATIONt TEMPERATURE GAIN ERROR NONUNEARITY COMMERCIAL .i:2LSB PM7543BO PM7543BRC/883 PM7543FO PM7S43FP PM7543FS PM7543FPC Fordevicesprocessed intotal compliance toMIL-STD-883. add/883afler number. 9111011111112'/13 PM7543EO PM7543GP :t1LSB :l:1lSB :l:1lSB :l:1LSB .i:2LSB I INDUSTRIAL :l:1/2LSB .i:2LSB . MILITARY. :l:112LSB PM7543AO .i:1LSB :t2LSB .i:2LSB RANGE EXTENDEDttf Consultlactory Burn.in is available on commercia! and industrial temperature CarDIP. packages- plastic DIP. and part lor /883 data sheet. TO-can 1T For availability and burn-ininformationon SO and PlCC range packages. 16-PIN EPOXY DIP (P.Sufflx) 16-PIN CERDIP (a-Suffix) 16-PINSOL (S-Suffix) ir f/) &'!t.i IZ !LIi! ...J!If/) Of/) 2o-PIN Lce (RC-Suffix) 20.PIN PLCe (PC-Suffix) parts in contact FUNCTIONAL BLOCK DIAGRAM your local sales office. ttt CerDIP ture and range epoxy 01 -'lO.C devices are available in the exlended industrial tempera- PM-7543 to+8SoC. CROSS REFERENCE PMI AD! PM7543AO PM7543AO PM7543Ba AD7543GTD AD7543TD AD7543SD PM7543EO PM7543EO PM7543FO AD7543G8D AD75438D AD7543AD PM7543GP PM7543GP PM7543FP PM7543FPC AD7S43GKN AD7543KN AD7543JN AD7S43JP TEMPERATURE RANGE VAEf - IOU,, 15 lOUT> 3-AGNO MIL ----.- IND CLR - 13 LO' LD~o-! STBI- 4 7 -SRI '4 - VOD 12- DGND COM REV.D Informationfurnishedby Analog Devices isbelieved to be accurate and reliable. However. no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights ofthird parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Tel: 6171329-4700 Telex: 924491 Way, P.O. Box 9106, Norwood. MA 02062-9106. U.S.A Fax: 6171326-8703 Twx; 710/394-6577 Cable: ANALOG NORWOODMASS ANALOG DEVICES fAX-ON-DEMAND HOTLINE - Page 15 PM-7543 GENERAL DESCRIPTION Continued Separate LOAD control inputs allow simultaneous output updating of multiple DACs. An asynchronous CLEAR input resets the DAC register without altering the data in the input register. Operating Temperature AOIBO Versions EO/FO/FP/FPC/FS , Lead Temperature ABSOLUTE MAXIMUM RATINGS (TA .. +25C, unless 1- 60 see) 81"(Note1) -65C to +150C +300C 81C UNITS 94 12 .CIW 76 88 88 73 33 33 25 33 .CIW .CIW .CIW .CIW 8.,. is specified for worst case mounting conditions. i.e., 8.,. is specified dkvice in socket for CerDIP. P.DIP. andLCC pac:kages; i,. is specified for for device soldered to printed circuit board for SOL and PLCC ~ackages. CAUTION: +17V :t25V :t25V VDD+ O.3V 1 . Do not apply voltage higher than VCD or less than DGND potential on any terminal VDD + O.3V -o.3V to VDO ,... -o.3V to VDD Output Voltage (Pin 1. Pin 2) (Soldering, PACKAGE TYPE 16-PinHermetic DIP(0) 16-Pin Plastic DIP(P) 20.Contac:tLCC (RC) 2o-Pin SOL (5) 2o-Contact PLCC (PC) NOTE: otherwide noted.) AGND to DGND Digital Input Voltage Range """""""""""""""'" DOCto +70C +150C m CerDIP and epoxy devices are available in the extended industrial temperature range of -40C to +B5C. DGNDto AGND """"""""""""""""""""""""""" -55C to + 125C -4aoC to +85C Versions GP Version"""""""""""""""""""""""""'" Junction Temperature Storage Temperature Improved linearity and gain error performance may permit reduced circuit parts count through the elimination of trimming components. Fast interface timing may reduce timing design considerations while minimizing microprocessor wait states. The PM-7543 is available in standard plast ic and CerDIP packages that are compatible with autoinsertion equipment. Foran even smalJerpackage, considerthe DAC8043, available in an a-pin mini-DIP. Voo to DGND VREF to DGND VRFBto DGND Range except VREF (Pin 15) and RFB (Pin 16). 2. The digital control input are zener-protected; hoWever, permanent damage mayoccuron unprotectedunits from high-energyelectrostatic;fields. Keep units in conductive foam at all times until ready to use. 3. Use proper antistatic handling procedures. 4. Absolute Maximum Ratings apply to both packaged device& and DICE. Slresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. ELECTRICAL CHARACTERISTICS at VOD" +5V; VREF" +1 OV;VOUT1.. VOUT2.. VAGND"VDGND= OV;T" .. Full Temperature Range specified under Absolute Maximum Ratings, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN PM-7543 TYP MAX UNITS STATIC ACCURACY N Resolution Nonlinearity INl (Nole 1) Differential Nonlinearity (Note2) DNl 12 - PM-7S43A1EIG - PM-7S4381F PM.7S43A!E PM-754381F/G T,.- +2S.C - PM.7543AiE GainError GFSE (Note 3) Power Supply Rejection Ratio - - TA=FuIlTemp.Range All Grades - - - - TCGFS PSRR - PM-75438/F /G Gain Tempco (AGain/A Temp) (Note 6) - - AVCD - %5% iO.OOO6 :t 1/2 :1:1 %112 :1:1 :1:1 %2 Bits lSB lS8 lSB :1:2 :1:5 iO.OO2 ppml. %/% (t>.Gain/II VDC) T" = +2S.C Output leakage (Notes 4.5) Current ILKG T" - Full Temp. Range PM-7543AIB PM-7S43EIF/G Zero Scale Error (Notes B. 13) Input Resistance (Note 9) 'zSE RIN - T" = +2S.C T" FullTemp. Range PM-7543AIB PM-7543EIF/G - - - - - :1:0.002 - :to.OS - 7 VREF pin -2- :1:1 nA :1:100 %10 :1:0_006 :to.01 iO.61 :to.06 11 15 L58 kG REV. D ANALOG DEVICES FAX-ON-DEMANDHOTLINE - Page 16 PM- 7543 ELECTRICAL CHARACTERISTICS Range under Absolute specified Maximum at Voo "" +5V; Ratings, VREF"" +10V; unless otherwise VOUT1 "" VOUT2 <=VAGND = VOGND "" oV; TA "" Full Tempera1ure noted. Continued PM-7543 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS - 0.380 1 fl.s - - 2.0 rnV p.p - - 20 nVs AC PERFORMANCE Output Current Setting Time (Notes 6,7) t. AC Feedthrough Error (VAEF to IOUTI) (Note6,12) FT = VREF 20Vp-p@l= TA = +2SoC 10kHz VREF=OV Digital to Analog Glitch Energy lOUT Load Q DAC register loaded alternately all Os and aliI s (Note6,11) Total Harmonic Distortion =1000 CEXT= 13pF THO (Note 6) Output Noise Voltage Density (Notes6,14) en with - VREF = 6V RMS @ 1kHz DAC register loaded with all 1s dB -92 --- 10Hz 10100kHz - - 2.4 - nVIHz 13 between RFBand lOUT DIGITAL INPUTS Digital Input HIGH Digital Input LOW V1H - YIL Input Leakage Current (Note 10) IIN 0.8 - V1N=OVto+SV ANALOG (Note 6) Output Capacitance (Note 6) fl.A 8 GIN VIN=OV COUTt Digital Inputs = all1s COUT2 Digital Inputs = all Os - COUT' Digital Inputs = all Os - COUT2 Digital pF Inputs 90 - 60 - = all1s pF 90 pr 60 CHARACTERISTICS Serial Input to STB1 used TA =+2SoC 50 loS1 as the strobe TA = Full Temp. Range 50 STB2used T A = +2S.C 20 IDS2 as the strobe TA = Full Temp. Range 20 TA = +25C 10 TA = Full Temp. Range 20 Strobe Setup Times (tSTB :1;1 V OUTPUTS Outpul Capacitance TIMING ..- -- Input Capacitance (Note 6) V .....-- 80n8) Serialinpul to Strobe Hold Times (ISTB = 60nS) 8TB3 used tOS3 as the strobe 8TB4 used T A = +2S"C 20 tOS4 as the strobe T... = Full Temp. Range 20 STB1 used T A = +2S"C 40 tDHI as the strobe T A = Full Temp. Range 50 ST82 used TA tDH2 tOH3 t!)H4 REV.D as the strobe 50 +2S"C TA = Full Temp. Range 60 8TB3 used T A = +2S"C 60 as the strobe TA 80 8T84 T A = +2S"C used as the strobe TA Full Temp. Range =Full Temp. -3- ns ns 60 Range 80 "-'-'-'" ANALOGDEVICES fAX-ON-DEHAND HOTLINE - Page 17 PM-7543 .. ELECTRICAL CHARACTERISTICS at VOO +5V; VREF'" +10V; VOUT1.. VOUT2.. VAGND"VDGND.. OV;TA.. Full Temperature Range specified under Absolute Maximum Ratings. unless otherwise noted. Continued MIN PARAMETER SYMBOL CONDITIONS SRI Data Pulse Width tSAI T... = Full Temp. tsTe, T... = Full Temp. Range Range PM-7543 TYP MAX UNITS 100 ns 60 ns STBI Pulse Width (STB1 = 80ns) (Note 15) STB2 Pulse Width (5T82 - 10ns) (Note 15) 15TB2 T...- FullTemp. Range ST83 Pulse Width (5T83 = 80ns) (Nole 15) 'STB3 TA tsTe4 T... = Full Temp. Range - = Full Temp. Range 80 ns 80 ns 60 ns 140 180 ns 0 ns 80 ns 5184 Pulse Width (S1B4 = 80ns) (Note 15) Load Pulse Width tLo,' tLO2 T... =+2SoC T... .. Full Temp. Range L5B Strobe into Input Register to Load DAC Register Time tAse TA CLR Pulse Width tCLA T..." Full Temp. Range = Full. Temp. Range POWER SUPPLY Supply Voltage Supply Current 4.75 VOD '00 All Digital Inputs.. All Digital Inputs 5 VIH or VIL .. OV or V DO NOTES: 1. :1:1/2L5B = :to.012"1o of Full Scale. 2. Allgrades are monotonic to 12-bits over temperature. 3. Using internal feedback resistor. 5.25 v 2 0.1 mA 9. Absolutetemperaturecoefficientis less than +300ppnv"C. 4. Appliesto IOUT1;alldigitalinputs= VIL' VAEF= +10V. 5. Specificationalso applies for 'OUT2when all digital inputs = VIH' by design and not tested. 10. Digital inputs are CMOS gates; 'IN is typically 1nA at +25C. 11. 12. VREF=oV,alldigitalinpuls=OVtoVDporVooI00V. All digital inputs = oV. 13. Calculated from worst case RRE F: 6. Guaranteed 7. loun Load.. 1000. CEXT" 13pF, digital input =OV to VODorVOD toOV, Extrapolated to 1/2 LS8; ts" propagation delay (tpo) + 91:,where -r= measured time constant of the final RC decay. 14. 8, VREFD+10V,alldigitalinputs-OV. 15. -4- IZSE(in LSBs).. RREFx 'LKGx 4096) iVREF' Calculations from e = v4K TRB where: K = Boltzmann con;tant, JlOK R =resistance 0 T .. resistor temperature, oK B = bandwidth. Hz Minimum low time pulse width for ST81. ST82. and 51B4. and minimum high time pulse width forST83. REV.D ANALOGDEVICES fAX-ON-DEHAND HOTLINE - Page 18 PM-7543 DICE CHARACTERISTICS . loun 2. loUT2 3. AGND 4. STB1 5. LD1 6. N.C. 7. SAI 8. STB2 1 Substrate 10 VDO' 9. 10. 11. 12. 13. LD2 STB3 STB4 DGND CLA 14. 15. 16. Voo (Substrate) VREF RFB (die backside) is internally connected DIE SIZE 0.099 x 0.107 inch, 10,543 sq. mils (2.51 x 2.72 mm, 6.83 sq. mm) WAFER TEST LIMITS at VDD= +5V; VREF= +1aV; Your' = VOUT2= VAGND = VDGND= av, TA = +25C. PM-7543G SYMBOL PARAMETER STATIC CONDITIONS LIMITS UNITS Bi:s MIN _uuu_..-LSB MAX ACCURACY Resolution N 12 Integral Nonlinearity INL :t1 Differential Nonlineari!)' DNL Gain Error GFSE Power Supply Rejection Ratio PSAA Using internal feedback resistor ILKG Digital Inputs RIN VREF pad LSB MAX LSB MAX :to.002 AVOO=:t5% Output Leakage Current (Ioun> :1:1 :t2 ~ :1:1 VIL %1% MAX nA MAX REFERENCE INPUT ................-- Input Resistance 7/15 k!l MINIMAX DiGITAL INPUTS Digital Input HIGH VIH 2.4 VMIN Digital Input lOW VIL 0.8 VMAX ..........---.. Input Leakage Current IlL :ti VINKOVtoVoO POWER SUPPLY Supply Current fLAMAX --'00 Digital Inputs Digital Inputs K V'H or V'l =OV or V DO 2.0 0.1 mA MAX ...-- NOTE: Electrical tests <Ire performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is nol guaranteed lor standard product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing. REV.D -5- .. Page ANALOGDEVICES fAX-ON-DEMAND HOTLINE 19 PM-7543 TYPICAL PERFORMANCE CHARACTERISTICS MULTIPLYINGMODE FREQUENCYRESPONSE vs DIGITALCODE MULTIPLYING MODE TOTAL HARMONIC DISTORTION vs FREQUENCY -70 ALLalTsON 0.032 r-(MSa) an I:: P ~~ P.. SI. B. a. 81 ~S "0 B. 8. ~; 0... a. a. ~ -75 36 iD ~ -. ! ~ 72 (LSB) ao 84 ..- . 100 Ik 'Ok . . .. "'--'n ..,. -&5 ..., 0.0032 108 10M -95 10 100 Ik tOk SUPPLYCURRENTvs LOGICINPUTVOLTAGE LINEARITYERRORvs REFERENCEVOLTAGE LINEARITYERROR vs DIGITAL CODE , ! I , 0.5 0.4-l'..+ i 0.3_~ _.!. . t-+.~ , , Itt--t-i-,.. ..+ 0.2 !. 8 !Ii a ~ -0.1 ~ ~ ! , ., 0.5 +_., j! L~ ~ a:: ~ 1_ -+1_..+...+...' .. c i ; 0.0018 lOOk (Hz' FREQUENCY 1& l ! ... 0.0056 ..... -90 FREQUENCY (Hz) 2 "".0.010 <96 1M lOOk ""'" iD ~ !i 6Offi a, 0.018 -&0 ~ ..-< 48 82 ::. - VIII .6VRNS OUTPUT oP AMP: OP-42 , --+..-..-.. 8 10 0.25 , ' iD JJ> :!. . 0 g -41.250-.... ::; -41.2 -0.3 -0.5 -0.4 0 0 2 -41.5 - 6 3 a 512 t024 1536 2048 2560 3072 3684 6 2 .095 VRE,(VOLTS, DIGITAL INPUT CODE (DECIMAL) VI" (VOLTS) DNLERROR vs REFERENCE VOLTAGE 0.5 0.25 iD JJ> :!. ... z c -41.5 3 7 9 11 4 6 8 10 YRE' (YOLTS) VOD (VOLTS' -6- REV.D ANALOGDEVICESfAX-ON-DEMAND HOTLINE - Page 20 PM-7543 SPECIFICATION RESOLUTION DEFINITIONS v." The resolutionof a DACis the number of states (2n) that the fullscale range (FSR) is divided (or resolved) into, where "n" is equal to the number of bits. SETTLING TIME Time required for the analog output of the DAC to settle to within 1/2 LSB of its final value for a given digital input stimulus; i.e. zero to full scale. 20... 200J! 5, 5. 10kl1 20kJJ 20kll ,I Ratio of the DAC's external operational amplifier output voltage to the V REFinput voltage when all digital inputs are HIGH. 5,. BIT 1 IMSBI ERROR , , 6 6 I I , 6 Error caused by capacitive coupling from VREF to output. Feedthrough error limits are specified with all switches OFF. BIT 2 (SWITCHES i 1Okll ~ BIT 12 IlSBJ DIGITAL INPUTS SHOWN FOR DIGITAL INPUTS "HIGH") Current appearing at loun when all digital inputs are LOW, or at IOUT2terminal when all inputs are HIGH. ..ON the feedback resistor and the R-2R ladder's terminating resIstor. The "Simplified DAC Circuit," Figure 1 ,shows the location of these switches. These series switches are equivalently scaled to two times switch 1 (MSB) and to switch 12 (LSB) to maintain constant relative voltage drops with varying temperature. Dur- GENERAL CIRCUIT INFORMATION The PM-7543 is a 12-bit multiplying D/A converter with a very low temperature coefficient, R-2R resistor ladder network, data input and control logic, and two data registers. The digital circuitry forms an interface in which serial data can be loaded, under microprocessor control, into a 12-bit shift register and then transferred, in parallel, to the 12-bit DAC register. An asynchronous CLEAR function allows resetting the DAC register to a zero code (0000 0000 0000) without altering data stored in the registers. A simplified circuit of the PM-7543 DAC is shown in Figure 1. An inverted R-2R ladder network consisting of silicon-chrome, thinfilm resistors, and twelve pairs of NMOS current-steering switches. These switches steer binarily weighted currents into either loun or IOUT2'Switching current to IOUT1 or IOUT2 yields a constant current in each ladder leg, regardless of digital input code. This constant current results in a constant input resis- ing any testing of the resistor ladder or coming inspection), series switches. RFEEDBACK (such as in- VDD must be present to turn "ON" these ESO PROTECTION The PM-7543 data inputs have been designed with ESD resistance incorporated through careful layout and the inclusion of input protection circuitry. Figure 2 shows the input protection diodes. High voltage static charges applied to the digital inputs are shunted to the supply and ground rails through forward biased diodes. These protection diodes were designed to clamp the inputs well below dangerous levels during static discharge conditions. Von at V AEF equal to R (typically 11kQ). The V REF input may be driven by any reference voltage or current, AC or DC, that is within the limits stated in the Absolute Maximum Ratings chart. The twelve output current-steering switches are in series with the R-2R resistor ladder, and therefore, can introduce bit errors. It was essential to design these switches such that the switch "ON" resistance be binarily scaled so that the voltage drop across each switch remains constant. If, for example, switch 1 of Figure 1 was designed with an "ON" resistance of 10 ohms, switch 2 for 20 ohms, etc., a constant 5mV drop would then be maintained across each switch. DTliTTl,CMOS INPUTS -= FIGURE 2: Digital Input Protection temperature range, permanently "ON" MaS switches were included in series with REV. D PERMANENTLY FIGURE 1: Simplified DAC Circuit OUTPUT LEAKAGE CURRENT across the full IOU", RHlDBACK 6 BIT3 .. THESESWITCHES Capacitancefrom lOUT' to ground. To further insure accuracy lOUT> I r--, ~-" OUTPUT CAPACITANCE tance 20kl1 I I I I I I GAIN FEEDTHROUGH won ,oon -7- ANALOG DEVICES fAX-ON-DEMAND HOTLINE - Page 21 PM-7543 I FI,..OBACK A _. 10kH 10"T1 t 'R" - R-\Ok" 'om 2 v"" t The gain and phase stability of the output amplifier, board layout, and power supply decoupling will all affect the dynamic performance of the PM-7543. The use of a small compensation capacitor may be required when high-speed operational amplifiers are used. It may be connected across the amplifiers feedback resistor to provide the necessary phase compensation to critically damp the output. The considerations when using high-speed amplifiers are: 1. Phase compensation (see Figures 7 and 8). 2. Power supply decoupling at the device socket and use of proper grounding techniques. APPLICATIONS INFORMATION APPLICATIONTIPS In most applications, linearity depends upon the potential of FIGURE 3: PM-7543 Equivalent Circuit (All Inputs LOW) IOUT1''OUT2'and AGND (pins 1,2, and 3) being exactly equal to AFEEDSACk each other. In most applications,the DACis connected to an R" 10'H '"" - R.,0kH 'OUT VREF external op amp with its noninverting input tied to ground (see Figures 7 and 8). The amplifier selected should have a low input bias current and low drift over temperature. The amplifier's input offset voltage should be nulled to less than :t200~V (less than 10% of 1 LSB). The operational amplifier's non inverting input should have a minimum resistance connection to ground; the usual bias current compensation resistor should not be used. This resistor can cause a variable offset voltage appearing as a varying output 1 t 'OUT> t error. Allgrounded pins should tie to a single common ground point, avoiding ground loops. The VOD power supply should have a low noise level with no transients greater than + 17V. FIGURE 4: PM- 7543 Equivalent Circuit (All Digital Inputs HIGH) It is recommended that the digital inputs be taken to ground or V DOvia a high value (1 Mn) resistor; this will prevent the accu- EQUIVALENT CIRCUITANALVSIS Figures 3 and 4 show equivalent circuits for the PM-7543's internal DAC with all bits LOW and HIGH, respectively. The reference current is switched to IOUT2when all data bits are LOW, and to lOUT' when aU bits are HIGH. The ILEAKAGE current source is the combination of surface and junction leakages to the substrate. The 1/4096 current source represents the constant 1-bit current drain through the ladder's terminating resistor. mulation of static charge if the PC card is disconnected system. from the Peak supply current flows as the digital inputs pass through the transition region (see the Supply Current vs logic Input Voltage graph under the Typical Performance Characteristics). The supply current decreases as the input voltage approaches the supply rails (Voo or DGND), i.e. rapidly slewing logic signals that settle very near the supply rails will minimize supply current. Output capacitance is dependent upon the digital input code. OUTPUT This is because the gate capacitance of MOS transistors increases with applied gate voltage. This output capacitance varies between the low and high values. AMPLIFIER CONSIDERATIONS When using high speed op amps, a small feedback capacitor (typically 5-30pF) should be used across the amplifier to minimize overshoot and ringing, For low speed or static applications, AC specifications of the amp1ifier are not very critical. In highspeed applications, slew rate, settling time, open-loop gain, and gain/phase margin specifications of the amplifier should be se- DYNAMIC PERFORMANCE OUTPUT IMPEDANCE The output resistance, as in the case of the output capacitance, varies with the digital input code. This resistance, looking back into the 'OUT1terminal, may be between 11kn (the feedback resistor alone when all digital inputs are LOW) and 7.5kQ (the feedback resistor in parallel with approximately 30kQ of the R2R ladder network resistance when any single bit logic is HIGH). Static accuracy and dynamic performance will be affected by these variations. lected for the desired performance. It has already been noted that an offset can be caused by including the usual bias current compensation resistor in the amplifier's non inverting input terminal. This resistor should not be used. Instead, the amplifier should have a bias current which is low over the temperature range of interest. -8- REV. 0 ANALOG DEVICES fAX-ON-DEMAND HOTLINE - Page 22 PM-7543 .. R v~~-~- A 2R an amplifier with inherently fow Vos' Amplifiers with sufficiently low Vos include PMl's OP- 77, OP-97. OP-O7, OP-27 and OP-42INTERFACE LOGIC OPERATION The microprocessor interface of the PM-7543 has been designed with multiple STROBE and LOAD inputs to maximize interfacing options, Control signals decoding may be done onchip or with the use of external decoding circuitry (see Figure 11). HC 2R fA r If' Serial data can be clocked into the input register with STB 1. STB2, or STB4. The strobe inputs are active on the rising edge. STB3 may be used with a falling edge to clock-in data. Holding any STROBE input at its selected state (i.e. STB1. FIGURE5: Simplified Circuit STB2or STB4at logicHIGHor S"f'B3 at logicLOW) will act to Static accuracy is affected by the variation in the DAC's output resistance. This variation is best illustrated by using the circuit of Figure 5 and the equation: When a new data word has prevent any further data input. it is transferred inputs. INTERFACE INPUT DESCRIPTION STB1 (Pin 4), STB2 (Pin 8), STB4 (Pin 11) - Input Register Strobe. Inputs Active on Rising Edge. Selected to load serial =2 Vas = Vas (1 +!Qk!~ 1okQ ) data into input register. See Table 1 for details. STB3 (Pin 10) -Input Register Strobe Input. Active on Failing Edge. Selected to load serial data into input register See at code 0100 0000 0000, VERR0R2 = Voo 10ka 1 + --30kn ( Table 1 for details. = 4/3 Voo ) LD1 (Pin 5), LD2 (Pin 9) - Load DAC Register Inputs. Active Low. Selected together to load contents of Input Register into The error difference is 2/3 Vos' DAC register. Since one LSB has a weight (for VREF= +1OV)of 2.4mV for the PM7543. itis clearly important that Vas be minimized, either using the amplifier's nullingpins, an external nullingnetwork, or by selection of CLR (Pin 13) SRI BIT1 ,H'. "I 'STRO BEIHPUTos>< os<(STB1ST, 2, STB4) . I - Clear Input. Active Low. Asynchronous. When LOW, 12-bit DAC register is forced to a zero code (0000 0000 0000) regardless of other interface inputs, l =i~~ I X _.~' - I--~ :X .... 10"" f2 to X I - 1'1"1 tn., BIT 11 8~~~2 x= X=: '0 ..3. 0..0 t'Tltt.m 1ST.' 1ST.' 1- r tin; lfio; trnli ' ~t i:P1 AND LD2 LOADSERIALDATA INTOINPUTREGISTER 4 t... +--1 ':'0' r l::J NOTES; LOAD INPUT REGISTER'S DATAINTOCAe REGISTER 'STROBE WAVEFORM IS IItVERTED IF STB3IS USED TO STROBE SERIAL DATA BITS INTO REGISTER. "DATA LOADED ,,"SB FIRST. FIGURE 6: Timing Diagram REV. 0 into the input register, The CLA input allows asynchronous resetting of the DAC register to 0000 0000 0000. Th is reset does not affect data held in the input registers. While in unipolar mode, a CLEAR will result in the analog output going to OV.ln bipolar mode, the output will go to -V REF' VERROR= Vas (1 + r;:~) where Ro is a function of the digital code, and: Ao = 1Oka for more than four bits of logic 1, Ro = 30kn for any single bit of logic 1. Therefore, the offset gain varies as follows: at code 0011 1111 1111, VERROR, been entered to the DAC register by asserting both LOAD -9- ANALOGDEVICES - Page fAX-ON-DEnAND HOTLINE 23 PM-7543 TABLE 1: PM-7543 Truth Table PM-7543 logic Inputs Control Inputs 5TB4 0 0 -- 5TB2 0 STB1 CLR lD2 lD1 S X X X S 0 X X X X X X X 5TB3 1 1 0 DAC Register 1- 0 0 X 1 1 X _____n__" 0 X 0 X 0 X X X 1 X X X --- S X X X X Control Inputs Serial Data Bit Loaded (Input Register) __nn___X X (Code: DAC Register to Zero Code 0000 0000 (Asynchronous X X 1 0 0 1 code. The relationship put is shown input voltage In many very on applications low gain ponents in Table range (R1 between 2. The of the op the error permit and the be used with an AC circuit'soutput willrange (4095/4096) PM- depending V REF voltage 7543's or :t25V. RFEEDBACK) Load DAC Register with the Contents range QV DIGITAL the analog MSB 1 1 1 1 1 1 1 1 1 1 1 1 1000 0000 000 1000 0000 0000 -VAEF (~~~~) is lowest. scale of the trimming without lSB out- is the maximum zero NOMINALANALOG OUTPUT (VOUTas shown in Figures 7 and 8) INPUT and error and -v REF 1 204~" (4096) of the com- adverse effects 01 -'-5V 1 1 0000 SERIAl DATA INPUT 0000 -VREF(~~~~) = -vREF ~ 201I 1 1 1 1 1 1 1 1 (4096 ) --------- 0000 000 -v REF bo1-6) ------ -v REF (40~6) = 0 0000 1 0000 NOTES: 1. Nominalfullscale forthecircuits01Figures7 and 8 is givenby FS =-VREF4095 - Vour {4096 } CLR CONTROl. 3 ----- circuit performance. VA" -10V 3 Register) ---- or DC the digitalinput and whichever negligible the elimination external between upon the digital input amp (DAC TABLE2: UnipolarCode Table UNIPOLAR OPERATION (2-aUADRANT) approximately-VREF No Operation ------------------ 2- Serial data is loaded into Input Register MS8 lI'st, on edges shown .f IS positive edge. 1. is negative edge. 3- 0 = Logic LOW. 1 = Logie HIGH, X= Don'tCare- ~ ellee! on Input Register. in Figures 7 and 8 may 1,3 0000) Operation) of Input Register NOTES: 1- CLR 0 Asynchronouslyresets DACRegisterto 00000000 0000,but has no voltage. The 2.3 3 No Operation 0 reference from SRI intoInputRegister Reset The circuitshown Notes PM-7543 Operation Input Register I . -ISV INPUTS: 2. 1 Nominal LSB magnitude LSB =VREF = for !he drcuits (-1--4096) or VREF (2--<1) 01 Figures 7 and 8 is given by - For applications requiring a tighter gain error than 0_024% FIGURE 7: Unipolar Operation with High Accuracy Op Amp (2Quadrant) -10- forthe top grade part,or 0.048% in Figure 8 may be used. Gain for the lower grade part, error may be trimmed by at25"C the circuit adjusting R1 - REV.D ANALOGDEVICES fAX-ON-DEMAND HOTLINE - Page c~ PM-7543 AO 16-61T ADDRESS BUS At. RM VIMo----J!.IRFB VDD M~ +SV u2 PM.7543 11 loun Deo 115 VRF DBT .5V 6 VOUT FROM . RESET SYSTEM ANALOG CIRCUITRY OMITTED FOR SIMPLICITY FIGURE11: PM-7543 - MC6BOO Interface FIGURE 10: Analog/Digital Divider The transfer function is modified when the DAC is connected in the Vo = (5~-~ :~~H ADDRESSBUS 116> (9) feedback of an operational amplifier as shown in Figure 10 and is: 8095 ~) Ao-1O --' ALE WR+W The above transfer function is the division of an analog voltage (VREF) by a digital word. The amplifier goes to the rails with all bits "OFF" since division by zero is infinity. With all bits "ON," the gain is 1 (:t1 LSB). The gain becomes 4096 with the LSB, bit 12, "ON." (9)AD0-1 SOD DATA r- INTERFACING TO THE MC6800 As shown in Figure 11, the PM- 7543 may be interfaced to the 6800 by successively executing memory WRITE instructions while ma. nipulatingthe data between WRITEs, so that each WRITE presents the next bit. . ANALOG CIRCUITRY OMITTED FIGURE 12: PM- 7543 In this example, the most significant bits are found in memory locations 0000 and 0001. The four MSBs are found in the lower half of - FOR SlIolPUClTV 80B5 Interface 0000, the eight LSBs in 0001. The data is taken from the DB? line. Data is strobed into the PM- 7543 by executing memory write instructions. The strobe 2 input is generated by decoding an address location and WR. Data is loaded into the DAC register with a memory write instruction to another address location. The serial data loading is triggered by STB1 which is asserted by a decoded memory WRITE to a me.morylocation, ANI. and $2. A WRITE to another address location transfers data from input register to DAC register. Serial data supplied to the PM- 7543 must be present in the rightjustified format in registers Hand L ofthe microprocessor. PM.7543 INTERFACE TO THE 8085 The PM-7543'sinterfacetothe8085 microprocessor is shown in Figure 12. Note that the microprocessor's SOD line is used to present data serially to the DAC. -11- REV.D rr-- 1001 Audio 1002 1003 Audio Audio 1043 sumer Audio/SpeakerPhon Alldio Automotive # T elematics System X mmunications(Wired) CableModem X mun mmun " (Wired) Communi # SL X C"""" 104211 Communications 1046 !r.nmmlln X X tion X t/SoftCell PDA reless) # Drive 1018 ImagingNideo 1019 ImagingNideo 1020 Industrial X r # ICamera Ima,i!:1gNid, ImagingNideo 1017 X X rd , 1016 X ax X Flow MeterinQ X ial Machine 1022 ial Measurement/Process 1023 ial 1025 ial Contro # X X VibrationAnalysis X !Weigh Scale 1026 X ATE Equipment 1027 X ntation 1028 1029 Instrumentation Instrumentation i I! L Ie System Q", X Tester ..".... X # X r Medical ? ' Medical Medical Medical Medical X igCqUisition uL;U/Je Instrumentation 1 1033 1034 1035 1048 Vision Motor Control I 1024 1032 X # !Video Capture Board 1021 1031 X s) ireless) 1015 'Imaginideo 1030 X I ;,..,n n"rI""m ver IP 1010 '(Wireless) 1011 less) 1047 1013 X ""'""""'"'Y 1009 iCommunicati 1012 X x 1007 .iCommun 1014 X High-Side Current Sense omotive 1004 1005 1006 1008 X X iSpeech Audio .. 1044 1045 X # '-", X callmaging/Ultrasound or X X .......... 1036 Militar /Aerospace 1037 orking 1038 orking orkin 1039 1040 1041 king 1049 Optical Networking s FA r Cross-Connect X # X # Solution X X r EDFA (High-Power) T OC!t Equipment X I NOTE: 11ST ten live; 21-30 end of July/1st of August; all 49 needed for Matrix 3.0 release end of June 03 ANALOGDEVICES fAX-ON-DEMAND HOTLINE - Page 25 PM-7543 TABLE 3: Bipolar (Offset Binary) Code Table R, DIGITAL INPUT MSB Vo., -10V SERI"L DAn '"POT LSB NOMINALANALOG OUTPUT (VOUT8sshown in Figure 9) 1 1 1 1 , , 1, , , 1 , + VREF (~~:}) , 000 0000 000 , + VREF (2048 ) 1a0a 0000 0000 0 1 " l' 1 1 1 1 0000 0000 000' 0000 0000 000 VOUT cu. 3,AGNO CONTROL INPUTS -=- FIGURE 8: Unipolar Operation with Fast Op Amp and Gain ErrorTrimming(2-Quadrant) 1 1 ~._ 0 -V REF (---1-) 2048 -VREF (?_Q1?_) 2048 a -V REF (}6::-) NOTES: 1. Nomina!full scale for the circuits of Figure 9 is given by FS ~ VRf,F 2047 ) The DACregistermustfirstbe loaded withall is. R1 is then adjusted until VOUT =-V REF(4095/4096). Inthe case of an adjustable VREF' R1 and RFEEOBACK may be omitted, with VREFadjusted to yield the desired full-scale output. 2. BIPOLAR OPERATION (4-aUADRANT) Figure 9 details a suggested circuitfor bipolar, or offset binary operation. Table 3 shows the digital input to analog output relationship, The circuit uses offset binary coding, Two's complement code can be converted to offset binary by software inversion of the MSB or by the addition of an external inverter to the MSB input. adjusting the ratio of RJ to A4 to yield VOUT= OV. Full scale can be adjusted by loading the DAC register with 111' 11" , 111 and either adjusting the amplitude of V REForthe value of As until the desired VOUTis achieved. temperature coefficient match. Mismatching between AJ and A4causes offset and full-scale errors while an A5 to A4 and R3 mismatch will result in full-scale error. is performed 0000and adjusting by loading the DAC register with 2048 Lffi=VREF/~\. \20481 ANALOG/DIGITAL DIVISION The transfer function for the PM-7543 connected in the multiplying mode as shown in Figures 7 and 8 is: Resistors R , R4' and Rs must be selected to match within 0.0' % and must air be of the same (preferably metal foil) type to assure Calibration 1 Nominal LSB magnitude tOf !he circuits of Figure 9 is given by VO=-VIN ,0000000 (;; + ;.~ +;~ + "';i~) where Ax assumes avalueof 1 for an "ON" bit and Oforan "OFF" bit R1 until VOUT= OV. R, and R2 may be omitted by R, 'SY R. 20kQ R, IS V,N PM-7543 Vo., R, 100" COfjTROL BITS 8-11 VOIlT '.~ AH"LOG COMMON FROM CONTROL INPUTS SYSTEM RESH I SERIAL DATA INPUT FIGURE 9: Bipolar Operation (4-Quadrant, Offset Binary) REV. D -12-