MB90F387SPMT-GSE1 - Fujitsu - Datasheet.Directory

DS07-13717-3E

FUJITSU SEMICONDUCTOR

DATA SHEET

16-bit Proprietary Microcontroller

CMOS

F2MC-16LX MB90385 Series

MB90387/387S/F387/F387S/MB90V495G

■DESCRIPTION

MB90385 series devices are general-purpose high-performance 16-bit micro controllers designed for process

control of consumer products, which require high-speed real-time processing. The de vices of this series hav e the

built-in full-CAN interface.

The system, inheriting the architecture of F2MC* family, employs additional instr uction ready for high-level lan-

guages, e xpanded addressing mode , enhanced multiply-divide instructions, and enriched bit-processing instruc-

tions. Furthermore, employment of 32-bit accumulator achieves processing of long-word data (32 bits).

The peripheral resources of MB90385 series include the following:

8/10-bit A/D converter, UART (SCI), 8/16-bit PPG timer, 16-bit input-output timer (16-bit free-run timer, input

capture 0, 1, 2, 3 (ICU)), and CAN controller.

*: “F2MC”, an abbreviation for FUJITSU Flexible Microcontroller, is a registered trademark of FUJITSU Ltd.

■FEATURES

•

••

• Clock

• Built-in PLL clock frequency multiplication circuit

• Selection of machine clocks (PLL clocks) is allowed among frequency division by two on oscillation clock, and

multiplication of 1 to 4 times of oscillation clock (for 4-MHz oscillation clock, 4 MHz to 16 MHz).

• Operation by sub-clock (8.192 kHz) is allowed.

• Minimum ex ecution time of instruction: 62.5 ns (when operating with 4-MHz oscillation cloc k, and 4-time m ulti-

plied PLL clock).

(Continued)

■PACKAGE

48-pin plastic-LQFP

(FPT-48P-M26)

MB90385 Series

•

••

• 16 Mbyte CPU memory space

• 24-bit internal addressing

•

••

• Instruction system best suited to controller

• Wide choice of data types (bit, byte, word, and long word)

• Wide choice of addressing modes (23 types)

• Enhanced multiply-divide instructions and RETI instructions

• Enhanced high-precision computing with 32-bit accumulator

•

••

• Instruction system compatible with high-level language (C language) and multitask

• Employing system stack pointer

• Enhanced various pointer indirect instructions

• Barrel shift instructions

•

••

• Increased processing speed

• 4-byte instruction queue

•

••

• Powerful interrupt function with 8 levels and 34 factors

•

••

• Automatic data transfer function independent of CPU

• Expanded intelligent I/O service function (EI2 OS): Maximum of 16 channels

•

••

• Low power consumption (standby) mode

• Sleep mode (a mode that halts CPU operating clock)

• Time-base timer mode (a mode that operates oscillation clock, sub clock, time-base timer and clock timer only)

• Clock mode (a mode that operates sub clock and clock timer only)

• Stop mode (a mode that stops oscillation clock and sub clock)

• CPU b locking operation mode

•

••

• Pr ocess

•CMOS technology

•

••

• I/O port

• General-purpose input/output port (CMOS output) :

MB90387, MB90F387 : 34 ports (including 4 high-current output ports)

MB90387S, MB90F387S : 36 ports (including 4 high-current output ports)

•

••

• Timer

• Time-base timer, clock timer, watchdog timer: 1 channel

• 8/16-bit PPG timer: 8-bit x 4 channels, or 16-bit x 2 channels

• 16-bit reload timer: 2 channels

• 16-bit input/output timer

- 16-bit free run timer: 1 channel

- 16-bit input capture: (ICU): 4 channels

Interrupt request is issued upon latching a count value of 16-bit free run timer by detection of an edge on pin

input.

•

••

• CAN controller: 1 channel

• Compliant with Ver2.0A and Ver2.0B CAN specifications

• 8 built-in message buffers

• Transmission rate of 10 Kbps to 1 Mbps (by 16 MHz machine clock)

•CAN wake-up

•

••

• UART (SCI): 1 channel

• Equipped with full-duplex double buffer

• Clock-asynchronous or clock-synchronous serial transmission is available.

(Continued)

MB90385 Series

(Continued)

•

••

• DTP/External interrupt: 4 channels, CAN wakeup: 1channel

• Module for activation of expanded intelligent I/O service (EI2OS), and generation of external interrupt.

•

••

• Delay interrupt generator module

• Generates interrupt request for task switching.

•

••

• 8/10-bit A/D converter: 8 channels

• Resolution is selectable between 8-bit and 10-bit.

• Activation by external trigger input is allowed.

• Conversion time: 6.125 µs (at 16-MHz machine clock, including sampling time)

•

••

• Program patch function

• Address matching detection for 2 address pointers.

MB90385 Series

■PRODUCT LINEUP

(Continued)

Part Number MB90F387/S MB90387/S MB90V495G

Parameter

Classification Flash ROM Mask ROM Evaluation product

ROM capacity 64 Kbytes 

RAM capacity 2 Kbytes 6 Kbytes

Process CMOS

Package LQFP-48 (0.50 mm width) PGA256

Operating power supply voltage 3.5 V to 5.5 V 4.5 V to 5.5 V

Special power supply for

emulator*1None

CPU functions

Number of basic instructions

Instruction bit length

Instruction length

Data bit length

: 351 instructions

: 8 bits and 16 bits

: 1 byte to 7 bytes

: 1 bit, 8 bits, 16 bits

Minimum instruction execution time : 62.5 ns (at 16-MHz machine clock)

Interrupt processing time : 1.5 µs at minimum (at 16-MHz machine clock)

Low power consumption

(standby) mode Sleep mode/Clock mode/Time-base timer mode/

Stop mode/CPU intermittent

I/O port General-purpose input/output ports (CMOS output) : 34 ports (36 ports*2)

including 4 high-current output ports (P14 to P17)

Time-base timer 18-bit free-run counter

Interrupt cycle : 1.024 ms, 4.096 ms, 16.834 ms, 131.072 ms

(with oscillation clock frequency at 4 MHz)

Watchdog timer Reset generation cycle: 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms

(with oscillation clock frequency at 4 MHz)

16-bit input/

output timer

16-bit free-run

timer Number of channels: 1

Interrupt upon occurrence of overflow

Input capture Number of channels: 4

Retaining free-run timer value set by pin input (rising edge, falling edge, and

both edges)

16-bit reload timer

Number of channels: 2

16-bit reload timer operation

Count clock cycle: 0.25 µs, 0.5 µs, 2.0 µs

(at 16-MHz machine clock frequency)

External event count is allowed.

Clock timer 15-bit free-run counter

Interrupt cycle: 31.25 ms, 62.5 ms, 12 ms, 250 ms, 500 ms, 1.0 s, 2.0 s

(with 8.192 kHz sub clock)

8/16-bit PPG timer

Number of channels: 2 (four 8-bit channels are available also.)

PPG operation is allowed with four 8-bit channels or one 16-bit channel.

Outputting pulse wave of arbitrary cycle or arbitrary duty is allowed.

Count clock: 62.5 ns to 1 µs

(with 16 MHz machine clock)

MB90385 Series

(Continued)

*1 : Settings of DIP switch S2 for using emulation pod MB2145-507. For details, see MB2145-507 Hardware Manual

(2.7 Power Pin solely for Emulator).

*2 : MB90387S, MB90F387S

■PACKAGES AND PRODUCT MODELS

: Yes × : No

Note : Refer to PACKAGE DIMENSION fo r details of the package.

■PRODUCT COMPARISON

Memory space

When testing with test product for evaluation, check the differences between the product and a product to be

used actually. Pay attention to the following points:

• The MB90V495G has no built-in ROM. However, a special-pur pose development tool allows the operations

as those of one with built-in ROM. ROM capacity depends on settings on a development tool.

• On MB90V495G, an image from FF4000H to FFFFFFH is viewed on 00 bank and an image of FE0000H to

FF3FFFH is viewed only on FE bank and FF bank. (Modified on settings of a development tool.)

• On MB90F387/S/387/S, an image from FF4000H to FFFFFFH is vie w ed on 00 bank and an image of FE0000H

to FF3FFFH is viewed only on FF bank.

Part Number MB90F387/S MB90387/S MB90V495G

Parameter

Delay interrupt generator

module Interrupt generator module for task switching. Used for realtime OS.

DTP/External interrupt Number of inputs: 4

Activated by rising edge, falling edge, “H” level or “L” level input.

External interrupt or expanded intelligent I/O service (EI2OS) is available.

8/10-bit A/D converter

Number of channels: 8

Resolution: Selectable 10-bit or 8-bit.

Conversion time: 6.125 µs (at 16-MHz machine clock, including sampling time)

Sequential conversion of two or more successive channels is allowed. (Setting

a maximum of 8 channels is allowed.)

Single conversion mode : Selected channel is converted only once.

Sequential conversion mode: Selected channel is converted repetitively.

Halt conversion mode : Conversion of selected channel is stopped and

activated alternately.

UART(SCI)

Number of channels: 1

Clock-synchronous transfer: 62.5 Kbps to 2 Mbps

Clock-asynchronous transfer: 9,615 bps to 500 Kbps

Communication is allowed by bi-directional serial communication function and

master/slave type connection.

CAN

Compliant with Ver 2.0A and Ver 2.0B CAN specifications.

8 built-in message buffers.

Transmission rate of 10 Kbps to 1 Mbps (by 16 MHz machine clock)

CAN wake-up

Package MB90F387/S MB90387/S

FPT-48P-M26

MB90385 Series

■PIN ASSIGNMENT

AVCC

AVR

P50/AN0

P51/AN1

P52/AN2

P53/AN3

P54/AN4

P55/AN5

P56/AN6

P57/AN7

P37/ADTG

P20/TIN0

P17/PPG3

P16/PPG2

P15/PPG1

P14/PPG0

P13/IN3

P12/IN2

P11/IN1

P10/IN0

VSS

AVSS

X1A/P36*

X0A/P35*

P33

P32

P31

P30

P44/RX

P43/TX

P42/SOT1

P41/SCK1

P40/SIN1

P21/TOT0

P22/TIN1

P23/TOT1

P24/INT4

P25/INT5

P26/INT6

P27/INT7

MD2

MD1

MD0

RST

VCC

(FPT-48P-M26)

(TOP VIEW)

* : MB90387, MB90F387 : X1A, X0A

MB90387S, MB90F387S: P36, P35

MB90385 Series

■PIN DESCRIPTION

(Continued)

Pin No. Pin name Circuit

type Function

1AVccVcc power input pin for A/D converter.

2 AVR Power (Vref+) input pin for A/D converter. Use as input for Vcc or lower.

3 to 10 P50 to P57 EGeneral-purpose input/output ports.

AN0 to AN7 Functions as analog input pin for A/D converter. Valid when analog

input setting is “enabled.”

11 P37 DGeneral-purpose input/output ports.

ADTG Function as an external trigger input pin for A/D converter. Use the pin by

setting as input port.

12 P20 DGeneral-purpose input/output ports.

TIN0 Function as an event input pin for reload timer 0. Use the pin by setting as

input port.

13 P21 DGeneral-purpose input/output ports.

TOT0 Function as an event output pin for reload timer 0. Valid only when output

setting is “enabled.”

14 P22 DGeneral-purpose input/output ports.

TIN1 Function as an event input pin for reload timer 1. Use the pin by setting as

input port.

15 P23 DGeneral-purpose input/output ports.

TOT1 Function as an event output pin for reload timer 1. Valid only when output

setting is “enabled.”

16 to 19 P24 to P27 DGeneral-purpose input/output ports.

INT4 to INT7 Functions as external interrupt input pin. Use the pin by setting as input port.

20 MD2 F Input pin for specifying operation mode. Connect directly to Vss.

21 MD1 C Input pin for specifying operation mode. Connect directly to Vcc.

22 MD0 C Input pin for specifying operation mode. Connect directly to Vcc.

23 RST B External reset input pin.

24 Vcc Power source (5 V) input pin.

25 Vss Power source (0 V) input pin.

26 C Capacitor pin for stabilizing power source. Connect a ceramic capacitor of

approximately 0.1 µF.

27 X0 A Pin for high-rate oscillation.

28 X1 A Pin for high-rate oscillation.

29 to 32 P10 to P13 DGeneral-purpose input/output ports.

IN0 to IN3 Functions as trigger input pins of input capture channels 0 to 3. Use the

pins by setting as input ports.

MB90385 Series

(Continued)

* : MB90387, MB90F387 : X1A, X0A

MB90387S, MB90F387S: P36, P35

Pin No. Pin name Circuit

type Function

33 to 36 P14 to P17 GGeneral-purpose input/output ports. High-current output ports.

PPG0 to PPG3 Functions as output pin of PPG timers 01 and 23. Valid when output

setting is “enabled.”

37 P40 DGeneral-purpose input/output port.

SIN1 Serial data input pin for UART. Use the pin by setting as input port.

38 P41 DGeneral-purpose input/output port.

SCK1 Serial clock input pin for UART. Valid only when serial clock input/output

setting on UART is “enabled.”

39 P42 DGeneral-purpose input/output port.

SOT1 Serial data input pin for UART. Valid only when serial data input/output set-

ting on UART is “enabled.”

40 P43 DGeneral-purpose input/output port.

TX Transmission output pin for CAN. Valid only when output setting is

“enabled.”

41 P44 DGeneral-purpose input/output port.

RX Transmission output pin for CAN. Valid only when output setting is

“enabled.”

42 to 45 P30 to P33 D General-purpose input/output ports.

46 X0A* APin for low-rate oscillation.

P35* General-purpose input/output port.

47 X1A* APin for low-rate oscillation.

P36* General-purpose input/output port.

48 AVss Vss power source input pin for A/D converter.

MB90385 Series

■I/O CIRCUIT TYPE

(Continued)

Type Circuit Remarks

• High-rate oscillation feedback

resistor, approx.1 MΩ

• Low-rate oscillation feedback

resistor, approx.10 MΩ

• Hysteresis input with pull-up

resistor.

• Pull-up resistor, approx.50 kΩ

• Hysteresis input

• CMOS hysteresis input

• CMOS level output

• Standby control provided

• CMOS hysteresis input

• CMOS level output

• Shared for analog input pin

• Standby control provided

X1A

X0A

Clock input

Standby control signal

Vcc

RHysteresis input

Pch

Nch

Vcc

Vss

Digital output

Hysteresis input

Standby control

Pch

Nch

Vcc

Vss

Digital output

Hysteresis input

Standby control

Analog input

MB90385 Series

(Continued)

Type Circuit Remarks

• Hysteresis input with pull-down

resistor

• Pull-down resistor, approx. 50 kΩ

• FLASH product is not provided with

pull-down resistor.

• CMOS hysteresis input

• CMOS level output (high-current

output)

• Standby control provided

Vss

RHysteresis input

Pch

Nch

Vcc

Vss

High-current output

Hysteresis input

Standby control

MB90385 Series

■HANDLING DEVICES

•

••

• Do Not Exceed Maximum Rating (preventing “latch up”)

• On a CMOS IC, latch-up may occur when applying a voltage higher than Vcc or a voltage lower than Vss to

input or output pin, which has no middle or high withstand voltage. Latch-up may also occur when a voltage

exceeding maximum rating is applied across Vcc and Vss.

• Latch-up causes drastic increase of power current, which may lead to destruction of elements by heat. Extreme

caution must be taken not to exceed maximum rating.

• When tur ning on and off analog power source, take extra care not to apply an analog power voltages (AVcc

and AVR) and analog input voltage that are higher than digital power voltage (Vcc).

•

••

• Handling Unused Pins

• Leaving unused input pins open may cause permanent destr uction by malfunction or latch-up. Apply pull-up

or pull-down process to the unused pins using resistors of 2 kΩ or higher . Leav e unused input pins open under

output status, or process as input pins if they are under input status.

•

••

• Using External Clock

• When using an e xternal clock, driv e only X0 pin and leav e X1 pin open. An e xample of using an external clock

is shown belo w.

•

••

• Notes When Using No Sub Clock

• If an oscillator is not connected to X0A and X1A pin, apply pull-down resistor to X0A pin and leave X1A pin open.

•

••

• About Power Supply Pins

• If two or more Vcc and Vss ex ist, the pins that should be at the same potential are connected to each other

inside the device. For reducing unwanted emissions and preventing malfunction of strobe signals caused by

increase of ground level, however , be sure to connect the Vcc and Vss pins to the power source and the ground

externally.

• Pay attention to connect a power supply to Vcc and Vss of MB90385 series device in a lowest-possible

impedance.

• Near pins of MB90385 series device, connecting a bypass capacitor is recommended at 0.1 µF across Vcc

and Vss.

•

••

• Crystal Oscillator Circuit

• Noises around X0 and X1 pins cause malfunctions on a MB90385 series device . Design a print circuit so that

X0 and X1 pins, an crystal oscillator (or a ceramic oscillator), and bypass capacitor to the g round become as

close as possible to each other. Furthermore, avoid wires to X0 and X1 pins crossing each other as much as

possible.

• Print circuit designing that surrounds X0 and X1 pins with grounding wires, which ensures stable operation,

is strongly recommended.

•

••

• Caution on Operations during PLL Cloc k Mode

• If the PLL clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit even

when there is no e xternal oscillator or external clock input is stopped. Perf ormance of this operation, howe v er,

cannot be guaranteed.

Open MB90385 series

• Using external clock

MB90385 Series

•

••

• Sequence of Turning on Power of A/D Converter and Applying Analog Input

• Be sure to turn on digital pow e r (Vcc) before applying signals to the A/D converter and applying analog input

signals (AN0 to AN7 pins).

• Be sure to turn off the power of A/D converter and analog input before turning off the digital power source.

• Be sure not to apply AVR exceeding AVcc when turning on and off. (No problems occur if analog and digital

power is turn ed on and off simultaneously.)

•

••

• Handling Pins When A/D Converter is Not Used

• If the A/D converter is not used, connect the pins under the following conditions: “AVcc=AVR=Vcc,” and

“AVss=Vss”

•

••

• Note on Turning on Power

• For preventing malfunctions on built-in step-down circuit, maintain a minimum of 50 µs of voltage rising time

(between 0.2 V and 2.7V) when turning on the power.

•

••

• Stabilization of supply voltage

• A sudden change in the supply voltage may cause the device to malfunction even within the specified VCC

supply voltage operating range. Therefore, the VCC supply voltage should be stabilized.

For reference, the supply voltage should be controlled so that VCC r ipple var iations (peak-to-peak values) at

commercial frequencies (50 Hz to 60 Hz) f all below 10% of the standard VCC supply voltage and the coefficient

of fluctuation does not exceed 0.1 V/ms at instantaneous power switching.

MB90385 Series

■BLOCK DIAGRAM

IN0 to IN3

RAM

ROM/FLASH

INT4 to INT7

PPG0 to PPG3

TIN0,TIN1

TOT0,TOT1

X0A,X1A

RST

X0,X1

SCK1

SOT1

SIN1

AVcc

AN0 to AN7

AVss

AVR

ADTG

UART1

CAN

Clock

control circuit

Clock timer

Time-base timer

Prescaler

CPU

F2MC-16LX core

16-bit

free-run timer

Input

capture

(4ch)

16-bit

PPG timer

(2ch)

16-bit

reload timer

(2ch)

DTP/External

interrupt

8/10-bit A/D

converter (8ch)

Internal data bus

MB90385 Series

■MEMORY MAP

MB90385 series allows specifying a memory access mode “single chip mode.”

1. Memory allocation of MB90385

MB90385 series model has 24-bit wide internal address bus and up to 24-bit bus of external address bus.

A maximum of 16 Mbyte memory space of external access memory is accessible.

2. Memory map

Note : When internal ROM is oper ating, F2MC-16LX allo ws view ing R OM data image on FF bank at upper-le v el of

00 bank. This function is called “mirroring ROM,” which allows effective use of C compiler small model.

F2MC-16LX assigns the same low order 16-bit address to FF bank and 00 bank, which allows referencing

table in ROM without specifying “far” using pointer.

For example, when accessing to “00C000H”, ROM data at “FFC000H” is accessed actually . However, because

ROM area of FF bank e xceeds 48 Kbytes, viewing all areas is not possible on 00 bank image. Because ROM

data of “FF4000H” to “FFFFFFH” is viewed on “004000H” to “00FFFFH” image, store a ROM data table in area

“FF4000H” to “FFFFFFH.”

FFFFFFH

FE0000H

010000H

003800H

004000H

000100H

0000C0H

000000H

MB90V495G

MB90F387/S

MB90387/S

001900H

000900H

FF0000H

(with ROM mirroring

function enabled)

Peripheral

RAM area

Extension IO

area

ROM area

(FF bank image)

ROM area

Address #1

Model

: Internal access memory

: Access disallowed

* : On MB90387/S or MB90F387/S, to read “FE0000H” to “FEFFFFH” is to read out

“FF0000H” to “FFFFFFH”.

ROM area*

MB90385 Series

■I/O MAP

(Continued)

Address Register

abbreviation Register Read/

Write Resource Initial value

000000H (Reserved area) *

000001HPDR1 Port 1 data register R/W Port 1 XXXXXXXXB

000002HPDR2 Port 2 data register R/W Port 2 XXXXXXXXB

000003HPDR3 Port 3 data register R/W Port 3 XXXXXXXXB

000004HPDR4 Port 4 data register R/W Port 4 XXXXXXXXB

000005HPDR5 Port 5 data register R/W Port 5 XXXXXXXXB

000006H

000010H (Reserved area) *

000011HDDR1 Port 1 direction data register R/W Port 1 00000000B

000012HDDR2 Port 2 direction data register R/W Port 2 00000000B

000013HDDR3 Port 3 direction data register R/W Port 3 000X0000B

000014HDDR4 Port 4 direction data register R/W Port 4 XXX00000B

000015HDDR5 Port 5 direction data register R/W Port 5 00000000B

000016H

00001AH (Reserved area) *

00001BHADER Analog input permission register R/W 8/10-bit

A/D converter 11111111B

00001CH

000025H (Reserved area) *

000026HSMR1 Serial mode register 1 R/W

UART1

00000000B

000027HSCR1 Serial control register 1 R/W, W 00000100B

000028HSIDR1/

SODR1 Serial input data register 1/ Serial

output data register 1 R, W XXXXXXXXB

000029HSSR1 Serial status data register 1 R, R/W 00001000B

00002AH (Reserved area) *

00002BHCDCR1 Communication prescaler control

00002CH

00002FH (Reserved area) *

000030HENIR DTP/External interrupt permission

DTP/External

interrupt

00000000B

000031HEIRR DTP/External interrupt permission

000032HELVR Detection level setting register R/W 00000000B

000033HR/W 00000000B

MB90385 Series

(Continued)

Address Register

abbreviation Register Read/

Write Resource Initial value

000034HADCS A/D control status register R/W

8/10-bit

A/D converter

00000000B

000035HR/W, W 00000000B

000036HADCR A/D data register W, R XXXXXXXXB

000037HR 00101XXXB

000038H

00003FH (Reserved area) *

000040HPPGC0 PPG0 operation mode control

8/16-bit

PPG timer 0/1

0X000XX1B

000041HPPGC1 PPG1 operation mode control

000042HPPG01 PPG0/1 count clock selection

000043H (Reserved area) *

000044HPPGC2 PPG2 operation mode control

8/16-bit

PPG timer 2/3

0X000XX1B

000045HPPGC3 PPG3 operation mode control

000046HPPG23 PPG2/3 count clock selection

000047H

00004FH (Reserved area) *

000050HIPCP0 Input capture data register 0 R

16-bit input/output

timer

XXXXXXXXB

000051HXXXXXXXXB

000052HIPCP1 Input capture data register 1 R XXXXXXXXB

000053HXXXXXXXXB

000054HICS01 Input capture control status register R/W 00000000B

000055HICS23 00000000B

000056HTCDT Timer counter data register R/W 00000000B

000057H00000000B

000058HTCCS Timer counter control status register R/W 00000000B

000059H (Reserved area) *

00005AHIPCP2 I nput capture data register 2 R 16-bit input/output

timer

XXXXXXXXB

00005BHXXXXXXXXB

00005CHIPCP3 Input capture data register 3 R XXXXXXXXB

00005DHXXXXXXXXB

MB90385 Series

(Continued)

Address Register

abbreviation Register Read/

Write Resource Initial value

00005EH

000065H (Reserved area) *

000066HTMCSR0

Timer control status register

R/W 16-bit reload timer 0 00000000B

000067HR/W XXXX0000B

000068HTMCSR1 R/W 16-bit reload timer 1 00000000B

000069HR/W XXXX0000B

00006AH

00006EH (Reserved area) *

00006FHROMM ROM mirroring function selection

function selection

module XXXXXXX1B

000070H

00007FH (Reserved area) *

000080HBVALR Message buffer enabling register R/W CAN controller 00000000B

000081H (Reserved area) *

000082HTREQR Send request register R/W CAN controller 00000000B

000083H (Reserved area) *

000084HTCANR Send cancel register W CAN controller 00000000B

000085H (Reserved area) *

000086HTCR Send completion register R/W CAN controller 00000000B

000087H (Reserved area) *

000088HRCR Receive completion register R/W CAN controller 00000000B

000089H (Reserved area) *

00008AHRRTRR Receive RTR register R/W CAN controller 00000000B

00008BH (Reserved area) *

00008CHROVRR Receive overrun register R/W CAN controller 00000000B

00008DH (Reserved area) *

00008EHRIER Receive completion interrupt

permission register R/W CAN controller 00000000B

00008FH

00009DH (Reserved area) *

00009EHPACSR Address detection control register R/W Address matching

detection function 00000000B

00009FHDIRR Delay interrupt request generation/

release register R/W Delay interrupt

generation module XXXXXXX0B

MB90385 Series

(Continued)

Address Register

abbreviation Register Read/

Write Resource Initial value

0000A0HLPMCR Lower power consumption mode

control register W,R/W Lower power

consumption mode 00011000B

0000A1HCKSCR Clock selection register R,R/W Clock 11111100B

0000A2H

0000A7H (Reserved area) *

0000A8HWDTC Watchdog timer control register R,W Watchdog timer XXXXX111B

0000A9HTBTC Time-base timer control register R/W,W Time-base timer 1XX00100B

0000AAHWTC Clock timer control register R,R/W Clock timer 1X001000B

0000ABH

0000ADH (Reserved area) *

0000AEHFMCS Flash memory control status

memory 000X0000B

0000AFH (Reserved area) *

0000B0HICR00 Interrupt control register 00

R/W Interrupt controller

00000111B

0000B1HICR01 Interrupt control register 01 00000111B

0000B2HICR02 Interrupt control register 02 00000111B

0000B3HICR03 Interrupt control register 03 00000111B

0000B4HICR04 Interrupt control register 04 00000111B

0000B5HICR05 Interrupt control register 05 00000111B

0000B6HICR06 Interrupt control register 06 00000111B

0000B7HICR07 Interrupt control register 07 00000111B

0000B8HICR08 Interrupt control register 08 00000111B

0000B9HICR09 Interrupt control register 09 00000111B

0000BAHICR10 Interrupt control register 10 00000111B

0000BBHICR11 Interrupt control register 11 00000111B

0000BCHICR12 Interrupt control register 12 00000111B

0000BDHICR13 Interrupt control register 13 00000111B

0000BEHICR14 Interrupt control register 14 00000111B

0000BFHICR15 Interrupt control register 15 00000111B

0000C0H

0000FFH (Reserved area) *

MB90385 Series

(Continued)

Address Register

abbreviation Register Read/

Write Resource Initial value

001FF0H

PADR0

Detection address setting register 0

(low-order)

R/W

Address matching

detection function

XXXXXXXXB

001FF1HDetection address setting register 0

(middle-order) XXXXXXXXB

001FF2HDetection address setting register 0

(high-order) XXXXXXXXB

001FF3H

PADR1

Detection address setting register 1

(low-order)

R/W

XXXXXXXXB

001FF4HDetection address setting register 1

(middle-order) XXXXXXXXB

001FF5HDetection address setting register 1

(high-order) XXXXXXXXB

003900HTMR0/

TMRLR0 16-bit timer register 0/16-bit reload

003901HXXXXXXXXB

003902HTMR1/

TMRLR1 16-bit timer register 1/16-bit reload

003903HXXXXXXXXB

003904H

00390FH (Reserved area) *

003910HPRLL0 PPG0 reload register L R/W

8/16-bit PPG timer

XXXXXXXXB

003911HPRLH0 PPG0 reload register H R/W XXXXXXXXB

003912HPRLL1 PPG1 reload register L R/W XXXXXXXXB

003913HPRLH1 PPG1 reload register H R/W XXXXXXXXB

003914HPRLL2 PPG2 reload register L R/W XXXXXXXXB

003915HPRLH2 PPG2 reload register H R/W XXXXXXXXB

003916HPRLL3 PPG3 reload register L R/W XXXXXXXXB

003917HPRLH3 PPG3 reload register H R/W XXXXXXXXB

003918H

00392FH (Reserved area) *

003930H

003BFFH (Reserved area) *

003C00H

003C0FHRAM (General-purpose RAM)

MB90385 Series

(Continued)

Address Register

abbreviation Register Read/

Write Resource Initial value

003C10H

003C13HIDR0 ID register 0 R/W

CAN controller

XXXXXXXXB

003C14H

003C17HIDR1 ID register 1 R/W XXXXXXXXB

XXXXXXXXB

003C18H

003C1BHIDR2 ID register 2 R/W XXXXXXXXB

XXXXXXXXB

003C1CH

003C1FHIDR3 ID register 3 R/W XXXXXXXXB

XXXXXXXXB

003C20H

003C23HIDR4 ID register 4 R/W XXXXXXXXB

XXXXXXXXB

003C24H

003C27HIDR5 ID register 5 R/W XXXXXXXXB

XXXXXXXXB

003C28H

003C2BHIDR6 ID register 6 R/W XXXXXXXXB

XXXXXXXXB

003C2CH

003C2FHIDR7 ID register 7 R/W XXXXXXXXB

XXXXXXXXB

003C30H

003C31HDLCR0 DLC register 0 R/W XXXXXXXXB

XXXXXXXXB

003C32H

003C33HDLCR1 DLC register 1 R/W XXXXXXXXB

XXXXXXXXB

003C34H

003C35HDLCR2 DLC register 2 R/W XXXXXXXXB

XXXXXXXXB

003C36H

003C37HDLCR3 DLC register 3 R/W XXXXXXXXB

XXXXXXXXB

003C38H

003C39HDLCR4 DLC register 4 R/W XXXXXXXXB

XXXXXXXXB

003C3AH

003C3BHDLCR5 DLC register 5 R/W XXXXXXXXB

XXXXXXXXB

MB90385 Series

(Continued)

Address Register

abbreviation Register Read/

Write Resour ce Initial value

003C3CH

003C3DHDLCR6 DLC register 6 R/W

CAN controller

XXXXXXXXB

003C3EH

003C3FHDLCR7 DLC register 7 R/W XXXXXXXXB

XXXXXXXXB

003C40H

003C47HDTR0 Data register 0 R/W XXXXXXXXB

XXXXXXXXB

003C48H

003C4FHDTR1 Data register 1 R/W XXXXXXXXB

XXXXXXXXB

003C50H

003C57HDTR2 Data register 2 R/W XXXXXXXXB

XXXXXXXXB

003C58H

003C5FHDTR3 Data register 3 R/W XXXXXXXXB

XXXXXXXXB

003C60H

003C67HDTR4 Data register 4 R/W XXXXXXXXB

XXXXXXXXB

003C68H

003C6FH

DTR5 Data register 5 R/W XXXXXXXXB

XXXXXXXXB

003C70H

003C77HDTR6 Data register 6 R/W XXXXXXXXB

XXXXXXXXB

003C78H

003C7FHDTR7 Data register 7 R/W XXXXXXXXB

XXXXXXXXB

003C80H

003CFFH (Reserved area) *

003D00H

003D01HCSR Control status register R/W, R CAN controller 0XXXX001B

00XXX000B

003D02HLEIR Last event display register R/W 000XX000B

003D03H (Reserved area) *

003D04H

003D05HRTEC Send/receive error counter R

CAN controller

00000000B

003D06H

003D07HBTR Bit timing register R/W 11111111B

X1111111B

003D08HIDER IDE register R/W XXXXXXXXB

003D09H (Reserved area) *

003D0AHTRTRR Send RTR register R/W CAN controller 00000000B

MB90385 Series

(Continued)

Initial values :

0 : Initial value of this bit is “0.”

1 : Initial value of this bit is “1.”

X : Initial value of this bit is undefined.

* : “Reserved area” should not be written anything. Result of reading from “Reserved area” is undefined.

Address Register

abbreviation Register Read/

Write Resource Initial value

003D0BH (Reserved area) *

003D0CHRFWTR Remote frame receive wait register R/W CAN controller XXXXXXXXB

003D0DH (Reserved area) *

003D0EHTIER Send completion interrupt

permission register R/W CAN controller 00000000B

003D0FH (Reserved area) *

003D10H

003D11HAMSR Acceptance mask selection register R/W CAN controller XXXXXXXXB

XXXXXXXXB

003D12H

003D13H (Reserved area) *

003D14H

003D17HAMR0 Acceptance mask register 0 R/W

CAN controller

XXXXXXXXB

003D18H

003D1BHAMR1 Acceptance mask register 1 R/W XXXXXXXXB

XXXXXXXXB

003D1CH

003DFFH (Reserved area) *

003E00H

003EFFH (Reserved area) *

003FF0H

003FFFH (Reserved area) *

MB90385 Series

■INTERRUPT SOURCES, INTERRUPT VECTORS, AND INTERRUPT CONTROL REGISTERS

(Continued)

Interrupt sour ce EI2OS

readiness Interrupt vector Interrupt control register Priority*3

Number Address ICR Address

Reset #08 08HFFFFDCHHigh

INT 9 instruction #09 09HFFFFD8H↑

Exceptional treatment #10 0AHFFFFD4H

CAN controller reception

completed (RX) ×#11 0BHFFFFD0H

ICR00 0000B0H*1

CAN controller transmission

completed (TX) / Node status

transition (NS) ×#12 0CHFFFFCCH

Reserved #13 0DHFFFFC8HICR01 0000B1H

Reserved #14 0EHFFFFC4H

CAN wakeup ∆#15 0FHFFFFC0HICR02 0000B2H*1

Time-base timer #16 10HFFFFBCH

16-bit reload timer 0 ∆#17 11HFFFFB8HICR03 0000B3H*1

8/10-bit A/D converter ∆#18 12HFFFFB4H

16-bit free-run timer overflow ∆#19 13HFFFFB0HICR04 0000B4H*1

Reserved #20 14HFFFFACH

Reserved #21 15HFFFFA8HICR05 0000B5H*2

PPG timer ch0, ch1 underflow ×#22 16HFFFFA4H

Input capture 0-input ∆#23 17HFFFFA0HICR06 0000B6H*1

External interrupt (INT4/INT5) ∆#24 18HFFFF9CH

Input capture 1-input ∆#25 19HFFFF98HICR07 0000B7H*1

PPG timer ch2, ch3 underflow ×#26 1AHFFFF94H

External interrupt (INT6/INT7) ∆#27 1BHFFFF90HICR08 0000B8H*1

Clock timer ∆#28 1CHFFFF8CH

Reserved #29 1DHFFFF88HICR09 0000B9H*1

Input capture 2-input

Input capture 3-input ×#30 1EHFFFF84H

Reserved #31 1FHFFFF80HICR10 0000BAH*1

Reserved #32 20HFFFF7CH

Reserved #33 21HFFFF78HICR11 0000BBH*1

Reserved #34 22HFFFF74H

Reserved #35 23HFFFF70HICR12 0000BCH*1↓

16-bit reload timer 1 #36 24HFFFF6CHLow

MB90385 Series

(Continued)

: Available

: Unavailable

: Available El2OS function is provided.

∆ : Available when a cause of interrupt sharing a same ICR is not used.

*1 : • Peripheral functions sharing an ICR register have the same interrupt level.

• If peripheral functions share an ICR register, only one function is available when using expanded intelligent

I/O service.

• If peripheral functions share an ICR register , a function using expanded intelligent I/O service does not allow

interrupt by another function.

*2 : Only 16-bit reload timer is ready for EI2OS . Because PPG is not ready for EI2OS , disable PPG interrupt when

using EI2OS with 16-bit reload timer.

*3 : Priority when two or more interrupts of a same level occur simultaneously.

Interrupt source EI2OS

readiness Interrupt vector Interrupt control register Priority*3

Number Address ICR Address

UART1 reception completed #37 25HFFFF68HICR13 0000BDH*1High

UART1 transmission completed ∆#38 26HFFFF64H↑

Reserved #39 27HFFFF60HICR14 0000BEH*1

Reserved #40 28HFFFF5CH

Flash memory #41 29HFFFF58HICR15 0000BFH*1

Delay interrupt generation

module #42 2AHFFFF54H↓

Low

MB90385 Series

■PERIPHERAL RESOURCES

1. I/O Ports

The I/O ports are used as general-pur pose input/output ports (parallel I/O por ts). The MB60385 ser ies model

is provided with 5 ports (34 inputs). The ports function as input/output pins for peripheral functions also.

•

••

• I/O port functions

An I/O port, using port data resister (PDR), outputs the output data to I/O pin and input a signal input to I/O port.

The port direction register (DDR) specifies direction of input/output of I/O pins on a bit-by-bit basis.

The following summarizes functions of the ports and sharing peripheral functions :

• Port 1 : General-purpose input/output port, used also for PPG timer output and input capture inputs.

• P ort 2 : General-purpose input/output port, used also for reload timer input/output and e xternal interrupt input.

• Port 3 : General-purpose input/output port, used also for A/D converter activation trigger pin.

• Port 4 : General-purpose input/output port, used also for UART input/output and CAN controller send/receive

pin.

• Port 5 : General-purpose input/output port, used also analog input pin.

•

••

• Port 1 pins block diagram (single-chip mode)

•

••

• Port 1 registers (single-chip mode)

• Port 1 registers include port 1 data register (PDR1) and port 1 direction register (DDR1).

• The bits configuring the register correspond to port 1 pins on a one-to-one basis.

Relation between port 1 registers and pins

Port name Bits of register and corresponding pins

Port 1 PDR1, DDR1 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

Corresponding pins P17 P16 P15 P14 P13 P12 P11 P10

Pch

Nch

Peripheral

function input Peripheral

function output

Port data register (PDR)

PDR read

Output latch

PDR write

Peripheral function

output permission

Port direction register (DDR)

Direction

latch

DDR write

DDR read Standby control (SPL=1)

Standby control : Control among Stop mode (SPL=1), Time-base timer mode (SPL=1), and clock mode

(SPL=1).

Internal data bus

MB90385 Series

•

••

• Port 2 pins block diagram (general-purpose input/output port)

•

••

• Port 2 registers

• Port 2 registers include port 2 data register (PDR2) and port 2 direction register (DDR2).

• The bits configuring the register correspond to port 2 pins on a one-to-one basis.

Relation between port 2 registers and pins

Port name Bits of register and corresponding pins

Port 2 PDR2,DDR2 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

Corresponding pins P27 P26 P25 P24 P23 P22 P21 P20

Pch

Nch

Peripheral

function input Peripheral

function output

Port data register (PDR)

PDR read

Output latch

PDR write

Peripheral function

output permission

Port direction register (DDR)

Direction

latch

DDR write

DDR read Standby control (SPL=1)

Standby control : Control among Stop mode (SPL=1), Time-base timer mode (SPL=1), and clock mode

(SPL=1).

Internal data bus

MB90385 Series

•

••

• Port 3 pins block diagram (general-purpose input/output port)

•

••

• Port 3 registers

• Port 3 registers include port 3 data register (PDR3) and port 3 direction register (DDR3).

• The bits configuring the register correspond to port 3 pins on a one-to-one basis.

Relation between port 3 registers and pins

* : P35 and P36 do not exist on MB90387and MB90F387.

Port name Bits of register and corresponding pins

Port 3 PDR3, DDR3 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

Corresponding pins P37 P36* P35* P33 P32 P31 P30

Pch

Nch

Peripheral

function input Peripheral

function output

Port data register (PDR)

PDR read

Output latch

PDR write

Peripheral function

output permission

Port direction register (DDR)

Direction

latch

DDR write

DDR read Standby control (SPL=1)

Internal data bus

Standby control : Control among Stop mode (SPL=1), Time-base timer mode (SPL=1), and clock mode

(SPL=1).

MB90385 Series

•

••

• Port 4 pins block diagram

•

••

• Port 4 registers

• Port 4 registers include port 4 data register (PDR4) and port 4 direction register (DDR4).

• The bits configuring the register correspond to port 4 pins on a one-to-one basis.

Relation between port 4 registers and pins

Port name Bits of register and corresponding pins

Port 4 PDR4, DDR4 bit4 bit3 bit2 bit1 bit0

Corresponding pins P44 P43 P42 P41 P40

Pch

Nch

Peripheral

function input Peripheral

function output

Port data register (PDR)

PDR read

Output latch

PDR write

Peripheral function

output permission

Port direction register (DDR)

Direction

latch

DDR write

DDR read Standby control (SPL=1)

Internal data bus

Standby control : Control among Stop mode (SPL=1), Time-base timer mode (SPL=1), and clock mode

(SPL=1).

MB90385 Series

•

••

• Port 5 pins block diagram

•

••

• Port 5 registers

• Port 5 registers include por t 5 data register (PDR5), port 5 direction register (DDR5), and analog input per-

mission register (ADER).

• Analog input permission register (ADER) allows or disallows input of analog signal to the analog input pin.

• The bits configuring the register correspond to port 5 pins on a one-to-one basis.

Relation between port 5 registers and pins

Port name Bits of register and corresponding pins

Port 5

PDR5, DDR5 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

ADER ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0

Corresponding pins P57 P56 P55 P54 P53 P52 P51 P50

ADER

Pch

Nch

Standby control: Control among Stop mode (SPL=1), Time-base timer mode (SPL=1), and clock mode

(SPL=1).

Port data register (PDR)

PDR read

Output latch

PDR write Pin

Port direction register (DDR)

Direction

latch

DDR write

DDR read Standby control (SPL=1)

Internal data bus

Analog input

MB90385 Series

2. Time-Base Timer

The time-base time is an 18-bit free-run counter (time-base timer counter) that counts up in synchronization with

the main clock (dividing main oscillation clock by 2).

• Four choices of interval time are selectable, and generation of interrupt request is allowed for each interval time.

• Provides operation clock signal to oscillation stabilizing wait timer and peripheral functions.

•

••

• Interval timer function

• When the counter of time-base timer reaches an interval time specified by interval time selection bit

(TBTC:TBC1, TBC0), an ov erflow (carrying-ov er) occurs (TBTC: TBOF=1) and interrupt request is generated.

• If an interrupt by overflow is permitted (TBTC: TBIE=1), an interrupt is generated when overflow occurs (TBTC:

TBOF=1).

• The following four interval time settings are selectable :

Interval time of time-base timer

HCLK: Oscillation clock

Values in parentheses “( )” are those under operation of 4-MHz oscillation clock.

Count clock Interval time

2/HCLK (0.5 µs)

212/HCLK (Approx. 1.0 ms)

214/HCLK (Approx. 4.1 ms)

216/HCLK (Approx. 16.4 ms)

219/HCLK (Approx. 131.1 ms)

MB90385 Series

•

••

• Time-base timer block diagram

Actual interrupt request number of time-base timer is as follows:

Interrupt request number: #16 (10H)

21/HCLK

CKSCR : MCS = 1 0 1

CKSCR : SCS = 0 1 2

OF OF OF OF

TBIE TBOF TBC1 TBC0TBR

2122

211 212 213 214 215 216 217 218

210

· · · · · ·

To PPG timer

Time-base timer counter

To watchdog

timer

To clock controller

oscillation stabilizing

wait time selector

Interval timer

selector

Counter-

clear circuit

Power-on reset

Stop mode

TBOF clear TBOF set

Time-base timer control register

(TBTC) Re-

served

OF : Overflow

HCLK : Oscillation clock

*1 : Switch machine clock from main clock to PLL clock.

*2 : Switch machine clock from sub clock to main clock.

Time-base timer interrupt signal

MB90385 Series

3. Watchdog Timer

The watchdog timer is a 2-bit counter that uses time-base timer or clock timer as count clock. If the counter is

not cleared within an interval time, CPU is reset.

•

••

•Watchdog timer functions

• The watchdog timer is a timer counter that prevents runaway of a program. Once a watchdog timer is activated,

the counter of watchdog timer must always be cleared within a specified time of inter val. If specified inter val

time elapses without clearing the counter of a watchdog timer, CPU resetting occurs. This is the function of a

watchdog timer.

• The interval time of a watchdog timer is determined by a cloc k cycle, which is input as a count clock. W atchdog

resetting occurs between a minimum time and a maximum time specified.

• The output target of a clock source is specified b y the watchdog cloc k selection bit (WTC: WDCS) in the clock

timer control register.

• Inter val time of a watchdog timer is specified by the time-base timer output selection bit/clock timer output

selection bit (WDTC: WT1, WT0) in the watchdog timer control register.

Interval timer of watchdog timer

HCLK: Oscillation clock ( 4 MHz) , CSCLK: Sub clock (8.192 kHz)

Notes: • If the time-base timer is cleared when watchdog timer count clock is used as time base timer output

(carry-over signal), watchdog reset time may become longer.

• When using the sub clock as machine clock, be sure to specify watchdog timer cloc k source selection bit

(WDCS) in clock timer control register (WTC) at “0,” selecting output of clock timer.

Min Max Clock cycle Min Max Clock cycle

Approx. 3.58 ms Approx. 4.61 ms 214±211

/HCLK Approx. 0.457 s Approx. 0.576 s 212±29

/SCLK

Approx. 14.33 ms Approx. 18.3 ms 216±213

/HCLK Approx. 3.584 s Approx. 4.608 s 215±212

/SCLK

Approx. 57.23 ms Approx. 73.73 ms 218±215

/HCLK Approx. 7.168 s Approx. 9.216 s 216±213

/SCLK

Approx.

458.75 ms Approx.

589.82 ms 221±218

/HCLK Approx.

14.336 s Approx.

18.432 s 217±214

/SCLK

MB90385 Series

•

••

• Watchdog timer block diagram

2122 211 212 213 214 215 216 217 218

210

SRST WT1 WT0

WTE

PONR WRST

ERST

WDCS

2122 28 29210 211 212 213 214 215

Watchdog timer control register(WDTC) Clock timer control register (WTC)

Watchdog timer

Reset occurs

Shift to sleep mode

Shift to time-base

timer mode

Shift to clock mode

Shift to stop mode

Counter

clear control

circuit Count clock

selector 2-bit

counter

Watchdog

reset

generation

circuit

Internal reset

generation

circuit

Clear

Main clock

(dividing HCLK by 2)

Sub clock

SCLK

Time-base timer counter

Clock counter

HCLK: Oscillation clock

SCLK: Sub clock

Activate

MB90385 Series

4. 16-bit Input/Output Timer

The 16-bit input/output timer is a compound module composed of 16-bit free-run timer , (1 unit) and input capture

(2 units, 4 input pins). The timer, using the 16-bit free-run timer as a basis, enables measurement of cloc k cycle

of an input signal and its pulse width.

•

••

• Configuration of 16-bit input/output timer

The 16-bit input/output timer is composed of the following modules:

• 16-bit free-run timer (1 unit)

• Input capture (2 units, 2 input pins per unit)

•

••

• Functions of 16-bit input/output timer

(1) Functions of 16-bit free-run timer

The 16-bit free-run timer is composed of 16-bit up counter, timer counter control status register, and prescaler.

The 16-bit up counter increments in synchronization with dividing ratio of machine clock.

• Count clock is set among four types of machine clock dividing rates.

• Generation of interrupt is allowed by counter value overflow.

• Activation of expanded intelligent I/O service (EI2OS) is allowed by interrupt generation.

• Counter value of 16-bit free-run timer is cleared to “0000H” by either resetting or software-clearing with timer

count clear bit (TCCS: CLR).

• Counter value of 16-bit free-run timer is output to input capture, which is available as base time for capture

operation.

(2) Functions of input capture

The input capture, upon detecting an edge of a signal input to the input pin from e xternal device, stores a counter

value of 16-bit free-run timer at the time of detection into the input capture data register. The function includes

the input capture data registers corresponding to f our input pins , input capture control status register, and edge

detection circuit.

• Rising edge, falling edge, and both edges are selectable for detection.

• Generating interrupt on CPU is allowed by detecting an edge of input signal.

• Expanded intelligent I/O service (EI2OS) is activated by interrupt generation.

• The four input capture input pins and input capture data registers allows monitoring of a maximum of four events.

MB90385 Series

•

••

• 16-bit input/output timer block diagram

•

••

• 16-bit free-run timer

Counter value of 16-bit free-run timer is used as reference time (base time) of input capture.

•

••

• Input capture

Input capture detects rising edge, f alling edge or both edges and retains a counter value of 16-bit free-run timer .

Detection of edge on input signal is allowed to generate interrupt.

•

••

• 16-bit free-run timer block diagram

Internal data bus

Input capture Special-

purpose bus 16-bit free-run

timer

IVF IVFE CLK2 CLK1 CLK0STOP CLR

CLK STOP CLR

Re-

served

16-bit free-run timer

Timer counter data register

(TCDT) Output counter value

to input capture

Prescaler

Timer counter

control status register

(TCCS)

Free-run timer

interrupt request

φ : Machine clock

OF : Overflow

Internal data bus

MB90385 Series

•

••

• Detailed pin assignment on block diagram

The 16-bit input/output timer includes a 16-bit free-run timer. Interrupt request number of the 16-bit free-run

timer is as follows:

Interrupt request number: 19 (13H)

•

••

• Prescaler

The prescaler divides a machine clock and provides a counter clock to the 16-bit up counter. Dividing ratio of

the machine clock is specified by timer counter control status register (TCCS) among four values.

•

••

• Timer counter data register (TCDT)

The timer counter data register is a 16-bit up counter . A current counter v alue of the 16-bit free-run timer is read.

Writing a value during halt of the counter allows setting an arbitrary counter value.

MB90385 Series

•

••

•Input capture block diagram

EG00EG01EG10EG11ICE0ICE1ICP0ICP1

IN1

IN0

EG00EG01EG10EG11ICE0ICE1ICP0ICP1

IN3

IN2

16-bit free-run timer

Input capture data register 3 (IPCP3)

Input capture data register 2 (IPCP2)

Edge detection

circuit

Input capture control

status register

(ICS23)

Input capture

interrupt request

Input capture control

status register

(ICS01)

Input capture data register 1 (IPCP1)

Edge detection

circuit

Input capture data register 0 (IPCP0)

Internal data bus

MB90385 Series

5. 16-bit Reload Timer

The 16-bit reload timer has the following functions:

• Count clock is selectable among 3 internal clocks and external event clock.

• Activation trigger is selectable between software trigger and external trigger.

• Generation of CPU interrupt is allow ed upon occurrence of underflo w on 16-bit timer register. A v ailab le as an

interval timer using the interrupt function.

• When underflow of 16-bit timer register (TMR) occurs, one of two reload modes is selectable between one-

shot mode that halts counting operation of TMR, and reload mode that reloads 16-bit reload register value to

TMR, continuing TMR counting operation.

• The 16-bit reload timer is ready for expanded intelligent I/O service (EI2OS).

• MB90385 series device has 2 channels of built-in 16-bit reload timer.

•

••

• Operation mode of 16-bit reload timer

•

••

• Internal clock mode

• The 16-bit reload timer is set to internal clock mode, by setting count clock selection bit (TMCSR: CSL1, CSL0)

to “00B”, “01B”, “10B”.

• In the internal clock mode, the counter decrements in synchronization with the internal clock.

• Three types of count clock cycles are selectable by count clock selection bit (TMCSR: CSL1, CSL0) in timer

control status register.

• Edge detection of software trigger or external trigger is specified as an activation trigger.

Count clock Activation trigger Operation upon underflow

Internal clock mode Software trigger, external trigger One-shot mode, reload mode

Event count mode Software trigger One-shot mode, reload mode

MB90385 Series

•

••

• 16-bit reload timer block diagram

CSL1 CSL0

MOD2 MOD1 OUTLOUTE

RELD INTE

CNTE TRG

MOD0

TMR

TMRLR

TOT

TIN

CLK

Internal data bus

16-bit reload register Reload

control

circuit

Reload signal

16-bit timer register UF

Wait signal

Count clock generation

circuit

Machine

clock

φPrescaler Gate

input Valid

clock

decision

circuit Output to internal

peripheral

functions

Output control

circuit

Internal

clock

Clear

Pin Pin

Input

control

circuit

Clock

selector

Output signal

generation

circuit

External clock

Select function

Select

signal Operation control

circuit generation

circuit

Timer control status register (TMCSR) Interrupt request

output

MB90385 Series

6. Clock Timer Outline

The clock timer is a 15-bit free-run counter that increments in synchronization with sub clock.

• Interval time is selectable among 7 choices, and generation of interrupt request is allowed for each interval.

• Provides operation clock to the subclock oscillation stabilizing wait timer and watchdog timer.

• Always uses subclock as a count clock regardless of settings of clock selection register (CKSCR).

•

••

• Interval timer function

• In the clock timer, a bit corresponding to the interv al time overflows (carry-over) when an interval time, which

is specified by interval time selection bit, is reached. Then overflow flag bit is set (WTC: WTOF=1).

• If an interrupt by overflow is permitted (WTC: WTIE=1), an interrupt request is generated upon setting an

overflow flag bit.

• Interval time of clock timer is selectable among the following seven choices :

•

••

• Interval time of clock timer

SCLK: Sub clock frequency

Values in parentheses “( )” are calculation when operating with 8.192 kHz clock.

Sub clock cycle Interval time

SCLK (122 µs)

28/SCLK (31.25 ms)

29/SCLK (62.5 ms)

210/SCLK (125 ms)

211/SCLK (250 ms)

212/SCLK (500 ms)

213/SCLK (1.0 s)

214/SCLK (2.0 s)

MB90385 Series

•

••

• Cloc k timer block diagram

Actual interrupt request number of clock timer is as follows :

Interrupt request number : #28 (1CH)

•

••

• Cloc k timer counter

A 15-bit up counter that uses sub clock (SCLK) as a count clock.

•

••

• Counter clear circuit

A circuit that clears the clock timer counter.

WTOF

WTR

WTC1 WTC0WTC2

WDCS

SCE

WTIE

2129

210 211 212 213 214 215

SCLK

OF OF

OFOF OF

OF OF

To watchdog

timer

Clock timer counter

Power-on reset

Shift to hardware standby

Shift to stop mode To sub clock oscillation

stabilizing wait time

Interval timer

selector

Clock time interrupt

OF : Overflow

SCLK : Sub clock Clock timer control register (WTC)

Counter

clear

circuit

MB90385 Series

7. 8/16-bit PPG Timer Outline

The 8/16-bit PPG timer is a 2-channel reload timer module (PPG0 and PPG1) that allows outputting pulses of

arbitrary cycle and duty cycle. Combination of the two channels allows selection among the f ollowing operations:

• 8-bit PPG output 2-channel independent operation mode

• 16-bit PPG output operation mode

• 8-bit and 8-bit PPG output operation mode

MB90385 series device has two 8/16-bit built-in PPG timers. This section describes functions of PPG0/1. PPG2/

3 have the same functions as those of PPG0/1.

•

••

• Functions of 8/-16-bit PPG timer

The 8/-16-bit PPG timer is composed of f our 8-bit reload register (PRLH0/PRLL0, PRLH1/PRLL1) and two PPG

down counters (PCNT0, PCNT1).

• Widths of “H” and “L” in output pulse are specifiable independently. Cycle and duty factor of output pulse is

specifiabl e arbitrarily.

• Count clock is selectable among 6 internal clocks.

• The timer is usable as an interval timer, by generating interrupt requests for each interval.

• The time is usable as a D/A converter, with an external circuit.

MB90385 Series

•

••

• 8/16-bit PPG timer 0 block diagram

PPG0

CLK

PEN0

PE0

PIE0 PUF0

PCS2 PCS0 PCM2 PCM1 PCM0PCS1

Re-

served

Re-

versed

“H” level side data bus

“L” level side data bus

PPG0 reload

Interrupt

request output*

Operation mode

control signal

Select

signal

Reload register

L/H selector

PPLH0

(“H” level side) PPLL0

(“L” level side)

PPG0 temporary

buffer 0(PRLBH0)

Count start

value Reload Clear

PPG0 down counter

(PCNT0) Underflow

PPG1 underflow

PPG0 underflow

(To PPG1)

Pulse selector

PPG0

output latch

PPG output control circuit

Time-base timer output

(512/HCLK)

Peripheral clock (1/φ)

Peripheral clock (2/φ)

Peripheral clock (4/φ)

Peripheral clock (8/φ)

Peripheral clock (16/φ)Count clock

selector

Select signal

PPG0/1 count clock selection register (PPG01)

− : Undefined

Reserved : Reserved bit

HCLK : Oscillation clock frequency

φ : Machine clock frequency

* : Interrupt output of 8/16-bit PPG timer 0 is incorporated into one by the OR circuit against

interrupt output of 8/16-bit PPG timer 1.

MB90385 Series

•

••

• 8/16-bit PPG timer 1 block diagram

CLK MD0

PEN1

PE1

PIE1 PUF1

MD1 MD0

PCS2 PCS0 PCM2 PCM1 PCM0PCS1

PPG1

Re-

versed

Re-

served

“H” level side data bus

“L” level side data bus

PPG1 reload

Interrupt

request output*

Select signal

Reload selector

L/H selector

PRLH1

(“H” level side) PRLL1

(“L” level side)

PPG1 temporary

buffer 0(PRLBH1)

Count start

value Reload Clear

PPG1 down

counter (PCNT1)

Under-

flow PPG1

output latch

PPG output control circuit

Time-base timer output

(512/HCLK)

Peripheral clock (1/φ)

Peripheral clock (2/φ)

Peripheral clock (4/φ)

Peripheral clock (8/φ)

Peripheral clock (16/φ)

Count clock

selector Select signal

PPG0/1 count clock selection register (PPG01)

− : Undefined

Reserved : Reserved bit

HCLK : Oscillation clock frequency

φ : Machine clock frequency

* : Interrupt output of 8/16-bit PPG timer 1 is incorporated into one by the OR circuit against

interrupt output of 8/16-bit PPG timer 0.

Operation

mode

control

signal

PPG1 underflow

(To PPG0)

PPG0 underflow

(From PPG0)

MB90385 Series

8. Delay Interrupt Generation Module Outline

The delay interr upt generation module is a module that generates interrupts for switching tasks. Generation of

a hardware interrupt request is performed by software.

•

••

• Delay interrupt generation module outline

Using the dela y interrupt generation module, hardware interrupt request is generated and released b y software .

Delay interrupt generation module outline

•

••

• Delay interrupt generation module block diagram

•

••

• Interrupt request latch

A latch that retains settings on delay interrupt request generation/release register (generation or release of dela y

interrupt request).

•

••

• Delay interrupt request generation/release register (DIRR)

Generates or releases delay interrupt request.

•

••

• Interrupt number

An interrupt number used in delay interrupt generation module is as follows:

Interrupt number: #42 (2AH)

Function and control

Cause of interrupt

Set “1” in R0 bit of delay interrupt request generation/release register (DIRR: R0=1),

generating an interrupt request.

Set “0” in R0 bit of delay interrupt request generation/release register (DIRR: R0=0),

releasing an interrupt request.

Interrupt number #42 (2AH)

Interrupt control No setting of permission register is provided.

Interrupt flag Retained in DIRR: R0 bit

EI2OS Not ready for expanded intelligent I/O service.

Internal data bus

Delay interrupt request generation/release

− : Not defined

S Interrupt request

R Latch Interrupt

request signal

MB90385 Series

9. DTP/External Interrupt and CAN Wakeup Outline

DTP/e xternal interrupt transf ers an interrupt request generated by an external peripheral de vice or a data trans-

mission request to CPU, generating exter nal interr upt request and activating expanded intelligent I/O service.

Input RX of CAN controller is used as external interrupt input.

•

••

• DTP/external interrupt and CAN wakeup function

An interrupt request input from external peripheral device to e xternal input pins (INT7 to INT4) and RX pin, just

as interrupt request of peripheral device, generates an interrupt request. The interrupt request generates an

external interrupt and activates expanded intelligent I/O service (EI2OS).

If the expanded intelligent I/O service (EI2OS) has been disabled by interrupt control register (ICR: ISE=0),

external interrupt function is enabled and branches to interrupt processing.

If the EI2OS has been enabled, (ICR: ISE=1), DTP function is enabled and automatic data transmission is

performed by EI2OS . After performing specified number of data transmission processes , the process br anches

to interrupt processing.

DTP/external interrupt and CAN wakeup outline

External interrupt DTP function

Input pin 5 pins (RX, and INT4 to INT7)

Interrupt cause Specify for each pin with detection level setting register (ELVR).

Input of “H” level/“L” level/rising edge/falling

edge. Input of “H” level/ “L” level

Interrupt number #15 (0FH) , #24 (18H) , #27 (1BH)

Interrupt control Enabling or disabling output of interrupt request, using DTP/external interrupt permission

Interrupt flag Retaining interrupt cause with DTP/external interrupt cause register (EIRR).

Process selection Disable EI2OS (ICR: ISE=0) Enable EI2OS (ICR: ISE=1)

Process Branch to external interrupt process After automatic data transmission by EI2OS for

specified number of times, branch to interrupt

process.

MB90385 Series

•

••

• DTP/External interrupt/CAN wakeup block diagram

LA4LB4LA5LB5LA6LB6LA7LB7 LA0LB0

EN0EN4EN5EN6EN7

ER0ER4ER5ER6ER7

INT7

INT6

INT5

INT4 RX

Re-

served Re-

served

Re-

served

Re-

served Re-

served

Re-

served

Re-

served Re-

served

Re-

served Re-

served

Re-

served

Detection level setting register (ELVR)

Level/edge

selector

Pin Pin

DTP/external interrupt input

detection circuit

Interrupt

request signal

DTP/external interrupt

cause register (EIRR)

Interrupt

request signal

DTP/external interrupt

permission register (ENIR)

Level/edge

selector

Level/edge

selector

Level/edge

selector Level/edge

selector

Internal data bus

MB90385 Series

10. 8/10-bit A/D Converter

The 8/10-bit A/D converter converts an analog input voltage into 8-bit or 10/bit digital value, using the RC-type

successive approximation conversion method.

• Input signal is selected among 8 channels of analog input pins.

• Activation trigger is selected among software trigger, internal timer output, and external trigger.

•

••

• Functions of 8/10-bit A/D converter

The 8/10-bit A/D converter converts an analog voltage (input voltage) input to analog input pin into an 8-bit or

10-bit digital value (A/D conversion).

The 8/10-bit A/D converter has the following functions:

• A/D conversion takes a minimum of 6.12 µs* for 1 channel, including sampling time. (A/D conversion)

• Sampling of one channel takes a minimum of 2.0 µs*.

• RC-type successive approximation conversion method, with sample & hold circuit is used for conversion.

• Resolution of either 8 bits or 10 bits is specifiable.

• A maximum of 8 channels of analog input pins are allowed for use.

• Generation of interrupt request is allowed, by storing A/D conversion result in A/D data register.

• Activation of EI2OS is allowed upon occurrence of an interrupt request. With use of EI2OS, data loss is avoided

even if A/D conversion is performed successively.

• An activation trigger is selectable among software trigger , internal timer output, and external trigger (fall edge).

*: When operating with 16-MHz machine clock

•

••

• 8/10-bit A/D converter conversion mode

Conversion mode Description

Singular conversion

mode The A/D conversion is performed form a start channel to an end channel sequentially.

Upon completion of A/D conversion on an end channel, A/D conversion function stops.

Sequential conversion

mode

The A/D conversion is performed form a start channel to an end channel sequentially.

Upon completion of A/D conversion on an end channel, A/D conversion function re-

sumes from the start channel.

Pausing conversion

mode

The A/D conversion is performed by pausing at each channel. Upon completion of A/D

conversion on an end channel, A/D conversion and pause functions resume from the

start channel.

MB90385 Series

•

••

• 8/10-bit A/D converter block diagram

INTE

INT

PAUS STS1 STS0 STRTBUSY ANS2

MD0

ANS1 ANS0 ANE2 ANE1 ANE0

MD1

AVR

AVcc

AVss

AN0

AN1

AN2

AN3

AN4

AN5

AN6

AN7

ADTG

ST0ST1 CT1 CT0 D9 D8S10 D5D6 D4 D3 D2 D1 D0D7

Re-

served

Interrupt request output

A/D control

status register

(ADCS)

Activation

selector Decoder

Control circuit

Sample&

hold circuit

Comparator

Analog

channel

selector

D/A converter

A/D data

(ADCR)

TO : Internal timer output

− : Not defined

Reserved : Be sure to set to “0”

φ : Machine clock

Internal data bus

MB90385 Series

11. UART Outline

UART is a general-purpose serial data communication interface for synchronous and asynchronous communi-

cation using external devices.

• Provided with bi-directional communication function for both clock-synchronous and clock-asynchronous

modes.

• Provided with master/slave communication function (multi-processor mode). (Only master side is available.)

• Interrupt request is generated upon completion of reception, completion of transmission and detection of

reception error.

• Ready for expanded intelligent service, EI2OS.

UART functions

Note : Start/stop bit is not added upon clock-synchronous transmission. Data only is transmitted.

UART operation modes

 : Disallowed

*1 : “+1” is an address/data selection bit used for communication control (bit 11 of SCR1 register: A/D).

*2 : Only 1 bit is detected as a stop bit on data reception.

Description

Data buffer Full-duplex double buffer

Transmission mode Clock synchronous (No start/stop bit, no parity bit)

Clock asynchronous (start-stop synchronous)

Baud rate

Built-in special-purpose baud-rate generator. Setting is selectable

among 8 values.

Input of external values is allowed.

Use of clock from external timer (16-bit reload timer 0) is allowed.

Data length 7 bits (only asynchronous normal mode)

8 bits

Signaling system Non Return to Zero (NRZ) system

Reception error detection

Framing error

Overrun error

Parity error (not detectable in operation mode 1 (multi-processor

mode))

Interrupt request

Receive interrupt (reception completed, reception error detected)

Transmission interrupt (transmission completed)

Ready for expanded intelligent I/O service (EI2OS) in both transmis-

sion and reception

Master/slave communication function

(asynchronous, multi-processor mode) Communication between 1 (master) and n (slaves) are available

(usable as master only).

Operation mode Data length Synchronization Stop bit length

With parity Without parity

0Asynchronous mode

(normal mode) 7-bit or 8-bit Asynchronous 1- bit or 2-bit *2

1 Multi processor mode 8+1*1Asynchronous

2 Synchronous mode 8 Synchronous No

MB90385 Series

•

••

• UART block diagram

SIN1

SCK1

SOT1

MD1

MD0

CS2

CS1

SCKE

SOE

TDRE

BDS

PEN

SBL

A/D

REC

RXE

CS0

TXE RIE

TIE

ORE

FRE

RDRF

RST

DIV2

DIV1

DIV0

Control bus

Special-purpose

baud-rate

generator

16-bit reload

timer Clock

selector

Reception

clock Reception

control

circuit

Transmission

control

circuit

Start bit

detection circuit Transmission

start circuit

Transmission

bit counter

Transmission

parity counter

Transmission

clock

Reception interrupt

request output

Transmission interrupt

request output

Reception bit

counter

Reception

parity counter Pin

Pin Shift register for

reception

Serial input data

Shift register for

transmission

Serial output data

transmission

Recep-

tion

com-

pleted Reception error

occurrence

signal for EI2OS

(to CPU)

Reception status

decision circuit

Internal data bus

Communi-

cation

prescaler

control

Serial

mode

Serial

control

Serial

status

MB90385 Series

12. CAN Controller

The Controller Area Network (CAN) is a serial communication protocol compliant with CANV er2.0A and V er2.0B.

The protocol allows data tr ansmission and reception in both standard frame f ormat and expanded fr ame format.

•

••

• Features of CAN controller

• CAN controller format is compliant with CANVer2.0A and Ver2.0B.

• The protocol allows data transmission and reception in standard frame format and expanded frame format.

• Automatic transmission of data frame by remote frame reception is allowed.

• Baud rate ranges from 10 Kbps to 1 Mbps (with 16-MHz machine clock).

Data transmission baud rate

• Provided with 8 transmission/reception message buffers.

• Transmission/reception is allowed at ID11bit in standard format, and at ID29bit in expanded frame format.

• Specifying 0 byte to 8 bytes is allowed in message data.

• Multi-level message buffer configuration is allowed.

• CAN controller has two built-in acceptance masks. Mask settings are independently allowed for the two ac-

ceptance masks on reception IDs.

• The two acceptance masks allow reception in standard frame format and expanded frame format.

• For types of masking, all-bit comparison, all-bit masking, and partial masking with acceptance mask register

0/1, are specifiable.

Machine clock Baud rate (Max)

16 MHz 1 Mbps

12 MHz 1 Mbps

8 MHz 1 Mbps

4 MHz 500 Kbps

2 MHz 250 Kbps

MB90385 Series

•

••

• CAN controller block diagram

Set and clear reception

buffer and transmission buffer

Set reception

buffer ID selection

CRC error

Reception

DLC CRC generation circuit/

error check

Stuffing

error

Reception

shift register Destuffing/stuffing

error check

Acceptance

filter Reception

buffer

decision circuit

Reception buffer

RAM address

generation circuit Reception buffer, transmission buffer,

reception DLC, transmission DLC, ID selection

Arbitration lost Arbitration

check

Bit error Bit error

check

ACK error Acknowledgment

error check

Form error Form error

check

Input

latch Pin

BTR

PSC

TS1

TS2

RSJ

TOE

HALT

NIE

NS1,0

CSR

RTEC

BVALR

TREQR

TCANR

TRTRR

RFWTR

TCR

TIER

RCR

RIER

RRTRR

ROVRR

AMSR

AMR0

AMR1

LEIR

IDR0 to 7

DLCR0 to 7

DTR0 to 7

RAM

IDER

CPU

operation

clock Prescaler

(dividing by 1 to 64) Bit timing

generation circuit

Node status

transition interrupt

generation circuit

Node status

transition

interrupt signal

Bus

status

decision

circuit

Idle, interrupt, suspend,

transmit, receive, error,

and overload

Error

control

circuit Transmission/

reception

sequence

Clear transmission

buffer

Transmission

buffer

decision circuit

Trans-

mission

buffer

Data

counter Acceptance

filter control

circuit

Trans-

mission

DLC

Recep-

tion

DLC

selection

Bit error, stuff error,

CRC error, frame

error, ACK error

Arbitration

lost

Error frame

generation

circuit

Overload

frame

generation

circuit Output

driver

Transmission

buffer

Transmission

shift register

Transmission

DLC

CRC

generation

circuit

Stuffing

ACK

generation

circuit

Set and clear

transmission buffer

Transmission

completion interrupt

generation circuit

Trans-

mission

completion

interrupt

signal

Set reception buffer

Reception completion

interrupt generation

circuit

Reception

completion

interrupt

signal

Operation clock (TQ)

Sync segment

Time segment 1

Time segment 2

F2MC-16LX bus

MB90385 Series

13. Address Matching Detection Function Outline

The address matching detection function checks if an address of an instruction to be processed next to a currently-

processed instruction is identical with an address specified in the detection address register. If the addresses

match with each other, an instruction to be processed next in prog ram is forcibly replaced with INT9 instruction,

and process branches to the interrupt process program. Using INT9 interrupt, this function is available for

correcting progr am by batch processing.

•

••

• Address matching detection function outline

• An address of an instruction to be processed next to a currently-processed instruction of the program is always

retained in an address latch via inter nal data bus. By the address matching detection function, the address

v alue retained in the address latch is alwa ys compared with an address specified in detection address setting

is forcibly replaced with INT9 instruction, and an interrupt process program is executed.

• Two detection address setting registers are provided (PADR0 and PADR1), and each register is provided with

interrupt permission bit. Generation of interrupt, which is caused by address matching between the address

retained in address latch and the address specified in address setting register, is permitted and prohibited on

a register-by-register basis.

•

••

• Address matching detection function block diagram

• Address latch

Retains address value output to internal data bu s.

• Address detection control register (PACSR)

Specifies if interrupt is permitted or prohibited when addresses match with each other.

• Detection address setting (PADR0, PADR1)

Specifies addresses to be compared with values in address latch.

PADR0 24bit

AD1E AD0E

PACSR

PADR1 24bit

Reserved ReservedReservedReservedReservedReserved

Address latch

Detection address setting register 0

Detection address setting register 1

INT9 instruction

(generate INT9 interrupt)

Address detection control register (PACSR)

Reserved: Be sure to set to “0.”

Internal data bus

Comparator

MB90385 Series

14. ROM Mirror Function Selection Module Outline

The ROM mirror function selection module sets the data in ROM assigned to FF bank so that the data is read

by access to 00 bank.

•

••

• ROM mirror function selection module block diagram

•

••

• FF bank access by ROM mirror function

ROM

Reserved Reserved Reserved Reserved

ReservedReservedReserved

ROM mirror function selection register

(ROMM)

Address

Data

Address area

FF bank 00 bank

Internal data bus

FFFFFFH

FF4000H

FF0000H

FEFFFFH

00FFFFH

004000H

MB90F387

MB90387

FC0000H

MB90V495G

FBFFFFH

ROM mirror area

00 bank

FF bank (ROM

mirror applicable

area)

MB90385 Series

15. 512 Kbit Flash Memory Outline

The following three methods are provided for data writing and deleting on flash memory:

1. Parallel writer

2. Serial special-purpose writer

3. Writing/deleting by program execution

This section describes “3. Writing/deleting by program execution.”

•

••

• 512 Kbit flash memory outline

The 512K-bit flash memory is allocated on FFH bank of CPU memory map . Using the function of flash memory

interface circuit, the memory allows read access and program access from CPU.

Writing/deleting on flash memor y is perfor med by instruction from CPU via flash memory interface. Because

rewriting is allowed on mounted memory, modifying program and data is performed efficiently.

•

••

• Features of 512 Kbit flash memory

• 128 K words x 8 bits/64 K words x 16 bits (16 K + 8 K + 8 K + 32 K) sector configuration

• Automatic program algorithm (Embedded AlgorithmTM* : Similar to MBM29LV200.)

• Built-in deletion pause/deletion resume function

• Detection of completed writing/deleting by data polling and toggle bits.

• Detection of completed writing/deleting by CPU interrupt.

• Deletion is allowed on a sector-by-sector basis (sectors are combined freely).

• Number of writing/deleting operations (minimum): 10,000 times

• Sector protection

• Expanded sector protection

• Temporaly sector unprotection

* : Embedded AlgorithmTM is a registered trademark of Advanced Micro Devices.

Note : A function of reading manufacture code and device code is not provided. These codes are not accessible

by command either.

•

••

• Flash memory writing/deleting

• Writing and reading data is not allowed simultaneously on the flash memory.

• Data writing and deleting on the flash memory is performed by the processes as follows: Make a copy of

program on flash memory onto RAM. Then, execute the program copied on the RAM.

•

••

• List of registers and reset values in flash memory

00000X00

76bit 543210

× : Undefined

Flash memory control status register (FMCS)

MB90385 Series

•

••

• Sector configuration

For access from CPU, SA0 to SA3 are allocated in FF bank register.

•

••

• Sector configuration of 512 Kbit flash memory

FF0000H

FF7FFFH

FF8000H

FF9FFFH

FFA000H

FFBFFFH

FFC000H

FFFFFFH

70000H

77FFFH

78000H

79FFFH

7A000H

7BFFFH

7C000H

7FFFFH

Flash memory CPU address Writer address*

SA0 (32 Kbytes)

SA1 (8 Kbytes)

SA2 (8 Kbytes)

SA3 (16 Kbytes)

* : “Writer address” is an address equivalent to CPU address, which is used

when data is written on flash memory , using parallel writer. When writing/

deleting data with general-purpose writer , the writer address is used for

writing and deleting.

MB90385 Series

■ELECTRIC CHARACTERISTICS

1. Absolute Maximu m Rating (VSS = AVSS = 0 V)

*1 : AVcc and AVR should not exceed Vcc.

*2 : VI and VO should not exceed Vcc + 0.3 V.

*3 : A peak value of an applicable one pin is specified as a maximum output current.

*4 : An average current value of an applicable one pin within 100 ms is specified as an average output current.

(Average value is found by multiplying operating current by operating rate.)

*5 : An average current value of all pins within 100 ms is specified as an average total output current. (Average

value is found by multiplying operating current by operating rate.)

(Continued)

Parameter Symbol Rating Unit Remarks

Min Max

Power supply voltage

VCC VSS − 0.3 VSS + 6.0 V

AVCC VSS − 0.3 VSS + 6.0 V VCC = AVCC*1

AVR VSS − 0.3 VSS + 6.0 V AVCC ≥ AVR*1

Input voltage VIVSS − 0.3 VSS + 6.0 V *2

Output voltage VOVSS − 0.3 VSS + 6.0 V *2

Maximum clamp current ICLAMP − 2.0 + 2.0 mA *6

Total maximum clamp current ∑ | ICLAMP | 20 mA *6

“L” level maximum output current IOL1 15 mA Normal output*3

IOL2 40 mA High-current output*3

“L” level average output current IOLAV1 4 mA Normal output*4

IOLAV2 30 mA High-current output*4

“L” level maximum total output current ∑IOL1 125 mA Normal output

∑IOL2 160 mA High-current output

“L” level average total output current ∑IOLAV1 40 mA Normal output*5

∑IOLAV2 40 mA High-current output*5

“H” level maximum output current IOH1 −15 mA Normal output*3

IOH2 −40 mA High-current output*3

“H” level average output current IOHAV1 −4 mA Normal output*4

IOHAV2 −30 mA High-current output*4

“H” level maximum total output current ∑IOH1 −125 mA Normal output

∑IOH2 −160 mA High-current output

“H” level average total output current ∑IOHAV1 −40 mA Normal output*5

∑IOHAV2 −40 mA High-current output*5

Power consumption PD245 mW

Operating temperature TA−40 +105 °C

Storage temperature Tstg −55 +150 °C

MB90385 Series

(Continued)

*6 : • Applicable to pins: P10 to P17, P20 to P27, P30 to P33, P35*, P36*, P37, P40 to P44, P50 to P57

*: P35 and P36 are MB90387S and MB90F387S only.

• Use within recommended operating conditions.

• Use at DC voltage (current) .

• The +B signal should always be applied a limiting resistance placed between the +B signal and the

microcontroller.

• The v alue of the limiting resistance should be set so that when the +B signal is applied the input current to the

microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.

• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input potential

may pass through the protective diode and increase the potential at the VCC pin, and this may affect other

devices.

• Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V) , the power supply is

provided from the pins, so that incomplete operation may result.

• Note that if the +B input is applied during power-on, the power supply is provided from the pins and the

resulting supply voltage may not be sufficient to operate the power-on reset.

• Care must be taken not to leave the +B input pin open.

• Note that analog system input/output pins other than the A/D input pins (LCD drive pins, comparator input

pins, etc.) cannot accept +B signal input.

• Sample recommended circuits:

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

P-ch

N-ch

VCC

• Input/Output Equivalent circuits

+B input (0 V to 16 V)

Limiting

resistance

Protective diode

MB90385 Series

2. Recommended Operating Conditions (VSS = AVSS = 0.0V)

*1 : Use a ceramic capacitor, or a capacitor of similar frequency characteristics. On the Vcc pin, use a bypass

capacitor that has a larger capacity than that of Cs.

Refer to the following figure for connection of smoothing capacitor Cs.

*2 : AVcc is a voltage at which accuracy is guaranteed. AVcc should not exceed Vcc.

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device is

operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation

outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on

the data sheet. Users considering application outside the listed conditions are advised to contact their

FUJITSU representatives beforehand.

Parameter Symbol Value Unit Remarks

Min Typ Max

Power supply voltage VCC

3.5 5.0 5.5 V Under normal operation

3.0 5.5 V Retain status of stop

operation

AVCC 4.0 5.5 V *2

Smoothing capacitor CS0.1 1.0 µF*1

Operating temperature T A−40 +105 °C

• C pin connection diagram

MB90385 Series

3. DC Characteristics (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)

(Continued)

Parame-

ter Sym

bol Pin name Conditions Value Unit Remarks

Min Typ Max

“H” level

input

voltage

VIHS CMOS

hysteresis input

pin — 0.8 VCC —VCC + 0.3 V

VIHM MD input pin — VCC − 0.3 — VCC + 0.3 V

“L” level

input

voltage

VILS CMOS

hysteresis input

pin —V

SS − 0.3 — 0.2 VCC V

VILM MD input pin — VSS − 0.3 — VSS + 0.3 V

“H” level

output

voltage

VOH1 Pins other than

P14 to P17 VCC = 4.5 V,

IOH = −4.0 mA VCC – 0.5 — — V

VOH2 P14 to P17 VCC = 4.5 V,

IOH = −14.0 mA VCC – 0.5 — — V

“L” level

output

voltage

VOL1 Pins other than

P14 to P17 VCC = 4.5 V,

IOL = 4.0 mA ——0.4V

VOL2 P14 to P17 VCC = 4.5 V,

IOL = 20.0 mA ——0.4V

Input

leak

current IIL All input pins VCC = 5.5 V,

VSS < VI < VCC –5 — +5µA

Power

supply

current*

ICC

VCC

VCC = 5.0 V,

Internally operating at

16 MHz, normal operation. —2530mA

VCC = 5.0 V,

Internally operating at

16 MHz, writing on flash

memory.

— 45 50 mA MB90F387/S

VCC = 5.0 V,

Internally operating at

16 MHz, deleting on flash

memory.

— 45 50 mA MB90F387/S

ICCS VCC = 5.0 V,

Internally operating at

16 MHz, sleeping. —812mA

ICTS

VCC = 5.0 V,

Internally operating at

2 MHz, transition from

main clock mode, in time-

base timer mode.

—

0.75 1.0

MB90F387/S

0.2 0.35 MB90387/S

MB90385 Series

(Continued)

(VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)

* : Test conditions of power supply current are based on a device using external clock.

Parame-

ter Sym-

bol Pin name Conditions Rating Unit Remarks

Min Typ Max

Power

supply

current*

ICCL

VCC

VCC = 5.0 V,

Internally operating at

8 kHz, subclock oper-

ation,

TA = + 25°C

— 0.3 1.2 mA MB90F387/S

— 40 100 µA MB90387/S

ICCLS

VCC = 5.0 V,

Internally operating at

8 kHz, subclock,

sleep mode,

TA = + 25°C

—1030µA

ICCT

VCC = 5.0 V,

Internally operating at

8 kHz, clock mode,

TA = + 25°C

—825µA

ICCH Stopping,

TA = + 25°C—520µA

Input

capacity CIN

Other than

AVCC, AVSS,

AVR, C, VCC,

VSS

— 5 15 pF

Pull-up

resistor RUP RST 25 50 100 kΩ

Pull-down

resistor RDOWN MD2 25 50 100 kΩFLASH product is

not provided with

pull-down resistor.

MB90385 Series

4. AC Characteristics

(1) Cloc k timing (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)

*1 : Internal operation clock frequency should not exceed 16 MHz.

*2 : When selecting the PLL clock, the range of clock frequency is limitted. Use this product within range as mentioned

in “Relation among external clock frequency and internal clock frequency”.

Parameter Symbol Pin name Value Unit Remarks

Min Typ Max

Clock frequency fCX0, X1 3—8MHz

When crystal or ceramic

resonator is used*2

3 — 16 MHz External clock *1, *2

fCL X0A, X1A — 32.768 — kHz

Clock cycle time tHCYL X0, X1 125 — 333 ns

tLCYL X0A, X1A — 30.5 — µs

Input clock pulse width PWH, PWL X0 10 — — ns Set duty factor at 30% to

70% as a guideline.

PWLH,PWLL X0A — 15.2 — µs

Input clock rise time and fall

time tCR, tCF X0 — — 5 ns When external clock is

used

Internal operation clock

frequency fCP — 1.5 — 16 MHz When main clock is used

fLCP — — 8.192 — kHz When sub clock is used

Internal operation clock cycle

time tCP — 62.5 — 666 ns When main clock is used

tLCP — — 122.1 — µs When sub clock is used

tHCYL

tCF tCR

0.8 VCC

0.2 VCC

PWH PWL

X0A

tLCYL

tCF tCR

0.8 VCC

0.2 VCC

PWLH PWLL

• Clock timing

MB90385 Series

Rating values of alternating current is defined by the measurement reference voltage values shown below:

34 8 16

5.5

4.0

3.0

3.5

34 8 16

121.5

Power voltage VCC (V)

Internal clock fCP (MHz)

Operation guarantee range of MB90F387/S and MB90387/S

PLL operation guarantee range

Internal clock fCP (MHz)

External clock fC (MHz)*

Multiply

by 4 Multiply

by 3 Multiply

by 2 Multiply by 1

x1/2

(no multiplication)

Relation between internal operation clock

frequency and power supply voltage

Relation among external clock frequency and internal clock frequency

• PLL operation guarantee range

A/D converter

accuracy

guarantee range

* : fc is 8 MHz at maximum when crystal or ceramic resonator circuit is used.

0.8 VCC

0.2 VCC

2.4 V

0.8 V

Hysteresis input pin

• Output signal waveform

Output pin

• Input signal waveform

MB90385 Series

(2) Reset input timing

*1 : Oscillation time of oscillator is time that the amplitude reached the 90%. In the crystal oscillator, the oscillation

time is between several ms to tens of ms. In FAR/ceramic oscillator, the oscillation time is between hundreds

of µs to several ms. In the external clock, the oscillation time is 0 ms.

*2 : Except for MB90F387S and MB90387S.

*3 : Refer to "(1) Clock timing" ratings for tCP (internal operation clock cycle time).

Parameter Symbol Pin

name Value Unit Remarks

Min Max

Reset input time tRSTL RST

16 tCP*3ns Normal operation

Oscillation time of oscillator*1

+ 100 µs + 16 tCP*3

In sub clock*2, sub

sleep*2, watch*2 and

stop mode

100 µs In timebase timer

tRSTL

0.2 VCC 0.2 VCC

100 s

+ 16 tCP

RST

• In sub clock, sub sleep, watch and stop mode

Internal operation

clock

Internal reset

Oscillation

time of

oscillator Wait time for stabilizing

oscillation Execute instruction

90% of

amplitude

MB90385 Series

(3) Power-on reset (VCC = 5.0 V ± 10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)

Parameter Symbol Pin name Conditions Value Unit Remarks

Min Max

Power supply rise time tRVCC 0.05 30 ms

Power supply shutdown

time tOFF VCC 1ms Repeated operation

VCC

VSS

3.0 V

tOFF

2.7 V

0.2 V 0.2 V0.2 V

Sudden change of power supply voltage may activate the power-on reset function. When

changing power supply voltages during operation, raise the power smoothly by suppressing

variation of voltages as shown below. When raising the power, do not use PLL clock. Howev-

er, if voltage drop is 1V/s or less, use of PLL clock is allowed during operation.

Limiting the slope of rising within

50 mV/ms is recommended.

RAM data hold period

MB90385 Series

(4) UART timing (VCC = 4.5 V to 5.5 V, VSS = 0.0 V, TA = −40 °C to +105 °C)

* : Refer to "(1) Clock timing" ratings for tCP (internal operation clock cycle time).

Notes: • AC rating in CLK synchronous mode.

• CL is a load capacitance value on pins for testing.

Parameter Symbol Pin name Conditions Value Unit Remarks

Min Max

Serial clock cycle time tSCYC SCK1

Internal shift clock

mode output pin is :

CL = 80 pF+1TTL.

8 tCP *ns

SCK ↓ → SOT delay time tSLOV SCK1,

SOT1 −80 +80 ns

Valid SIN → SCK ↑tIVSH SCK1,

SIN1 100 ns

SCK ↑ → valid SIN hold time tSHIX SCK1,

SIN1 60 ns

Serial clock “H” pulse width tSHSL SCK1

External shift clock

mode output pin is :

CL = 80 pF+1TTL.

4 tCP *ns

Serial clock “L” pulse width tSLSH SCK1 4 tCP *ns

SCK ↓ → SOT delay time tSLOV SCK1,

SOT1 150 ns

Valid SIN → SCK ↑tIVSH SCK1,

SIN1 60 ns

SCK ↑ → valid SIN hold time tSHIX SCK1,

SIN1 60 ns

MB90385 Series

• Internal shift clock mode

SCK

SOT

SIN

tSCYC

tSLOV

tIVSH tSHIX

0.8 V 0.8 V

2.4 V

0.8 V

0.8 VCC

0.2 VCC

0.8 VCC

0.2 VCC

• External shift clock mode

SCK

SOT

SIN

tSLSH tSHSL

tSLOV

tIVSH tSHIX

0.2 VCC 0.2 VCC

0.8 VCC 0.8 VCC

2.4 V

0.8 V

0.8 VCC

0.2 VCC

0.8 VCC

0.2 VCC

MB90385 Series

(5) Timer input timing (VCC = 4.5 V to 5.5 V, VSS = 0.0 V, TA = −40 °C to +105 °C)

* : Refer to "(1) Clock timing" ratings for tCP (internal operation clock cycle time).

(6) Trigger input timing (VCC = 4.5 V to 5.5 V, VSS = 0.0 V, TA = −40 °C to +105 °C)

* : Refer to "(1) Clock timing" ratings for tCP (internal operation clock cycle time).

Parameter Symbol Pin name Conditions Value Unit Remarks

Min Max

Input pulse width tTIWH TIN0, TIN1 4 tCP *ns

tTIWL IN0 to IN3

Parameter Symbol Pin name Conditions Value Unit Remarks

Min Max

Input pulse width tTRGH

tTRGL INT4 to INT7,

ADTG 5 tCP *ns

0.8 VCC 0.8 VCC

0.2 VCC 0.2 VCC

tTIWH tTIWL

TIN0, TIN1,

IN0 to IN3

• Timer input timing

0.8 VCC 0.8 VCC

0.2 VCC 0.2 VCC

tTRGH tTRGL

INT4 to INT7,

ADTG

• Trigger input timing

MB90385 Series

5. A/D converter

(VCC = AVCC = 5.0 V ± 10%, VSS = AVSS = 0.0 V, 3.0 V ≤ AVR − AVSS, TA = −40 °C to +105 °C)

*1 : Refer to "(1) Clock timing" ratings for tCP (internal operation clock cycle time).

*2 : If A/D converter is not operating, a current when CPU is stopped is applicable (Vcc=AVcc=AVR=5.0 V).

Parameter Symbol Pin

name Conditions Value Unit Remarks

Min Max

Resolution    10 bit

Total error    ± 3.0 LSB

Nonlinear error    ± 2.5 LSB

Differential linear error    ± 1.9 LSB

Zero transition voltage VOT AN0 to

AN7 AVSS − 1.5

LSB AVSS + 0.5

LSB AVSS + 2.5

LSB V1 LSB = AVR/1024

Full-scale transition

voltage VFST AN0 to

AN7 AVR − 3.5

LSB AVR − 1.5

LSB AVR + 0.5

LSB V

Compare time 

66 tCP *1ns With 16 MHz

machine clock

5.5 V ≥ AVCC ≥ 4.5 V

88 tCP *1ns With 16 MHz

machine clock

4.5 V > AVCC ≥ 4.0 V

Sampling time 

32 tCP *1ns With 16 MHz

machine clock

5.5 V ≥ AVCC ≥ 4.5 V

128 tCP *1ns With 16 MHz

machine clock

4.5 V > AVCC ≥ 4.0 V

Analog port input

current IAIN AN0 to

AN7 10 µA

Analog input voltage VAIN AN0 to

AN7 AVSS AVR V

Reference voltage AVR AVSS + 2.7 AVCC V

Power supply current IAAVCC 3.5 7.5 mA

IAH AVCC 5µA*2

Reference voltage

supplying current IRAVR 165 250 µA

IRH AVR 5µA*2

Variation among

channels AN0 to

AN7 4LSB

MB90385 Series

6. Definition of A/D Converter Terms

(Continued)

Resolution : Analog variation that is recognized by an A/D converter.

Linear error : Deviation between a line across zero-transition line (“00 0000 00 0 0” ←→“00 0000 0001”)

and full-scale transition line (“11 1111 11 1 0” ←→ “11 1111 1111”) and actual conversion

characteristics.

Differential linear

error : Deviation of input voltage, which is required for changing output code by 1 LSB, from an

ideal value.

Total error : Difference between an actual value and an ideal value. A total error includes zero transition

error, full-scale transition error, and linear error.

3FF

3FE

3FD

004

003

002

001

AVss AVR

1.5 LSB

0.5 LSB

{1 LSB × (N − 1) + 0.5 LSB}

VNT

Total error

Total error of digital output “N” = VNT − {1 LSB × (N − 1) + 0.5 LSB} [LSB]

1 LSB

1 LSB = (Ideal value) AVR − AVSS [V]

1024

VOT (Ideal value) = AVSS + 0.5 LSB [V]

VFST (Ideal value) = AVR − 1.5 LSB [V]

VNT : A voltage at which digital output transits from (N-1) to N.

Digital output

Actual conversion

characteristics

(Actually-measured value)

Actual conversion

characteristics

Analog input

Ideal characteristics

MB90385 Series

(Continued)

3FF

3FE

3FD

004

003

002

001

AVss AVR AVss AVR

N + 1

N − 1

N − 2

VOT (actual measurement value)

VFST (actual

measurement

value)

Actual conversion

characteristics

{1 LSB × (N − 1)

+ VOT }

Actual conversion

characteristics

Ideal characteristics

Actual conversion

characteristics

V (N + 1) T

(actual measurement

value)

VNT

(actual measurement value)

Actual conversion

characteristics

VNT (actual

measurement value)

Differential linear error

Linear error

Linear error of digital output N = VNT − {1 LSB × (N − 1) + VOT}

1 LSB [LSB]

Differential linear error of digital output N = V (N + 1) T − VNT

1 LSB −1LSB [LSB]

VFST − VOT

1022 [V]

1 LSB =

VOT : Voltage at which digital output transits from “000H” to “001H.”

VFST : Voltage at which digital output transits from “3FEH” to “3FFH.”

Digital output

Analog input Analog input

MB90385 Series

7. Notes on A/D Converter Section

Use the device with external circuits of the following output impedance for analog inputs:

Recommended output impedance of external circuits are: Approx. 3.9 kΩ or lower (4.5 V ≤ AVc c ≤ 5.5 V)

(sampling period=2.00 µs at 16-MHz machine clock), Approx. 11 kΩ or lower (4.0 V ≤ AVcc < 4.5 V) (sampling

period=8.0 µs at 16-MHz machine clock).

If an e x ternal capacitor is used, in consideration of the eff ect by tap capacitance caused by external capacitors

and on-chip capacitors, capacitance of the external one is recommended to be se veral thousand times as high

as internal capacitor.

If output impedance of an external circuit is too high, a sampling period for an analog v oltage may be insufficient.

•

••

• About errors

As [AVR-AVss] become smaller, values of relative errors grow larger.

8. Flash Memory Program/Erase Characteristics

* : This value comes from the technology qualification (using Arrhenius equation to translate high temperature

measurements into normalized value at + 85 °C) .

Parameter Conditions Value Unit Remarks

Min Typ Max

Sector eraset time

TA = + 25 °C

VCC = 5.0 V

115s

Excludes 00H programming

prior to erasure

Chip erase time 4sExcludes 00H programming

prior to erasure

Word (16 bit width)

programming time 16 3,600 µsExcept for the over head

time of the system

Program/Erase cycle 10,000 cycle

Flash Data Retention

Time Average

TA = + 85 °C20 Year *

• Analog input circuit model

Note : Use the values in the figure only as a guideline.

MB90F387/S, MB90387/S

4.5 V ≤ AVCC ≤ 5.5 V R := 2.35 kΩ, C := 36.4 pF

4.0 V ≤ AVCC < 4.5 V R := 16.4 kΩ, C := 36.4 pF

Comparator

Analog input

MB90385 Series

■EXAMPLE CHARACTERISTICS

•

••

• MB90F387

(Continued)

ICC − VCC TA = +25 °C, In external clock operation

f = Internal operating frequency

ICCS − VCC TA = +25 °C, In external clock operation

f = Internal operating frequency

ICCL − VCC TA = +25 °C, In external clock operation

f = Internal operating frequency

ICC (mA)

VCC (V)

2.5

3.5 4.5 5.5 6.5

f = 16 MHz

f = 10 MHz

f = 8 MHz

f = 4 MHz

f = 2 MHz

ICCS (mA)

VCC (V)

2.5

3.5 4.5 5.5 6.5

f = 16 MHz

f = 10 MHz

f = 8 MHz

f = 4 MHz

f = 2 MHz

ICCL ( A)

VCC (V)

4567

200

250

300

350

f = 8 kHz

100

150

MB90385 Series

(Continued)

ICCLS − VCC TA = +25 °C, In external clock operation

f = Internal operating frequency

ICCT − VCC TA = +25 °C, In external clock operation

f = Internal operating frequency

ICCH − VCC Stopping, TA = +25 °C

ICCLS ( A)

VCC (V)

4567

f = 8 kHz

ICCT ( A)

VCC (V)

4567

f = 8 kHz

ICCH ( A)

VCC (V)

4567

MB90385 Series

(Continued)

(VCC - VOH) − IOH TA = +25 °C, VCC = 4.5 V

VOL − IOL TA = +25 °C, VCC = 4.5 V

H level input voltage/ L level input voltage

VIN − VCC TA = +25 °C

VCC VOH (mV)

IOH (mA)

46810

600

900

1000

200

400

100

300

500

700

800

5793

VOL (mV)

IOL (mA)

46810

600

900

1000

200

400

100

300

500

700

800

VIN (V)

VCC (V)

2.5

3.5 4 4.5 6

3 5 5.5

VIH

VIL

MB90385 Series

•

••

• MB90387

(Continued)

ICC − VCC TA = +25 °C, In external clock operation

f = Internal operating frequency

ICCS − VCC TA = +25 °C, In external clock operation

f = Internal operating frequency

ICCL − VCC TA = +25 °C, In external clock operation

f = Internal operating frequency

ICC (mA)

VCC (V)

2.5

3.5 4 4.5 6

3 5 5.5 6.5 7

f = 10 MHz

f = 16 MHz

f = 8 MHz

f = 4 MHz

f = 2 MHz

ICCS (mA)

VCC (V)

2.5

3.5 4.5

5.5 6.5

f = 10 MHz

f = 16 MHz

f = 8 MHz

f = 4 MHz

f = 2 MHz

ICCL ( A)

VCC (V)

f = 8 kHz

100

MB90385 Series

(Continued)

ICCLS − VCC TA = +25 °C, In external clock operation

f = Internal operating frequency

ICCT − VCC TA = +25 °C, In external clock operation

f = Internal operating frequency

ICCH − VCC Stopping, TA = +25 °C

ICCLS ( A)

VCC (V)

f = 8 kHz

ICCT ( A)

VCC (V)

ICCH ( A)

VCC (V)

4567

MB90385 Series

(Continued)

(VCC - VOH) − IOH TA = +25 °C, VCC = 4.5 V

VOL − IOL TA = +25 °C, VCC = 4.5 V

H level input voltage/ L level input voltage

VIN − VCC TA = +25 °C

VCC VOH (mV)

IOH (mA)

500

900

200

300

700

810

100

400

600

800

1000

5793

VOL (mV)

IOL (mA)

500

900

200

300

700

810

100

400

600

800

1000

5793

VCC (V)

2.5

4 4.5

5.5 6

33.5 5

VIN (V)

VIH

VIL

MB90385 Series

■ORDERING INFORMATION

Part number Package Remarks

MB90F387PMT

MB90387PMT

MB90F387SPMT

MB90387SPMT

48-pin plastic LQFP

(FPT-48P-M26)

MB90385 Series

■PACKAGE DIMENTION

48-pin plastic LQFP

(FPT-48P-M26)

Note 1) * : These dimensions include resin protrusion.

Note 2) Pins width and pins thickness include plating thickness.

Note 3) Pins width do not include tie bar cutting remainder.

Dimensions in mm (inches)

Note : The values in parentheses are reference values.

2003 FUJITSU LIMITED F48040S-c-2-2

36 25

INDEX

9.00±0.20(.354±.008)SQ

0.145±0.055

(.006±.002)

0.08(.003)

"A" 0˚~8˚

.059 –.004

+.008

–0.10

+0.20

1.50

0.60±0.15

(.024±.006)

0.10±0.10

(.004±.004)

(Stand off)

0.25(.010)

Details of "A" part

112

0.08(.003) M

(.008±.002)

0.20±0.05

0.50(.020)

LEAD No.

(Mounting height)

.276 –.004

+.016

–0.10

+0.40

7.00

MB90385 Series

FUJITSU LIMITED

The contents of this document are subject to change without notice.

Customers are advised to consult with FUJITSU sales

representatives before ordering.

The information, such as descriptions of function and application

circuit examples, in this document are presented solely for the

purpose of reference to show examples of operations and uses of

Fujitsu semiconductor device; Fujitsu does not warrant proper

operation of the device with respect to use based on such

information. When you develop equipment incorporating the

device based on such information, you must assume any

responsibility arising out of such use of the information. Fujitsu

assumes no liability for any damages whatsoever arising out of

the use of the information.

Any information in this document, including descriptions of

function and schematic diagrams, shall not be construed as license

of the use or exercise of any intellectual property right, such as

patent right or copyright, or any other right of Fujitsu or any third

party or does Fujitsu warrant non-infringement of any third-party’s

intellectual property right or other right by using such information.

Fujitsu assumes no liability for any infringement of the intellectual

property rights or other rights of third parties which would result

from the use of information contained herein.

The products described in this document are designed, developed

and manufactured as contemplated for general use, including

without limitation, ordinary industrial use, general office use,

personal use, and household use, but are not designed, developed

and manufactured as contemplated (1) for use accompanying fatal

risks or dangers that, unless extremely high safety is secured, could

have a serious effect to the public, and could lead directly to death,

personal injury, severe physical damage or other loss (i.e., nuclear

reaction control in nuclear facility, aircraft flight control, air traffic

control, mass transport control, medical life support system, missile

launch control in weapon system), or (2) for use requiring

extremely high reliability (i.e., submersible repeater and artificial

satellite).

Please note that Fujitsu will not be liable against you and/or any

third party for any claims or damages arising in connection with

above-mentioned uses of the products.

Any semiconductor devices have an inherent chance of failure. You

must protect against injury, damage or loss from such failures by

incorporating safety design measures into your facility and

equipment such as redundancy, fire protection, and prevention of

over-current levels and other abnormal operating conditions.

If any products described in this document represent goods or

technologies subject to certain restrictions on export under the

Foreign Exchange and Foreign Trade Law of Japan, the prior

authorization by Japanese government will be required for export

of those products from Japan.

F0405

 FUJITSU LIMITED Printed in Japan