Low Noise, Precision, Rail-to-Rail Output,
JFET Dual/Quad Operational Amplifiers
Data Sheet
ADA4610-2/ADA4610-4
FEATURES
Low offset voltage
B grade: 0.4 mV maximum (ADA4610-2 only)
A grade: 1 mV maximum
Low offset voltage drift
B grade: 4 µV/°C maximum (ADA4610-2 only)
A grade: 8 µV/°C maximum
Low input bias current: 5 pA typical
Dual-supply operation: ±5 V to ±15 V
Low voltage noise: 0.45 µV p-p at 0.1 Hz to 10 Hz
Voltage noise density: 7.3 nV/√Hz at f = 1 kHz
Low distortion (THD + noise): 0.00006%
No phase reversal
Rail-to-rail output
Unity-gain stable
APPLICATIONS
Instrumentation
Medical instruments
Multipole filters
Precision current measurement
Photodiode amplifiers
Sensors
Audio
PIN CONFIGURATIONS
NOTES
1. THE EXPOSED PAD MUST BE
CONNECTED TO V–.
1OUT A 2
–IN A 3+IN A 4V–
7OUT B
8 V+
6–IN B
5+IN B
09646-001
PIN 1
INDICATOR
ADA4610-2
TOP VIEW
(No t t o Scal e)
Figure 1. ADA4610-2, 8-Lead LFCSP (CP Suffix)
09646-002
OUT A
1
–IN A
2
+IN A
3
V–
4
V+
8
OUT B
7
–IN B
6
+I N B
5
ADA4610-2
TOP VIEW
(No t t o Scale)
Figure 2. ADA4610-2, 8-Lead SOIC_N (R Suffix) and 8-Lead MSOP (RM Suffix)
OUT A
1
–IN A
2
+IN A
3
V+
4
OUT D
14
–IN D
13
+IN D
12
V–
11
+IN B
5
+IN C
10
–IN B
6
–IN C
9
OUT B
7
OUT C
8
ADA4610-4
TOP VIEW
(No t t o Scal e)
09646-103
Figure 3. ADA4610-4, 14-Lead SOIC _N (R Suffix)
GENERAL DESCRIPTION
The ADA4610-2/ADA4610-4 are precision JFET amplifiers that
feature low input noise voltage, current noise, offset voltage,
input bias current, and rail-to-rail output. The ADA4610-2/
ADA4610-4 are dual and quad amplifiers, respectively.
The combination of low offset, noise, and very low input bias
current makes these amplifiers especially suitable for high
impedance sensor amplification and precise current
measurements using shunts. With excellent dc precision, low
noise, and fast settling time, the ADA4610-2/ADA4610-4
provide superior accuracy in medical instruments, electronic
measurement, and automated test equipment. Unlike many
competitive amplifiers, the ADA4610-2/ADA4610-4 maintain
fast settling performance with substantial capacitive loads.
Unlike many older JFET amplifiers, the ADA4610-2/ADA4610-4
do not suffer from output phase reversal when input voltages
exceed the maximum common-mode voltage range.
The fast slew rate and great stability with capacitive loads make
the ADA4610-2/ADA4610-4 perfect fits for high performance
filters. Low input bias currents, low offset, and low noise result
in a wide dynamic range for photodiode amplifier circuits. Low
noise and distortion, high output current, and excellent speed
make the ADA4610-2/ADA4610-4 great choices for audio
applications.
The ADA4610-2/ADA4610-4 are specified over the −40°C to
+125°C extended industrial temperature range.
The ADA4610-2 is available in 8-lead narrow SOIC, 8-lead
MSOP, a nd 8 -lead LFCSP packages. The ADA4610-4 is available
in a 14-lead narrow SOIC package.
Table 1. Related Precision JFET Operational Amplifiers
Single Dual Quad
AD8510
AD8512
AD8513
AD8610 AD8620 N/A1
AD820 AD822 AD824
ADA4627-1/ADA4637-1 N/A1 N/A1
N/A1 ADA4001-2 N/A1
1 N/A = not available in this device family.
Rev. D Document Feedback
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Technical Support www.analog.com
ADA4610-2/ADA4610-4 Data Sheet
Rev. D | Page 2 of 22
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Pin Configurations ........................................................................... 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Electrical Characteristics ............................................................. 4
Absolute Maximum Ratings ............................................................ 6
Thermal Resistance ...................................................................... 6
ESD Caution .................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
Typical Performance Characteristics ..............................................9
Comparative Voltage and Variable Voltage Graphs ............... 15
Functional Description .................................................................. 18
Applications Information .............................................................. 19
Input Overvoltage Protection ................................................... 19
Peak Detector .............................................................................. 19
I to V Conversion Applications ................................................ 19
Comparator Operation .............................................................. 20
Outline Dimensions ....................................................................... 21
Ordering Guide .......................................................................... 22
REVISION HISTORY
11/14—Rev. C to Rev. D
Change to Figure 56 ....................................................................... 19
5/14—Rev. B to Rev. C
Added ADA4610-4 ............................................................. Universal
Added 14-Lead SOIC ......................................................... Universal
Added Voltage Noise Density to Features Section, Figure 3, and
Table 1; Renumbered Sequentially ................................................. 1
Changes to Table 2 ............................................................................ 3
Changes to Table 3 ............................................................................ 4
Changes to Table 4 ............................................................................ 6
Added Pin Configurations and Function Descriptions
Section, Figure 4 to Figure 6, Table 6, and Table 7 ....................... 7
Changes to Typical Performance Characteristics Section ........... 8
Added Functional Description Section ....................................... 17
Added Input Overvoltage Protection Section, Peak Detector
Section, I to V Conversion Applications Section, and
Photodiode Circuits Section ......................................................... 18
Change to Figure 56 ....................................................................... 18
Added Figure 62, Outline Dimensions ........................................ 20
Changes to Ordering Guide .......................................................... 20
8/12—Rev. A to Rev. B
Changes to Figure 9 ........................................................................... 8
5/12—Rev. 0 to Rev. A
Changes to Data Sheet Title and General Description Section ... 1
Changed Input Impedance Parameter, Differential to Input
Capacitance Parameter, and Differential Parameter, Table 1 ...... 3
Added Input Resistance in Table 1 .................................................. 3
Changed Input Impedance, Differential Parameter to Input
Capacitance, Differential Parameter, Table 2 ................................. 4
Added Input Resistance Parameter, Table 2 ................................... 4
Added Figure 9, Figure 10, and Figure 14; Renumbered
Sequentially ........................................................................................ 8
Added Figure 15 ................................................................................ 9
Updated Outline Dimensions ....................................................... 16
Changes to Ordering Guide .......................................................... 17
12/11—Revision 0: Initial Version
Data Sheet ADA4610-2/ADA4610-4
SPECIFICATIONS
VSY = ±5 V, VCM = 0 V, TA = 25°C, unless otherwise noted.
Table 2.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
INPUT CHARACTERISTICS
Offset Voltage VOS
B Grade (ADA4610-2 Only) 0.2 0.4 mV
−40°C < TA < +125°C 0.8 mV
A Grade 0.4 1 mV
−40°C < TA < +125°C 1.8 mV
ΔV
OS
/ΔT
B Grade1 (ADA4610-2 Only) 0.5 4 µV/°C
A Grade1 1 8 µV/°C
Input Bias Current IB 5 25 pA
−40°C < TA < +125°C 1.5 nA
Input Offset Current IOS 2 20 pA
−40°C < TA < +125°C 0.25 nA
Input Voltage Range −2.5 +2.5 V
Common-Mode Rejection Ratio CMRR VCM = −2.5 V to +2.5 V 94 110 dB
−40°C < TA < +125°C 86 dB
Large Signal Voltage Gain AVO RL = 2 kΩ, VOUT = −3.5 V to +3.5 V
ADA4610-2 98 100 dB
−40°C < TA < +125°C 86 dB
ADA4610-4 96 98 dB
−40°C < TA < +125°C 84 dB
Input Capacitance VCM = 0 V
Differential 3.1 pF
4.8
pF
Input Resistance VCM = 0 V >1013 Ω
OUTPUT CHARACTERISTICS
Output Voltage High VOH RL = 2 kΩ 4.85 4.90 V
−40°C < TA < +125°C 4.60 V
RL = 600 Ω 4.60 4.89 V
−40°C < TA < +125°C 4.05 V
Output Voltage Low VOL RL = 2 kΩ −4.95 −4.90 V
−40°C < T
A
< +125°C
−4.75
V
RL = 600 Ω −4.90 −4.80 V
−40°C < TA < +125°C −4.40 V
Short-Circuit Current ISC ±63 mA
POWER SUPPLY
Power Supply Rejection Ratio PSRR VSY = ±4.5 V to ±18 V
ADA4610-2 106 125 dB
−40°C < TA < +125°C 103 dB
ADA4610-4 104 117 dB
−40°C < TA < +125°C 100 dB
Supply Current per Amplifier ISy IOUT = 0 mA 1.50 1.70 mA
−40°C < TA < +125°C 1.85 mA
Rev. D | Page 3 of 22
ADA4610-2/ADA4610-4 Data Sheet
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
DYNAMIC PERFORMANCE
Slew Rate ±SR RL = 2 kΩ, AV = +1 ±151 +21/−46 V/µs
Gain Bandwidth Product GBP VIN = 5 mV p-p, RL = 2 kΩ, AV = +100 15.4 MHz
Unity-Gain Crossover UGC VIN = 5 mV p-p, RL = 2 kΩ,AV = +1 9.3 MHz
φ
M
61
Degrees
−3 dB Closed-Loop Bandwidth −3 dB AV = +1, VIN = 5 mV p-p 10.6 MHz
Total Harmonic Distortion (THD) + Noise THD + N 1 kHz, AV = +1, RL = 2 kΩ, VIN = 1 V rms 0.00025 %
NOISE PERFORMANCE
Voltage Noise en p-p 0.1 Hz to 10 Hz 0.45 μV p-p
Voltage Noise Density en f = 10 Hz 14 nV/√Hz
f = 100 Hz 8.20 nV/√Hz
f = 1 kHz 7.30 nV/√Hz
f = 10 kHz 7.30 nV/√Hz
1 Guaranteed by design and characterization.
ELECTRICAL CHARACTERISTICS
VSY = ±15 V, VCM = 0 V, T A = 25°C, unless otherwise noted.
Table 3.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
INPUT CHARACTERISTICS
Offset Voltage
V
OS
B Grade (ADA4610-2 Only) 0.2 0.4 mV
−40°C < TA < +125°C 0.8 mV
A Grade 0.4 1 mV
−40°C < TA < +125°C 1.8 mV
Offset Voltage Drift
ΔV
OS
/ΔT
B Grade (ADA4610-2 Only)1 0.5 4 µV/°C
A Grade1 1 8 µV/°C
Input Bias Current IB 5 25 pA
−40°C < TA < +125°C 1.50 nA
Input Offset Current IOS 2 20 pA
−40°C < TA < +125°C 0.25 nA
Input Voltage Range −12.5 +12.5 V
Common-Mode Rejection Ratio CMRR VCM = −12.5 V to +12.5 V 100 115 dB
−40°C < TA < +125°C 96 dB
Large Signal Voltage Gain AVO RL = 2 kΩ, VOUT = ±13.5 V
ADA4610-2 104 107 dB
−40°C < TA < +125°C 91 dB
ADA4610-4 102 104 dB
−40°C < TA < +125°C 86 dB
Input Capacitance VCM = 0 V
Differential 3.1 pF
Common-Mode
4.8
pF
Input Resistance VCM = 0 V >1013 Ω
OUTPUT CHARACTERISTICS
Output Voltage High VOH RL = 2 kΩ 14.80 14.90 V
−40°C < TA < +125°C 14.65 V
RL = 600 Ω 14.25 14.47 V
−40°C < TA < +125°C 13.35 V
Rev. D | Page 4 of 22
Data Sheet ADA4610-2/ADA4610-4
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
Output Voltage Low VOL RL = 2 kΩ −14.90 −14.85 V
−40°C < TA < +125°C −14.75 V
RL = 600 Ω −14.68 −14.60 V
−40°C < TA < +125°C −14.30 V
Short-Circuit Current
I
SC
±79
mA
POWER SUPPLY
Power Supply Rejection Ratio PSRR VSY = ±4.5 V to ±18 V
ADA4610-2 106 125 dB
−40°C < TA < +125°C 103 dB
ADA4610-4 104 117 dB
−40°C < TA < +125°C 100 dB
Supply Current per Amplifier ISY IOUT = 0 mA 1.60 1.85 mA
−40°C < TA < +125°C 2.0 mA
DYNAMIC PERFORMANCE
Slew Rate ±SR RL = 2 kΩ , AV = +1 ±171 +25/−61 V/µs
Gain Bandwidth Product
GBP
V
IN
= 5 mV p-p, R
L
= 2 kΩ, A
V
= +100
16.3
MHz
Unity-Gain Crossover UGC VIN = 5 mV p-p, RL = 2 kΩ, AV = +1 9.3 MHz
Phase Margin φM 66 Degrees
−3 dB Closed-Loop Bandwidth −3 dB AV = +1, VIN = 5 mV p-p 9.5 MHz
Total Harmonic Distortion (THD) + Noise THD + N 1 kHz, AV = +1, RL = 2 kΩ, VIN = 5 V rms 0.00006 %
NOISE PERFORMANCE
Peak-to-Peak Voltage Noise en p-p 0.1 Hz to 10 Hz bandwidth 0.45 µV p-p
Voltage Noise Density en f = 10 Hz 14 nV/√Hz
f = 100 Hz 8.50 nV/√Hz
f = 1 kHz
7.30
nV/√Hz
f = 10 kHz 7.30 nV/√Hz
1 Guaranteed by design and characterization.
Rev. D | Page 5 of 22
ADA4610-2/ADA4610-4 Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter Rating
Supply Voltage ±18 V
Input Voltage
±V
S
Input Current1 ±10 mA
Storage Temperature Range −65°C to +150°C
Operating Temperature Range −40°C to +125°C
Junction Temperature Range −65°C to +150°C
Lead Temperature (Soldering, 10 sec) 300°C
Electrostatic Discharge (Human Body
Model)2
2500 V
Field Induced Charge Device Model (FICDM)3 1250 V
1 The input pins have clamp diodes connected to the power supply pins. Limit
the input current to 10 mA or less whenever input signals exceed the power
supply rail by 0.3 V.
2 ESDA/JEDEC JS-001-2011 applicable standard.
3 JESD22-C101 (ESD FICDM standard of JEDEC) applicable standard.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
Table 5. Thermal Resistance
Package Type θJA1 θJC Unit
8-Lead MSOP 142 45 °C/W
8-Lead SOIC_N 120 43 °C/W
8-Lead LFCSP_VD 57 12 °C/W
14-Lead SOIC_N 115 36 °C/W
1 θJA is specified for worst-case conditions, that is, θJA is specified for a device
soldered in a circuit board for surface-mount packages.
ESD CAUTION
Rev. D | Page 6 of 22
Data Sheet ADA4610-2/ADA4610-4
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
09646-104
OUT A
1
–IN A
2
+IN A
3
V–
4
V+
8
OUT B
7
–IN B
6
+IN B
5
ADA4610-2
TOP VIEW
(No t t o Scal e)
Figure 4. ADA4610-2 Pin Configuration, 8-Lead SOIC_N (R Suffix) and
8-Lead MSOP (RM Suffix)
NOTES
1. THE EXPOSED PAD MUST BE
CONNECTED TO V–.
1
OUT A 2
–IN A 3
+IN A 4
V–
7OUT B
8V+
6–IN B
5+IN B
09646-105
PIN 1
INDICATOR
ADA4610-2
TOP VIEW
(No t t o Scal e)
Figure 5. ADA4610-2 Pin Configuration, 8-Lead LFCSP_VD (CP Suffix)
Table 6. ADA4610-2 Pin Function Descriptions, 8-Lead SOIC_N, 8-Lead MSOP, and 8-Lead LFCSP_VD
Pin No. Mnemonic Description
1 OUT A Output Channel A.
2 −IN A Inverting Input Channel A.
3 +IN A Noninverting Input Channel A.
4 V− Negative Supply Voltage.
5 +IN B Noninverting Input Channel B.
6 −IN B Inverting Input Channel B.
7 OUT B Output Channel B.
8 V+ Positive Supply Voltage.
EPAD
Exposed Pad. The exposed pad must be connected to V−.
Rev. D | Page 7 of 22
ADA4610-2/ADA4610-4 Data Sheet
OUT A 1
–IN A 2
+IN A 3
V+ 4
OUT D
14
–IN D
13
+IN D
12
V–
11
+IN B 5+I N C
10
–IN B 6–IN C
9
OUT B 7OUT C
8
ADA4610-4
TOP VIEW
(No t t o Scal e)
09646-106
Figure 6. ADA4610-4 Pin Configuration, 14-Lead SOIC_N (R Suffix)
Table 7. ADA4610-4 Pin Function Descriptions, 14-Lead SOIC_N
Pin No. Mnemonic Description
1 OUT A Output Channel A.
2 −IN A Inverting Input Channel A.
3 +IN A Noninverting Input Channel A.
4 V+ Positive Supply Voltage.
5 +IN B Noninverting Input Channel B.
6 −IN B Inverting Input Channel B.
7 OUT B Output Channel B.
8 OUT C Output Channel C.
9 −IN C Inverting Input Channel C.
10 +IN C Noninverting Input Channel C.
11 V− Negative Supply Voltage.
12 +IN D Noninverting Input Channel D.
13 −IN D Inverting Input Channel D.
14 OUT D Output Channel D.
Rev. D | Page 8 of 22
Data Sheet ADA4610-2/ADA4610-4
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
400
350
300
250
200
150
100
50
0
–1000 –800 –600 –400 –200 0200 400 600 800 1000 1200
OFFSET VOLTAGE (µV)
NUMBER O F CHANNELS
09646-003
SOIC
Figure 7. Input Offset Voltage Distribution, VSY = ±5 V
350
300
250
200
150
100
50
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5
10.0
10.5
TCV
OS
(µV/°C)
NUMBER O F CHANNELS
09646-004
SOIC
Figure 8. Input Offset Voltage Drift (TCVOS) Distribution, VSY = ±5 V
09646-005
–1500
–1000
–500
0
500
1000
1500
–5 –4 –3 –2 –1 012345
VCM (V)
INPUT OFFSET VOLTAGE (µV)
MEAN
MEAN + 3σ
MEAN – 3σ
Figure 9. Input Offset Voltage vs. Common-Mode Input Voltage (VCM),
VSY = ±5 V, RL = ∞ (Sample Size = 200)
400
350
300
250
200
150
100
50
0
–1000 –800 –600 –400 –200 0200 400 600 800 1000 1200
OFFSET VOLTAGE (µV)
NUMBER O F CHANNELS
09646-006
SOIC
Figure 10. Input Offset Voltage Distribution, VSY = ±15 V
350
300
250
200
150
100
50
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5
10.0
10.5
TCV
OS
(µV/°C)
NUMBER O F CHANNELS
09646-007
SOIC
Figure 11. TCVOS Distribution, VSY = ±15 V
09646-008
–1500
–1000
–500
0
500
1000
1500
–15 –10 –5 0
V
CM
(V)
510 15
INPUT OFFSET VOLTAGE (uV)
MEAN
MEAN + 3σ
MEAN – 3σ
Figure 12. Input Offset Voltage vs. Input Common-Mode Voltage (VCM),
VSY = ±15 V, RL = ∞ (Sample Size = 200)
Rev. D | Page 9 of 22
ADA4610-2/ADA4610-4 Data Sheet
09646-055
–50
–40
–30
–20
–10
0
10
20
30
40
50
–5 –4 –3 –2 –1 0
VCM (V) 12345
INPUT BI AS CURRE NT (pA)
MEAN
MEAN + 3σ
MEAN – 3σ
Figure 13. Input Bias Current vs. Common-Mode Input Voltage (VCM),
VSY = ±5 V, RL = ∞ (Sample Size = 700 Channels)
10
1
100
1k
10k
100k
0.01
0.1
–5
INPUT BI AS CURRE NT (pA)
V
CMI
(V)
09646-056
+125°C
+25°C
–4 –3 –2 –1 012345
–40°C
SOIC
Figure 14. Input Bias Current vs. Common-Mode Input Voltage and
Temperature (VCMI), VSY = ±5 V, RL = ∞ (Sample Size = 700 Channels)
100
10
1
0.1
–50 –25 025 50 75 100 125
TEMPERATURE (°C)
INPUT BI AS CURRE NT (pA)
09646-009
Figure 15. Input Bias Current vs. Temperature, VSY = ±5 V
–15 –10 10–5 50 15
INPUT BI AS CURRE NT (pA)
VCM (V)
09646-057
–50
–40
–30
–20
–10
0
10
20
30
40
50
MEAN
MEAN + 3σ
MEAN – 3σ
Figure 16. Input Bias Current vs. Common-Mode Input Voltage (VCM),
VSY = ±15 V, RL = ∞ (Sample Size = 700 Channels)
–15 –10 10–5 50 15
INPUT BI AS CURRE NT (pA)
V
CMI
(V)
09646-058
10
1
100
1k
10k
100k
0.1
+125°C
+25°C
–40°C
SOIC
Figure 17. Input Bias Current vs. Common-Mode Input Voltage and
Temperature (VCMI), VSY = ±15 V, RL = ∞ (Sample Size = 700 Channels)
100
10
1
0.1
–50 –25 025 50 75 100 125
TEMPERATURE (°C)
INPUT BI AS CURRE NT (pA)
09646-012
Figure 18. Input Bias Current vs. Temperature, VSY = ±15 V
Rev. D | Page 10 of 22
Data Sheet ADA4610-2/ADA4610-4
1
0.1
0.01
0.1 110 100
I
OUT
SOURCE ( mA)
(V+ – V
OUT
) (V)
09646-011
Figure 19. Dropout Voltage (V+ − VOUT) vs. Source Current, VSY = ±5 V
0.1 110 100
I
OUT
SINK ( mA)
09646-015
10
1
0.1
0.01
(VOUT – V–) (V)
Figure 20. Dropout Voltage (VOUT − V−) vs. Sink Current, VSY = ±5 V
120 270
225
180
135
90
45
0
–45
–90
100
80
60
40
20
0
–20
–40
0.01 0.1 110 100 1k 10k 100k
FRE Q UE NCY ( kHz )
GAI N (dB)
PHASE ( Degrees)
09646-016
Figure 21. Open-Loop Gain and Phase vs. Frequency, VSY = ±5 V, RL = 2 kΩ
0.01
0.1 110 100
I
OUT
SOURCE ( mA)
09646-014
1
0.1
0.01
(V+ – V
OUT
) (V)
Figure 22. Dropout Voltage (V+ − VOUT) vs. Source Current, VSY = ±15 V
10
1
0.1
0.01 10.10.01 10 100
I
OUT
SINK ( mA)
(VOUT – V–) (V)
09646-018
Figure 23. Dropout Voltage (VOUT − V−) vs. Sink Current, VSY = ±15 V
120 270
225
180
135
90
45
0
–45
–90
100
80
60
40
20
0
–20
–40
0.01 0.1 110 100 1k 10k 100k
FRE Q UE NCY ( kHz )
GAI N (dB)
PHASE ( Degrees)
09646-019
Figure 24. Open-Loop Gain and Phase vs. Frequency, VSY = ±15 V, RL = 2 kΩ
Rev. D | Page 11 of 22
ADA4610-2/ADA4610-4 Data Sheet
60
40
20
0
–20
–40110 100 1k 10k 100k
FRE Q UE NCY ( kHz )
GAI N (dB)
09646-017
A
V
= +100
A
V
= +10
A
V
= +1
Figure 25. Closed-Loop Gain vs. Frequency, VSY = ±5 V
1k
100
10
1
0.1
0.01 10.1 10 100 1k 10k 100k
FRE Q UE NCY ( kHz )
ZOUT (Ω)
09646-021
AV = +100
A
V
= +10
AV = +1
Figure 26. Closed-Loop Output Impedance (ZOUT) vs. Frequency, VSY = ±5 V
120
100
80
60
40
20
0
–20 10.1 10 100 1k 10k
FRE Q UE NCY ( kHz )
PSRR (dB)
09646-022
PSRR–
PSRR+
Figure 27. PSRR vs. Frequency, VSY = ±5 V
60
40
20
0
–20
–40110 100 1k 10k 100k
FRE Q UE NCY ( kHz )
GAI N (dB)
09646-020
A
V
= +100
A
V
= +10
A
V
= +1
Figure 28. Closed-Loop Gain vs. Frequency, VSY = ±15 V
1k
100
10
1
0.1
0.01 10.1 10 100 1k 10k 100k
FRE Q UE NCY ( kHz )
ZOUT (Ω)
09646-024
AV = +100
AV = +10
AV = +1
Figure 29. Closed-Loop Output Impedance (ZOUT) vs. Frequency, VSY = ±15 V
120
100
80
60
40
20
0
–20 10.1 10 100 1k 10k
FRE Q UE NCY ( kHz )
PSRR (dB)
09646-025
PSRR–
PSRR+
Figure 30. PSRR vs. Frequency, VSY = ±15 V
Rev. D | Page 12 of 22
Data Sheet ADA4610-2/ADA4610-4
120
140
100
80
60
40
20
010.1 10 100 1k 10k
FREQUENCY ( kHz )
CMRR (dB)
09646-023
Figure 31. CMRR vs. Frequency, VSY = ±5 V
3
2
1
0
–1
–2
–30123 4 5 6 7 8 9 10
TIME (µs)
OUTPUT VOLTAGE (V)
09646-027
Figure 32. Large Signal Transient Response, VSY = ±5 V, AV = +1,
RL = 2 kΩ, CL = 100 pF
75
50
25
0
–25
–50
–75012345 6 7 8 9 10
TIME (µs)
OUTPUT VOLTAGE (mV)
09646-028
Figure 33. Small Signal Transient Response, VSY = ±5 V, AV = +1,
RL = 2 kΩ, CL = 100 pF
120
140
100
80
60
40
20
01
0.1 10 100 1k 10k
FRE Q UE NCY ( kHz )
CMRR (dB)
09646-026
Figure 34. CMRR vs. Frequency, VSY = ±15 V
12
8
4
0
–4
–8
–12012 3 4 5 6 7 8 910
TIME (µs)
OUTPUT VOLTAGE (V)
09646-030
Figure 35. Large Signal Transient Response, VSY = ±15 V, AV = +1,
RL = 2 kΩ, CL = 100 pF
75
50
25
0
–25
–50
–750123 4 5 6 7 8 9 10
TIME (µs)
OUTPUT VOLTAGE (mV)
09646-031
Figure 36. Small Signal Transient Response, VSY = ±15 V, AV = +1,
RL = 2 kΩ, CL = 100 pF
Rev. D | Page 13 of 22
ADA4610-2/ADA4610-4 Data Sheet
100
10
1
0.001 0.01 0.1 110 100
FRE Q UE NCY ( kHz )
VOLTAGE NO ISE DENSITY (n V/ Hz)
09646-033
Figure 37. Voltage Noise Density vs. Frequency, VSY = ±5 V
50
40
30
20
0
10
0.01 0.1 1
LOAD CAPACI TANCE ( nF )
OVERSHOOT (%)
09646-034
OS–
OS+
Figure 38. Overshoot vs. Load Capacitance, VSY = ±5 V, AV = +1,
RL = 2 kΩ, VIN = 100 mV p-p
100
10
1
0.001 0.01 0.1 110
FRE Q UE NCY ( kHz )
VOLTAGE NO ISE DENSITY (n V/ Hz)
09646-036
Figure 39. Voltage Noise Density vs. Frequency, VSY = ±15 V
50
40
30
0
20
10
0.01 0.1 1
LOAD CAPACI TANCE ( nF )
OVERSHOOT (%)
09646-037
OS–
OS+
Figure 40. Overshoot vs. Load Capacitance, VSY = ±15 V, AV = +1,
RL = 2 kΩ, VIN = 100 mV p-p
Rev. D | Page 14 of 22
Data Sheet ADA4610-2/ADA4610-4
COMPARATIVE VOLTAGE AND VARIABLE VOLTAGE GRAPHS
0.00001
0.0001
0.001
0.01
0.1
1
10
0.001 0.01 0.1 1
THD + N ( %)
AMPLITUDE ( V rms)
09646-205
Figure 41. THD + N vs. Amplitude VSY = ±5 V
09646-204
0.00001
0.0001
0.001
0.01
0.1
1
0.01 0.1 110 100
THD + N ( %)
FREQUENCY (kHz)
80kHz BAND-P ASS FI LT E R
500kHz BAND-P AS S FI LT E R
Figure 42. THD + N vs. Frequency VSY = ±5 V
–60
–80
–120
–140
–160
–100
–40
0.1 110 100
FRE Q UE NCY ( kHz )
CHANNEL SE P ARATI ON (dB)
09646-039
Figure 43. Channel Separation vs. Frequency
1
0.1
0.01
0.001
0.0001
0.00001 0.1
0.010.001 110
AMPLITUDE ( V rms)
THD + N ( %)
09646-040
Figure 44. THD + N vs. Amplitude VSY = ±15 V
09646-141
0.00001
0.0001
0.001
0.01
0.1
1
0.01 0.1 110 100
THD + N ( %)
FREQUENCY (kHz)
80kHz BAND-P ASS FI LT E R
500kHz BAND-P AS S FI LT E R
Figure 45. THD + N vs. Frequency VSY = ±15 V
16
12
8
4
0
–4
–8
–12
–1600.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
TIME (ms)
VOLTAGE (V)
09646-042
OUTPUT
INPUT
Figure 46. No Phase Reversal, VSY = ±15 V, AV = +1, RL = 2 kΩ, CL = 100 pF
Rev. D | Page 15 of 22
ADA4610-2/ADA4610-4 Data Sheet
300
200
100
0
–100
–200
–300
–400
–500012345 6 7 8 910
TIME ( sec)
VOLTAGE (nV)
09646-043
Figure 47. Voltage Noise, 0.1 Hz to 10 Hz
12
10
8
6
4
2
000.2 0.4 0.6 0.8 1.0
0.1%
0.01%
1.2 1.4
SETTLING TIME (µs)
STEP SIZ E (V)
09646-044
Figure 48. Positive Step Settling Time
–4
–2
0
2
4
6
8
10
12
14
16
18
–0.5 00.5 1.0 1.5 2.0 2.5 3.0
V
OUT
(V)
V
IN
TIME (µs)
V
OUT
09646-200
R
S
0.9kΩ
R
F
10kΩ
R
I
1kΩ
R
L
V
OUT
OSCILLOSCOPE
AVCL = 11
V
IN
= 1.5 × V
OUT
MAX
V
IN
PULSE
GENERATOR
DUT
V
SY
+
V
SY
–
Figure 49. Positive Overload Recovery
V
SY
(V)
09646-047
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
0510 15 20 25 30 35
I
SY
PER AMPLIF IER ( mA)
–40°C
+25°C
+85°C
+125°C
Figure 50. Supply Current (ISY) per Amplifier vs. Supply Voltage (VSY) at
Various Temperatures
12
10
8
6
4
2
000.2 0.4 0.6 0.8 1.0
0.1%
0.01%
1.2 1.4
SETTLING TIME (µs)
STEP SIZ E (V)
09646-045
Figure 51. Negative Step Settling Time
–0.5 00.5 1.0 1.5 2.0 2.5 3.0
V
OUT
(V)
V
IN
TIME (µs)
V
OUT
09646-201
–18
–16
–14
–12
–10
–8
–6
–4
–2
0
2
4
R
S
0.9kΩ
R
F
10kΩ
R
I
1kΩ
R
L
OUT
OSCILLOSCOPE
AVCL = 11
V
IN
= 1.5 × V
OUT
MAX
IN
PULSE
GENERATOR
DUT
V
SY
+
V
SY
–
Figure 52. Negative Overload Recovery
Rev. D | Page 16 of 22
Data Sheet ADA4610-2/ADA4610-4
–5
–4
–3
–2
–1
0
1
2
3
4
5
–0.2 00.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
V
IN
, V
OUT
(V)
V
IN
TIME (µs)
V
OUT
09646-203
Figure 53. Positive and Negative Slew Rate (VSY = ±5 V, AV = +1, RL = 2 kΩ)
–15
–10
–5
0
5
10
15
–2.0 –1.5 –1.0 –0.5 00.5 1.0
V
IN
, V
OUT
(V)
TIME (µs)
V
IN
V
OUT
09646-202
Figure 54. Positive and Negative Slew Rate (VSY = ±15 V, AV = +1, RL = 2 kΩ)
Rev. D | Page 17 of 22
ADA4610-2/ADA4610-4 Data Sheet
FUNCTIONAL DESCRIPTION
The ADA4610-2/ADA4610-4 are manufactured using the
Analog Devices, Inc. iPolar® process, a 36 V dielectrically
isolated (DI) process with P-channel JFET technology. The
unique architecture of the ADA4610x family makes it possible
to combine high precision and high speed characteristics into a
high voltage, low power op amp. A simplified schematic for the
ADA4610-2/ADA4610-4 is shown in Figure 55. The JFET input
stage architecture offers advantages of low input bias current,
high bandwidth, high gain, low noise, and no phase reversal
when the applied input signal exceeds the common voltage
range. The output stage is rail to rail with high drive
characteristics and low dropout voltage for both sinking and
sourcing currents.
The ADA4610x family is unconditionally stable for all gain
configurations, even with capacitive loads well in excess of 1 nF.
The devices have internal protective circuitry that allows
voltages as high as 0.3 V beyond the supplies to be applied at the
input of either terminal without causing damage (for higher
input voltages, refer to the Input Overvoltage Protection
section). The ADA4610-2 B grades achieve less than 0.4 mV of
offset and 4 μV/°C of offset drift; these characteristics are
usually associated with very high precision bipolar input
amplifiers. The gate current of a typical JFET doubles every
10°C, resulting in a similar increase in input bias current over
temperature. The low power consumption characteristic of the
ADA4610x family minimizes the die temperature, which
warrants low input bias currents even at elevated ambient
temperatures, making the amplifiers ideal for applications that
require low leakage specifications without active cooling. Give
special care to the printed circuit board (PCB) layout to
minimize leakage currents between PCB traces. Improper
layout and board handling may generate leakage currents
exceeding the bias currents of the op amp.
The ADA4610x family is fully specified with supply voltages
from ±5 V to ±15 V over the extended industrial temperature
range of −40°C to +125°C. The ADA4610-2 is offered in the
8-lead MSOP, 8-lead SOIC_N, and 8-lead LFCSP_VD, while the
ADA4610-4 is offered in a 14-lead SOIC_N. All these packages
are surface-mount type.
1++ –
D31
Q28
Q27
VOUT
09646-054
V–
Q15Q14
Q13 Q17Q16Q23
Q29Q30
J1 J2
Q9
Q5
Q4
Q8
Q1
Q6
Q7
Q25
Q24
Q18
Q12
I2I3I4
C2
C1
C3
DE1
VIN+
VIN–
C4
A2A1
R16
R7R6
R3
R5
R2
R10 R11
RC4
D26
R15
V+
DE5
DE6
DE3
DE2
DE4
Figure 55. Simplified Schematic
Rev. D | Page 18 of 22
Data Sheet ADA4610-2/ADA4610-4
APPLICATIONS INFORMATION
INPUT OVERVOLTAGE PROTECTION
The ADA4610-2/ADA4610-4 have internal protective circuitry
that allows voltages as high as 0.3 V beyond the supplies to be
applied at the input of either terminal without causing damage.
For higher input voltages, a series resistor is necessary to limit
the input current. The resistor value can be determined by
mA10≤
−
S
S
IN
R
VV
where:
VIN is the input voltage.
VS is the voltage of either V+ or V−.
RS is the series resistor.
With a very low bias current of <1.5 nA up to 125°C, higher
resistor values can be used in series with the inputs. A 5 kΩ
resistor protects the inputs from voltages as high as 25 V
beyond the supplies and adds less than 10 µV to the offset.
PEAK DETECTOR
The function of a peak detector is to capture the peak value of a
signal and produce an output equal to it. By taking advantage of
the dc precision and super low input bias current of the JFET
input amplifiers, such as the ADA4610-2/ADA4610-4, a highly
accurate peak detector can be built, as shown in Figure 56.
V
CC
V
IN
+
–
ADA4610-2 ADA4610-2
V
EE
U2A
3
24
8
15
64
8
7
C4
50pF C3
1µF
R6
1kΩ
R7
10kΩ
D2
1N448
D3
1N4148
+PEAK
D4
1N4148 U2B
09646-149
Figure 56. Positive Peak Detector
In this application, Diode D3 and Diode D4 act as uni-
directional current switches, which open up when the output is
kept constant (in hold mode). To detect a positive peak, U2A
drives C3 through D3, and D4 until C3 is charged to a voltage
equal to the input peak value. Feedback from the output of the
U2B (+peak) through R6 limits the output voltage of U2A.
After detecting the peak, the output of U2A swings low but is
clamped by D2. Diode D3 reverses bias and the common node
of D3, D4, and R7 is held to a voltage equal to +peak by R7. The
voltage across D4 is zero; therefore, its leakage is small. The bias
current of U2B is also small. With almost no leakage, C3 has a
long hold time.
The ADA4610-2, shown in Figure 56, is a perfect fit for building
a peak detector because U2A requires dc precision and high
output current during fast peaks, and U2B requires low input
bias (IB) current to minimize capacitance discharge between
peaks. A low leakage and low dielectric absorption capacitor
such as polystyrene or polypropylene is required for C3.
Reversing the diode directions causes the circuit to detect
negative peaks.
I TO V CONVERSION APPLICATIONS
Photodiode Circuits
Common applications for I to V conversion include photodiode
circuits where the amplifier is used to convert a current emitted
by a diode placed at the negative input terminal into an output
voltage.
The low input bias current, wide bandwidth, and low noise of
the ADA4610-2/ADA4610-4 make them excellent choices for
various photodiode applications, including fax machines, fiber
optic controls, motion sensors, and bar code readers.
The circuit shown in Figure 57 uses a silicon diode with zero
bias voltage. This setup is a photovoltaic mode, which uses
many large photodiodes. This configuration limits the overall
noise and is suitable for instrumentation applications.
4
8
3
1
2
1/2
ADA4610-2
C
F
R
F
R
D
C
T
V
EE
V
CC
09646-154
Figure 57. Equivalent Preamplifier Photodiode Circuit
A larger signal bandwidth can be attained at the expense of
additional output noise. The total input capacitance (CT)
consists of the sum of the diode capacitance (typically 30 pF to
40 pF) and the amplifier input capacitance (<10 pF), which
includes external parasitic capacitance. CT creates a zero in the
frequency response that can lead to an unstable system. To
ensure stability and optimize the bandwidth of the signal, place
a capacitor in the feedback loop of the circuit shown in Figure 57.
The capacitor creates a pole and yields a bandwidth with a
corner frequency of
1/(2π(RFCF))
where:
RF is the feedback resistor.
CF is the feedback capacitor.
The value of RF can be determined by the ratio
V/ID
where:
V is the desired output voltage of the op amp.
ID is the diode current.
Rev. D | Page 19 of 22
ADA4610-2/ADA4610-4 Data Sheet
For example, if ID is 100 µA and a 10 V output voltage is desired,
RF must be 100 kΩ. The resistance of the photodiode (RD) is a
junction resistance (see Figure 57).
A typical value for RD is 1000 MΩ. Because RD >> RF, the circuit
behavior is not impacted by the effect of the junction resistance.
The maximum signal bandwidth is
T
F
MAX
CR
ft
fπ
=
2
where ft is the unity-gain frequency of the op amp.
CF can be calculated by
ft
R
C
C
F
T
Fπ
=
2
where ft is the unity-gain frequency of the op amp, and it achieves
a phase margin, φM, of approximately 45°.
A higher phase margin can be obtained by increasing the value
of CF. Setting CF to twice the previous value yields approximately
φM = 65° and a maximal flat frequency response, but it reduces the
maximum signal bandwidth by 50%.
Using the previous parameters with a CF ≈ 7 pF, the signal
bandwidth is approximately 250 kHz.
COMPARATOR OPERATION
Although op amps are quite different from comparators,
occasionally an unused section of a dual or a quad op amp can
be used as a comparator; however, this is not recommended for
any rail-to-rail output op amp. For rail-to-rail output op amps,
the output stage is generally a ratioed current mirror with bipolar
or MOSFET transistors. With the device operating open loop,
the second stage increases the current drive to the ratioed mirror
to close the loop. However, the second stage cannot close the loop,
which results in an increase in supply current. With the
ADA4610-2/ADA4610-4 op amps configured as comparators,
the supply current can be significantly higher (see Figure 58 for
supply current vs. supply voltage in the ADA4610-4).
Configuring an unused section as a voltage follower with the
noninverting input connected to a voltage within the input
voltage range is recommended. The ADA4610-2/ADA4610-4
have a unique output stage design that reduces the excess supply
current but does not entirely eliminate this effect when the op
amp is operating open loop.
09646-053
0
1
2
3
4
5
6
7
8
9
0 5 10 15 20 25 30 35 40
I
SY
FORALL CHANNEL S ( mA)
V
SY
(V)
COM PARATO R, V
OUT
= HIGH
COM PARATO R, V
OUT
= LOW
FOLLOWER
Figure 58. Supply Current vs. Supply Voltage (ADA4610-4 Only)
Rev. D | Page 20 of 22
Data Sheet ADA4610-2/ADA4610-4
OUTLINE DIMENSIONS
CONTROLLINGDIMENSIONS AREI
NMILLIMETERS; INCHDIMENSIONS
(INPARENTHESES)AREROUNDED-OFFMILLIMETEREQUIVALENTS FOR
REFERENCEONLYANDARENOT APPROPRIATEFOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDSMS-012-AA
012407-A
0.25 (0.0098)
0.17(0.0067)
1.27(0.0500)
0.40(0.0157)
0.50(0.0196)
0.25(0.0099)45°
8°
0°
1.75(0.0688)
1.35(0.0532)
SEATING
PLANE
0.25(0.0098)
0.10 (0.0040)
4
1
85
5.00(0.1968)
4.80(0.1890)
4.00(0.1574)
3.80(0.1497)
1.27(0.0500)
BSC
6.20(0.2441)
5.80(0.2284)
0.51(0.0201)
0.31 (0.0122)
COPLANARITY
0.10
Figure 59. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
COM P LIANT T O JEDE C S TANDARDS M O-187- AA
6°
0°
0.80
0.55
0.40
4
8
1
5
0.65 BSC
0.40
0.25
1.10 M AX
3.20
3.00
2.80
COPLANARITY
0.10
0.23
0.09
3.20
3.00
2.80
5.15
4.90
4.65
PIN 1
IDENTIFIER
15° M AX
0.95
0.85
0.75
0.15
0.05
10-07-2009-B
Figure 60. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
1
EXPOSED
PAD
BOTTOM VIEW
0.50
BSC
PIN 1
INDICATOR
0.50
0.40
0.30
TOP VI EW
12° M AX 0.70 MAX
0.65TYP
0.90 M AX
0.85 NO M 0.05 M AX
0.01 NO M
0.20 REF
2.23
2.13
2.03
4
1.60
1.50
1.40
3.25
3.00 SQ
2.75
2.95
2.75 SQ
2.55
58
PIN 1
INDICATOR
SEATING
PLANE 0.30
0.23
0.18
0.60 M AX
0.60 M AX
FO R P ROPE R CONNECTI ON O F
THE EXPOSED PAD, REFER TO
THE P IN CO NFI GURAT IO N AND
FUNCTION DES CRIPTI ONS
SECTION OF THIS DATA SHEET.
04-06-2012-A
Figure 61. 8-Lead Lead Frame Chip Scale Package [LFCSP_VD]
3 mm × 3 mm Body, Very Thin, Dual Lead
(CP-8-9)
Dimensions shown in millimeters
Rev. D | Page 21 of 22
ADA4610-2/ADA4610-4 Data Sheet
Rev. D | Page 22 of 22
CONTRO LLING DIME NS IO NS ARE IN M IL LI METERS ; INCH DIME NS IONS
(IN PARENTHESES) ARE ROUNDED-O FF MIL LI M ETER EQ UIVALENT S F OR
REF E RENCE ON LYAND ARE NO T APPROPRIATE F OR USE IN DE SIGN.
COMPL IANT TO JEDEC STANDARDS MS - 0 12-AB
060606-A
14 8
7
1
6.20 ( 0 . 2441)
5.80 ( 0 . 2283)
4.00 ( 0.1575)
3.80 ( 0.1496)
8.75 (0. 3 44 5)
8.55 (0. 3 36 6)
1.27 (0. 0 500 )
BSC
SEATING
PLANE
0.25 (0. 0 098 )
0.10 (0. 0 039 )
0.51 ( 0 . 0201)
0.31 ( 0 . 0122)
1.75 (0.0689)
1.35 (0.0531)
0.50 (0. 0 197 )
0.25 (0. 0 098 )
1.27 ( 0 .0500)
0.40 ( 0 .0157)
0.25 (0.0098)
0.17 (0.0067)
COPLANARITY
0.10
8°
0°
45°
Figure 62. 14-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-14)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option Branding
ADA4610-2ACPZ-R7 −40°C to +125°C 8-Lead Lead Frame Chip Scale Package [LFCSP_VD] CP-8-9 A2U
ADA4610-2ACPZ-RL −40°C to +125°C 8-Lead Lead Frame Chip Scale Package [LFCSP_VD] CP-8-9 A2U
ADA4610-2ARMZ −40°C to +125°C 8-Lead Mini Small Outline Package [MSOP] RM-8 A2U
ADA4610-2ARMZ-R7 −40°C to +125°C 8-Lead Mini Small Outline Package [MSOP] RM-8 A2U
ADA4610-2ARMZ-RL −40°C to +125°C 8-Lead Mini Small Outline Package [MSOP] RM-8 A2U
ADA4610-2ARZ −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
ADA4610-2ARZ-R7 −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
ADA4610-2ARZ-RL −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
ADA4610-2BRZ −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
ADA4610-2BRZ-R7 −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
ADA4610-2BRZ-RL −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
ADA4610-4ARZ −40°C to +125°C 14-Lead Standard Small Outline Package [SOIC_N] R-14
ADA4610-4ARZ-R7 −40°C to +125°C 14-Lead Standard Small Outline Package [SOIC_N] R-14
ADA4610-4ARZ-RL −40°C to +125°C 14-Lead Standard Small Outline Package [SOIC_N] R-14
1 Z = RoHS Compliant Part.
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registered trademarks are the property of their respective owners.
D09646-0-11/14(D)
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