—1— E90603H0Z-PS
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
Absolute Maximum Ratings (Ta=25 °C)
•Supply voltage AVDD, DVDD 7V
•Input voltage (All pins) VIN VDD+0.5 to VSS–0.5 V
•Output current (Every each channel)
IOUT 0 to 15 mA
•Storage temperature Tstg –55 to +150 °C
Recommended Operating Conditions
•Supply voltage AVDD, AVSS 4.75 to 5.25 V
DVDD, DVSS 4.75 to 5.25 V
•Reference input voltage
VREF 2.0 V
•Clock pulse width
TPW1, TPW0 11.2 ns (min.) to 1.1 µs (max.)
•Operating temperatureTopr –40 to +85 °C
Description
The CXD1178Q is an 8-bit high-speed D/A converter
for video band use. It has an input/output equivalent
to 3 channels of R, G and B. It is suitable for use of
digital TV, graphic display, and others.
Features
•Resolution 8-bit
•Maximum conversion speed 40MSPS
•RGB 3-channel input/output
•Differential linearity error ±0.3LSB
•Low power consumption 240 mW
(200 Ωload at 2 Vp-p output)
•Single 5 V power supply
•Low glitch noise
•Stand-by function
Structure
Silicon gate CMOS IC
8-bit 40MSPS RGB 3-channel D/A Converter
48 pin QFP (Plastic)
CXD1178Q
—2—
CXD1178Q
Block Diagram
DECODER
DECODER
DECODER
DECODER
DECODER
DECODER
LATCHES
LATCHES
LATCHES
32
35
34
42
29
41
40
31
30
33
28
39
38
46
45
44
43
27
37
36
48
47
2LSB’S
CURRENT
CELLS
6MSB’S
CURRENT
CELLS
CLOCK
GENERATOR
2LSB’S
CURRENT
CELLS
6MSB’S
CURRENT
CELLS
CLOCK
GENERATOR
2LSB’S
CURRENT
CELLS
6MSB’S
CURRENT
CELLS
CLOCK
GENERATOR
CURRENT CELLS
(FOR FULL SCALE)
BIAS VOLTAGE
GENERATOR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
(LSB) R0
(MSB) R7
(LSB) G0
(MSB) G7
(LSB) B0
B1
B2
B3
B4
B5
B6
(MSB) B7
BLK
CE
R1
R2
R3
R4
R5
R6
G1
G2
G3
G4
G5
G6
DVDD
DVDD
RO
RO
RCK
AVDD
AVDD
AVDD
AVDD
GO
GO
GCK
AVSS
DVSS
DVSS
BO
BO
BCK
VG
VREF
IREF
VB
—3—
CXD1178Q
Pin Configuration
R0
R1
R2
R3
R4
R5
R6
R7
G0
G1
G2
G3
B7
B6
B5
B4
B3
B2
B1
B0
G7
G6
G5
G4
BCK
RO
IREF
VREF
AVSS
VB
DVSS
DVSS
GCK
RCK
CE
BLK
RO
GO
GO
BO
BO
VG
AVDD
AVDD
AVDD
AVDD
DVDD
DVDD
1 2 3 4 5 6 7 8 9 10 11 12
13
14
15
16
17
18
19
20
21
22
23
24
252627282930313233343536
37
38
39
40
41
42
43
44
45
46
47
48
Pin Description and I/O Pins Equivalent Circuit
Pin No. Symbol I/O Equivalent circuit Description
1 to 8
9 to 16
17 to 24
25
32
R0 to R7
G0 to G7
B0 to B7
BLK
VB
I
I
O
1
24
DVDD
DVSS
to
DVDD
DVSS
25
DVDD
DVSS
32
DVDD
Digital input
R0 (LSB) to R7 (MSB)
G0 (LSB) to G7 (MSB)
B0 (LSB) to B7 (MSB)
Blanking input.
This is synchronized with the clock
input signal for each channel.
No signal at “H” (Output 0 V).
Output condition at “L”.
Connect a capacitor of about 0.1 µF.
—4—
CXD1178Q
Pin No. Symbol I/O Equivalent circuit Description
27
28
29
30, 31
33
26
35
34
42
43 to 46
RCK
GCK
BCK
DVSS
AVSS
CE
IREF
VREF
VG
AVDD
I
—
—
I
O
I
O
—
DVDD
DVSS
28
27
29
DVDD
DVSS
26
AVDD
AVSS
34
35
AVDD
AVSS
AVDD
AVDD
AVSS
42
Clock input.
Note) Even though 1 channel and/ or
2 channel are used, be sure to input
the clock signal to RCK.
Digital GND
Analog GND
Chip enable input.
This is not synchronized with the
clock input signal.
No signal (Output 0 V) at “H” and
minimizes power consumption.
Reference current output.
Connect a resistance 16 times
“16ROUT” that of output resistance
value “ROUT”.
Reference voltage input.
Set full scale output value.
Connect a capacitor of about 0.1 µF.
Analog VDD
—5—
CXD1178Q
Pin No. Symbol I/O Equivalent circuit Description
37
39
41
36
38
40
47, 48
RO
GO
BO
RO
GO
BO
DVDD
O
—
AVDD
AVSS
41
39
37
AVDD
AVSS
36
38
40
Current output pins.
Voltage output can be obtained by
connecting a resistance.
Inverted current output.
Normally dropped to analog GND.
Digital VDD
—6—
CXD1178Q
(fCLK=40 MHz, AVDD=DVDD=5 V, ROUT=200 Ω, VREF=2.0 V, Ta=25 °C)
Item
Resolution
Conversion speed
Integral non-linearity error
Differential non-linearity error
Output full-scale voltage
Output full-scale ratio ∗1
Output full-scale current
Output offset voltage
Glitch energy
Crosstalk
Supply current
Analog input resistance
Input capacitance
Digital input voltage
Digital input current
Setup time
Hold time
Propagation delay time
CE enable time ∗2
CE disable time ∗2
Symbol
n
fCLK
EL
ED
VFS
FSR
IFS
VOS
GE
CT
IDD
ISTB
RIN
CI
VIH
VIL
IIH
IIL
ts
th
tPD
tE
tD
Measurement conditions
AVDD=DVDD=4.75 to 5.25 V
Ta=–40 to 85 °C
Endpoint
When “00000000” data input
ROUT=75 Ω
When 1 MHz sine wave input
14.3MHz color bar CE= “L”
data input CE= “H”
VREF
AVDD=DVDD=4.75 to 5.25 V
Ta=–20 to 75 °C
AVDD=DVDD=4.75 to 5.25 V
Ta=–20 to 75 °C
ROUT=75 Ω
ROUT=75 Ω
CE= H→L
CE= L→H
Min.
0.5
–2.5
–0.3
1.8
0
1
2.4
–5
5
10
Typ.
8
2.0
1.5
10
30
57
42
1
10
1.8
1.8
Max.
40
2.5
0.3
2.2
3.0
15
1
48
2
9
0.8
5
4
4
Unit
bit
MSPS
LSB
LSB
V
%
mA
mV
pV•s
dB
mA
MΩ
pF
V
µA
ns
ns
ns
ms
ms
Full-scale voltage of channel
∗1Full-scale output ratio = Average of the full-scale voltage of the channels –1×100 (%)
∗2When the external capacitor for the VG pin is 0.1 µF.
—7—
CXD1178Q
Electrical Characteristics Measurement Circuit
Analog Input Resistance Measurement Circuit
Digital Input Current
CXD1178Q
+5.25V
AVDD, DVDD
AVSS, DVSS
V
A
Maximum Conversion Velocity Measurement Circuit
8bit
COUNTER
with
LATCH
0.1µ
DVSS
25
26
32
27
28
29
CLK
40MHz
SQUARE
WAVE
OSCILLOSCOPE
200 AVSS
200 AVSS
200 AVSS
AVDD
0.1µ
3.3k
AVSS
BLK
CE
VB
RCK
GCK
BCK
RO
GO
BO
VG
VREF
IREF
39
41
42
34
35
37
1k
R0 to R7
1 to 8
G0 to G7
9 to 16
B0 to B7
17 to 24
}
—8—
CXD1178Q
Crosstalk Measurement Circuit
DIGITAL
WAVEFORM
GENERATOR
200 AVSS
AVDD
0.1µ
3.3k
AVSS
BLK
CE
VB
RCK
GCK
BCK
RO
GO
BO
VG
VREF
IREF
0.1µ
DVSS
25
26
32
27
28
29
CLK
40MHz
SQUARE
WAVE
1k
200 AVSS
200 AVSS
39
41
42
34
35
37
SPECTRUM
ANALIZER
ALL “1”
R0 to R7
1 to 8
G0 to G7
9 to 16
B0 to B7
17 to 24
Setup Time
Hold Time Measurement Circuit
Glitch Energy
8bit
COUNTER
with
LATCH
DELAY
CONTROLLER AVDD
0.1µ
1.2k
AVSS
75
AVSS
75
AVSS
75
AVSS
0.1µ
DVSS
BLK
CE
VB
RCK
GCK
BCK
RO
GO
BO
VG
VREF
IREF
39
41
42
34
35
37
DELAY
CONTROLLER
25
26
32
27
28
29
1k
OSCILLOSCOPE
CLK
1MHz
SQUARE
WAVE
R0 to R7
1 to 8
G0 to G7
9 to 16
B0 to B7
17 to 24
}
—9—
CXD1178Q
DC Characteristics Measurement Circuit
200 AVSS
200 AVSS
200 AVSS
AVDD
0.1µ
3.3k
AVSS
BLK
CE
VB
RCK
GCK
BCK
RO
GO
BO
VG
VREF
IREF
0.1µ
DVSS
CLK
40MHz
SQUARE
WAVE
CONTROLLER DVM
1k
25
26
32
27
28
29
39
41
42
34
35
37
R0 to R7
1 to 8
G0 to G7
9 to 16
B0 to B7
17 to 24
Propagation Delay Time Measurement Circuit
200 AVSS
200 AVSS
200 AVSS
CLK
10MHz
SQUARE
WAVE
BLK
CE
VB
RCK
GCK
BCK
RO
GO
BO
VG
VREF
IREF
0.1µ
DVSS
25
26
32
27
28
29
FREQUENCY
DEMULTIPLIER
AVDD
0.1µ
3.3k
AVSS
1k
39
41
42
34
35
37
OSCILLOSCOPE
R0 to R7
1 to 8
G0 to G7
9 to 16
B0 to B7
17 to 24
—10—
CXD1178Q
Description of Operation
Timing Chart
I/O Chart (when full scale output voltage at 2.00 V)
Application Circuit
CLK
AA
AA
AA
AAA
AAA
AAA
AA
AA
AA
AAA
AAA
AAA
DATA
D/A OUT
tPW1 tPW0
2V
tsthtsthtsth
tPD tPD
tPD 100%
50%
0%
DVDD AVDD
0.1µ
2V
(LSB)
(MSB)
(LSB)
1
2
3
4
5
6
7
8
9
10
11
12
R (Red) IN
G (Green) IN
B (Blue) IN
(MSB)
(LSB)
(MSB)
200
200
200
B (Blue) OUT
AVSS
G (Green) OUT
AVSS
R (Red) OUT
AVSS
373839404142434445464748
3.3k
AVSS
AVDD
1k
AVSS
0.1µF
DVSS
DVSS
CLOCK IN
36
35
34
33
32
31
30
29
28
27
26
25
13 14 15 16 17 18 19 20 21 22 23 24
•
•
•
•
•
•
•
•• ••••••
Input code
MSB LSB
1 1 1 1 1 1 1 1
:
1 0 0 0 0 0 0 0
:
0 0 0 0 0 0 0 0
Output voltage
2.0 V
1.0 V
0 V
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
Note) Even though 1 channel
and/ or 2 channel are used, be
sure to input the clock signal to
RCK(Pin 27).
—11—
CXD1178Q
Notes on Operation
•How to select the output resistance
The CXD1178Q is a D/A converter of the current output type. To obtain the output voltage connect the
resistance to current output pins (RO, GO and BO). For specifications we have;
Output full scale voltage VFS=1.8 to 2.2 [V]
Output full scale current IFS=less than 15 [mA]
Calculate the output resistance value from the relation of VFS=IFS ×ROUT. Also, 16 times resistance of the
output resistance is connected to reference current pin IREF. In some cases, however, this turns out to be a
value that does not actually exist. In such a case a value close to it can be used as a substitute.
Here please note that VFS becomes
VFS=VREF ×16ROUT/RIR.
VREF is the voltage set at the VREF pin and ROUT is the resistance connected to current output pins (RO, GO
and BO) while RIR is connected to IREF.
Increasing the resistance value can curb power consumption. On the other hand glitch energy and data
settling time will inversely increase. Set the most suitable value according to the desired application.
•Phase relation between data and clock
To obtain the expected performance as a D/A converter, it is necessary to set properly the phase relation
between data and clock applied from the exterior. Be sure to satisfy the provisions of the setup time (tS) and
hold time (tH) as stipulated in the Electrical Characteristics.
•Power supply and ground
To reduce noise effects separate analog and digital systems in the device periphery. For power supply pins,
both digital and analog, bypass respective grounds by using a ceramic capacitor of about 0.1 µF, as close as
possible to the pin.
•Latch up
Analog and digital power supply have to be common at the PCB power supply source. This is to prevent
latch up due to voltage difference between AVDD and DVDD pins when power supply is turned ON.
•On inverted current output pins
The RO, GO and BO are the inverted current output terminal as described in the Pin Description.
The sums shown below become the constant value for any input data.
a) The sum of the currents output from the RO and RO pins.
b) The sum of the currents output from the GO and GO pins.
c) The sum of the currents output from the BO and BO pins.
However, the output current from the RO, GO and BO pins is not guaranteed of its performances such as
linearity errors, etc.
•On output full-scale voltage
When the output full-scale voltage is used without adjustment in the application that uses the RGB signal, the
color balance may be broke.
•Clock input signal
Even though 1 channel and/ or 2 channel are used, be sure to input the clock signal to RCK(Pin 27).
—12—
CXD1178Q
Latch Up Prevention
The CXD1178Q is a CMOS IC which required latch up precautions. Latch up is mainly generated by the lag in
the voltage rising time of AVDD (Pins 43 to 46) and DVDD (Pins 47 and 48), when power supply is ON.
1. Correct usage
a. When analog and digital supplies are from different sources
b. When analog and digital supplies are from a common source
(i)
(ii)
43
CXD1178Q
AVSS
AVDD
44 45 46
33
AVDD DVDD
DVSSAVSS
CC
31
DVSS
+5V +5V
30
47 48
DIGITAL IC
DVDD
43
CXD1178Q
AVSS
44 45 46
33
AVDD DVDD
DVSSAVSS
CC
31
DVSS
+5V
30
47 48
DIGITAL IC
DVDD
43
CXD1178Q
AVSS
44 45 46
33
AVDD DVDD
DVSSAVSS
CC
31
DVSS
+5V
30
47 48
DIGITAL IC
DVDD
—13—
CXD1178Q
2. Example when latch up easily occurs
a. When analog and digital supplies are from different sources
b. When analog and digital supplies are from common source
(i)
(ii)
43
CXD1178Q
AVSS
AVDD
44 45 46
33
AVDD DVDD
DVSSAVSS
CC
31
DVSS
+5V +5V
30
47 48
DIGITAL IC
DVDD
43
CXD1178Q
AVSS
44 45 46
33
AVDD DVDD
DVSSAVSS
CC
31
DVSS
+5V
30
47 48
DIGITAL IC
DVDD
AVDD
43
CXD1178Q
AVSS
44 45 46
33
AVDD DVDD
DVSSAVSS
C
31
DVSS
+5V
30
47 48
DIGITAL IC
DVDD
AVDD
—14—
CXD1178Q
Example of Representative Characteristics
Output full scale voltage vs. Reference voltage
Reference voltage VREF [V]
Output full scale voltage VFS [V]
100
Glitch energy vs. Output resistance
Output resistance ROUT [Ω]
200
Crosstalk CT [dB]
Crosstalk vs. Output frequency
Output frequency FOUT [Hz]
2.0
1.0
01.0 2.0
200
100
AVDD=DVDD=5V
VREF=2.0V
RIR≈16ROUT
Ta=25°C
60
50
40
100k 1M 10M
AVDD=DVDD=5V
VREF=2.0V
ROUT=200Ω
RIR=3.3kΩ
Ta=25°C
AVDD=DVDD=5V
ROUT=200Ω
RIR=3.3kΩ
Ta=25°C
2.0
1.9
0–25 0 25 50 75
AVDD=DVDD=5V
VREF=2.0V
ROUT=200
RIR=3.3k Ω
Ω
–40 85
Output full scale VFS [V]
Output full scale voltage vs. Ambient temperature
Ambient temperature Ta [°C]
Glitch energy GE [pV•s]
SONY CODE
EIAJ CODE
JEDEC CODE
M
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE MASS
EPOXY RESIN
SOLDER PLATING
42/COPPER ALLOY
48PIN QFP (PLASTIC)
15.3 ± 0.4
12.0 – 0.1
+ 0.4
0.8 0.3 – 0.1
+ 0.15
0.24
13
24
2536
37
48
112
2.2 – 0.15
+ 0.35
0.9 ± 0.2
0.1 – 0.1
+ 0.2
13.5
0.15 – 0.05
+ 0.1
QFP-48P-L04
QFP048-P-1212
0.7g
0.15
Package Outline Unit : mm
CXD1178Q
—15—
—16—
CXD1178Q
Sony Corporation
SONY CODE
EIAJ CODE
JEDEC CODE
M
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE MASS
EPOXY RESIN
PALLADIUM PLATING
COPPER ALLOY
48PIN QFP (PLASTIC)
15.3 ± 0.4
12.0 – 0.1
+ 0.4
0.8 0.3 – 0.1
+ 0.15
0.24
13
24
2536
37
48
112
2.2 – 0.15
+ 0.35
0.9 ± 0.2
0.1 – 0.1
+ 0.2
13.5
0.15 – 0.05
+ 0.1
QFP-48P-L04
QFP048-P-1212
0.7g
0.15
Package Outline Unit : mm
