XL Family of Low Phase Noise Quartz-based PLL Oscillators Description Features The IDT XL devices (XO and VCXO options) are ultra-precision crystal oscillators with 750 to 890fs typical phase jitter over 12kHz to 20MHz bandwidth. Available in a wide frequency range from 0.750MHz to 1350MHz, the XL series crystal oscillators utilize a family of proprietary ASICs, with a key focus on noise reduction technologies. XL Datasheet Output types: LVDS, LVPECL, LVCMOS Phase jitter (12kHz to 20MHz): 750fs to 890fs typical Supply voltage: 2.5V or 3.3V Package options: * 3.2 x 2.5 x 1.0 mm (not available for VCXO) * 5.0 x 3.2 x 1.2 mm * 7.0 x 5.0 x 1.3 mm Operating temperature: -20C to +70C * Frequency stability options: 20, 25, 50, or 100 ppm (XO only) The 3rd order Delta Sigma Modulator reduces noise to the levels that are comparable to traditional Bulk Quartz and SAW oscillators. With short lead-time, low cost, low noise, wide frequency range, excellent ambient performance, the XL devices are an excellent choice over the conventional technologies. The XL (XO option) devices have stabilities as tight as 20ppm and the XL (VCXO option) devices have 50ppm APR. Either option provides extremely quick delivery for both standard and custom frequencies. * 50ppm APR (VCXO only) Operating temperature: -40C to +85C * Frequency stability options: 25, 50, or 100 ppm (XO only) * 50ppm APR (VCXO only) Operating temperature: -40C to +105C (XO only) * Frequency stability options: 50 or 100 ppm kV of 85ppm/volt typical from 0.5VDC to VDD (VCXO only) * Better than 10% linearity for Vc range Pin Assignments (XO option) 2 3 1 NC / E/D GND Table 1. XO 6-pin Package OUT 1 3 2 GND VDD 4 NC OUT 4 NC OUT2 5 E/D VDD 6 E/D / NC NOTE: To minimize power supply line noise, a 0.01F bypass capacitor should be placed between V DD (Pin 6) and GND (Pin 3) on 6-pin devices, or VDD (Pin 4) and GND (Pin 2) on 4-pin devices. Table 2. XO 4-pin Package Number Name Description Number Name Description 1 E/D NC 2 NC E/D 1 2 3 4 GND OUT OUT2 VDD E/D GND OUT VDD Enable/Disable [a][b] Connect to ground Output Supply voltage 3 4 5 6 Enable/Disable [a][b] No connect No connect Enable/Disable [a][b] Connect to ground Output Complementary output Supply voltage (c)2020 Renesas Electronics Corporation [a] Pulled high internally. [b] Low = output disabled. See Ordering Information (XO) for more details. 1 April 27, 2020 XL Datasheet Pin Assignments (VCXO option) OUT2 OUT 5 4 1 2 3 E/D GND VDD 6 Vc NOTE: To minimize power supply line noise, a 0.01F bypass capacitor should be placed between VDD (Pin 6) and GND (Pin 3). Table 3. VCXO 6-pin Package Number Name Description 1 Vc Voltage control 2 E/D Enable/Disable [a][b] 3 GND Connect to ground 4 OUT Output 5 OUT2 Complementary output (NC LVCMOS) 6 VDD Supply voltage [a] Pulled high internally. [b] Low = output disabled. See Ordering Information (VCXO) for more details. (c)2020 Renesas Electronics Corporation 2 April 27, 2020 XL Datasheet Contents Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin Assignments (XO option) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin Assignments (VCXO option) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ESD Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Mechanical Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Solder Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Output Waveforms - LVDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Output Waveforms - LVPECL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Output Waveforms - LVCMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Package Outline Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Ordering Information (XO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Ordering Information (VCXO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 (c)2020 Renesas Electronics Corporation 3 April 27, 2020 XL Datasheet Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the device. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Table 4. Absolute Maximum Ratings Item Rating -0.5 to +5.0V -0.5V to VDD + 0.5V -0.5V to VDD + 0.5V -55C to 125C 125C 65mA maximum VDD E/D OUT Storage Temperature Maximum Junction Temperature Core Current Theta JA Theta JB JU6 7.0 x 5.0 x 1.3 mm 75.9 C/W 48.6C/W JS6 5.0 x 3.2 x 1.2 mm 89.6 C/W 54.3 C/W 94.7 C/W 66.8 C/W JX6 3.2 x 2.5 x 1.0 mm ESD Compliance Table 5. ESD Compliance Human Body Model (HBM 1000V Machine Model (MM) 150V Mechanical Testing Table 6. Mechanical Testing Parameter Test Method Mechanical Shock Drop from 75cm to hardwood surface-3 times. Mechanical Vibration 10-55Hz, 1.5mm amplitude, 1 minute sweep; 2 hours each in 3 directions (X, Y, Z). High Temperature Burn-in Under power at 125C for 2000 hours. He pressure: 4 1kgf/cm2 2 hour soak. Hermetic Seal Solder Reflow Profile tP 10 seconds Max within 5C of 260C peak 260C Ramp up 3C/s Max 225C 180C 120 20 seconds in pre-heating area 160C 50 10 seconds above 225C reflow area Ramp down not to exceed 6C/s 25C 400 seconds MAX from +25C to 260C peak (c)2020 Renesas Electronics Corporation 4 April 27, 2020 XL Datasheet DC Electrical Characteristics Table 7. 3.3V IDD DC Electrical Characteristics VDD = 3.3V 5%, TA = -20C to +70C; -40C to +85C, -40C to +105C. Symbol IDD Parameter Output Type Conditions Minimum Typical Maximum LVDS -- -- -- 100 LVPECL -- -- -- 120 0.75MHz to 20MHz. -- -- 32 20+MHz to 50MHz. -- -- 35 50+MHz to 130MHz. -- -- 47 130+MHz to 200MHz. -- -- 55 200+MHz to 250MHz. -- -- 60 Minimum Typical Maximum 0.75MHz to 20MHz. -- -- 26 20+MHz to 220MHz. -- -- 34 220+MHz to 630MHz. -- -- 44 630+MHz to 1000MHz. -- -- 65 0.75MHz to 20MHz. -- -- 33 20+MHz to 220MHz. -- -- 41 220+MHz to 630MHz. -- -- 63 630+MHz to 1000MHz. -- -- 72 0.75MHz to 20MHz. -- -- 22 20+MHz to 50MHz. -- -- 25 50+MHz to 100MHz. -- -- 29 100+MHz to 130MHz. -- -- 32 130+MHz to 160MHz. -- -- 35 160+MHz to 180MHz. -- -- 37 Power Supply Current LVCMOS Units mA Table 8. 2.5V IDD DC Electrical Characteristics VDD = 2.5V 5%, TA = -20C to +70C; -40C to +85C, -40C to +105C. Symbol Parameter Output Type LVDS LVPECL IDD Power Supply Current LVCMOS (c)2020 Renesas Electronics Corporation Conditions 5 Units mA April 27, 2020 XL Datasheet Table 9. LVDS DC Electrical Characteristics VDD = 3.3V, 2.5V 5%, T A = -20C to +70C; -40C to +85C, -40C to +105C. Below are guaranteed for listed standard frequencies. Symbol Parameter Conditions Minimum Typical Maximum VDD = 3.3V 5%. -- -- 0.6 VDD = 2.5V 5%. -- -- 0.4 VDD = 3.3V 5%. -- -- 1.3 VDD = 2.5V 5%. -- -- 1.25 VOD Differential Output Voltage VOS Output Offset Voltage VIH Enable/Disable Input High Voltage (Output enabled) -- 70% VDD -- -- VIL Enable/Disable Input Low Voltage (Output disabled) -- -- -- 30% VDD Units V Table 10. LVPECL DC Electrical Characteristics VDD = 3.3V, 2.5V 5%, T A = -20C to +70C; -40C to +85C, -40C to +105C. Below are guaranteed for listed standard frequencies. Symbol Parameter Conditions Minimum Typical Maximum VDD = 3.3V 5%. 2.055 VDD = 2.5V 5%. -- VDD = 3.3V 5%. 1.305 VDD = 2.5V 5%. -- 0.68 -- 2.405 VOD Differential Output Voltage VOS Output Offset Voltage VIH Enable/Disable Input High Voltage (Output enabled) -- 70% VDD -- -- VIL Enable/Disable Input Low Voltage (Output disabled) -- -- -- 30% VDD (c)2020 Renesas Electronics Corporation 6 Units 1.4 -- 1.65 V April 27, 2020 XL Datasheet Table 11. LVCMOS DC Electrical Characteristics VDD = 3.3V, 2.5V 5%, T A = -20C to +70C; -40C to +85C, -40C to +105C. Below are guaranteed for listed standard frequencies. Symbol Parameter Conditions VDD = 3.3V 5%. VOH Output High Voltage VDD = 2.5V 5%. VDD = 3.3V 5%. VOL Output Low Voltage VDD = 2.5V 5%. Minimum Typical Maximum 0.75MHz to 150MHz. 90% VDD -- -- 150+MHz to 250MHz. 80% VDD -- -- 0.75MHz to 160MHz. 90% VDD -- -- 160+MHz to 180MHz. 80% VDD -- -- 0.75MHz to 150MHz. -- -- 10% VDD 150+MHz to 250MHz. -- -- 20% VDD 0.75MHz to 160MHz. -- -- 10% VDD 160+MHz to 180MHz. -- -- 20% VDD VIH Enable/Disable Input High Voltage (Output enabled) -- -- 70% VDD -- -- VIL Enable/Disable Input Low Voltage (Output disabled) -- -- -- -- 30% VDD (c)2020 Renesas Electronics Corporation 7 Units V April 27, 2020 XL Datasheet AC Electrical Characteristics Table 12. 3.3V AC Electrical Characteristics VDD = 3.3V 5%, TA = -20C to +70C; -40C to +85C, -40C to +105C. Symbol F Parameter Output Frequency Range Frequency Stability tR Minimum Typical Maximum LVDS. 0.75 -- 1350 LVPECL. 0.75 -- 1350 LVCMOS. 0.75 -- 250 Temperature = -20C to +70C. 20 -- 100 ppm Temperature = -40C to +85C. 25 -- 100 ppm Temperature = -40C to +105C. 50 -- 100 ppm -- -- 3 ppm Aging (10 years) TA = 25C. -- -- 10 ppm Start-up Time Output Rise Time LVDS. Differential. -- 100 -- LVPECL. VDD - 2.0V. -- 50 -- LVCMOS. To GND. -- 15 -- pF Output valid time after VDD meets minimum specified level. -- -- 10 ms LVDS. -- -- 400 -- -- 400 -- -- 3 -- -- 400 -- -- 400 -- -- 3 LVDS. 45 -- 55 LVPECL. 45 -- 55 FOUT < 62.5MHz. 45 -- 55 FOUT > 62.5MHz. 40 -- 60 -- -- 100 LVDS. -- 3 -- LVPECL. -- 5.8 -- -- 5 -- LVDS. -- 1.3 -- LVPECL. -- 1.29 -- -- 0.6 -- LVDS. -- 5.8 -- LVPECL. -- 9.3 -- -- 10 -- 20% to 80% Vpp. LVPECL. 10% to 90% VDD. LVDS. Output Fall Time 80% to 20% Vpp. LVPECL. LVCMOS. ODC Output Clock Duty Cycle 90% to 10% VDD. LVCMOS. TOE JPER Output Enable/ Disable Time Period Jitter, RMS -- LVCMOS. RJ Random Jitter LVCMOS. DJ MHz TA = 25C. LVCMOS. tF Units Aging (1st year) Output Load TST Test Condition Deterministic Jitter LVCMOS. (c)2020 Renesas Electronics Corporation FOUT = 125MHz. FOUT = 125MHz. FOUT = 125MHz. 8 ps ns ps ns % ns ps ps ps April 27, 2020 XL Datasheet Table 12. 3.3V AC Electrical Characteristics (Cont.) VDD = 3.3V 5%, TA = -20C to +70C; -40C to +85C, -40C to +105C. Symbol TJ Parameter Total Jitter Test Condition Minimum Typical Maximum LVDS. -- 23.6 -- LVPECL. -- 27.7 -- -- 19 -- LVDS. -- 890 -- LVPECL. -- 860 -- -- 750 -- Minimum Typical Maximum LVDS. 0.75 -- 1000 LVPECL. 0.75 -- 1000 LVCMOS. 0.75 -- 180 Temperature = -20C to +70C. 20 -- 100 ppm Temperature = -40C to +85C. 25 -- 100 ppm Temperature = -40C to +105C. 50 -- 100 ppm LVCMOS. fJITTER Phase Jitter (12kHz-20MHz) FOUT = 125MHz. FOUT = 125MHz. LVCMOS. Units ps fs Table 13. 2.5V AC Electrical Characteristics VDD = 2.5V 5%, TA = -20C to +70C; -40C to +85C, -40C to +105C. Symbol F Parameter Output Frequency Range Frequency Stability tR -- -- 3 ppm Aging (10 years) TA = 25C. -- -- 10 ppm Start-up Time Output Rise Time LVDS. Differential. -- 100 -- LVPECL. VDD - 2.0V. -- 50 -- LVCMOS. To GND. -- 15 -- pF Output valid time after VDD meets minimum specified level. -- -- 10 ms LVDS. -- -- 400 -- -- 400 -- -- 3.5 -- -- 400 -- -- 400 -- -- 3 LVDS. 45 -- 55 LVPECL. 45 -- 55 LVCMOS. 45 -- 55 -- -- 100 20% to 80% Vpp. LVPECL. 10% to 90% VDD. LVDS. Output Fall Time 80% to 20% Vpp. LVPECL. LVCMOS. ODC TOE MHz TA = 25C. LVCMOS. tF Units Aging (1st year) Output Load TST Test Condition Output Clock Duty Cycle Output Enable/ Disable Time (c)2020 Renesas Electronics Corporation 90% to 10% VDD. -- 9 ps ns ps ns % ns April 27, 2020 XL Datasheet Table 13. 2.5V AC Electrical Characteristics (Cont.) VDD = 2.5V 5%, TA = -20C to +70C; -40C to +85C, -40C to +105C. Symbol JPER Parameter Period Jitter, RMS Test Condition Minimum Typical Maximum LVDS. -- 4 -- LVPECL. -- 5.12 -- -- 3.3 -- LVDS. -- 1.4 -- LVPECL. -- 1.36 -- -- 1.3 -- LVDS. -- 9.2 -- LVPECL. -- 10 -- -- 6.7 -- LVDS. -- 29.2 -- LVPECL. -- 29.3 -- -- 25.6 -- LVDS. -- 1040 -- LVPECL. -- 1200 -- -- 850 -- LVCMOS. RJ Random Jitter LVCMOS. DJ Deterministic Jitter LVCMOS. TJ Total Jitter LVCMOS. fJITTER Phase Jitter (12kHz-20MHz) LVCMOS. FOUT = 125MHz. FOUT = 125MHz. FOUT = 125MHz. FOUT = 125MHz. FOUT = 125MHz. Units ps ps ps ps fs Notes for all AC Electrical Characteristics tables: 1 All jitter values provided at 156.25MHz, unless noted otherwise. (c)2020 Renesas Electronics Corporation 10 April 27, 2020 XL Datasheet Output Waveforms - LVDS Output Levels/Rise Time/Fall Time Measurements TF TR OUTPUT 2 50% VPP 20% to 80% VPP VOS VOD OUTPUT 1 Oscillator Symmetry Ideally, Symmetry should be 50/50 for 1/2 period -Other expressions are 45/55 or 55/45 VOH OUTPUT 2 50% VPP OUTPUT 1 VOL 1/2 Period Period Output Waveforms - LVPECL Rise Time/Fall Time Measurements TF TR VOH OUTPUT 2 20% to 80% VPP OUTPUT 1 VOL Oscillator Symmetry VOH OUTPUT 2 50% VPP OUTPUT 1 VOL 1/2 Period Period (c)2020 Renesas Electronics Corporation 11 April 27, 2020 XL Datasheet Output Waveforms - LVCMOS (c)2020 Renesas Electronics Corporation 12 April 27, 2020 XL Datasheet Package Outline Drawings The package outline drawings are appended at the end of this document and are accessible from the links below. The package information is the most current data available. www.idt.com/document/psc/js6-package-outline-50-x-32-mm-body-11-mm-thick www.idt.com/document/psc/jx6-package-outline-32-x-25-mm-body-09-mm-thick www.idt.com/document/psc/ju6-package-outline-70-x-50-mm-body-13-mm-thick www.idt.com/document/psc/js4-package-outline-50-x-32-mm-body-11-mm-thick www.idt.com/document/psc/ju4-package-outline-70-x-50-mm-body-13-mm-thick www.idt.com/document/psc/jx4-package-outline-32-x-25-mm-body-09-mm-thick Ordering Information (XO) XL L 5 3 5 125.000000 I FamilyandASIC OutputType Package Voltage Precision Frequency TemperatureRange 2:2.5VDC5% 3: 3.3VDC5% 3: 3.2x2.5mm 5: 5.0x3.2mm 7:7.0x5.0mm I: Industrialrange: 40to+85C K: Extendedindustrialrange:40to+105C X: Extendedcommercialrange:20t o+70C 125.000000listedinMHzasexample 3digitsbeforedecimaland6digitsafterdecimal H: HCMOSEnable/DisablePin1 J: HCMOSEnable/DisablePin2 L:LVDSEnable/DisablePin1 M:LVDSEnable/DisablePin2 P:LVPECLEnable/DisablePin1 Q:LVPECLEnable/DisablePin2 X:XHCMOSCompHCMOSEnable/DisablePin1 Y:XHCMOSCompHCMOSEnable/DisablePin2 000.750000to000.999999 75kHzto999.999kHz 001.000000to009.999999 1MHzto9.999999MHz 010.000000to099.999999 10MHzto99.999999MHz 100.000000to999.999999 100MHzto999.999999MHz A00.000000toA99.999999 1000MHzto1099.999MHz B00.000000toB99.999999 1100MHzto1199.999MHz C00.000000toC99.9999991200MHzto1299.999MHz D00.000000toD50.000000 1300MHzto1 350MHz XL: 1,000fsjitter 0:100ppm** 5: 50ppm** 6:25ppm 8: 20ppm* *20ppmforX(20to+70C)only. **100ppmand50ppmforK(40Cto+105C)only. (c)2020 Renesas Electronics Corporation 13 April 27, 2020 XL Datasheet Ordering Information (VCXO) XL L 5 3 FamilyandASIC OutputType Package Voltage V 125.000000 I Frequency TemperatureRange 2:2.5VDC5% 3: 3.3VDC5% 5: 5.0x3.2mm 7:7.0x5.0mm I: Industrialrange: 40to+85C X: Extendedcommercialrange:20to+70C 125.000000listedinMHzasexample 3digitsbeforedecimaland6digitsafterdecimal 000.750000to000.999999 001.000000to009.999999 010.000000to099.999999 100.000000to999.999999 H: HCMOSEnable/Disable L:LVDSEnable/Disable P:LVPECLEnable/Disable 75kHzto999.999kHz 1MHzto9.999999MHz 10MHzto99.999999MHz 100MHzto999.999999MHz A00.000000toA99.999999 1000MHzto1099.999MHz B00.000000toB99.999999 1100MHzto1199.999MHz C00.000000toC99.9999991200MHzto1299.999MHz D00.000000toD50.000000 1300MHzto1350MHz XL: 1,000fsjitter V:VCXOoption (c)2020 Renesas Electronics Corporation 14 April 27, 2020 XL Datasheet Revision History Revision Date Description of Change April 27, 2020 Updated ODC parameter. 2nd LVCMOS row to be changed from <= to > 62.5 MHz. September 7, 2018 Updated frequency stability options value from 20ppm to 25ppm for -40C to +85C XO only. June 25, 2018 Updated Package Outline Drawings section. May 4, 2018 January 12, 2018 Initial release. Added XO and VCXO options. Updated description and Features sections. Updated Package Outline Drawings section. Added VCXO Ordering Information decoder diagram. (c)2020 Renesas Electronics Corporation 15 April 27, 2020 IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES ("RENESAS") PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES "AS IS" AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. You are solely responsible for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. Renesas grants you permission to use these resources only for development of an application that uses Renesas products. Other reproduction or use of these resources is strictly prohibited. No license is granted to any other Renesas intellectual property or to any third party intellectual property. Renesas disclaims responsibility for, and you will fully indemnify Renesas and its representatives against, any claims, damages, costs, losses, or liabilities arising out of your use of these resources. Renesas' products are provided only subject to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use of any Renesas resources expands or otherwise alters any applicable warranties or warranty disclaimers for these products. (Rev.1.0 Mar 2020) Corporate Headquarters Contact Information TOYOSU FORESIA, 3-2-24 Toyosu, Koto-ku, Tokyo 135-0061, Japan www.renesas.com For further information on a product, technology, the most up-to-date version of a document, or your nearest sales office, please visit: www.renesas.com/contact/ Trademarks Renesas and the Renesas logo are trademarks of Renesas Electronics Corporation. All trademarks and registered trademarks are the property of their respective owners. (c) 2020 Renesas Electronics Corporation. All rights reserved.