SLAS235B - JULY 1999 - REVISED APRIL 2004 D OR DGK PACKAGE (TOP VIEW) features D 8-Bit Voltage Output DAC D Programmable Internal Reference D Programmable Settling Time: D D D DIN SCLK CS FS 1 s in Fast Mode, 3.5 s in Slow Mode Compatible With TMS320 and SPI Serial Ports Differential Nonlinearity . . . <0.2 LSB Monotonic Over Temperature 1 8 2 7 3 6 4 5 VDD OUT REF AGND applications D D D D D Digital Servo Control Loops Digital Offset and Gain Adjustment Industrial Process Control Machine and Motion Control Devices Mass Storage Devices description The TLV5624 is a 8-bit voltage output DAC with a flexible 4-wire serial interface. The serial interface allows glueless interface to TMS320 and SPI, QSPI, and Microwire serial ports. It is programmed with a 16-bit serial string containing 4 control and 8 data bits. The resistor string output voltage is buffered by a x2 gain rail-to-rail output buffer. The programmable settling time of the DAC allows the designer to optimize speed vs power dissipation. With its on-chip programmable precision voltage reference, the TLV5624 simplifies overall system design. Because of its ability to source up to 1 mA, the reference can also be used as a system reference. Implemented with a CMOS process, the device is designed for single supply operation from 2.7 V to 5.5 V. It is available in an 8-pin SOIC and 8-pin MSOP package to reduce board space in standard commercial and industrial temperature ranges. AVAILABLE OPTIONS PACKAGE TA SOIC (D) MSOP (DGK) 0C to 70C TLV5624CD TLV5624CDGK -40C to 85C TLV5624ID TLV5624IDGK Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SPI and QSPI are trademarks of Motorola, Inc. Microwire is a trademark of National Semiconductor Corporation. Copyright 2002-2004, Texas Instruments Incorporated !"# $ %&'# "$ (&)*%"# +"#' +&%#$ %! # $('%%"#$ (' #,' #'!$ '-"$ $#&!'#$ $#"+"+ .""#/ +&%# (%'$$0 +'$ # '%'$$"*/ %*&+' #'$#0 "** (""!'#'$ WWW.TI.COM 1 SLAS235B - JULY 1999 - REVISED APRIL 2004 functional block diagram REF PGA With Output Enable Voltage Bandgap Power and Speed Control Power-On Reset 2 2 2-Bit Control Latch DIN Serial Interface and Control SCLK CS 8 8 8-Bit DAC Latch FS Terminal Functions TERMINAL NAME NO. I/O/P DESCRIPTION AGND 5 P Ground CS 3 I Chip select. Digital input active low, used to enable/disable inputs DIN 1 I Digital serial data input FS 4 I Frame sync input OUT 7 O DAC A analog voltage output REF 6 I/O Analog reference voltage input/output SCLK 2 I Digital serial clock input VDD 8 P Positive power supply 2 WWW.TI.COM x2 OUT SLAS235B - JULY 1999 - REVISED APRIL 2004 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage (VDD to AGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Reference input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to VDD + 0.3 V Digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to VDD + 0.3 V Operating free-air temperature range, TA: TLV5624C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C TLV5624I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to 85C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions Supply voltage, VDD VDD = 5 V VDD = 3 V Power on reset, POR DVDD = 2.7 V DVDD = 5.5 V Low-level digital input voltage, VIL DVDD = 2.7 V DVDD = 5.5 V Reference voltage, Vref to REF terminal NOM MAX 4.5 5 5.5 2.7 3 3.3 0.55 High-level digital input voltage, VIH Reference voltage, Vref to REF terminal MIN V V 2 V 2.4 0.6 1 VDD = 5 V (see Note 1) VDD = 3 V (see Note 1) Load resistance, RL AGND 2.048 AGND 1.024 VDD -1.5 VDD -1.5 2 Load capacitance, CL Clock frequency, fCLK Operating free-air temperature, TA 2 UNIT TLV5624C TLV5624I V V V k 100 pF 20 MHz 0 70 -40 85 C NOTE 1: Due to the x2 output buffer, a reference input voltage (VDD-0.4 V)/2 causes clipping of the transfer function. The output buffer of the internal reference must be disabled, if an external reference is used. WWW.TI.COM 3 SLAS235B - JULY 1999 - REVISED APRIL 2004 electrical characteristics over recommended operating conditions (unless otherwise noted) power supply PARAMETER IDD Power supply current Power down supply current PSRR Power supply rejection ratio TEST CONDITIONS TYP MAX Fast 2.3 3.3 Slow 1.5 1.9 See Figure 8 0.01 10 Zero scale, See Note 2 -65 Full scale, -65 No load, All inputs = AGND or VDD, DAC latch = 0x800 MIN UNIT mA See Note 3 A dB NOTES: 2. Power supply rejection ratio at zero scale is measured by varying VDD and is given by: PSRR = 20 log [(EZS(VDDmax) - EZS(VDDmin))/VDDmax] 3. Power supply rejection ratio at full scale is measured by varying VDD and is given by: PSRR = 20 log [(EG(VDDmax) - EG(VDDmin))/VDDmax] static DAC specifications PARAMETER TEST CONDITIONS MIN Resolution TYP MAX 8 UNIT bits INL Integral nonlinearity, end point adjusted See Note 4 0.3 0.5 LSB DNL Differential nonlinearity See Note 5 0.07 0.2 LSB EZS EZS TC Zero-scale error (offset error at zero scale) See Note 6 20 mV Zero-scale-error temperature coefficient See Note 7 EG Gain error See Note 8 10 ppm/C 0.6 % full scale V EG TC Gain error temperature coefficient See Note 9 10 ppm/C NOTES: 4. The relative accuracy or integral nonlinearity (INL) sometimes referred to as linearity error, is the maximum deviation of the output from the line between zero and full scale excluding the effects of zero code and full-scale errors. Tested from code 10 to code 255. 5. The differential nonlinearity (DNL) sometimes referred to as differential error, is the difference between the measured and ideal 1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code. Tested from code 10 to code 255. 6. Zero-scale error is the deviation from zero voltage output when the digital input code is zero. 7. Zero-scale-error temperature coefficient is given by: EZS TC = [EZS (Tmax) - EZS (Tmin)]/Vref x 106/(Tmax - Tmin). 8. Gain error is the deviation from the ideal output (2Vref - 1 LSB) with an output load of 10 k excluding the effects of the zero-error. 9. Gain temperature coefficient is given by: EG TC = [EG(Tmax) - EG (Tmin)]/Vref x 106/(Tmax - Tmin). output specifications PARAMETER VO Output voltage Output load regulation accuracy TEST CONDITIONS RL = 10 k VO = 4.096 V, 2.048 V MIN TYP 0 RL = 2 k MAX VDD-0.4 UNIT V % full 0.25 scale V 0.10 reference pin configured as output (REF) PARAMETER Vref(OUTL) Vref(OUTH) Low reference voltage Iref(source) Iref(sink) Output source current High reference voltage TEST CONDITIONS VDD > 4.75 V 4 TYP MAX UNIT 1.003 1.024 1.045 V 2.027 2.048 2.069 V 1 Output sink current -1 Load capacitance PSRR MIN 1 Power supply rejection ratio WWW.TI.COM mA mA 10 F -65 dB SLAS235B - JULY 1999 - REVISED APRIL 2004 electrical characteristics over recommended operating conditions (unless otherwise noted) (Continued) reference pin configured as input (REF) PARAMETER VI RI Input voltage CI Input capacitance TEST CONDITIONS MIN TYP 0 MAX VDD-1.5 Input resistance 10 Reference input bandwidth REF = 0.2 Vpp + 1.024 V dc Reference feedthrough REF = 1 Vpp at 1 kHz + 1.024 V dc (see Note 10) Slow V M 5 Fast UNIT pF 1.3 MHz 525 kHz -80 dB NOTE 10: Reference feedthrough is measured at the DAC output with an input code = 0x000. digital inputs PARAMETER IIH IIL High-level digital input current Ci Input capacitance Low-level digital input current TEST CONDITIONS VI = VDD VI = 0 V MIN TYP MAX 1 UNIT A A -1 8 pF analog output dynamic performance PARAMETER TEST CONDITIONS TYP MAX Fast MIN 1 3 Slow 3.5 7 Fast 0.5 1.5 Slow 1 2 Fast 8 Slow 1.5 ts(FS) Output settling time, full scale RL = 10 k, See Note 11 CL = 100 pF, ts(CC) Output settling time, code to code RL = 10 k, See Note 12 CL = 100 pF, SR Slew rate RL = 10 k, See Note 13 CL = 100 pF, Glitch energy DIN = 0 to 1, CS = VDD fCLK = 100 kHz, SNR Signal-to-noise ratio S/(N+D) Signal-to-noise + distortion THD Total harmonic distortion fs = 480 kSPS, fout = 1 kHz, RL = 10 kk,, CL = 100 pF Spurious free dynamic range 48 ss nV-S 57 47 -50 50 ss V/ s V/s 5 53 UNIT -48 dB 62 NOTES: 11. Settling time is the time for the output signal to remain within 0.5 LSB of the final measured value for a digital input code change of 0x020 to 0xFDFand 0xFDF to 0x020 respectively. Not tested, assured by design. 12. Settling time is the time for the output signal to remain within 0.5 LSB of the final measured value for a digital input code change of one count. Not tested, assured by design. 13. Slew rate determines the time it takes for a change of the DAC output from 10% to 90% full-scale voltage. WWW.TI.COM 5 SLAS235B - JULY 1999 - REVISED APRIL 2004 digital input timing requirements MIN tsu(CS-FS) tsu(FS-CK) MAX UNIT 10 ns 8 ns 10 ns Setup time, 16th positive SCLK edge (first positive after D0 is sampled) before CS rising edge. If FS is used instead of 16th positive edge to update DAC, then setup time between FS rising edge and CS rising edge. 10 ns twH twL SCLK pulse duration high 25 ns SCLK pulse duration low 25 ns tsu(D) tH(D) Setup time, data ready before SCLK falling edge 8 ns Hold time, data held valid after SCLK falling edge 5 ns twH(FS) FS pulse duration high 25 ns 16 X tsu(C16-FS) tsu(C16-CS) Setup time, CS low before FS falling edge NOM Setup time, FS low before first negative SCLK edge Setup time, 16th negative SCLK edge after FS low on which bit D0 is sampled before rising edge of FS PARAMETER MEASUREMENT INFORMATION twL SCLK X 1 2 tsu(D) X DIN twH 3 4 5 15 th(D) D15 D14 D13 D12 D1 D0 X tsu(C16-CS) tsu(CS-FS) CS twH(FS) tsu(FS-CK) tsu(C16-FS) FS Figure 1. Timing Diagram 6 WWW.TI.COM SLAS235B - JULY 1999 - REVISED APRIL 2004 TYPICAL CHARACTERISTICS OUTPUT VOLTAGE vs LOAD CURRENT OUTPUT VOLTAGE vs LOAD CURRENT 2.071 4.135 VDD = 3 V, REF = Int. 1 V, Input Code = 255 VDD = 5 V, REF = Int. 2 V, Input Code = 255 2.0705 4.134 2.0695 Output Voltage - V Output Voltage - V 2.07 Fast 2.0698 Slow 2.0685 2.068 2.0675 2.067 Fast 4.133 Slow 4.132 4.131 4.13 2.0665 2.066 0 0.5 1 1.5 2 2.5 3 3.5 4.129 4 0 0.5 1 Source Current - mA Figure 2 2 2.5 3 3.5 4 Figure 3 OUTPUT VOLTAGE vs LOAD CURRENT OUTPUT VOLTAGE vs LOAD CURRENT 3 5 VDD = 3 V, REF = Int. 1 V, Input Code = 0 VDD = 5 V, REF = Int. 2 V, Input Code = 0 4.5 2.5 4 2 Output Voltage - V Output Voltage - V 1.5 Source Current - mA Fast 1.5 1 3.5 3 Fast 2.5 2 1.5 1 0.5 0.5 Slow 0 Slow 0 0 0.5 1 1.5 2 2.5 3 3.5 4 Sink Current - mA 0 0.5 1 1.5 2 2.5 3 3.5 4 Sink Current - mA Figure 4 Figure 5 WWW.TI.COM 7 SLAS235B - JULY 1999 - REVISED APRIL 2004 TYPICAL CHARACTERISTICS SUPPLY CURRENT vs TEMPERATURE SUPPLY CURRENT vs TEMPERATURE 3 3 VDD = 5 V, REF = 2 V, Input Code = 255 VDD = 3 V, REF = 1 V, Input Code = 255 2.5 2.5 Supply Current - mA Supply Current - mA Fast Mode 2 Slow Mode 1.5 1 Fast Mode 2 1.5 Slow Mode 1 0.5 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 t - Temperature - C 0.5 -40-30-20 -10 0 10 20 30 40 50 60 70 80 90 t - Temperature - C Figure 6 Figure 7 POWER DOWN SUPPLY CURRENT vs TIME I DD - Power Down Supply Current - mA 2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 0 10 20 30 40 50 60 70 80 THD+N - Total Harmonic Distortion and Noise - dB TOTAL HARMONIC DISTORTION AND NOISE vs FREQUENCY t - Time - s -10 VDD = 5 V Vref = 1 V dc + 1 V p/p Sinewave Output Full Scale -20 -30 -40 -50 -60 Slow Mode -70 Fast Mode -80 -90 -100 100 1000 10000 f - Frequency - Hz Figure 8 8 0 Figure 9 WWW.TI.COM 100000 SLAS235B - JULY 1999 - REVISED APRIL 2004 TYPICAL CHARACTERISTICS TOTAL HARMONIC DISTORTION vs FREQUENCY THD - Total Harmonic Distortion - dB 0 VDD = 5 V Vref = 1 V dc + 1 V p/p Sinewave Output Full Scale -10 -20 -30 -40 -50 -60 -70 Slow Mode -80 Fast Mode -90 -100 100 10000 1000 100000 f - Frequency - Hz Figure 10 DNL - Differential Nonlinearity - LSB DIFFERENTIAL NONLINEARITY vs DIGITAL OUTPUT CODE 0.20 0.15 0.10 0.05 -0.00 -0.05 -0.10 -0.15 -0.20 0 32 64 96 128 160 192 224 256 Digital Output Code Figure 11 WWW.TI.COM 9 SLAS235B - JULY 1999 - REVISED APRIL 2004 TYPICAL CHARACTERISTICS INL - Integral Nonlinearity - LSB INTEGRAL NONLINEARITY vs DIGITAL OUTPUT CODE 0.50 0.25 0.00 -0.25 -0.50 0 32 64 96 128 160 192 224 256 Digital Output Code Figure 12 APPLICATION INFORMATION general function The TLV5624 is an 8-bit, single supply DAC, based on a resistor string architecture. It consists of a serial interface, a speed and power-down control logic, a programmable internal reference, a resistor string, and a rail-to-rail output buffer. The output voltage (full scale determined by reference) is given by: [V] 2 REF CODE 2n where REF is the reference voltage and CODE is the digital input value within the range 010 to 2n-1, where n = 8 (bits). The 16-bit word, consisting of control bits and a new DAC value, is illustrated in the data format section. A power on reset initially resets the internal latches to a defined state (all bits zero). serial interface The device has to be enabled with CS set to low. A falling edge of FS starts shifting the data bit-per-bit (starting with the MSB) to the internal register on high-low transitions of SCLK. After 16 bits have been transferred or FS rises, the content of the shift register is moved to the DAC latch, which updates the voltage output to the new level. The serial interface of the TLV5624 can be used in two basic modes: D Four wire (with chip select) D Three wire (without chip select) Using chip select (four-wire mode), it is possible to have more than one device connected to the serial port of the data source (DSP or microcontroller). Figure 13 shows an example with two TLV5624s connected directly to a TMS320 DSP. 10 WWW.TI.COM SLAS235B - JULY 1999 - REVISED APRIL 2004 APPLICATION INFORMATION serial interface (continued) TLV5624 TLV5624 CS TMS320 DSP FS DIN SCLK CS FS DIN SCLK XF0 XF1 FSX DX CLKX Figure 13. TMS320 Interface If there is no need to have more than one device on the serial bus, then CS can be tied low. Figure 14 shows an example of how to connect the TLV5624 to TMS320, SPI or Microwire using only three pins. TMS320 DSP FSX DX CLKX TLV5624 FS DIN SCLK SPI TLV5624 FS DIN SCLK I/O MOSI SCK CS CS Microwire I/O SO SK TLV5624 FS DIN SCLK CS Figure 14. Three-Wire Interface Notes on SPI and Microwire: Before the controller starts the data transfer, the software has to generate a falling edge on the I/O pin connected to FS. If the word width is 8 bits (SPI and Microwire), two write operations must be performed to program the TLV5624. After the write operation(s), the DAC output is updated automatically on the next positive clock edge following the 16th falling clock edge. serial clock frequency and update rate The maximum serial clock frequency is given by: f sclkmax + 1 + 20 MHz t whmin ) t wlmin The maximum update rate is: f updatemax + 1 + 1.25 MHz 16 t whmin ) t wlmin Note that the maximum update rate is just a theoretical value for the serial interface, as the settling time of the TLV5624 has to be considered, too. WWW.TI.COM 11 SLAS235B - JULY 1999 - REVISED APRIL 2004 APPLICATION INFORMATION data format The 16-bit data word for the TLV5624 consists of two parts: D Program bits D New data (D15..D12) (D11..D0) D15 D14 D13 D12 R1 SPD PWR R0 D11 D10 D9 D8 D7 D6 D5 D4 8 Data bits SPD: Speed control bit PWR: Power control bit 1 fast mode 1 power down D3 D2 D1 D0 0 0 0 0 0 slow mode 0 normal operation The following table lists the possible combination of the register select bits: register select bits R1 R0 REGISTER 0 0 Write data to DAC 0 1 Reserved 1 0 Reserved 1 1 Write data to control register The meaning of the 12 data bits depends on the selected register. For the DAC register, bits D11...D4 determine the new DAC output value: data bits: DAC D11 D10 D9 D8 D7 D6 D5 D4 New DAC Value D3 D2 D1 D0 0 0 0 0 If the control register is selected, then D1, D0 of the 12 data bits are used to program the reference voltage: data bits: CONTROL D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X X X X X REF1 REF2 X: don't care REF1 and REF0 determine the reference source and, if internal reference is selected, the reference voltage. reference bits REF1 REF0 REFERENCE 0 0 External 0 1 1.024 V 1 0 2.048 V 1 1 External NOTE: A 0.1F bypass capacitor must be installed on the reference pin (pin 6). If internal reference is used a 10 F capacitor must also be installed for reference voltage stability. CAUTION: If external reference voltage is applied to the REF pin, external reference MUST be selected. 12 WWW.TI.COM SLAS235B - JULY 1999 - REVISED APRIL 2004 APPLICATION INFORMATION Example: D Set DAC output, select fast mode, select internal reference at 2.048 V: 1. Set reference voltage to 2.048 V (CONTROL register): D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 1 0 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 2. Write new DAC value and update DAC output: D15 D14 D13 D12 0 1 0 0 D11 D10 D9 D8 D7 New DAC output value The DAC output is updated on the rising clock edge after D0 is sampled. To output data consecutively using the same DAC configuration, it is not necessary to program the CONTROL register again. linearity, offset, and gain error using single ended supplies When an amplifier is operated from a single supply, the voltage offset can still be either positive or negative. With a positive offset, the output voltage changes on the first code change. With a negative offset, the output voltage may not change with the first code, depending on the magnitude of the offset voltage. The output amplifier attempts to drive the output to a negative voltage. However, because the most negative supply rail is ground, the output cannot drive below ground and clamps the output at 0 V. The output voltage then remains at zero until the input code value produces a sufficient positive output voltage to overcome the negative offset voltage, resulting in the transfer function shown in Figure 15. Output Voltage 0V Negative Offset DAC Code Figure 15. Effect of Negative Offset (Single Supply) This offset error, not the linearity error, produces this breakpoint. The transfer function would have followed the dotted line if the output buffer could drive below the ground rail. For a DAC, linearity is measured between zero-input code (all inputs 0) and full-scale code after offset and full scale are adjusted out or accounted for in some way. However, single supply operation does not allow for adjustment when the offset is negative due to the breakpoint in the transfer function. So the linearity is measured between full-scale code and the lowest code that produces a positive output voltage. WWW.TI.COM 13 SLAS235B - JULY 1999 - REVISED APRIL 2004 APPLICATION INFORMATION power-supply bypassing and ground management Printed-circuit boards that use separate analog and digital ground planes offer the best system performance. Wire-wrap boards do not perform well and should not be used. The two ground planes should be connected together at the low-impedance power-supply source. The best ground connection may be achieved by connecting the DAC AGND terminal to the system analog ground plane, making sure that analog ground currents are well managed and there are negligible voltage drops across the ground plane. A 0.1-F ceramic-capacitor bypass should be connected between VDD and AGND and mounted with short leads as close as possible to the device. Use of ferrite beads may further isolate the system analog supply from the digital power supply. Figure 16 shows the ground plane layout and bypassing technique. Analog Ground Plane 1 8 2 7 3 6 4 5 0.1 F Figure 16. Power-Supply Bypassing definitions of specifications and terminology integral nonlinearity (INL) The relative accuracy or integral nonlinearity (INL), sometimes referred to as linearity error, is the maximum deviation of the output from the line between zero and full scale excluding the effects of zero code and full-scale errors. differential nonlinearity (DNL) The differential nonlinearity (DNL), sometimes referred to as differential error, is the difference between the measured and ideal 1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code. zero-scale error (EZS) Zero-scale error is defined as the deviation of the output from 0 V at a digital input value of 0. gain error (EG) Gain error is the error in slope of the DAC transfer function. total harmonic distortion (THD) THD is the ratio of the rms value of the first six harmonic components to the value of the fundamental signal. The value for THD is expressed in decibels. signal-to-noise ratio + distortion (S/N+D) S/N+D is the ratio of the rms value of the output signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for S/N+D is expressed in decibels. spurious free dynamic range (SFDR) Spurious free dynamic range is the difference between the rms value of the output signal and the rms value of the largest spurious signal within a specified bandwidth. The value for SFDR is expressed in decibels. 14 WWW.TI.COM PACKAGE OPTION ADDENDUM www.ti.com 16-Aug-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp TLV5624CD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV5624CDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV5624CDGK ACTIVE VSSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM TLV5624CDGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM TLV5624CDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM TLV5624CDGKRG4 ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM TLV5624ID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV5624IDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV5624IDGK ACTIVE VSSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM TLV5624IDGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM TLV5624IDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM TLV5624IDGKRG4 ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM TLV5624IDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV5624IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Addendum-Page 1 (3) Samples (Requires Login) PACKAGE OPTION ADDENDUM www.ti.com 16-Aug-2012 (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TLV5624CDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 TLV5624IDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 TLV5624IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV5624CDGKR VSSOP DGK 8 2500 367.0 367.0 35.0 TLV5624IDGKR VSSOP DGK 8 2500 367.0 367.0 35.0 TLV5624IDR SOIC D 8 2500 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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