MX29F004BQC-55G - Macronix International Co., Ltd.

MX29F004T/B

4M-BIT [512KX8] CMOS FLASH MEMORY

FEATURES

• 524,288 x 8 only

• Single power supply operation

- 5.0V only operation for read, erase and program op-

eration

• F ast access time: 70/90/120ns

• Low power consumption

- 30mA maximum active current (5MHz)

- 1uA typical standby current

• Command register architecture

- Byte Programming (7us typical)

- Sector Erase

(Sector structure:16KB/8KB/8KB/32KB and 64KBx7)

• Auto Erase (chip & sector) and Auto Program

- Automatically erase any combination of sectors with

Erase Suspend capability.

- Automatically program and verify data at specified

address

during erase and programming, while maintaining maxi-

mum EPROM compatibility.

MXIC Flash technology reliably stores memory

contents even after 100,000 erase and program

cycles. The MXIC cell is designed to optimize the

erase and programming mechanisms. In addition,

the combination of advanced tunnel oxide

processing and low internal electric fields for erase

and program operations produces reliable cycling.

The MX29F004T/B uses a 5.0V±10% VCC supply

to perform the High Reliability Erase and auto

Program/Erase algorithms.

The highest degree of latch-up protection is

achieved with MXIC's proprietary non-epi process.

Latch-up protection is proved for stresses up to 100

milliamps on address and data pin from -1V to VCC

+ 1V.

GENERAL DESCRIPTION

The MX29F004T/B is a 4-mega bit Flash memory orga-

nized as 512K bytes of 8 bits. MXIC's Flash memories

offer the most cost-effective and reliable read/write non-

v olatile random access memo ry. The MX29F004T/B is

packaged in 32-pin PLCC, TSOP, PDIP. It is designed

to be reprogrammed and erased in system or in stan-

dard EPROM programmers.

The standard MX29F004T/B offers access time as fast

as 70ns, allowing operation of high-speed microproces-

sors without wait states. To eliminate bus contention,

the MX29F004T/B has separate chip enable (CE) and

output enable (OE) controls.

MXIC's Flash memories augment EPROM functionality

with in-circuit electrical erasure and pro gramming. The

MX29F004T/B uses a command register to manage this

functionality. The command register allows for 100%

TTL level control inputs and fixed power supply levels

• Erase suspend/Erase Resume

- Suspends an erase operation to read data from, or

program data to, another sector that is not being

erased, then resumes the erase.

• Status Reply

- Data polling & Toggle bit for detection of program

and erase cycle completion.

• Chip protect/unprotect for 5V only system or 5V/12V

system.

• 100,000 minimum erase/program cycles

• Latch-up pro tected to 100mA fro m -1V to VCC+1V

• Low VCC write inhibit is equal to o r less than 3.2V

• P ackage type:

- 32-pin PLCC, TSOP o r PDIP

• Compatibility with JEDEC standard

- Pinout and software compatible with single-power

supply Flash

• 20 years data retention

P/N:PM0554 REV. 1.9, OCT. 19, 2004

MX29F004T/B

P/N:PM0554 REV. 1.9, OCT. 19, 2004

PIN CONFIGURATIONS

32 PLCC

32 TSOP (Standard T ype) (8mm x 20mm)

SYMBOL PIN NAME

A0~A18 Address Input

Q0~Q7 Data Input/Output

CE Chip Enable Input

WE Write Enable Input

OE Output Enable Input

GND Ground Pin

VC C +5.0V single power supply

PIN DESCRIPTION

32 PDIP

MX29F004T/B

A18

A16

A15

A12

GND

VCC

A17

A14

A13

A11

A10

14 17 20

32 30 A14

A13

A11

A10

GND

A12

A15

A16

A18

VCC

A17

MX29F004T/B

A11

A13

A14

A17

VCC

A18

A16

A15

A12

A10

GND

MX29F004T/B

P/N:PM0554 REV. 1.9, OCT. 19, 2004

Sector Size Address Range (in hexadecimal)

Sector A18 A17 A16 A15 A14 A13 (Kbytes) (x8) Address Range

SA0000XXX 64 00000h-0FFFFh

SA1001XXX 64 10000h-1FFFFh

SA2010XXX 64 20000h-2FFFFh

SA3011XXX 64 30000h-3FFFFh

SA4100XXX 64 40000h-4FFFFh

SA5101XXX 64 50000h-5FFFFh

SA6110XXX 64 60000h-6FFFFh

SA71110 XX 32 70000h-77FFFh

SA81111 00 8 78000h-79FFFh

SA91111 01 8 7A000h-7BFFFh

SA10 1111 1X 16 7C000h-7FFFFh

SECTOR STRUCTURE

MX29F004T TOP BOOT SECTOR ADDRESS TABLE

Sector Size Address Range (in hexadecimal)

Sector A18 A17 A16 A15 A14 A13 (Kbytes) (x8) Address Range

SA00000 0X 16 00000h-03FFFh

SA10000 10 8 04000h-05FFFh

SA20000 11 8 06000h-07FFFh

SA30001 XX 32 08000h-0FFFFh

SA4001XXX 64 10000h-1FFFFh

SA5010XXX 64 20000h-2FFFFh

SA6011XXX 64 30000h-3FFFFh

SA7100XXX 64 40000h-4FFFFh

SA8101XXX 64 50000h-5FFFFh

SA9110XXX 64 60000h-6FFFFh

SA10 111XXX 64 70000h-7FFFFh

MX29F004B BOTT OM BOOT SECTOR ADDRESS T ABLE

MX29F004T/B

P/N:PM0554 REV. 1.9, OCT. 19, 2004

BLOCK DIAGRAM

CONTROL

INPUT

LOGIC

PROGRAM/ERASE

HIGH V OLTAGE

WRITE

STATE

MACHINE

(WSM)

STATE

MX29F004T/B

FLASH

ARRAY

X-DECODER

ADDRESS

LATCH

AND

BUFFER Y-PASS GATE

Y-DECODER

ARRAY

SOURCE

HV COMMAND

DATA

DECODER

COMMAND

DATA LATCH

I/O BUFFER

PGM

DATA

PROGRAM

DATA LATCH

SENSE

AMPLIFIER

Q0-Q7

A0-A18

MX29F004T/B

P/N:PM0554 REV. 1.9, OCT. 19, 2004

AUTOMATIC PROGRAMMING

The MX29F004T/B is byte programmable using the Au-

tomatic Programming algorithm. The Automatic Pro-

gramming algorithm makes the external system do not

need to have time out sequence nor to verify the data

programmed. The typical chip pro gramming time at room

temperature of the MX29F004T/B is less than 4 sec-

onds.

AUTOMATIC CHIP ERASE

The entire chip is bulk erased using 10 ms erase pulses

according to MXIC's Automatic Chip Erase algorithm.

Typical erasure at ro om temperature is acco mplished in

less than 4 second. The Automatic Erase algorithm

automatically programs the entire array prior to electri-

cal erase. The timing and verificatio n of electrical erase

are controlled internally within the device.

AUTOMATIC SECTOR ERASE

The MX29F004T/B is sector(s) erasable using MXIC's

Auto Sector Erase algorithm. Sector erase modes allow

sectors of the array to be erased in one erase cycle.

The Automatic Sector Erase algorithm automatically

programs the specified sector(s) prior to electrical erase.

The timing and verification of electrical erase are con-

trolled internally within the device.

AUTOMATIC PROGRAMMING ALGORITHM

MXIC's Automatic Programming algorithm requires the

user to only write program set-up commands (including

2 unlock write cycle and A0H) and a program command

(pro g ram data and address). The de vice automatically

times the programming pulse width, provides the pro-

gram verification, and counts the number of sequences.

A status bit similar to D ATA polling and a status bit to g-

gling between consecutive read cycles, provide feed-

back to the user as to the status of the programming

operation.

AUTOMATIC ERASE ALGORITHM

MXIC's Automatic Erase algorithm requires the user to

write commands to the command register using stan-

dard micro processo r write timings. The device will auto-

matically pre-program and verification the entire array.

Then the device automatically times the erase pulse

width, pro vides the er ase verify, and co unts the number

of sequences. A status bit toggling between consecu-

tive read cycles provides feedback to the user as to the

status of the programming operation.

machine which controls the erase and programming cir-

cuitry. During write cycles, the co mmand register inter-

nally latches address and data needed for the program-

ming and erase operations. During a system write cycle,

addresses are latched o n the falling edge o f WE or CE,

whichever happens later, and data are latched on the

rising edge o f WE o r CE, whiche v er happens first.

MXIC's Flash technology combines years of EPROM

e xperience to produce the highest lev els of quality, reli-

ability, and cost eff ectiveness . The MX29F004T/B elec-

trically erases all bits simultaneously using Fowler- tun-

neling. The bytes are pro grammed by using the EPROM

programming mechanism of hot electron injection.

During a program cycle, the state-machine will control

the program sequences and command register will not

respond to any command set. During a Sector Erase

cycle, the command register will only respond to Erase

Suspend command. After Erase Suspend is completed,

the device stays in read mode. After the state machine

has completed its task, it will allow the command regis-

ter to respond to its full command set.

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P/N:PM0554 REV. 1.9, OCT. 19, 2004

First Bus Second Bus Third Bus Fourth Bus Fifth Bus Sixth Bus

Command Bus Cycle Cycle Cycle Cycle Cycle Cycle

Cycle Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Reset 1 XXXH F0H

Read 1 RA RD

Read Silicon ID 4 555H AAH 2AAH 55H 555H 90H ADI DDI

Chip Protect Verify 4 555H AAH 2AAH 55H 555H 90H SA 00H

x02 01H

Program 4 555H AAH 2AAH 55H 555H A0H PA PD

Chip Erase 6 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H 555H 10H

Sector Erase 6 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H SA 30H

Sector Erase Suspend 1 XXXH B0H

Sector Erase Resume 1 XXXH 30H

Unlock for chip 6 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H 555H 20H

protect/unprotect

TABLE1. SOFTWARE COMMAND DEFINITIONS

Note:

1. ADI = Address of Device identifier; A1=0, A0 = 0 for manufacture code,A1=0, A0 =1 for device code A2~A18=Do not care.

(Refer to table 3)

DDI = Data of Device identifier : C2H for manufacture code, 45H/46H for device code.

X = X can be VIL o r VIH

RA=Address of memory location to be read.

RD=Data to be read at location RA.

2. PA = Address of memor y location to be programmed.

PD = Data to be programmed at location PA.

SA = Address to the sector to be erased.

3. The system should generate the following address patterns: 555H or 2AAH to Address A10~A0.

Address bit A11~A18=X=Don't care for all address commands except for Program Address (PA) and Sector Address (SA).

Write Sequence may be initiated with A11~A18 in either state.

4. For Chip Protect Ver ify Operation :If read out data is 01H, it means the chip has been protected. If read out data is 00H, it

means the chip is still not being protected.

COMMAND DEFINITIONS

Device operations are selected by writing specific ad-

dress and data sequences into the command register.

Writing incorrect address and data values or writing them

in the improper sequence will reset the device to the

read mo de . Table 1 defines the v alid register co mmand

sequences. Note that the Erase Suspend (B0H) and

Erase Resume (30H) commands are valid only while the

Sector Erase operation is in progress. Either of the two

reset command sequences will reset the device (when

applicable).

MX29F004T/B

P/N:PM0554 REV. 1.9, OCT. 19, 2004

Mode Pins

CE OE WE A0 A1 A6 A9 Q0 ~ Q7

Read Silicon ID L L H L L X VID(2) C2H

Manufacturer Code (1)

Read Silicon ID L L H H L X VID(2) 45H/46H

Device Code (1)

Read L L H A0 A1 A6 A9 DOUT

Standby H X X X X X X HIGH Z

Output Disable L H H X X X X HIGH Z

Write L H L A0 A1 A6 A9 DIN(3)

Chip Protect with 12V L V ID(2) L X X L VID(2) X

system (6)

Chip Unprotect with 12V L VID(2) L X X H VID(2) X

system (6)

Verify Chip Protect L L H X H X VID(2) Code (5)

with 12V system

Chip Protect without 12V L H L X X L H X

system (6)

Chip Unprotect without 12V L H L X X H H X

system (6)

Verify Chip Protect/Unprotect L L H X H X H Code (5)

without 12V system (7)

Reset X X X X X X X HIGH Z

TABLE 2. MX29F004T/B BUS OPERATION

NOTES:

1. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table

2. VID is the Silicon-ID-Read high voltage, 11.5V to 12.5V.

3. Refer to Table 1 for valid Data-In during a write operation.

4. X can be VIL or VIH.

5. Code=00H means unprotected.

Code=01H means protected.

6. Refer to chip protect/unprotect algorithm and waveform.

Must issue "unlock for chip protect/unprotect" command before "chip protect/unprotect without 12V system"

command.

7. The "verify chip protect/unprotect without 12V system" is only following "Chip protect/unprotect without 12V

system" command.

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P/N:PM0554 REV. 1.9, OCT. 19, 2004

READ/RESET COMMAND

The read or reset operation is initiated by writing the read/

reset command sequence into the command register.

Micro processo r read cycles retrieve arra y data. The de-

vice remains enabled for reads until the command regis-

ter contents are altered.

If program-fail or erase-fail happen, the write of F0H will

reset the device to abort the operation. A valid com-

mand must then be written to place the device in the

desired state.

SILICON-ID-READ COMMAND

Flash memories are intended for use in applications where

the local CPU alters memory contents. As such, manu-

facturer and device codes must be accessible while the

device resides in the target system. PROM program-

mers typically access signature codes by raising A9 to

a high v o ltage. How ev er , multiple xing high voltage o nto

address lines is not generally desired system design prac-

tice.

The MX29F004T/B contains a Silicon-ID-Read operation

to supplement traditional PROM programming method-

ology. The operation is initiated by writing the read sili-

co n ID co mmand sequence into the co mmand register .

Following the command write, a read cycle with

A1=VIL,A0=VIL retrieves the manufacturer code of C2H.

A read cycle with A1=VIL, A0=VIH returns the device

code of 45H/46H for MX29F004T/B.

SET-UP AUTOMATIC CHIP/SECTOR ERASE

Chip erase is a six-bus cycle operation. There are two

"unlo c k" write cycles. These are f o llo wed by writing the

"set-up" command 80H. Two more "unlock" write cy-

cles are then followed by the chip erase command 10H.

The Automatic Chip Erase does not require the device

to be entirely pre-programmed prior to executing the Au-

tomatic Chip Erase. Upon executing the Automatic Chip

Erase, the device will automatically program and verify

the entire memory fo r an all-zero data pattern. When the

device is automatically verified to contain an all-zero

pattern, a self-timed chip erase and verify begin. The

erase and verify operations are completed when the data

on Q7 is "1" at which time the device returns to the

Read mode. The system is not required to provide any

control or timing during these operations.

When using the Automatic Chip Erase algorithm, note

that the erase automatically terminates when adequate

erase margin has been achieved for the memory array

(no erase verification command is required).

If the Erase operation was unsuccessful, the data on

Q5 is "1" (see Table 4), indicating the erase operation

exceed internal timing limit.

The automatic erase begins on the rising edge of the

last WE or CE, whichever happens first pulse in the

command sequence and terminates when the data on

Q7 is "1" and the data on Q6 stops toggling for two con-

secutive read cycles, at which time the device returns

to the Read mode.

Pins A0 A1 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Code (Hex)

Manufacture code VIL VIL 1 1 0 0 0 0 1 0 C2H

Device code for MX29F004T VIH VIL 0 1 0 0 0 1 0 1 45H

Device code for MX29F004B VIH VIL 0 1 0 0 0 1 1 0 46H

Chip Protection Verification X VIH 0 0 0 0 0 0 0 1 01H(Protected)

X VIH 0 0 0 0 0 0 0 0 00H(Unprotected)

TABLE 3. EXPANDED SILICON ID CODE

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P/N:PM0554 REV. 1.9, OCT. 19, 2004

SECTOR ERASE COMMANDS

The Automatic Sector Erase does not require the de-

vice to be entirely pre-programmed prior to executing

the Automatic Set-up Sector Erase command and Auto-

matic Sector Erase command. Upon executing the Au-

tomatic Sector Erase command, the device will auto-

matically program and verify the sector(s) memory for

an all-zero data pattern. The system is no t required to

provide any control or timing during these operations.

When the sector(s) is automatically verified to contain

an all-zero pattern, a self-timed sector erase and verify

begin. The erase and verify operations are complete

when the data on Q7 is "1" and the data on Q6 stops

toggling for two consecutive read cycles, at which time

the device returns to the Read mode. The system is no t

required to provide any control or timing during these

operations.

When using the Automatic Sector Erase algorithm, note

that the erase automatically terminates when adequate

erase margin has been achieved for the memory array

(no erase verification command is required). Sector erase

is a six-bus cycle operation. There are two "unlock"

write cycles. These are followed by writing the set-up

co mmand 80H. Two mo re "unlock" write cycles are then

fo llowed by the secto r erase co mmand 30H. The sector

address is latched on the falling edge of WE or CE,

whichever happens later, while the command (data) is

latched o n the rising edge of WE or CE, whichever hap-

pens first. Sector addresses selected are loaded into

internal register on the sixth falling edge of WE or CE,

whichever happens later. Each successive sector load

cycle star ted by the falling edge of WE or CE, which-

ever happens later must begin within 30us fro m the ris-

ing edge of the preceding WE or CE, whichever hap-

pens first. Otherwise, the lo ading perio d ends and inter-

nal auto secto r erase cycle starts. (Mo nito r Q3 to deter-

mine if the sector erase timer window is still open, see

section Q3, Sector Erase Timer.) Any command other

than Secto r Erase(30H) o r Erase Suspend(B0H) during

the time-o ut perio d resets the device to read mo de.

Status Q7 Q6 Q5 Q3 Q2

Note1 Note2

Byte Program in Auto Program Algorithm Q7 Toggle 0 N/A No Toggle

Auto Erase Algorithm 0 Toggle 0 1 Toggle

Erase Suspend Read 1 No 0 N/A Toggle

In Progress (Erase Suspended Sector) Toggle

Erase Suspended Mode Erase Suspend Read Data Data Data Data Data

(Non-Erase Suspended Sector)

Erase Suspend Program Q7 Toggle 0 N/A N/A

Byte Program in Auto Program Algorithm Q7 Toggle 1 N/A No Toggle

Exceeded Auto Erase Algorithm 0 Toggle 1 1 Toggle

Time Limits Erase Suspend Program Q7 Toggle 1 N/A N/A

TABLE 4. WRITE OPERATION STATUS

Note:

1. Q7 and Q2 require a valid address when reading status information. Refer to the appropriate subsection for further

details.

2. Q5 switches to '1' when an Auto Program or Auto Erase operation has exceeded the maximum timing limits.

See "Q5:Exceeded Timing Limits " for more information.

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P/N:PM0554 REV. 1.9, OCT. 19, 2004

ERASE SUSPEND

This command only has meaning while the state ma-

chine is executing Automatic Sector Erase operation,

and therefore will only be responded during Automatic

Secto r Erase o peratio n. When the Erase Suspend co m-

mand is written during a sector erase operation, the de-

vice requires a maximum of 100us to suspend the erase

operations. However, when the Erase Suspend co mmand

is written during the sector erase time-out, the device

immediately terminates the time-out period and suspends

the erase operation. After this command has been ex-

ecuted, the command register will initiate erase suspend

mo de. The state machine will return to read mode auto-

matically after suspend is ready. At this time, state ma-

chine only allows the command register to respond to

the Read Memor y Array, Erase Resume and program

commands.

The system can determine the status of the program

operation using the Q7 or Q6 status bits, just as in the

standard program operation. After an erase-suspend pro-

gram operation is complete, the system can once again

read array data within non-suspended sectors.

ERASE RESUME

This command will cause the command register to clear

the suspend state and return back to Sector Erase mode

but only if an Erase Suspend command was previously

issued. Erase Resume will not have any effect in all

other conditions. Another Erase Suspend command can

be written after the chip has resumed erasing.

SET-UP AUTOMATIC PROGRAM COMMANDS

To initiate Auto matic Program mode, A three-cycle co m-

mand sequence is required. There are two "unlo ck" write

cycles. These are fo llowed by writing the Auto matic Pro-

gram command A0H.

Once the Automatic Program command is initiated, the

next WE or CE pulse causes a transition to an active

programming operation. Addresses are latched on the

falling edge, and data are internally latched on the

rising edge of the WE or CE, whichever happens first

pulse. The rising edge of WE or CE, whichever hap-

pens first also begins the programming operatio n. The

system is no t required to pro vide further contro ls o r tim-

ings. The device will auto matically pro vide an adequate

internally generated pro gram pulse and verify margin.

If the program operation was unsuccessful, the data on

Q5 is "1"(see Tab le 4), indicating the pro gram operatio n

exceed internal timing limit. The auto matic pro gramming

operation is completed when the data read on Q6 stops

toggling for two consecutive read cycles and the data on

Q7 and Q6 are equivalent to data written to these two

bits, at which time the device returns to the Read mode

(no program verify command is required).

DATA POLLING-Q7

The MX29F004T/B also features Data Polling as a

method to indicate to the host system that the Auto-

matic Program or Erase algorithms are either in progress

or completed.

While the Automatic Programming algorithm is in opera-

tion, an attempt to read the device will produce the comple-

ment data of the data last written to Q7. Upon comple-

tion of the Automatic Program Algorithm an attempt to

read the device will produce the true data last written to

Q7. The Data P olling feature is valid after the rising edge

o f the fo urth WE o r CE, whichever happens first pulse of

the fo ur write pulse sequences fo r automatic program.

While the Automatic Erase algorithm is in operation, Q7

will read "0" until the erase operation is competed. Upon

completion of the erase operation, the data on Q7 will

read "1". The Data P o lling feature is valid after the rising

edge of the sixth WE or CE, whichever happens first

pulse of six write pulse sequences for automatic chip/

sector erase.

The Data P o lling f eature is active during Auto matic Pro-

gram/Erase algorithm or sector erase time-out. (see sec-

tion Q3 Secto r Erase Timer)

MX29F004T/B

P/N:PM0554 REV. 1.9, OCT. 19, 2004

Q2 toggles when the system reads at addresses within

those sectors that have been selected for erasure. (The

system may use either OE or CE to control the read

cycles.) But Q2 cannot distinguish whether the sector

is actively erasing or is erase-suspended. Q6, by com-

parison, indicates whether the device is actively eras-

ing, or is in Erase Suspend, but cannot distinguish which

sectors are selected for erasure. Thus , both status bits

are required for sectors and mode information. Refer to

Table 4 to compare outputs for Q2 and Q6.

Reading To ggle Bits Q6/ Q2

Whenever the system initially begins reading toggle bit

status, it must read Q7-Q0 at least twice in a row to

determine whether a toggle bit is to ggling. T ypically, the

system would note and store the value of the toggle bit

after the first read. After the second read, the system

would compare the new value of the toggle bit with the

first. If the toggle bit is not toggling, the device has

co mpleted the pro gram o r erase o peratio n. The system

can read array data on Q7-Q0 on the following read cycle.

How ever, if after the initial two read cycles, the system

determines that the toggle bit is still toggling, the sys-

tem also should note whether the value of Q5 is high

(see the section on Q5). If it is, the system should then

determine again whether the toggle bit is toggling, since

the toggle bit may have stopped toggling just as Q5 went

high. If the toggle bit is no longer toggling, the device

has successfully completed the program or erase op-

eration. If it is still toggling, the device did not complete

the operation successfully, and the system must wr ite

the reset command to return to reading array data.

The remaining scenario is that system initially determines

that the toggle bit is toggling and Q5 has not gone high.

The system may continue to monitor the toggle bit and

Q5 through successive read cycles, determining the sta-

tus as described in the previous paragraph. Alterna-

tively, it may choose to perfor m other system tasks. In

this case, the system m ust start at the beginning o f the

algorithm when it returns to determine the status of the

operation.

Q6:Toggle BIT I

To ggle Bit I on Q6 indicates whether an Automatic Pro-

gram or Erase algorithm is in progress or complete, or

whether the device has entered the Erase Suspend mode.

Toggle Bit I may be read at any address, and is valid

after the rising edge of the final WE or CE, whichever

happens first pulse in the command sequence (prior to

the program or erase operation), and during the sector

time-out.

During an Automatic Program or Erase algorithm opera-

tion, successive read cycles to any address cause Q6

to toggle. The system may use either OE o r CE to con-

tro l the read cycles. When the o peratio n is co mplete, Q6

stops toggling.

After an erase command sequence is written, if the chip

has been protected, Q6 toggles and returns to reading

array data.

The system can use Q6 and Q2 together to determine

whether a sector is actively erasing or is erase sus-

pended. When the device is actively erasing (that is, the

Automatic Erase algorithm is in progress), Q6 toggling.

When the device enters the Erase Suspend mode, Q6

stops toggling. However, the system must also use Q2

to determine which sectors are erasing or erase-sus-

pended. Alternatively, the system can use Q7.

If a program address falls within a protected secto r, Q6

toggles for approximately 2us after the program com-

mand sequence is written, then returns to reading array

data.

Q6 also toggles during the erase-suspend-program mode,

and stops toggling once the Automatic Program algo-

rithm is complete.

Table 4 sho ws the outputs for Toggle Bit I on Q6.

Q2:Toggle Bit II

The "To ggle Bit II" o n Q2, when used with Q6, indicates

whether a par ticular sector is actively erasing (that is,

the Automatic Erase algorithm is in process), or whether

that sector is erase-suspended. Toggle Bit I is valid af-

ter the rising edge of the final WE or CE, whichever

happens first pulse in the command sequence.

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P/N:PM0554 REV. 1.9, OCT. 19, 2004

Exceeded Timing Limits

Q5 will indicate if the program or erase time has ex-

ceeded the specified limits (internal pulse count). Under

these conditions Q5 will produce a "1". This time-out

condition indicates that the program or erase cycle was

no t successfully completed. Data P olling and To ggle Bit

are the only operating functions of the device under this

condition.

If this time-out condition occurs during sector erase op-

eration, it specifies that a particular secto r is bad and it

may no t be reused. However , other secto rs are still func-

tional and may be used for the program or erase opera-

tion. The device must be reset to use other sectors.

Write the Reset command sequence to the device, and

then execute pro gram or erase command sequence. This

allows the system to continue to use the other active

sectors in the device.

If this time-out condition occurs during the chip erase

operation, it specifies that the entire chip is bad or com-

bination of sectors are bad.

If this time-out condition occurs during the byte program-

ming operation, it specifies that the entire sector con-

taining that byte is bad and this sector may not be re-

used, (other sectors are still functional and can be re-

used).

The time-out condition may also appear if a user tries to

program a non blank location without erasing. In this

case the device locks out and never completes the Au-

tomatic Algorithm operation. Hence, the system never

reads a valid data on Q7 bit and Q6 never stops tog-

gling. Once the Device has exceeded timing limits, the

Q5 bit will indicate a "1". Please note that this is not a

device failure condition since the device was incorrectly

used.

DATA PROTECTION

The MX29F004T/B is designed to offer protection against

accidental erasure or programming caused by spurious

system level signals that may exist during power transi-

tion. During power up the device automatically resets

the state machine in the Read mode. In addition, with

its control register architecture, alteration of the memory

contents only occurs after successful completion of

specific co mmand sequences. The de vice also incorpo-

rates several features to prevent inadvertent write cycles

resulting fro m VCC power-up and power-down transitio n

or system noise.

Sector Erase Timer

After the completion of the initial sector erase command

sequence, the sector erase time-out will begin. Q3 will

remain low until the time-out is complete. Data Polling

and T o ggle Bit are valid after the initial secto r erase co m-

mand sequence.

If Data P o lling o r the Toggle Bit indicates the device has

been written with a valid erase command, Q3 may be

used to determine if the sector erase timer window is

still open. If Q3 is high ("1") the internally controlled

erase cycle has begun; attempts to write subsequent

commands to the device will be ignored until the erase

operation is completed as indicated by Data Polling or

To ggle Bit. If Q3 is low ("0"), the de vice will accept addi-

tional secto r erase co mmands . To insure the co mmand

has been accepted, the system software should check

the status of Q3 prior to and following each subsequent

sector erase command. If Q3 were high on the second

status check, the command may not have been accepted.

WRITE PULSE "GLITCH" PROTECTION

Noise pulses of less than 5ns(typical) on CE or WE will

not initiate a write cycle.

LOGICAL INHIBIT

Writing is inhibited by ho lding any o ne of OE = VIL, CE =

VIH o r WE = VIH. To initiate a write cycle CE and WE

must be a logical zero while OE is a logical one.

POWER SUPPLY DECOUPLING

In order to reduce power switching effect, each device

should have a 0.1uF ceramic capacitor connected be-

tween its VCC and GND .

MX29F004T/B

P/N:PM0554 REV. 1.9, OCT. 19, 2004

CHIP PROTECTION WITH 12V SYSTEM

The MX29F004T/B features chip protection, which will

disable both pro gram and erase o peratio ns . To activate

this mo d e, the programming equipment m ust force VID

on address pin A9 and contro l pin OE, (suggest VID=12V)

A6=VIL and CE=VIL.(see Table 2) Pro g ramming o f the

pro tectio n circuitry begins o n the falling edge o f the WE

o r CE, whichever happens later pulse and is terminated

on the rising edge. Please refer to chip protect algo-

rithm and waveform.

To verify programming o f the protectio n circuitry , the pro-

gramming equipment must f o rce VID o n address pin A9

( with CE and OE at VIL and WE at VIH). When A1=1, it

will produce a logical "1" code at device output Q0 for

the protected status. Otherwise the device will produce

00H for the unprotected status. In this mode, the ad-

dresses, except for A1, are don't care. Address loca-

tions with A1 = VIL are reserved to read manufacturer

and device codes. (Read Silicon ID)

It is also possible to determine if chip is protected in the

system by writing a Read Silicon ID command. Per-

forming a read operation with A1=VIH, it will produce a

logical "1" at Q0 for the protected status.

CHIP UNPROTECT WITH 12V SYSTEM

The MX29F004T/B also features the chip unprotect mode,

so that all sectors are unprotected after chip unprotect

is completed to incorporate any changes in the code.

To activate this mo de, the pro gramming equipment must

fo rce VID o n co ntrol pin OE and address pin A9. The CE

pins must be set at VIL. Pins A6 must be set to VIH.

(see Table 2) Refer to chip unprotect algorithm and

waveform for the chip unprotect algorithm. The

unprotection mechanism begins on the falling edge of

the WE or CE, whichever happens later pulse and is

terminated on the rising edge.

It is also possible to determine if the chip is unprotected

in the system by writing the Read Silicon ID command.

P erfo rming a read operation with A1=VIH, it will pro duce

00H at data o utputs(Q0-Q7) fo r an unprotected sector . It

is noted that all sectors are unprotected after the chip

unprotect algorithm is completed.

POWER-UP SEQUENCE

The MX29F004T/B powers up in the Read only mode. In

addition, the memory contents may only be altered after

successful completion of the predefined command se-

quences.

CHIP PROTECTION WITHOUT 12V SYSTEM

The MX29F004T/B also feature a chip protection method

in a system witho ut 12V power supply. The programming

equipment do not need to supply 12 volts to protect all

sectors. The details are shown in chip protect algorithm

and waveform.

CHIP UNPROTECT WITHOUT 12V SYSTEM

The MX29F004T/B also feature a chip unprotection

metho d in a system without 12V power supply. The pro-

gramming equipment do not need to supply 12 volts to

unprotect all sectors. The details are shown in chip

unprotect algorithm and waveform.

MX29F004T/B

P/N:PM0554 REV. 1.9, OCT. 19, 2004

29F004T/B-55 29F004T/B-70 29F004T/B-90 29F004T/B-12

Symbol PARAMETER MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. UNIT CONDITIONS

tACC Address to Output Delay 5 5 7 0 90 1 2 0 ns CE=OE=VIL

tCE CE to Output Delay 55 70 90 1 20 ns OE=VIL

tOE OE to Output Delay 40 40 40 50 ns CE=VIL

tDF OE High to Output Float 0 30 0 30 0 40 0 40 ns CE=VIL

(Note 1)

tOH Address to Output hold 0 0 0 0 ns CE=OE=VIL

NOTE:

1. tDF is defined as the time at which the output achieves the

open circuit condition and data is no longer driven.

TEST CONDITIONS:

•Input pulse levels: 0.45V/2.4V

•Input rise and fall times is equal to or less than 10ns

•Output load: 1 TTL gate + 100pF (Including scope and jig)

•Reference levels for measuring timing: 0.8V, 2.0V

NOTES:

1. VIL min. = -1.0V for pulse width is equal to or less than 50 ns.

VIL min. = -2.0V for pulse width is equal to or less than 20 ns. 2. VIH max. = VCC + 1.5V for pulse width is equal to or less

than 20 ns.

If VIH is over the specified maximum value, read operation

cannot be guaranteed.

READ OPERATION

DC CHARA CTERISTICS (T A = 0°C TO 70°C, VCC = 5V±±

±±

±10%)

SYMBOL PARAMETER MIN. TYP MAX. UNIT CONDITIONS

IL I Input Leakage Current 1 uA VIN = GND to VCC

ILO Output Leakage Current 10 uA VOUT = GND to VCC

ISB1 Standby VCC current 1 mA CE = VIH

ISB2 1 5 uA CE = VCC + 0.3V

ICC1 Operating VCC current 30 mA IOUT = 0mA, f=5MHz

ICC2 50 mA IOUT = 0mA, f=10MHz

VIL Input Low Voltage -0.3(NOTE 1) 0.8 V

VIH Input High Voltage 2.0 VCC + 0.3 V

VOL Output Low Voltage 0.45 V IOL = 2.1mA

VOH1 Output High Voltage(TTL) 2.4 V IOH = -2mA

VOH2 Output High Voltage(CMOS) Vcc-0.4 V IOH = -100uA,VCC=VCC min

CAPACITANCE (TA = 25oC, f = 1.0 MHz)

SYMBOL PARAMETER MIN. TYP MAX. UNIT CONDITIONS

CIN1 Input Capacitance 8 pF VIN = 0V

CIN2 Control Pin Capacitance 12 pF VIN = 0V

COUT Output Capacitance 12 pF VOUT = 0V

A C CHARACTERISTICS (TA = 0oC to 70oC, VCC = 5V±±

±±

±10%)

MX29F004T/B

P/N:PM0554 REV. 1.9, OCT. 19, 2004

ABSOLUTE MAXIMUM RATINGS

RATING VALUE

Ambient Operating Temperature 0oC to 70oC

Storage Temperature -65oC to 125oC

Applied Input Voltage -0.5V to 7.0V

Applied Output Voltage -0.5V to 7.0V

VCC to Ground Potential -0.5V to 7.0V

A9 & OE -0.5V to 13.5V

NOTICE:

Stresses greater than those listed under ABSOLUTE

MAXIMUM RATINGS may cause permanent damage to

the device. This is a stress rating only and functional

operational sections of this specification is not implied.

Exposure to absolute maximum rating conditions for

extended period may affect reliability.

NOTICE:

Specifications contained within the following tables are

subject to change.

READ TIMING WAVEFORMS

Addresses

tACC

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VOH

VOL

HIGH Z HIGH Z

D ATA V alid

tOE tDF

tCE

Outputs

tOH

ADD V alid

NOTES:

1. VIL min. = -0.6V for pulse width is equal to or less than 20ns.

2. If VIH is over the specified maximum value, programming

operation cannot be guaranteed.

3. ICCES is specified with the device de-selected. If the

device is read during erase suspend mode, current draw

is the sum of ICCES and ICC1 or ICC2.

4. All current are in RMS unless otherwise noted.

DC CHARA CTERISTICS (T A = 0oC to 70 oC, VCC = 5V±±

±±

±10%)

SYMBOL PARAMETER MIN. TYP MAX. UNIT CONDITIONS

ICC1 (Read) Operating VCC Current 30 mA IOUT=0mA, f=5MHz

ICC2 50 mA IOUT=0mA, f=10MHz

ICC3 (Program) 50 mA In Programming

ICC4 (Erase) 50 mA In Erase

ICCES VCC Erase Suspend Current 2 mA CE=VIH, Erase Suspended

COMMAND PROGRAMMING/DATA PROGRAMMING/ERASE OPERATION

MX29F004T/B

P/N:PM0554 REV. 1.9, OCT. 19, 2004

AC CHARACTERISTICS TA = 0oC to 70oC, VCC = 5V ± ±

± ±

± 10%

29F004T/B-55 29F004T/B-70 29F004T/B-90 29F004T/B-12

SYMBOL PARAMETER MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. UNIT

tOES OE setup time 50 50 50 50 n s

tCWC Command programming cycle 55 70 90 120 ns

tCEP WE programming pulse width 45 45 45 50 n s

tCEPH1 WE programming pulse width High 20 20 20 20 n s

tCEPH2 WE programming pulse width High 20 20 20 20 n s

tAS Address setup time 0 0 0 0 ns

tAH Address hold time 45 45 45 50 n s

tDS Data setup time 30 30 45 50 n s

t DH Data hold time 0 0 0 0 ns

tCESC CE setup time before command write 0 0 0 0 n s

t DF Output disable time (Note 1) 30 30 40 40 n s

tAETC Total erase time in auto chip erase 4(TYP.) 32 4(TYP.) 32 4(TYP.) 32 4(TYP.) 32 s

tAETB Total erase time in auto sector erase 1.3(TYP.)10.4 1.3(TYP.)10.4 1.3(TYP.) 10.4 1.3(TYP.) 10.4 s

tAVT Total programming time in auto verify 7 210 7 210 7 210 7 210 u s

tBAL Sector address load time 100 100 100 100 u s

tCH CE Hold Time 0 0 0 0 ns

tCS CE setup to WE going low 0 0 0 0 ns

tVLHT Voltage Transition Time 4 4 4 4 u s

tOES P OE Setup Time to WE Active 4 4 4 4 u s

tWPP1 Write pulse width for chip protect 10 10 10 10 u s

tWPP2 Write pulse width for chip unprotect 12 12 12 12 m s

NOTES:

1. tDF defined as the time at which the output achieves the open circuit condition and data is no longer driven.

MX29F004T/B

P/N:PM0554 REV. 1.9, OCT. 19, 2004

SWITCHING TEST CIRCUITS

SWITCHING TEST WAVEFORMS

COMMAND WRITE TIMING WAVEFORM

2.0V 2.0V

0.8V

0.8V TEST POINTS

2.4V

0.45V

AC TESTING: Inputs are driven at 2.4V for a logic "1" and 0.45V for a logic "0".

Input pulse rise and fall times are <20ns.

OUTPUT

INPUT

Addresses

DIN

tDS

tAH

Data

tDH

tCS tCH

tCWC

tCEPH1

tCEP

tOES

tAS

VCC

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

ADD V alid

DEVICE UNDER

TEST

DIODES=IN3064

OR EQUIVALENT

CL 1.2K ohm

1.6K ohm +5V

CL=100pF Including jig capacitance

MX29F004T/B

P/N:PM0554 REV. 1.9, OCT. 19, 2004

One byte data is programmed. Ver ify in fast algor ithm

and additional programming by external control are not

required because these operations are executed auto-

matically by internal control circuit. Programming

completion can be verified by DATA polling and toggle

bit checking after automatic verification starts. Device

o utputs DATA during pro gr amming and D ATA after pro-

gramming on Q7.(Q6 is for toggle bit; see toggle bit,

DATA po lling, timing wav efo rm)

AUTOMATIC PROGRAMMING TIMING WAVEFORM

tCWC

tAS

tCEP

tDS tDH tDF

Vcc 5V

Q0,Q1,Q2

Q4(Note 1)

A11~A18

tCEPH1

tAH

ADD V alid

tCESC

Command In

ADD V alid

A0~A10

Command In

Command In Data In

Data In

DATA

Command In Command In DATADATA

tAVT

tOE

DATA polling

2AAH

555H 555H

(Q0~Q7)

Command #55H Command #A0H

Notes:

(1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit

Command #AAH

AUTOMATIC PROGRAMMING TIMING WAVEFORM

MX29F004T/B

P/N:PM0554 REV. 1.9, OCT. 19, 2004

AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART

START

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Program Data/Address

Write Data A0H Address 555H

YES

Toggle Bit Checking

Q6 not Toggled

Verify Byte Ok

YES

Q5 = 1

Reset

Auto Program Completed

Auto Program Exceed

Timing Limit

Invalid

Command

YES

MX29F004T/B

P/N:PM0554 REV. 1.9, OCT. 19, 2004

All data in chip are erased. External erase verification is

not required because data is erased automatically by

internal control circuit. Erasure completion can be

verified by DATA polling and toggle bit checking after

automatic erase starts. Device outputs 0 during erasure

and 1 after erasure on Q7.(Q6 is for toggle bit; see toggle

bit, DATA polling, timing waveform)

AUTOMATIC CHIP ERASE TIMING WAVEFORM

tCWC

tAS

tCEP

tDS tDH

Vcc 5V

Q0,Q1,

Q4(Note 1)

A11~A18

tCEPH1

tAH

Command In

A0~A10

Command InCommand In

Command In Command InCommand In

tAETC

DATA polling

2AAH

555H 555H

Command #AAH Command #55H Command #80H

(Q0~Q7)

Notes:

(1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit, Q2: Toggle bit

555H 2AAH 555H

Command In

Command #AAH

Command In

Command #55H

Command In

Command #10H

MX29F004T/B

P/N:PM0554 REV. 1.9, OCT. 19, 2004

AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART

START

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data AAH Address 555H

Write Data 80H Address 555H

YES

Toggle Bit Checking

Q6 not Toggled

Write Data 10H Address 555H

Write Data 55H Address 2AAH

Reset

Auto Chip Erase Exceed

Timing Limit

DATA Polling

Q7 = 1

YES

Q5 = 1

Auto Chip Erase Completed

NO .

Invalid

Command

YES

MX29F004T/B

P/N:PM0554 REV. 1.9, OCT. 19, 2004

Sector data indicated by A13 to A18 are erased. External

erase verify is not required because data are erased

automatically by internal control circuit. Erasure comple-

tion can be verified by DATA polling and toggle bit

checking after automatic erase starts. Device outputs 0

during erasure and 1 after erasure on Q7.(Q6 is for toggle

bit; see toggle bit, DATA polling, timing waveform)

AUTOMATIC SECTOR ERASE TIMING WAVEFORM

tAH

Sector

Address0

555H 2AAH 2AAH

555H 555H

Sector

Address1 Sector

Addressn

Vcc 5V

Q0,Q1,

Q4(Note 1)

A13~A18

A0~A10

Command

In Command

Command

In Command

Command

In Command

Command

In Command

Command

In Command

Command

Command #30HCommand #30HCommand #30HCommand #55HCommand #AAHCommand #80HCommand #55HCommand #AAH

(Q0~Q7)

Command

tDH

tDS

tCEP

tCWC

tAETB

tBAL

DATA polling

tCEPH1

tAS

Notes:

(1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit, Q2: Toggle bit

MX29F004T/B

P/N:PM0554 REV. 1.9, OCT. 19, 2004

AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART

START

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data AAH Address 555H

Write Data 80H Address 555H

YES

Toggle Bit Checking

Q6 not Toggled

Write Data 30H Sector Address

Write Data 55H Address 2AAH

Reset

Auto Sector Erase Exceed

Timing Limit

DATA Polling

Q7 = 1

Q5 = 1

Auto Sector Erase Completed

Load Other Sector Addrss If Necessary

(Load Other Sector Address)

YES

Last Sector

to Erase

Time-out Bit

Checking Q3=1 ?

Toggle Bit Checking

Q6 Toggled ? Invalid Command

YES

MX29F004T/B

P/N:PM0554 REV. 1.9, OCT. 19, 2004

ERASE SUSPEND/ERASE RESUME FLOWCHART

START

Write Data B0H

Toggle Bit checking Q6

not toggled

YES

Write Data 30H

Continue Erase

Reading or

Programming End

Read Array or

Program

Another

Erase Suspend ? NO

YES

MX29F004T/B

P/N:PM0554 REV. 1.9, OCT. 19, 2004

TIMING WAVEFORM FOR CHIP PROTECTION FOR SYSTEM WITH 12V

tOE

Data

12V

tOESP

tWPP 1

tVLHT

Verify

01H F0H

MX29F004T/B

P/N:PM0554 REV. 1.9, OCT. 19, 2004

TIMING WAVEFORM FOR CHIP UNPROTECTION FOR SYSTEM WITH 12V

tOE

Data

12V

tOESP

tWPP 2

tVLHT

Verify

00H

F0H

MX29F004T/B

P/N:PM0554 REV. 1.9, OCT. 19, 2004

CHIP PROTECTION ALGORITHM FOR SYSTEM WITH 12V

START

PLSCNT=1

Chip Protection

Complete

Data=01H?

Yes

OE=VID,A9=VID,CE=VIL

A6=VIL

Activate WE Pulse

Time Out 10us

Set WE=VIH, CE=OE=VIL

A9 should remain VID

Read Data with A1=1

Remove VID from A9

Write Reset Command

Device Failed

PLSCNT=32?

Yes

MX29F004T/B

P/N:PM0554 REV. 1.9, OCT. 19, 2004

TIMING WAVEFORM FOR CHIP PROTECTION FOR SYSTEM WITHOUT 12V

tOE

Data

* See the following Note!

Verify

01H

Note: 1. Must issue "unlock for sector protect/unprotect" command

before chip protection for a system without 12V provided.

2. Except F0H

Toggle bit polling

Don't care

(Note 2)

tCEP

F0H

MX29F004T/B

P/N:PM0554 REV. 1.9, OCT. 19, 2004

TIMING WAVEFORM FOR CHIP UNPROTECTION FOR SYSTEM WITHOUT 12V

tOE

Data

Verify

00H

Note: 1. Must issue "unlock for sector protect/unprotect" command

before chip unprotection for a system without 12V provided.

2. Except F0H

tCEP

Toggle bit polling

Don't care

(Note 2)

* See the following Note!

F0H

MX29F004T/B

P/N:PM0554 REV. 1.9, OCT. 19, 2004

CHIP PROTECTION ALGORITHM FOR SYSTEM WITHOUT 12V

START

PLSCNT=1

Chip Protection

Complete

Data=01H?

Activate WE Pulse to start

Data don't care

Set CE=OE=VIL

A9=VIH

Read Data from chip,

A1=1

Write Reset Command

Device Failed

PLSCNT=32?

Yes

Increment PLSCNT

Write "unlock for chip protect/unprotect"

Command(Table1)

OE=VIH, A9=VIH

CE=VIL, A6=VIL

Toggle bit checking

Q6 not Toggled No .

Yes

MX29F004T/B

P/N:PM0554 REV. 1.9, OCT. 19, 2004

CHIP UNPROTECTION ALGORITHM FOR SYSTEM WITHOUT 12V

START

PLSCNT=1

Chip Unprotect

Complete

Toggle bit checking

Q6 not Toggled

Yes

Write "unlock for chip protect/unprotect"

Command (Table 1)

Set OE=A9=VIH

CE=VIL, A6=1

Set OE=CE=VIL,

A9=VIH, A1=1

Active WE Pulse to start

Data don't care

Data=00H?

Read Data from Device

Write Reset Command Device Failed

PLSCNT=1000?

No Increment

PLSCNT

Yes Yes

MX29F004T/B

P/N:PM0554 REV. 1.9, OCT. 19, 2004

ID CODE READ TIMING WAVEFORM

tACC

tCE

tACC

tOE

tOH tOH

tDF

DATA OUT

C2H 45H/46H

VID

VIH

VIL

ADD

A2-A8

A10-A18

ADD

DATA OUT

DATA

Q0-Q7

VCC 5V

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

MX29F004T/B

P/N:PM0554 REV. 1.9, OCT. 19, 2004

ORDERING INFORMATION

PLASTIC P ACKAGE

(To p Bo o t Secto r as an e xample, Fo r Botto m Bo o t Secto r o nes, MX29F004TXX will be changed to MX29F004Bxx)

Part No. Access Operating Current Standby Current Package Remark

Time (ns) MAX.(mA) MAX.(uA)

MX29F004TQC-55 55 30 5 32 Pin PLCC

MX29F004TQC-70 70 30 5 32 Pin PLCC

MX29F004TQC-90 90 30 5 32 Pin PLCC

MX29F004TQC-12 120 30 5 32 Pin PLCC

MX29F004TTC-55 55 30 5 32 Pin TSOP

(Normal Type)

MX29F004TTC-70 70 30 5 32 Pin TSOP

(Normal Type)

MX29F004TTC-90 90 30 5 32 Pin TSOP

(Normal Type)

MX29F004TTC-12 120 30 5 32 Pin TSOP

(Normal Type)

MX29F004TPC-55 55 30 5 32 Pin PDIP

MX29F004TPC-70 70 30 5 32 Pin PDIP

MX29F004TPC-90 90 30 5 32 Pin PDIP

MX29F004TPC-12 120 30 5 32 Pin PDIP

MX29F004TQC-55G 55 30 5 32 Pin PLCC Pb-free

MX29F004TQC-70G 70 30 5 32 Pin PLCC Pb-free

MX29F004TQC-90G 90 30 5 32 Pin PLCC Pb-free

MX29F004TQC-12G 120 30 5 32 Pin PLCC Pb-free

MX29F004TTC-55G 55 30 5 32 Pin TSOP Pb-free

(Normal Type)

MX29F004TTC-70G 70 30 5 32 Pin TSOP Pb-free

(Normal Type)

MX29F004TTC-90G 90 30 5 32 Pin TSOP Pb-free

(Normal Type)

MX29F004TTC-12G 120 30 5 32 Pin TSOP Pb-free

(Normal Type)

MX29F004T/B

P/N:PM0554 REV. 1.9, OCT. 19, 2004

MIN. MAX.

Input Voltage with respect to GND on all pins except I/O pins -1.0V 13.5V

Input Voltage with respect to GND on all I/O pins -1.0V Vcc + 1.0V

Current -100mA +100mA

Includes all pins except Vcc. Test conditions: Vcc = 5.0V, one pin at a time.

LIMITS

PARAMETER MIN. TYP.(2) MAX.(3) UNITS

Sector Erase Time 1.3 10.4 sec

Chip Erase Time 4 32 sec

Byte Programming Time 7 2 10 us

Chip Programming Time 4 12 sec

Erase/Program Cycles 100,000 Cycles

LATCH-UP CHARACTERISTICS

ERASE AND PROGRAMMING PERFORMANCE (1)

Note: 1. Not 100% Tested, Excludes external system level over head.

2. Typical values measured at 25°C,5V.

3. Maximum values measured at 25°C,4.5V.

PARAMETER MIN. UNIT

Data Retention Time 2 0 Years

DATA RETENTION

MX29F004T/B

P/N:PM0554 REV. 1.9, OCT. 19, 2004

PACKAGE INFORMATION

MX29F004T/B

P/N:PM0554 REV. 1.9, OCT. 19, 2004

MX29F004T/B

P/N:PM0554 REV. 1.9, OCT. 19, 2004

MX29F004T/B

P/N:PM0554 REV. 1.9, OCT. 19, 2004

REVISION HISTORY

Revision Description Page Date

1.0 To remo ve "Advanced Info rmatio n" data sheet marking and P1 JUL/01/1999

contain information on products in full production.

1. 1 To improve ICC1 spec:from 40mA @5MHz to 30mA @5MHz P1,14,15,33 JUL/12/1999

1. 2 1. Program/erase cycle times:10K cycles-->100K cycles P1,34 DEC/20/1999

2. To add data retentio n minimum 20 years P1,34

3. To modify timing o f sector address lo ading period while P 9

operating multi-sector erase from 80us to 30us

4. To modify tBAL from 80us to 100us P 1 6

5. To remove A9 from "timing wavefor m for sector protection for P28

system without 12V"

To remove A9 from "timing waveform for chip unprotection for P29

system without 12V"

1. 3 Add erase suspend ready max. 100us in ERASE SUSPEND's P1 0 MAY/30/2000

section at page 10

1.4 To modify "P ackage Information" P35~37 JUN/12/2001

1. 5 1. To corrected typing erro r All JUL/01/2002

1.6 1. Add 55ns speed option P14,16,33 JUL/18/2002

2. Add industrial grade level P14,15,16,33

1.7 1. Removed industrial grade P14~16,33 AUG/12/2002

1.8 To mo dify Package Info rmation P35~37 NOV/21/2002

1.9 1. Added Pb-free part no . in Ordering Info rmation P33 OCT/18/2004

MX29F004T/B

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MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.