M68HC05
Microcontrollers
MC68HC705C8A/D
Rev. 3, 3/ 2002
MC68HC705C8A
MC68HSC705C8A
Technic al Data
Freescale Semiconductor, I
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0&+&&$² 5HY
7HFKQLFDO'DWD
MC68HC705C8A
MC68HSC705C8A
Technical Data
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7HFKQLFDO'DWD 0&+&&$² 5HY
Technical Data
Revision History
Date Revision
Level Description Page
Number(s)
May, 2001 2.1
1.7 Pin Functions — Added description of programming voltage
(VPP) pin 1.7.2 VPP 29
Removed not e following 1.7.11 Port D I/O Pins (PD7 and
PD5–PD0) 33
14 .2 In t roducti on — Updat ed Motorola contact information 192
March, 2002 3 14.7 44-Pin Quad Flat Pack (QF P) — Corrected case outline
drawing from Case #824E to Case #824A 195
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MC68HC705C8A —Rev. 3 Tec hnical Data
MOTO ROLA List of S ect ions
Technical Data — MC68HC705C8 A
List of Sections
Section 1. General Description . . . . . . . . . . . . . . . . . . . .21
Section 2. Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Section 3. Central Processor Unit (CPU) . . . . . . . . . . . .43
Section 4. Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Section 5. Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Section 6. Low-Power Modes. . . . . . . . . . . . . . . . . . . . . .69
Section 7. Parallel Input/Output (I/O). . . . . . . . . . . . . . . .77
Section 8. Capture/Compare Timer. . . . . . . . . . . . . . . . .89
Section 9. EPROM/OTPROM (PROM) . . . . . . . . . . . . . .103
Section 10. Serial Communications Interface (SCI). . .121
Section 11. Serial Peripheral Interface (SPI). . . . . . . . .139
Section 12. Instruction Set. . . . . . . . . . . . . . . . . . . . . . .153
Section 13. Electrical Specifications . . . . . . . . . . . . . .171
Section 14. Mechanical Specifications . . . . . . . . . . . . .191
Section 15. Ordering Information . . . . . . . . . . . . . . . . .199
Appendix A. MC68HSC705C8A . . . . . . . . . . . . . . . . . . .201
Index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211
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Technical Data MC68HC705C8A —Rev. 3
6 List of S ect ions
Li st of Sec ti o ns
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MC68HC705C8A —Rev. 3 Tec hnical Data
MOTOROLA Table of Contents
Technical Data — MC68HC705C8 A
Table of Contents
Section 1. General Description
1.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
1.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
1.4 Programmable Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
1.5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
1.6 Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
1.7 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
1.7.1 VDD and VSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
1.7.2 VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
1.7.3 OSC1 and OSC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
1.7.4 External Reset Pin (RESET) . . . . . . . . . . . . . . . . . . . . . . . .32
1.7.5 External Interrupt Request Pin (IRQ) . . . . . . . . . . . . . . . . . .32
1.7.6 Input Capture Pin (TCAP) . . . . . . . . . . . . . . . . . . . . . . . . . .32
1.7.7 Output Compare Pin (TCMP). . . . . . . . . . . . . . . . . . . . . . . .33
1.7.8 Port A I/O Pins (PA7–PA0). . . . . . . . . . . . . . . . . . . . . . . . . .33
1.7.9 Port B I/O Pins (PB7–PB0). . . . . . . . . . . . . . . . . . . . . . . . . .33
1.7.10 Port C I/O Pins (PC7–PC0) . . . . . . . . . . . . . . . . . . . . . . . . .33
1.7.11 Port D I/O Pins (PD7 and PD5–PD0). . . . . . . . . . . . . . . . . .33
Sect io n 2. M em o ry
2.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
2.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
2.3 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
2.4 Input/Output (I/O) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
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Technical Data MC68HC705C8A —Rev. 3
8 Table of Contents
Table of Contents
2.5 RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
2.6 EPROM/OTPROM (PROM) . . . . . . . . . . . . . . . . . . . . . . . . . . .37
2.7 Bootloader ROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Section 3. Central Processor Unit (CPU)
3.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
3.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
3.3 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
3.3.1 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
3.3.2 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
3.3.3 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
3.3.4 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
3.3.5 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . .47
3.4 Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Section 4. Interrupts
4.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
4.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
4.3 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 0
4.3.1 Software Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
4.3.2 External Interrupt (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
4.3.3 Port B Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
4.3.4 Capture/Compare Timer Interrupts . . . . . . . . . . . . . . . . . . .55
4.3.5 SCI Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
4.3.6 SPI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
4.4 Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 7
Sec tio n 5. Resets
5.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
5.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
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Table of Contents
MC68HC705C8A —Rev. 3 T echnical Data
MOTOROLA Table of Contents
5.3 Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
5.3.1 Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
5.3.2 External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
5.3.3 Programmable and Non-Programmable
COP Watchdog Resets. . . . . . . . . . . . . . . . . . . . . . . . . .62
5.3.4 Clock Monitor Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Section 6. Low-Power Modes
6.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
6.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
6.3 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
6.3.1 SCI During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
6.3.2 SPI During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
6.3.3 Programmable COP Watchdog in Stop Mode . . . . . . . . . . .71
6.3.4 Non-Programmable COP Watchdog in Stop Mode . . . . . . .73
6.4 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
6.4.1 Programmable COP Watchdog in Wait Mode . . . . . . . . . . .75
6.4.2 Non-Programmable COP Watchdog in Wait Mode . . . . . . .75
6.5 Data-Retention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Se ct ion 7. Par al lel Inp u t/O utpu t (I/O )
7.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
7.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
7.3 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
7.3.1 Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
7.3.2 Data Direction Register A. . . . . . . . . . . . . . . . . . . . . . . . . . .7 9
7.3.3 Port A Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
7.4 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
7.4.1 Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
7.4.2 Data Direction Register B. . . . . . . . . . . . . . . . . . . . . . . . . . .8 2
7.4.3 Port B Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
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Table of Contents
7.5 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
7.5.1 Port C Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
7.5.2 Data Direction Register C. . . . . . . . . . . . . . . . . . . . . . . . . . .86
7.5.3 Port C Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
7.6 Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
Section 8. Capture/Compare Timer
8.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
8.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
8.3 Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
8.3.1 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
8.3.2 Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
8.4 Timer I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
8.4.1 Timer Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
8.4.2 Timer Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
8.4.3 Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
8.4.4 Alternate Timer Registers. . . . . . . . . . . . . . . . . . . . . . . . . . .98
8.4.5 Input Capture Registers . . . . . . . . . . . . . . . . . . . . . . . . . .100
8.4.6 Output Compare Registers. . . . . . . . . . . . . . . . . . . . . . . . .101
Section 9. EPROM/OTPROM (PROM)
9.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
9.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
9.3 EPROM/OTPROM (PROM) Programming. . . . . . . . . . . . . . .104
9.3.1 Program Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
9.3.2 Preprogramming Steps . . . . . . . . . . . . . . . . . . . . . . . . . . .110
9.4 PROM Programming Routines. . . . . . . . . . . . . . . . . . . . . . . .111
9.4.1 Program and Verify PROM. . . . . . . . . . . . . . . . . . . . . . . . .111
9.4.2 Verify PROM Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . .112
9.4.3 Secure PROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
9.4.4 Secure PROM and Verify. . . . . . . . . . . . . . . . . . . . . . . . . .113
9.4.5 Secure PROM and Dump . . . . . . . . . . . . . . . . . . . . . . . . . .113
9.4.6 Load Program into RAM and Execute . . . . . . . . . . . . . . . .114
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MC68HC705C8A —Rev. 3 T echnical Data
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9.4.7 Execute Program in RAM. . . . . . . . . . . . . . . . . . . . . . . . . .115
9.4.8 Dump PROM Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . .115
9.5 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
9.5.1 Option Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
9.5.2 Mask Option Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . .117
9.5.3 Mask Option Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . .118
9.6 EPROM Erasing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
Section 10. Serial Communications Interface (SCI)
10.1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
10.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
10.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
10.4 SCI Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
10.5 SCI Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
10.5.1 Transmitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
10.5.2 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
10.6 SCI I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
10.6.1 SCI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
10.6.2 SCI Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
10.6.3 SCI Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
10.6.4 SCI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
10.6.5 Baud Rate Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136
Sect ion 11. Serial Peripheral Interface (SPI)
11.1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
11.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
11.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
11.4 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142
11.4.1 Pin Functions in Master Mode . . . . . . . . . . . . . . . . . . . . . .143
11.4.2 Pin Functions in Slave Mode . . . . . . . . . . . . . . . . . . . . . . .144
11.5 Multiple-SPI Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145
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Table of Contents
11.6 Serial Clock Polarity and Phase . . . . . . . . . . . . . . . . . . . . . . .146
11.7 SPI Error Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
11.7.1 Mode Fault Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
11.7.2 Write Collision Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
11.7.3 Overrun Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148
11.8 SPI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148
11.9 SPI I/O Regi sters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148
11.9.1 SPI Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
11.9.2 SPI Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
11.9.3 SPI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151
Section 12. Instruction Set
12.1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153
12.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154
12.3 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154
12.3.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
12.3.2 Immediate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
12.3.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
12.3.4 Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
12.3.5 Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156
12.3.6 Indexed, 8-Bit Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156
12.3.7 Indexed, 16-Bit Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . .156
12.3.8 Relati ve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157
12.4 Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157
12.4.1 Register/Memory Instructions. . . . . . . . . . . . . . . . . . . . . . .158
12.4.2 Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . .159
12.4.3 Jump/Branch Instructions. . . . . . . . . . . . . . . . . . . . . . . . . .160
12.4.4 Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . .162
12.4.5 Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163
12.5 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .164
12.6 Opcode Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169
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Table of Contents
MC68HC705C8A —Rev. 3 T echnical Data
MOTOROLA Table of Contents
Section 13. Electrical Specifications
13.1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171
13.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171
13.3 Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172
13.4 Operating Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .173
13.5 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173
13.6 Power Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174
13.7 5.0-Volt DC Electrical Characteristics. . . . . . . . . . . . . . . . . . .175
13.8 3.3-Volt DC Electrical Characteristics . . . . . . . . . . . . . . . . . .176
13.9 5.0-Volt Control Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181
13.10 3.3-Volt Control Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182
13.11 5.0-Volt Serial Peripheral Interface (SPI) Timing . . . . . . . . . .185
13.12 3.3-Volt Serial Peripheral Interface (SPI) Timing . . . . . . . . . .187
Section 14. Mech anical Specificatio ns
14.1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191
14.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191
14.3 40-Pin Pl astic Dual In-Line Package (PDIP). . . . . . . . . . . . . .192
14.4 40-Pin Ceramic Dual In-Line Package (Cerdip) . . . . . . . . . . .193
14.5 44-Lead Plastic-Leaded C hip Carrier (PLCC) . . . . . . . . . . . .194
14.6 44-Lead Ceramic-Leaded Chip Carrier (CLCC) . . . . . . . . . . .195
14.7 44-Pin Quad Flat Pack (QFP). . . . . . . . . . . . . . . . . . . . . . . . .196
14.8 42-Pin Shrink Dual In-Line Package (SDIP). . . . . . . . . . . . . .197
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Technical Data MC68HC705C8A —Rev. 3
14 Table of Contents
Table of Contents
Section 15. Ordering Information
15.1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199
15.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199
15.3 MCU Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199
Appendix A. MC68HSC705C8A
A.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .201
A.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .201
A.3 5.0-Volt High-Speed DC Electrical Characteristics. . . . . . . . .202
A.4 3.3-Volt High-Speed DC Electrical Characteristics . . . . . . . .203
A.5 5.0-Volt High-Speed Control Timing. . . . . . . . . . . . . . . . . . . .204
A.6 3.3-Volt High-Speed Control Timing. . . . . . . . . . . . . . . . . . . .204
A.7 5.0-Volt High-Speed SPI Timing . . . . . . . . . . . . . . . . . . . . . .205
A.8 3.3-Volt High-Speed SPI Timing. . . . . . . . . . . . . . . . . . . . . . .207
A.9 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209
Index
Index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211
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MC68HC705C8A —Rev. 3 Tec hnical Data
MOTO ROLA List of Figures
Technical Data — MC68HC705C8 A
List of Figures
Figure Title Page
1-1 Option Register (Option) . . . . . . . . . . . . . . . . . . . . . . . . . . .23
1-2 MC68HC705C8A Block Diagram . . . . . . . . . . . . . . . . . . . . .25
1-3 40-Pin PDIP/Cerdip Pin Assignments . . . . . . . . . . . . . . . . .26
1-4 44-Lead PLCC/CLCC Pin Assignments. . . . . . . . . . . . . . . .27
1-5 44-Pin QFP Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . .27
1-6 42-Pin SDIP Pin Assignments . . . . . . . . . . . . . . . . . . . . . . .28
1-7 Bypassing Layout Recommendation . . . . . . . . . . . . . . . . . .29
1-8 Crystal Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
1-9 2-Pin Ceramic Resonator Connections . . . . . . . . . . . . . . . .31
1-10 3-Pin Ceramic Resonator Connections . . . . . . . . . . . . . . . .31
1-11 External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
2-1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
2-2 I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
3-1 Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .044
3-2 Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .045
3-3 Index Register (X) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .045
3-4 Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .046
3-5 Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . .046
3-6 Condition Code Register (CCR). . . . . . . . . . . . . . . . . . . . .047
4-1 External Interrupt Internal Function Diagram . . . . . . . . . . . .52
4-2 External Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . .52
4-3 Port B I/O Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
4-4 Interrupt Stacking Order. . . . . . . . . . . . . . . . . . . . . . . . . . . .58
4-5 Reset and Interrupt Processing Flowchart . . . . . . . . . . . . . .59
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Technical Data MC68HC705C8A —Rev. 3
16 List of Figures
Li st of Figu r es
Figure Title Page
5-1 Programmable COP Watchdog Diagram . . . . . . . . . . . . . . .63
5-2 Programmable COP Reset Register (COPRST) . . . . . . . . .6 4
5-3 Programmable COP Control Register (COPCR) . . . . . . . . .64
5-4 Non-Programmable COP Watchdog Diagram . . . . . . . . . . .67
6-1 Stop/W ait Mode Function Flowchart . . . . . . . . . . . . . . . . . .70
6-2 Programmable COP Watchdog
in Stop Mode (PCOPE = 1) Flowchart. . . . . . . . . . . . . . .72
6-3 Non-Programmable COP Watchdog
in Stop Mode (NCOPE = 1) Flowchart . . . . . . . . . . . . . .74
7-1 Port A Data Register (PORTA). . . . . . . . . . . . . . . . . . . . . . .78
7-2 Data Direction Register A (DDRA). . . . . . . . . . . . . . . . . . . .79
7-3 Port A I/O Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
7-4 Port B Data Register (PORTB). . . . . . . . . . . . . . . . . . . . . . .81
7-5 Data Direction Register B (DDRB). . . . . . . . . . . . . . . . . . . .82
7-6 Port B I/O Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
7-7 Port C Data Register (PORTC) . . . . . . . . . . . . . . . . . . . . . .85
7-8 Data Direction Register C (DDRC). . . . . . . . . . . . . . . . . . . .8 6
7-9 Port C I/O Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
7-10 Port D Fixed Input Register (PORTD) . . . . . . . . . . . . . . . . .88
8-1 Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
8-2 Timer I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . .91
8-3 Input Capture Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . .92
8-4 Output Compare Operation . . . . . . . . . . . . . . . . . . . . . . . . .93
8-5 Timer Control Register (TCR) . . . . . . . . . . . . . . . . . . . . . . .94
8-6 Timer Status Register (TSR) . . . . . . . . . . . . . . . . . . . . . . . .96
8-7 Timer Registers (TRH and TRL) . . . . . . . . . . . . . . . . . . . . .97
8-8 Timer Register Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
8-10 Alternate Timer Register Reads. . . . . . . . . . . . . . . . . . . . . .99
8-9 Alternate Timer Registers (ATRH and ATRL) . . . . . . . . . . .99
8-11 Input Capture Registers (ICRH and ICRL). . . . . . . . . . . . .100
8-12 Output Compare Registers (OCRH an d OCRL). . . . . . . . .101
9-1 EPROM/OTPROM Programming Flowchart . . . . . . . . . . .105
9-2 PROM Programming Circuit. . . . . . . . . . . . . . . . . . . . . . . .106
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List of Figures
MC68HC705C8A —Rev. 3 T echnical Data
MOTO ROLA List of Figures
Figure Title Page
9-3 Program Register (PROG). . . . . . . . . . . . . . . . . . . . . . . . .109
9-4 Option Register (Option) . . . . . . . . . . . . . . . . . . . . . . . . . .116
9-5 Mask Option Register 1 (MOR1) . . . . . . . . . . . . . . . . . . . .117
9-6 Mask Option Register 2 (MOR2) . . . . . . . . . . . . . . . . . . . .118
10-1 SCI Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
10-2 SCI Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
10-3 SCI Transmitter I/O Register Summary . . . . . . . . . . . . . . .125
10-4 SCI Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
10-5 SCI Data Register (SCDR). . . . . . . . . . . . . . . . . . . . . . . . .129
10-6 SCI Control Register 1 (SCCR1) . . . . . . . . . . . . . . . . . . . .130
10-7 SCI Control Register 2 (SCCR2) . . . . . . . . . . . . . . . . . . . .131
10-8 SCI Status Register (SCSR) . . . . . . . . . . . . . . . . . . . . . . .133
10-9 Baud Rate Register (B aud) . . . . . . . . . . . . . . . . . . . . . . . .136
11-1 SPI Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
11-2 SPI I/O Regi ster Summary. . . . . . . . . . . . . . . . . . . . . . . . .142
11-3 Master/Slave Connections . . . . . . . . . . . . . . . . . . . . . . . . .143
11-4 One Master and Three Slaves Block Di agram. . . . . . . . . .145
11-5 Two Master/Slaves and Three Slaves Block Diagram . . . .146
11-6 SPI Clock/Data Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . .146
11-7 SPI Data Register (SPDR). . . . . . . . . . . . . . . . . . . . . . . . .149
11-8 SPI Control Register (SPCR). . . . . . . . . . . . . . . . . . . . . . .149
11-9 SPI Status Register (SPSR). . . . . . . . . . . . . . . . . . . . . . . .151
13-1 Equivalent T est Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173
13-2 Typical Voltage Compar ed to Current . . . . . . . . . . . . . . . .177
13-3 Typical Current versus Internal
Frequency for Run and Wait Modes . . . . . . . . . . . . . . .179
13-4 Total Current Drain versus Frequency. . . . . . . . . . . . . . . .180
13-5 Timer Relationships . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182
13-6 Stop Recovery Timing Diagram . . . . . . . . . . . . . . . . . . . . .183
13-7 Power-On Reset and External Reset Timing Diagram. . . .184
13-8 SPI Master Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189
13-9 SPI Slave Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190
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Technical Data MC68HC705C8A —Rev. 3
18 List of Figures
Li st of Figu r es
Figure Title Page
14-1 MC68HC705C8AP Package Dimensions
(Case #711). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192
14-2 MC68HC705C8AS Package Dimensions
(Case #734A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193
14-3 MC68HC705C8AFN Package Dimensions
(Case #777). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194
14-4 MC68HC705C8AFS Package Dimensions
(Case #777B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195
14-5 MC68HC705C8AFB Package Dimensions
(Case #824A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196
14-6 MC68HC705C8AB Package Dimensions
(Case #858). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197
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MC68HC705C8A —Rev. 3 Tec hnical Data
MOTO ROLA List of Tables
Technical Data — MC68HC705C8 A
List of Tables
Table Title Page
2-1 Memory Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
4-1 Reset/Interrupt Vector Addresses . . . . . . . . . . . . . . . . . . . . .57
5-1 Programmable COP Timeout Period Selection . . . . . . . . . . .66
7-1 Port A Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
7-2 Port B Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
7-3 Port C Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
9-1 MC68HC05PGMR PCB Reference Designators . . . . . . . . .104
9-2 PROM Programming Routines. . . . . . . . . . . . . . . . . . . . . . .108
10-1 Baud Rate Generator Clock Prescaling . . . . . . . . . . . . . . . .136
10-2 Baud Rate Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
10-3 Baud Rate Selection Examples . . . . . . . . . . . . . . . . . . . . . .138
11-1 SPI Clock Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . .150
12-1 Regi ster/Memory Instructions. . . . . . . . . . . . . . . . . . . . . . . .158
12-2 Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . . .159
12-3 Jump and Branch Instructions . . . . . . . . . . . . . . . . . . . . . . .161
12-4 Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . . . .162
12-5 Control Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163
12-6 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . .164
12-7 Opcode Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170
15-1 MC68HC705C8A Order Numbers . . . . . . . . . . . . . . . . . . . .199
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Technical Data MC68HC705C8A —Rev. 3
20 List of Tables
Li st of Tables
Table Title Page
A-1 Programmable COP Timeout Period Selection . . . . . . . . . . .202
A-2 MC68HSC705C8A Order Numbers . . . . . . . . . . . . . . . . . . . .209
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MC68HC705C8A —Rev. 3 Tec hnical Data
MOTOROLA General Description
Technical Data — MC68HC705C8 A
Section 1. General De scrip tion
1.1 Contents
1.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2
1.4 Programmable Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
1.5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 4
1.6 Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
1.7 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
1.7.1 VDD and VSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
1.7.2 VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
1.7.3 OSC1 and OSC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
1.7.3.1 Crystal Resonator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 0
1.7.3.2 Ceramic Resonator . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
1.7.3.3 External Clock Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . .32
1.7.4 External Reset Pin (RESET) . . . . . . . . . . . . . . . . . . . . . . . .32
1.7.5 External Interrupt Request Pin (IRQ) . . . . . . . . . . . . . . . . . .32
1.7.6 Input Capture Pin (TCAP) . . . . . . . . . . . . . . . . . . . . . . . . . .32
1.7.7 Output Compare Pin (TCMP). . . . . . . . . . . . . . . . . . . . . . . .33
1.7.8 Port A I/O Pins (PA7–PA0). . . . . . . . . . . . . . . . . . . . . . . . . .33
1.7.9 Port B I/O Pins (PB7–PB0). . . . . . . . . . . . . . . . . . . . . . . . . .33
1.7.10 Port C I/O Pins (PC7–PC0) . . . . . . . . . . . . . . . . . . . . . . . . .33
1.7.11 Port D I/O Pins (PD7 and PD5–PD0). . . . . . . . . . . . . . . . . .33
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Technical Data MC68HC705C8A —Rev. 3
22 Gen eral D es cri ptio n
General Description
1.2 Introduction
The MC68HC705C8A, an enhanced version of the MC68HC705C8, is a
member of the low-cost, high-performance M68HC05 Family of 8-bit
micr ocontroller units (MCU). The MC68HSC705C8A, introduced in
Appendix A. MC68HSC705C8A, is an enhanced, high-speed version of
the MC68HC705C8A. The M68HC05 Family is based on the
customer-speci fied integrated circuit (CS IC) design strategy. All MCUs
in the family use the M68HC05 central processor unit (CPU) and are
available with a variety of subsystems, memory sizes and types, and
package types.
1.3 Features
Features of the MC68HC705C8A include:
•M68HC05 central processor unit (CPU)
•On-chip oscillator with crystal/ceramic resonator
•Memory-mapped input/output (I/O)
•Selectable memory configurations
•Selectable programmable and/or non-programmable computer
operating properly (COP) watchdog timers
•Selectable port B external interrupt capability
•Clock monitor
•High current drive on pin C7 (PC7)
•24 bidirectional I/O lines and 7 input-only lines
•Serial communications interface (SCI) system
•Seria l peripheral in terfa ce (SPI) syste m
•Bootstrap capability
•Power-saving stop, wait, and data-retention modes
•Single 3.0-volt to 5.5-volt supply (2-volt data-retention mode)
•Fully static operation
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General Descripti on
Programmable Options
MC68HC705C8A —Rev. 3 T echnical Data
MOTOROLA General Description
•Software-programmable external interrupt sensitivity
•Bidirectional RESET pin
NOTE: A line over a signal name indicates an active low signal. For example,
RESET is active high and RESET is active low. Any reference to voltage,
curren t, or fr eque ncy sp ecified in th is docu ment will re fer to the nomin al
values. The exact values and their tolerance or limits are specified in
Section 13. Electrical Specifications.
1.4 Programmable Options
These options are programmable in the mask option registers:
•Enabling of port B pullup devices (see 9.5.2 Mask Option
Register 1)
•Enabling of non-programmable COP watchdog (see 9.5.3 Mask
Option Register 2)
These option s are pro grammab le in the o ption register ( see Figure 1-1):
•One of four selectable memory configurations
•Programmable read-only memory (PROM) security1
•External interrupt sensitivity
1. No se c u rity fea t ur e is ab s o lu te ly sec u re . H o w ev e r , M ot o ro la’s strategy is to make reading or
copying the PROM difficult for unaut horized users.
Address: $1FDF
Bit 7654321Bit 0
Read: RAM0 RAM1 0 0 SEC*IRQ 0
Write:
Reset:0000*U10
*Implemented as an EPROM cell
= Unimplemented U = Unaffected
Figure 1-1. Option Register (Option)
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Technical Data MC68HC705C8A —Rev. 3
24 Gen eral D es cri ptio n
General Description
RAM0 — Random-Access Memory Control Bit 0
1 = Maps 32 bytes of RAM into page zero starting at address
$0030. Addresse s fr om $ 0020 to $002F a re reser ved. Thi s bit
can be read or written at any time, allowing memory
configuration to be changed during program execution.
0 = Provides 48 bytes of PROM at location $0020–$005F.
RAM1 — Random-Access Memory Control Bit 1
1 = Maps 96 bytes of RAM into page one starting at address $0100.
This bit can be read or written at any time, allowing memory
configuration to be changed during program execution.
0 = Provides 96 bytes of PROM at location $0100.
SEC — Security Bit
This bit is implemented as an erasable, programmable read-only
memory (EPROM) cell and is not affected by reset.
1 = Bootloader disabled; MCU operates only in single-chip mode
0 = Security off; bootloader can be enabled
IRQ — Interrupt Request Pin Sensitivit y Bit
IRQ is set only by reset, but can be cleared by software. This bit can
be wr itten only once.
1 = I RQ pin is both negative edge- and level-sensitive.
0 = I RQ pin is negative edge-sensitive only.
Bits 5, 4, and 0 — Not used; always read 0
Bit 2 — Unaffected by reset; reads either 1 or 0
1.5 Block Diagram
Figure 1-2 shows the structure of the MC68HC705C8A.
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General Descripti on
Block Diagram
MC68HC705C8A —Rev. 3 T echnical Data
MOTOROLA General Description
Figure 1-2. MC68HC705C8A Block Diagram
INTERNAL
PROCESSOR
CLOCK
TCAP
÷ 2
ACCUMULATOR
INDEX REGISTER
OSC1
OSC2 OSCILLATOR
IRQ
RESET
COP WATCH DO G
CPU
M68HC 05 CPU
ARITHMETIC
VDD
VSS
CPU RE GIS TERS
CONTROL
PORT A
DATA DIR ECTION A
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
POWER
OPTION
EPROM/OTPROM — 7744 BYTES
1100000
CZNIH111
16-BIT
CAPTURE/COMPARE
PORT B
DATA DIRECTION B
PB0*
PB1*
PB2*
PB3*
PB4*
PB5*
PB6*
PB7*
PORT C
DATA DIR ECTION C
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7†
TIMER SYST EM
BA UD RA TE
GENERATOR
PD7
RDI (PD0)
TDO (PD 1 )
MIS O (PD2)
MO S I (PD 3 )
SCK (PD4)
SS (PD5)
SCI
SPI
TCMP
RAM — 176 BYT ES
REGISTER
BOOT ROM — 240 BYTES
(144 BYTES CONFIGURABLE)
PROG RAM R EGISTER
EPR OM P R OGR AMMING
VPP
AND
CLOCK MONITOR
PORT D
LOGIC UNIT
(304 BYTES MAXIMUM)
CONTROL
PROGRAM COUNTER
STACK POINTER
CONDI TIO N CO DE REG IS T ER
* Port B pins al so function as external interrupts.
† PC7 has a high current sink and sour ce capability.
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Technical Data MC68HC705C8A —Rev. 3
26 Gen eral D es cri ptio n
General Description
1.6 Pin Assignments
The MC68HC705C8A is available in six packages:
•40-pin plastic dual in-line package (PDIP)
•40-pin ceramic dual in-line package (cerdip)
•44-lead plastic-leaded chip carrier (PLCC)
•44-lead ceramic-leaded chip carrier (CLCC)
•44-pin quad flat pack (QFP)
•42-pin shrink dual in-line package (SDIP)
The pin assignments for these packages are shown in Figure 1-3,
Figure 1-4, Figure 1-5, and Figure 1-6.
Figure 1-3. 40-Pin PDIP/Cerdip Pin Assignments
1
2
3
4
5
6
7
8
9
10
11
12
13
14 27
28
29
30
31
32
33
34
35
36
37
38
39
40 VDD
OSC1
OSC2
TCAP
PD7
TCMP
PD5/SS
PD4/SCK
PD3/MOSI
PD2/MISO
PD1/TDO
PD0/RDI
PC0
PC1
RESET
IRQ
VPP
PA7
PA5
PA4
PA3
PA2
PA1
PA0
PB0
PB1
PB2
PA6
15
16
17
18
19
20
PB4
PB5
PB6
PB7
VSS
PB3
21
22
23
24
25
26 PC2
PC3
PC4
PC5
PC6
PC7
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General Descripti on
Pin Assignments
MC68HC705C8A —Rev. 3 T echnical Data
MOTOROLA General Description
Figure 1-4. 44-Lead PLCC/CLCC Pin Assignments
Figure 1-5. 44-Pin QFP Pin Assignments
PA6
PA7
V
PP
NC
IRQ
RESET
V
DD
OSC1
OSC2
TCAP
NC
6
5
4
3
2
1
44
43
42
41
40
39
38
37
PD7
TCMP
PD5/SS
36
35 PD4/SCK
PD3/MOSI
34 PD2/MISO
33 PD1/TDO
32 PD0/RDI
31 PC0
30 PC1
29 PC2
28
27
26
25
24
23
22
21
20
19
18
NC
PB5
PB6
PB7
V
SS
NC
PC7
PC6
PC5
PC4
PC3
PB4
PB3
PB2
PB1
17
16
15
14
PB0
PA0
PA1
PA2
13
12
11
10
PA3 9
PA4 8
PA5 7
PD7
TCAP
OSC2
OSC1
VDD
NC
NC
RESET
IRQ
VPP
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
PB0
PB1
PB2
PB3
PD3/MOSI
PD2/MISO
PD4/SCK
PD5/SS
TCMP
PD1/TDO
PD0/RDI
PC0
PC1
PC2
PC3
NC
PC4
PC5
PC6
PC7
VSS
NC
PB7
PB6
PB5
PB4
1234567891011
12
13
14
15
16
17
18
19
20
21
22
2324252627282930313233
34
35
36
37
38
39
40
41
42
43 44
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Technical Data MC68HC705C8A —Rev. 3
28 Gen eral D es cri ptio n
General Description
Figure 1-6. 42-Pin SDIP Pin Assignments
VPP
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
PB0
PB1
PB2
PB3
NC
PB4
PB5
PB6
VSS
VDD
OSC1
OSC2
TCAP
PD7
TCMP
PD5/SS
PD4/SCK
PD3/MOSI
PD2/MISO
PD1/TDO
PD0/RDI
PC0
PC1
PC2
NC
PC3
PC4
PC5
PC6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22 PC7
PB7
21
RESET
IRQ
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General Descripti on
Pin Funct ions
MC68HC705C8A —Rev. 3 T echnical Data
MOTOROLA General Description
1.7 Pin Fu nctions
This subsection describes the MC68HC705C8A signals. Reference is
made, where applicable, to other sections that contain more detail about
the function being performed.
1.7.1 VDD and VSS
VDD a nd VSS are the power supply and g round pins. The MCU opera tes
from a single power supply.
Very fast signal transitions occur
on the MCU pins, placing high
short-duration current demands
on the power supply. To prevent
noise pro blems, take spe cia l care
to provide good power supply
bypassing at the MCU. Place
bypass capacito rs as close to the
MCU as possible, as shown in
Figure 1-7.
1.7.2 VPP
This pin provides the programming voltage to the EPROM array. For
normal operation, VPP shuld be tied to VDD.
NOTE: C on necting the VPP pin (programming voltage) to VSS (ground) could
result in damage to the MCU.
MCU C2
VDD
VSS
V+
+
C1
Figure 1-7. Bypassing Layout
Recommendation
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Technical Data MC68HC705C8A —Rev. 3
30 Gen eral D es cri ptio n
General Description
1.7.3 OSC1 and OSC2
The OSC1 and OSC2 pins are the control connections for the 2-pin
on-chi p oscillator. The osci llator can be driven by:
•Crystal resonator
•Ceramic resonato r
•External clock signal
NOTE: The frequency of the internal oscillator is fOSC. The MCU divides the
internal oscillator output by two to produce the internal clock with a
frequency of fOP.
1.7.3.1 Cr ystal Resonator
The circuit in Figure 1-8 shows a
crystal oscillator circuit for an AT-cut,
parallel resonant crystal. Follow the
crystal supplier’s recommendations,
because the crystal parameters
determine the external component
values required to provide reliable
startup and maximum stability. The
load capaci tance values used in the
oscillator circuit design should
account for all stray layout
capaci tance s. To minimize outpu t
distor tion, mount the crystal and
capacitors as close as possible to the
pins.
NOTE: Use an AT-cut crystal and not a strip or tuning fork crystal. The MCU
might overdrive or have the incorrect characteristic impedance for a strip
or tuning fork crystal.
MCU
OSC1 OSC2
XTAL
22 pF∗22 pF∗
10 MΩ∗
2 MHz
Figure 1-8. Crystal
Connections
∗Starting value only. Follow crystal supplier’s
recommendations regarding component
val ues th at w ill prov ide rel iable sta rt u p and
maximum stability.
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General Descripti on
Pin Funct ions
MC68HC705C8A —Rev. 3 T echnical Data
MOTOROLA General Description
1.7.3.2 Ceramic Resonator
To reduce cost, use a ceramic
resonat or ins tead of a crystal. Use the
circuit shown in Figure 1-9 for a 2-pin
ceramic r esonator or t he circuit show n
in Figure 1-10 for a 3-pin ceramic
resonator, and follow the resonator
manufacturer’s recommendations.
The external component values
required for maximum stability and
reliable starting depend upon the
resonator parameters. The load
capacitance values used in the oscillator circuit design should include all
stray layout capacitan ces. To minimize output distortion, mount the
resonator and capacitors as close as possible to the pins.
NOTE: The bus frequency (fOP) is one-half the external or crystal frequency
(fOSC), while the processor clock cycle (tCYC) is two times the fOSC
period.
MCU
OSC1 OSC2
CERAMIC
CC
R
RESONATOR
Fi gure 1-9. 2-P in Ce rami c
Resonator Connections
.
MCU
OSC1 OSC2
CERAMIC
RESONATOR
Figure 1-10. 3-Pin
Ceramic Resonator
Connections
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Technical Data MC68HC705C8A —Rev. 3
32 Gen eral D es cri ptio n
General Description
1.7.3.3 External Clock Signal
An external clock from another
CMOS-compatible device can drive the
OSC1 input, with the OSC2 pin
unconnected, as Figure 1-11 shows.
NOTE: The bus frequency (fOP) is one-half the external frequency (fOSC) while
the processor clock cycle is two times the fOSC period.
1.7.4 External Reset Pin (RESET)
A logic 0 on the bidirectional RESET pin forces the MCU to a known
startup state. The RESET pin contains an internal Schmitt trigge r as part
of its input to improve noise immunity. See Sect ion 5. Resets.
1.7.5 External Interrupt Request Pin (IRQ)
The IRQ pin is an asynchronous external interrupt pin. The IRQ pin
contains an internal Schmitt tr igger as part of its input to improve noise
immunity. See 4.3.2 External Interrupt (IRQ).
1.7.6 Input Capture Pin (TCAP)
The TCAP pin is the input capture pin for the on-chip capture/compare
timer. The TCAP pin contains an internal Schmitt trigger as part of its
input to improve noise immunity. See Secti on 8. Captur e/C omp ar e
Timer.
MCU
OSC1
OSC2
EXTERNAL
CMOS CLOCK
Figure 1-11. External
Clock
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General Descripti on
Pin Funct ions
MC68HC705C8A —Rev. 3 T echnical Data
MOTOROLA General Description
1.7.7 Output Compare Pin (TCMP)
The TCMP pin is the output compare pin for the on-chip
capt ure/co mpar e timer. See Section 8. Capture/Compar e Timer.
1.7.8 Port A I/O Pins (PA7–PA0)
These eight I/O lines comprise port A, a general-purpose, bidirectional
I/O port. The pins are programmable as either inputs or outputs under
software control of the data direction registers. See 7.3 Port A.
1.7.9 Port B I/O Pins (PB7–PB0)
These eight I/O pins comprise port B, a general-purpose, bidirectional
I/O port. The pins are programmable as either inputs or outputs under
software control of the data direction registers. Port B pins also can be
configured to function as external interrupts. See 7.4 Po rt B.
1.7.10 Port C I/O Pins (PC7–PC0)
These eight I/O pins comprise port C, a general-purpose, bidirectional
I/O port. The pins are programmable as either inputs or outputs under
software control of the data direction registers. PC7 has a high current
sink and source capability. See 7.5 Port C.
1.7.11 Port D I/O Pins (PD7 and PD5–PD0)
These seven lines comprise port D, a fixed input port. All special
functi ons that a re enabled (SPI and SCI) affe ct this port. See 7.6 Port D.
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Technical Data MC68HC705C8A —Rev. 3
34 Gen eral D es cri ptio n
General Description
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MC68HC705C8A —Rev. 3 Tec hnical Data
MOTOROLA Memory
Technical Data — MC68HC705C8 A
Section 2. Memory
2.1 Contents
2.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
2.3 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
2.4 Input/Output (I/O) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
2.5 RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
2.6 EPROM/OTPROM (PROM) . . . . . . . . . . . . . . . . . . . . . . . . . . .37
2.7 Bootloader ROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
2.2 Introduction
This section describes the organization of the on-chip memory.
2.3 Memory Map
The central processor unit (CPU) can address eight Kbytes of memory
and input/output (I/O) registers. The program counter typically advances
one address at a time through memory, reading the program instructions
and data. The programmable read-only memory (PROM) portion of
memory —either one-time programmable read-only memory
(OTPROM) or erasable, programmable read-only memory
(EPROM) —holds the program instructions, fixed data, user-defined
vectors, and interrupt service routines. The random-access memory
(RAM) portion of memory hold s variable data.
I/O register s are memory-mapped so that the CPU can access their
locations in the same way that it accesses all other memory locations.
The shared stack area is used during processing of an interrupt or
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Technical Data MC68HC705C8A —Rev. 3
36 Memory
Memory
subrouti ne call to save the CPU state. The stack pointer decrements
during pushes and increments during pulls.
Figure 2-1 is a memory map of the MCU. Addresses $0000–$001F,
shown in Figure 2-2, contain most of the control, status, and data
registers. Additional I/O registers have these addresses:
•$1FDF, option register
•$1FF0, mask option register 1 (MOR1)
•$1FF1, mask option register 2 (MOR2)
2.4 Input/Output (I/O)
The first 32 addr esses of memo ry space, from $0000 to $001 F, are the
I/O section. Th ese are the addr esses of the I/O contro l register s, status
registers, and data registers. See Figure 2-2 for more inform ation.
2.5 RAM
One of f our selectable mem ory configur ations is selected by the state of
the R AM 1 and RAM0 bits i n the option register locate d at $1FDF . Reset
or power-on reset (POR) clears these bits, automatically selecting the
first memory configuration as shown in Table 2-1. See 9.5.1 Option
Register.
NOTE: Be care ful when using n ested subroutines or multiple interrupt levels.
The CPU can overwrite data in the stack RAM during a subroutine or
during the interrupt stacking operation.
Table 2-1. Memory Configurations
RAM0 RAM1 RAM Bytes PROM Bytes
0 0 176 7744
1 0 208 7696
0 1 272 7648
1 1 304 7600
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Memory
EPROM/OTPROM (PROM)
MC68HC705C8A —Rev. 3 T echnical Data
MOTOROLA Memory
2.6 EPROM/OTPROM (PROM)
An MCU with a quartz window has a maximum of 7744 bytes of EPROM.
The quartz window allows the EPROM erasure with ultraviolet light. In
an MCU without a quartz window, the EPROM cannot be erased and
serves a maximum 7744 bytes of OTPROM (see Table 2-1). See
Sectio n 9. EPROM/OTP ROM (PROM).
2.7 Bootloader ROM
The 240 bytes at addresses $1F00–$1FEF are reserved ROM
addresse s that contain the instructions for the bootloader functions. See
Sectio n 9. EPROM/OTP ROM (PROM).
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Technical Data MC68HC705C8A —Rev. 3
38 Memory
Memory
Figure 2-1. Memory Map
$0000 I /O R EGI ST ER S
32 BYTES
PORT A DATA REGIST ER $0000
PORT B DATA REGIST ER $0001
$001F PORT C DATA R EGI ST ER $0002
$0020 UNUSED
16 BYTES USER PROM
48 BYTE S
PORT D F IXE D INPUT P O RT $0003
PORT A DATA DIRECTION REGISTER $0004
$002F PORT B DATA DIRE CTI ON REGIST ER $00 05
$0030 RAM
32 BYTES
PORT C DATA DIRECTION REGISTER $0006
UNUSED $0007
UNUSED $0008
$004F RAM0 = 1 (1) RAM 0 = 0(1) UNUSED $0009
$0050 SPI CONTROL REGISTER $000A
SPI STATUS REGISTER $000B
$00BF SPI DATA REGISTER $000C
$00C0 STACK
64 BYTE S
SCI BAUD RATE REGISTER $000D
SCI CONTROL REGISTER 1 $000E
$00FF SCI CONTROL REGISTER 2 $000F
$0100
USER PROM
96 BYTES RAM
96 BYTE S
SCI STAT US REGISTER $0010
SCI DATA REGISTER $0011
TIME R CO NTROL REGIS TE R $ 0 012
TIMER STATUS REGISTER $0013
INPUT CAPTURE REGISTER (HIGH) $0014
INPUT CAPTURE REGISTER (LOW) $0015
OUTPUT CO MPARE REGISTER (HI GH ) $0016
OUTPUT CO MPARE REGISTER (LOW ) $0017
$015F RAM1 = 0 (1) RAM 1 = 1(1) TIME R REGISTER (HIGH) $00 18
$0160 U SER PR OM
7584 BYTES
TIMER REGISTER (LOW) $0019
ALTE RNATE T IME R RE G IS TE R ( HIG H) $0 01A
$1EF F ALTE RNATE T IME R RE G IS TE R ( LOW) $001B
$1F00 B OOTLOADER RO M
240 BYT ES
EPROM PROGRAM REGISTER $001C
COP RESET REGISTER $00 1D
$1FDE COP CONTROL REGISTER $001E
$1FDF OPTIO N REGI ST ER UNUSED $001F
$1FE0
$1FEF
BOOT ROM VECT OR S
16 BYTES
$1FF0 MASK OPTION REGISTER 1 RESERVED $1FF2
RESERVED $1FF3
$1FF1 MASK OPTION REGISTER 2 SPI INTE RRUPT VEC TO R ( HIG H) $1 FF4
SPI INTE RRUPT VEC TO R ( LOW) $1 FF5
$1FF2 US ER PROM VEC TORS
12 BYTES
S CI IN TERRU P T V E CTOR (HIG H) $1FF 6
SCI INTERRUPT VECTOR (LOW) $1FF7
$1FFF TIMER INTERRUPT VECTOR (HIGH) $1FF8
TIMER INTE RRUPT VECTOR (LOW) $1FF9
EXTE RNA L I NTE RRU P T VE C TO R ( HIG H) $1 FFA
(1) See 9.5.1 Option Regis ter for information. EXTE RNA L IN TE RRU P T VE CT O R ( LOW) $1 FFB
SOFTWARE INTERRUPT VE CTOR (HIGH) $1FFC
SOFTWARE INTE RRUPT VEC TO R ( L OW ) $1FFD
RE SE T V E CTOR (HIGH) $1FFE
RESET VECTOR (LOW) $1FFF
RAM
176 BYTES
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Memory
Bootloader ROM
MC68HC705C8A —Rev. 3 T echnical Data
MOTOROLA Memory
Addr. Regist e r Na me Bi t 7 6 5 4 3 2 1 Bit 0
$0000 Port A Data Register
(PORTA)
See page 78 .
Read: PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0
Write:
Reset: Unaff ected by reset
$0001 Port B Data Register
(PORTB)
See page 81 .
Read: PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0
Write:
Reset: Unaff ected by reset
$0002 Po rt C Dat a Re g i s ter
(PORTC)
See page 85 .
Read: PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
Write:
Reset: Unaff ected by reset
$0003 Por t D Fixed Input Register
(PORTD)
See page 88 .
Read: PD7 SS SCK MOSI MISO TDO RDI
Write:
Reset: Unaff ected by reset
$0004 Po rt A Da ta Direct io n
Register (DDRA)
See page 79 .
Read: DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0
Write:
Reset: 0 0 0 0 0 0 0 0
$0005 Po rt B Da ta Direct io n
Register (DDRB)
See page 82 .
Read: DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0
Write:
Reset: 0 0 0 0 0 0 0 0
$0006 Po rt C Data Dire ction
(DDRC)
See page 86 .
Read: DDRC7 DDRC6 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0
Write:
Reset: 0 0 0 0 0 0 0 0
$0007 Unimplemented
$0008 Unimplemented
$0009 Unimplemented
= Unimplemented U = Unaffected
Figure 2-2. I/O Register Summary (Sheet 1 of 4)
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Technical Data MC68HC705C8A —Rev. 3
40 Memory
Memory
$000A SPI Control Register
(SPCR)
See page 149 .
Read: SPIE SPE MSTR CPOL CPHA SPR1 SPR0
Write:
Reset: 0 0 0 U U U U
$000B SPI Status Regist er
(SPSR)
See page 151 .
Read: SPIF WCOL MODF
Write:
Reset: 0 0 0
$000C S PI Da ta Regi s te r
(SPDR)
See page 149 .
Read: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 BIt 2 Bit 1 Bit 0
Write:
Reset: Unaff ected by reset
$000D Baud Rate Register
(Baud)
See page 136 .
Read: SCP1 SCP0 SCR2 SCR1 SCR0
Write:
Reset: U U 0 0 U U U U
$000E SCI C ontrol Register 1
(SCCR1)
See page 130 .
Read: R8 T8 M WAKE
Write:
Reset: U U U U
$000F SCI C ontrol Register 2
(SCCR2)
See page 131 .
Read: TIE TCIE RIE ILIE TE RE RWU SBK
Write:
Reset: 0 0 0 0 0 0 0 0
$0010 SCI Status Register
(SCSR)
See page 133 .
Read: TDRE TC RDRF IDLE OR NF FE
Write:
Reset: 1 1 0 0 0 0 0 U
$0011 SCI Dat a Re g ister
(SCDR)
See page 129 .
Read: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Write:
Reset: Unaff ected by reset
$0012 Timer Control Register
(TCR)
See page 94 .
Read: ICIE OCIE TOIE 0 0 0 IEDG OLVL
Write:
Reset: 0 0 0 0 0 0 U 0
Addr. Regist e r Na me Bi t 7 6 5 4 3 2 1 Bit 0
= Unimplemented U = Unaffected
Figure 2-2. I/O Register Summary (Sheet 2 of 4)
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Memory
Bootloader ROM
MC68HC705C8A —Rev. 3 T echnical Data
MOTOROLA Memory
$0013 Tim er Status Regi ster
(TSR)
See page 96 .
Read: ICF OCF TOF 0 0 0 0 0
Write:
Reset: U U U 0 0 0 0 0
$0014 Input Capture Regist er
High (ICRH)
See page 100 .
Read: Bit 15 Bit 14 Bit 13 Bi t 12 Bit 11 Bit 10 Bit 9 Bit 8
Write:
Reset: Unaff ected by reset
$0015 Input C apture Regi ster
Low (ICRL)
See page 100 .
Read: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Write:
Reset: Unaff ected by reset
$0016
Output Compare R egister
High (OCRH)
See page 101 .
Read: Bi t 1 5 B i t 1 4 Bit 13 Bi t 1 2 Bi t 11 Bi t 1 0 Bit 9 Bit 8
Write:
Reset: Unaffected by reset
$0017 Output Compare Register
Low (OCRL)
See page 101 .
Read: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Write:
Reset: Unaffected by reset
$0018 Timer Regi ster High
(TRH)
See page 97 .
Read: Bit 15 Bit 14 Bit 13 Bi t 12 Bit 11 Bit 10 Bit 9 Bit 8
Write:
Reset: Reset initi alizes TRH to $FF
$0019 Tim er Register Low
(TRL)
See page 97 .
Read: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Write:
Reset: R eset initiali zes TRL to $FC
$001A Alternate Timer Register
High (ATRH)
See page 99 .
Read: Bit 15 Bit 14 Bit 13 Bi t 12 Bit 11 Bit 10 Bit 9 Bit 8
Write:
Reset: Reset initi alizes ATRH t o $FF
$001B Alternate Timer Register
Low (ATRL)
See page 99 .
Read: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Write:
Reset: Reset initializes ATRL to $FC
Addr. Regist e r Na me Bi t 7 6 5 4 3 2 1 Bit 0
= Unimplemented U = Unaffected
Figure 2-2. I/O Register Summary (Sheet 3 of 4)
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Technical Data MC68HC705C8A —Rev. 3
42 Memory
Memory
$001C EPROM Programming
Register (PRO G )
See page 109 .
Read: 00 0 0 0LAT0PGM
Write:
Reset: 0 0 0 0 0 0 0 0
$001D Programmable COP R eset
Register (C O PRST)
See page 64 .
Read:
Write: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset: U U U U U U U U
$001E Programmable COP Contr ol
Register (COPCR)
See page 64 .
Read: 0 0 0 COPF CME PCOPE CM1 CM0
Write:
Reset: 0 0 0 U 0 0 0 0
$001F Unimplemented
$1FDF Option Register
(Option)
See page 116 .
Read: RAM0 RAM1 0 0 SEC*IRQ 0
Write:
Reset: 0 0 0 0 *U10
*Implemented as an EP ROM cell
$1FF0 Mask Option Register 1
(MOR1)
See page 117 .
Read: PBPU7 PBPU6 PBPU5 PBPU4 PBPU3 PBPU2 PBPU1 PBPU0/
COPC
Write:
Reset: Unaffected by reset
$1FF1 Mask Option Register 2
(MOR2)
See page 118 .
Read: NCOPE
Write:
Reset: Unaffected by reset
Addr. Regist e r Na me Bi t 7 6 5 4 3 2 1 Bit 0
= Unimplemented U = Unaffected
Figure 2-2. I/O Register Summary (Sheet 4 of 4)
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MC68HC705C8A —Rev. 3 Tec hnical Data
MOTOROLA Central Processor Unit (CPU)
Technical Data — MC68HC705C8 A
Section 3. Central Processor Unit (CPU)
3.1 Contents
3.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
3.3 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
3.3.1 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
3.3.2 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
3.3.3 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
3.3.4 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
3.3.5 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . .47
3.4 Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . .48
3.2 Introduction
This section describes the central processor unit (CPU) registers.
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Technical Data MC68HC705C8A —Rev. 3
44 Central Processor Unit (CPU)
Ce ntral Processor Unit (CPU)
3.3 CPU Registers
Figure 3-1 shows the five CPU registers. These are hard-wired registers
within the CPU and are not part of the memory map.
Figure 3-1. Programming Model
ACCUMUL ATO R (A)
INDEX REGISTER (X)
110000 0
ZCIN1H11
Bit 04Bit 7 5
CONDITION CODE REG ISTER (CCR)
PR O G RAM COUN TER (PC)
STACK POI NTER (SP)
HALF-CARRY FLAG
INTER RUP T MA S K
NEGA TIVE FLAG
ZERO FL A G
CA RRY /B O RRO W FL A G
6 321
Bit 04756 321
Bit 04756 321
Bit 04Bit 7 56 321
Bit 04Bit 7 56 321
8Bit 12 11 10 9
8Bit 12 11 10 9
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Central Processor Unit (CP U)
C PU Registers
MC68HC705C8A —Rev. 3 T echnical Data
MOTOROLA Central Processor Unit (CPU)
3.3.1 Accumulator
The accumulator (A ) shown in Figure 3-2 is a general-purpose 8-bit
regi ster. The CP U uses th e accumul ator to hold op erands an d results o f
arithmetic and non-arithmetic operations.
Figure 3-2. Accumulator (A)
3.3.2 Index Register
In the indexed addressing modes, the CPU uses the byte in the in dex
regi ster (X) sh own in Figure 3-3 to de termine th e condit ional address of
the operand. See 12.3.5 Indexed, No Offset, 12.3.6 Indexed, 8-Bit
Offset, and 12.3.7 Indexed, 16-Bit Offset for more information on
indexed addressing .
The 8-bit index regi ster also can serve as a temporary data storage
location.
Figure 3-3. Index Register (X)
Bit 7654321Bit 0
Read:
Write:
Reset: Unaffected by reset
Bit 7654321Bit 0
Read:
Write:
Reset: Unaffected by reset
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Technical Data MC68HC705C8A —Rev. 3
46 Central Processor Unit (CPU)
Ce ntral Processor Unit (CPU)
3.3.3 Stack Pointer
The stack pointer (SP) shown in Figure 3-4 is a 13-bit register that
contains the address of the next free location on the stack. During a reset
or after the reset stack pointer (RSP) instruction, the stack pointer
initializes to $00FF. The address in the stack pointer decrements as data
is pushed onto the stack and increments as data is pulled from the stack.
The seven most significant bits of the stack pointer are fixed
perma nently at 00 00011, so the stack point er produces ad dresses from
$00C0 to $00FF. If subroutines and interrupts use more than 64 stack
loca tions, th e stack p ointer wraps arou nd to a ddre ss $00F F and be gi ns
writing over the previously stored data. A subroutine uses two stack
locations. An interrupt uses five locations.
Figure 3-4. Stack Pointer (SP)
3.3.4 Program Counter
The program counter (PC) shown in Figure 3-5 is a 13-bit register that
contains the address of the next instruction or operand to be fetched.
Normal ly, the ad dress in the pr ogra m counte r auto maticall y incre ments
to the next sequential memory location every time an instruction or
operand is fetched. Jump, branch, and interrupt operations load the
program counter with an address other than that of the next sequential
location.
Bit 121110987654321Bit 0
Read: 0 000011
Write:
Reset:0 000011111111
= Unimplemented
Bit 121110987654321Bit 0
Read:
Write:
Reset: Loaded with reset vector f rom $1FFE and $1FFF
Figure 3-5. Program Co unter (PC)
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Central Processor Unit (CP U)
C PU Registers
MC68HC705C8A —Rev. 3 T echnical Data
MOTOROLA Central Processor Unit (CPU)
3.3.5 Condition Code Register
The condition code register (CCR) shown in Figure 3-6 is an 8-bit
register whose three most significant bits are permanently fixed at 111.
The condition code register contains the interrupt mask and four bits that
indicate the results of prior instructions.
H — Half-Carry Bit
The CPU sets the half-carry flag when a carr y occurs betwee n bi ts 3
and 4 of the accumulator during an add without carry (ADD) or add
with carry (ADC) operation. The half-carry bit is required for
binary-coded decimal (BCD) arithmetic operations. Reset has no
affect on the half-carry flag.
I — Interrupt Mask Bit
Setting the interrupt mask (I) disables interrupts. If an interrupt
request occurs while the interrupt mask is a logic 0, the CPU saves
the CPU registers on the stack, sets the interrupt mask, and then
fetches the interrupt vector. If an interrupt request occurs while the
interrupt mask is set, the interrupt request is latched. The CPU
processes the latched in terrupt as soon as the in terrupt mask is
cleared again.
A return-from-interrupt (RTI) instruction pulls the CPU registers from
the stack, restoring the interrupt mask to its cleared state. After a
reset, the interrupt mask is set and can be cleared only by a CLI,
STOP, or WAIT instruction.
Bit 7654321Bit 0
Read: 1 1 1 HINZC
Write:
Reset:111U1UUU
= Unimplemented U = Unaff ected
Figure 3-6. Condition Code Register (CCR)
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Technical Data MC68HC705C8A —Rev. 3
48 Central Processor Unit (CPU)
Ce ntral Processor Unit (CPU)
N — Negative Flag
The C PU sets t he negative flag when an ar i thmet ic operation , log ical
operation, or data manipulation produces a negative result (bit 7 in the
results is a logic 1). Reset has no effect on the negative flag.
Z — Zero Flag
The CPU sets the zero flag when an arithmetic operation, logical
operation, or data manipulation produces a result of $00. Reset has
no effect on the zero flag.
C — Carry/Borrow Flag
The CPU sets the carry/borrow flag when an addition operati on
produces a carry out of bit 7 of the accumulator or when a subtraction
operation requires a borrow. Some logical operations and data
mani pulation instructi ons also clear or set the car ry/borro w bit. Reset
has no effect on the carry/borrow flag.
3.4 Arithmetic/Logic Unit (ALU)
The arithmetic/logic unit (ALU) performs the arithmetic and logical
operations defined by the instruction set. The binary arithmetic circuits
decode i nstructio ns and set u p the ALU for the sele cted opera tion. Most
binary arithmetic is based on the addition algorithm, carrying out
subtraction as negative addition. Multiplication is not performed as a
discrete operation but as a chain of addition and shift operations within
the ALU. The m u ltiply instruction requires 11 internal clock cycles to
complete thi s chain of ope ration s.
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MC68HC705C8A —Rev. 3 Tec hnical Data
MOTOROLA Interrupts
Technical Data — MC68HC705C8 A
Section 4. Interr upts
4.1 Contents
4.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
4.3 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 0
4.3.1 Software Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
4.3.2 External Interrupt (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
4.3.3 Port B Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
4.3.4 Capture/Compare Timer Interrupts . . . . . . . . . . . . . . . . . . .55
4.3.5 SCI Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
4.3.6 SPI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
4.4 Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 7
4.2 Introduction
This section describes how interrupts temporarily change the normal
processing sequence.
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Technical Data MC68HC705C8A —Rev. 3
50 Interrupts
Interrupts
4.3 Interrupt Sources
These sources can generate interrupts:
•Software instructions (SWI)
•External interrupt pin (IRQ)
•Port B pins
•Serial communications interface (SCI):
–SCI transmit data register empty
–SCI transmission complete
–SCI receive data register full
–SCI receiver overrun
–SCI receiver input idle
•Serial peripheral interfa c e (SPI):
–SPI transm ission complete
–SPI mode fault
–SPI overrun
The IRQ pin, port B pins, SCI, and SPI can be masked (disabled) by
setting the I b it of the condition code reg ister (CCR). The software
interrupt (SWI) instruction is non-maskable.
An interrupt temporarily changes the program sequence to process a
particular event. An interrupt does not stop the execution of the
instruction in progress but takes effect when the current in struction
completes its execution. Interrupt processing automatically saves the
central processor unit (CPU) registers on the stack and loads the
program counter with a user-defined vector address.
4.3.1 Software Interrupt
The software interrupt instruction (SWI) causes a non-maskable
interrupt.
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Interrupts
Interrupt Sources
MC68HC705C8A —Rev. 3 T echnical Data
MOTOROLA Interrupts
4.3.2 External Interrupt (IRQ)
An interrupt signal on the IRQ pin latches an external interrupt request.
After completing the current instruction, the CPU tests these bits:
•IRQ latch
•I bit in the CC R
Setting the I bit in the CCR d isa bles external interrupts.
If the IRQ latch is set and the I bit is clear, the CPU then begins the
interrupt sequence. The CPU clears the IRQ latch while it fetches the
interrupt vector, so that another external interrupt request can be latched
duri ng the in terrupt se rvice r outine. A s soon as t he I bit i s cleared durin g
the return-from-interrupt (RTI) instruction, the CPU can recognize the
new interr upt re quest. Figure 4-1 shows the logic for external interrupts.
Figure 4-1 shows an external interrupt functional diagram. Figure 4-2
shows an external interrupt timing diagram for the interrupt line. The
timing diagram illustrates two treatments of the interrupt line to the
processor.
1. Two single pulses on the interrupt line are spaced far enough
apart to be serviced. The minimum time between pulses is a
function of the length of the interrupt service.
Once a pulse occurs, the next pulse normally should not occur
until an RTI occurs. This time (tILIL) is obtained by adding 19
instruction cycles to the total number of cycles needed to complete
the service routine (not including the RTI instruction).
2. Many interrupt lines are “wire-ORed” to the IRQ line. If the interrupt
line remains low after servicing an interrupt, then the CPU
continues to recognize an interrupt.
NOTE: The internal interrupt latch is cleared in the first part of the interrupt
service routine. Therefore, a new external interrupt pulse could be
latched and serviced as soon as the I bit is cleared.
If the IRQ pin is not in use, connect it to the VDD pin.
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Technical Data MC68HC705C8A —Rev. 3
52 Interrupts
Interrupts
Figure 4-1. External Interrupt Internal Function Diagram
Figure 4-2. External Interrupt Timing
R
C
DQ
Q
VDD
EXTERNAL
INTERRUPT
REQUEST
I BIT (CCR)
INTERNAL RESET (COP)
EXTERNAL RESET
EXTERNAL INTERRUPT BEING SERVICED
(VE CTOR FETC H)
EDGE- AND LEV EL-SEN SITIVE TRIG GER
OPTION REGISTER
INTERRUPT PIN
IRQ LATCH
POR
NORMALLY
USED WITH
WIRED-OR
CONNECTION
IRQ
tILIH
tILIL
tILIH
IRQ PI N
IRQ1
IRQn
.
.
.
a. Edge-Sensitive Trigger Condition. The minimum pulse width (tILIH) is ei ther 125 ns (fOP = 2.1 MHz )
or 250 ns (f OP = 1 MHz). The per iod tILIL should not be less than the number of tCYC cycles it t akes to
execute the interrupt ser vice routine pl us 19 tCYC cycles .
b. Level-Sensitive Trigger Condition. If the interrupt line remai ns low after servicing an interrupt, then the
CPU continues t o recognize an interrupt.
(INT E RNA L )
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Interrupts
Interrupt Sources
MC68HC705C8A —Rev. 3 T echnical Data
MOTOROLA Interrupts
4.3.3 Port B Interrupts
When these three conditions are true, a port B pin (PBx) acts as an
external interrupt pin:
•The corresponding port B pullup bit (PBPUx) in mask option
register 1 (MOR1) is programmed to a logic 1.
•The corresponding port B data direction bit (DDRBx) in data
direction register B (DDRB) is a logic 0 .
•The clear interrupt mask (CLI) instruction has cleared the I bit in
the CCR.
MOR1 is an erasable, programmable read-only memory (EPROM)
register that enables the port B pullup device. Data from MOR1 is
latched on the rising edge of the voltage on the RESE T pin. See 9.5.2
Mask Option Register 1.
Port B external interrupt pins can be falling-edge sensitive only or both
falling-edge and low-level sensitive, depending on the state of the IRQ
bit in the option register at location $1FDF.
When the IRQ bit is a logic 1, a falling edge or a lo w level on a port B
external interrupt pin latches an external interrupt request. As long as
any port B external interrupt pin is low, an external interrupt request is
present , and the CPU conti nues to execute th e interru pt service r outine.
When the IRQ bit is a logic 0, a falling-edge only on a port B external
interrupt pin latches an external interrupt request. A subsequent port B
external interrupt request can be latched only after the voltage level of
the previ ous port B exte rnal inte rrupt signal return s t o a logic 1 and then
falls again to a logic 0.
Figure 4-3 shows the port B input/output (I/O) logic.
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Technical Data MC68HC705C8A —Rev. 3
54 Interrupts
Interrupts
Figure 4-3. Port B I/O Logic
PB7
EXTERNAL
INTERRUPT
REQUEST
DATA DIRECTION
REGISTER B
BIT DDRB 7
PORT B DATA
REGISTER
BIT PB7
READ $0005
WRITE $0001
READ $0001
RESET
INTERNAL DATA BUS
WRITE $0005
PBPU7
FROM OT HER
VDD
PORT B PINS
D
C
Q
RQ
I BIT
VDD
FRO M C CR
RESET
EXTERNA L IN TE RRU PT VECTO R FETCH
IRQ
IRQ
FROM OPTION
REGISTER
FROM MOR1
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Interrupts
Interrupt Sources
MC68HC705C8A —Rev. 3 T echnical Data
MOTOROLA Interrupts
4.3.4 Capture/Compare Timer Interr upts
Setting the I bit in the CCR d isa bles all interrupts except for SWI.
4.3.5 SCI Interrupts
The serial communicati ons interface (SCI) can generate these
interrupts:
•Transmit data register empty interrupt
•Transmission complete interrupt
•Receive data register full interrupt
•Receiver overrun interr upt
•Receiver input idle interrupt
Setting the I bit in the CCR d isa bles all SCI interrupts.
•SCI Transmit Data Register Empty Interrupt — The transmi t
data re gister empty bit (TDRE) indicates that the SCI data register
is ready to receive a byte for transmission. TDRE becomes set
when data in the SCI data register transfers to the transmit shift
register. TDRE generates an interrupt request if the transmit
interrupt enable bit (TIE) is set also.
•SCI Transmission Complete Interrupt — The transmission
complete bit (TC) indicates the completion of an SCI transmission.
TC becomes set when the TDRE bit becomes set and no data,
preamble, or break character is being transmitted. TC generates
an interrupt request if the transmission complete interrupt enable
bit (TCIE) is set also.
•SCI Receive Data Register Full Interrupt — The receive data
regi ster ful l bit (RD RF) indica tes that a byt e is ready to be read in
the SCI data register. RDRF becomes set when the data in the
receive shift register transfers to the SCI data register. RDRF
generates an interrupt request if the receive interrupt enable bit
(RIE) is set also.
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Technical Data MC68HC705C8A —Rev. 3
56 Interrupts
Interrupts
•SCI Receiver Overrun In terrupt — The overrun bit (OR)
indicates that a received byte is lost because software has not
read the previously received byte. OR becomes set when a byte
shifts into the receive shift register before software reads the word
already in the SCI data register. OR generates an interrupt
request if the receive interrupt enable bit (RIE) is set also.
•SCI Receiver Input Idle Interrupt — The receiver input idle bit
(IDL E) indicates that the SCI receiver input is not receiving data.
IDLE b ecome s set w he n 10 or 11 conse cutive l ogic 1s app ear on
the receiver input. IDLE generates an interrupt request if the idle
line interrupt enable bit (ILIE) is set also.
4.3.6 SPI Interrupts
The serial peripheral interrupt (SPI) can generate these interrupts:
•SPI transmission complete interrupt
•SPI mode fault interrupt
Setting the I bit in the CCR d isa bles all SPI interrupts.
•SPI Transmission Complete Interrupt — The SPI flag bit (SPIF)
in the SPI status register indicates the completion of an SPI
transmission. SPIF becom es set when a byte shifts into or out of
the SPI data register. SPIF generates an interrupt request if the
SPIE bit is set also.
•SPI Mode Fault Interrupt — The mode fault bit (MODF) in the SPI
status register indicates an SPI mode error. MODF becomes set
when a logic 0 occurs on the PD5/SS pin while the master bit
(MST R) in the SPI control register is set. MODF generates an
interrupt request if the SPIE bit is set also.
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Interrupts
Interrupt Processing
MC68HC705C8A —Rev. 3 T echnical Data
MOTOROLA Interrupts
4.4 Interrupt Processing
The CPU takes these actions to begin servicing an interrupt:
1. Stores the CPU registers on the stack in the order shown in
Figure 4-4
2. Sets the I bit in the CCR to preven t fu rther interrupts
3. Loads the program counter with the contents of the appropriate
interrupt vector locations as shown in Table 4-1.
The return-from-interrupt (RTI) instruction causes the CPU to recover
the CPU registers from the stack as shown in Figu re 4-4.
Table 4-1. Reset/Interrupt Vector Addresses
Function Source Local
Mask Global
Mask Priority
(1 = Highest) V ector Addres s
Reset Power-on
logic None None 1 $1FFE–$1FFF
RESET pin
Software
interrupt
(SWI) User code None None Same priority
as any
instruction $1FFC–$1FFD
External
interrupt IRQ pin N one I bit 2 $1FFA –$1FFB
Port B pi ns
Timer
interrupts
ICF bit ICIE bit
I bit 3 $1FF8–$1FF9OCF bit OCIE bit
TOF bit TOIE bit
SCI
interrupts
TDRE bit TCIE bit
I bit 4 $1FF6–$1FF7
TC bi t
RDRF bit RIE bit
OR bit
IDLE bit ILIE bit
SPI
interrupts SPIF bit SPIE I bit 5 $1FF4–$1FF5
MO D F b it
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Technical Data MC68HC705C8A —Rev. 3
58 Interrupts
Interrupts
Figure 4-4. Interrupt Stacking Order
NOTE: If more than one interrupt request is pending, the CPU fetches the vector
of the higher priority interrupt first. A higher priority interrupt does not
interrupt a lower priority interrupt service routine unless the lower priority
interrupt service routine clears the I bit. See Table 4-1 for a priority
listing.
Figure 4-5 shows the sequence of events caused by an interrupt.
CONDI TIO N CO DE REG IS TE R
$00C0 (BOTTOM OF STAC K)
$00C1
$00C2
•
•
•
ACCUMULATOR
INDEX REGISTER
PROGRAM COUNTER (HIGH BYTE)
PROG RA M COU NTER (LOW BYTE)
•
•
•
•
•
•
•
•
•
$00FD
$00FE
$00FF (TOP OF STAC K)
1
2
3
4
5
5
4
3
2
1
UNSTACKING
ORDER
STACKING
ORDER
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Interrupts
Interru pt Processing
MC68HC705C8A —Rev. 3 T echnical Data
MOTOROLA Interrupts
Figu re 4-5. Reset and Inter rupt Pr oce ssin g Flowc hart
EXTERNAL
I BIT IN
FROM
RESET
TIMER
INTERRUPT?
FETCH NEXT
INSTRUCTION
SWI
INSTRUCTION?
RTI
INSTRUCTION?
1. STACK PC, X, A, CCR
2. SET I BIT
3. LOAD PC WITH VECTOR
YES
YES
YES
YES
YES RESTORE REGISTERS FROM STACK:
EXECUTE INSTRUCTION
CLEAR
IRQ
REQUEST LATCH
NO
NO
NO
NO
NO
SCI
INTERRUPT?
YES
YES
NO
NO
CCR REGISTER
SPI
INTERRUPT?
SWI:
IRQ:
TIMER:
SCI:
SPI:
$1FFC–$1FFD
$1FFA–$1FFB
$1FF8–$1FF9
$1FF6–$1FF7
$1FF4–$1FF5
SET?
IRQ
INTERRUPT?
CCR, A, X, PC
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Technical Data MC68HC705C8A —Rev. 3
60 Interrupts
Interrupts
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MC68HC705C8A —Rev. 3 Tec hnical Data
MOTOROLA Resets
Technical Data — MC68HC705C8 A
Section 5. Resets
5.1 Contents
5.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
5.3 Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
5.3.1 Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
5.3.2 External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
5.3.3 Programmable and Non-Programmable
COP Watchdog Resets. . . . . . . . . . . . . . . . . . . . . . . . . .62
5.3.3.1 Programmable COP Watchdog Reset. . . . . . . . . . . . . . .63
5.3.3.2 Non-Programmable COP Wa tchdog . . . . . . . . . . . . . . . .66
5.3.4 Clock Monitor Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
5.2 Introduction
This section describes how re sets initialize the microcontroller unit
(MCU).
5.3 Reset Sources
A reset immediately stops the operation of the instruction being
executed, initializes certain control bits, and loads the program counter
with a user-defined reset vector address. These conditions produce a
reset:
•Power-on reset (POR) — Initial power-up
•External reset — A logic 0 applied to the RESET pin
•Internal programmable computer operating properly (COP)
watchdog timer reset
•Internal non-programmable COP watchdog timer reset
•Internal clock monitor reset
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62 Resets
Resets
5.3.1 Power-On Reset (POR)
A positive transition on the VDD pin generates a power-on reset (POR).
The POR is strictly for the power-up condition and cannot be used to
detect drops in power supply voltage.
A 4064 tCYC (internal clock cycle) delay after the oscillator become s
active allows the clock generator to stabilize. If the RESET pin is at
log ic 0 at the end of 4064 tCYC, the MCU remains in the reset condition
until the signal on the RESET pin goes to logic 1.
5.3.2 External Reset
The minimum time required for the MCU to recognize a reset is 1 1/2
tCYC. Howeve r, to guarante e that the MCU recognize s a n external reset
as an external reset and not as a COP or clock monitor reset, the RESET
pin must be low for eight tCYC. After six tCYC, the input on the RESET pin
is sampled. If the pin is still low, an external reset has occurred. If the
input is high, then the MCU assumes that the reset was initiated
internally by eith er the COP watch dog timer or by th e clock monitor. This
method of di fferenti at ing betwe en exte rnal a nd inter nal r eset con diti ons
assumes that the RESET pin will rise to a logic 1 less than two t CYC after
its rele ase and that an exter nally gener ated reset should stay active for
at least eight tCYC.
5.3.3 Programmable and Non-Programmable COP Watchdog Resets
A timeout of a COP watchdog generates a COP reset. A COP watchdog,
once enabled, is part of a software error detection system and must be
cleared periodically to start a new timeout period.
The MC68HC705C8A has two different COP watchdogs for compatibility
with devices such as the MC68HC705C8 and the MC68HC05C4A:
1. Programmable COP watchdog reset
2. Non-programmable COP watchdog
One COP has four programmable timeout periods and the other has a
fixed non-programmabl e timeout period.
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Resets
Reset Sou r ces
MC68HC705C8A —Rev. 3 T echnical Data
MOTOROLA Resets
5.3.3.1 Programmable COP Watchdog Reset
A timeout of the 18-stage ripple counter in the programmable COP
watchdog generates a reset. Figure 5-1 is a diagram of the
programmable COP watchdog. Two registers control and monitor
operation of the programmable COP watchdog:
•COP reset register (COPRST), $001D
•COP control register (COPCR), $001E
To clear the programmable COP watchdog and begin a new timeout
period, write these values to the COP reset register (COPRST).
See Figure 5-2 .
1. $55
2. $AA
The $55 write must precede the $AA write. Instructions may be executed
betw een the write ope rations provi ded that the C OP watch dog does not
time out before the second write.
Figu re 5-1. Prog ra mm able COP Wa tch do g Diagra m
÷2÷2÷2÷2÷2÷2÷2÷2÷2÷2÷2÷2÷2÷2÷2÷4
÷ 4÷ 2÷ 2÷ 2÷ 2÷ 2÷ 2221
219
217
213
215
CM1
CM0
COPRST
PCOPE
RESET
INTERNAL
CLOCK
(fOP)
PROGRAM M ABLE C OP WATCHDOG (MC68HC705C8 TYPE )
÷2
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Technical Data MC68HC705C8A —Rev. 3
64 Resets
Resets
The pr ogramma ble COP control reg ist er (COPCR ) shown in Figure 5-3
does these functions:
•Flags programmable COP watchdog resets
•Enables the clock monitor
•Enables the programmable COP watchdog
•Controls the timeout period of the programmable COP watchdog
COPF — COP Fla g
This read-only bit is set when a timeout of the programmable COP
watch dog occu rs or when the clock monito r dete c ts a slow or ab sent
internal clock. Clear the COPF bit by reading the COP control register.
Reset has no effect on the COPF bit.
1 = COP timeout or internal clock failure
0 = No COP timeout and no internal clock failure
Address: $001D
Bit 7654321Bit 0
Read:
Write:Bit 7654321Bit 0
Reset:UUUUUUUU
= Unimplemented U = Unaffected
Figu re 5-2. Prog ram m able COP Re set Regist er (COPR ST)
Address: $001E
Bit 7654321Bit 0
Read: 0 0 0 COPF CME PCOPE CM1 CM0
Write:
Reset:000U0000
= Unimplemented U = Unaffected
Figure 5-3. Programmable COP Control Register (COPCR)
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Resets
Reset Sou r ces
MC68HC705C8A —Rev. 3 T echnical Data
MOTOROLA Resets
CME — Clock Monitor Enable Bit
This read/wr ite bit enables the clock monitor. The clock monitor sets
the COPF bit and generates a reset if it detects an absent internal
clock for a period of from 5 µs to 100 µs. CME is readable and writable
at any time. Reset clears the CME bit.
1 = Clock monitor enabled
0 = Clock monitor disabled
NOTE: Do not enable the clock monitor in applications with an internal clock
frequency of 200 kHz or less.
If the clock monitor detects a slow clock, it drives the bidirectional
RESET pin low for four clock cycles. If the clock monitor detects an
absent clock, it drives the RESET pin low until the clock recovers.
PCOPE — Programmable COP Enable Bit
This read/write bit enables the programmable COP watchdog.
PCOPE is readable at any time but can be written only once after
reset. Reset clears the PCOPE bit.
1 = Programmable COP watchdog enabled
0 = Programmable COP watchdog disabled
NOTE: Programming the non-programmable COP enable bit (NCOPE) in mask
option register 2 (MOR2) to logic 1 enables the non-programmable COP
watchdog. Setting the PCOPE bit while the NCOPE bit is programmed
to logic 1 enables both COP watchdogs to operate at the same time.
(See 9.5.3 Mask Option Register 2.)
CM1 and CM0 — COP Mode Bits
These read/write bits select the timeout period of the programmable
COP watchdog. (See Ta ble 5-1.) CM1 and CM0 can be read anytime
but can be written only once. They can be cleared only by reset.
Bits 7–5 — Unused
Bits 7–5 always read as logic 0s. Reset clears bits 7–5.
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Technical Data MC68HC705C8A —Rev. 3
66 Resets
Resets
5.3.3.2 Non-Programmable COP Watchdog
A timeo ut of the 18-stage ri pple co unter in the non-program mab l e COP
watchdog generates a reset. The timeout period is 65.536 ms when
fOSC = 4 MHz. The t imeou t period for the non-p rogramm able COP time r
is a direct function of the crystal frequency. The equation is:
Tw o memory l ocations control o pera tion of t he non- programm able C OP
watchdog:
1. Non- programmable COP enable bit (NCOPE) in mask option
register 2 (MOR2)
Programming the NCOPE bit in MOR2 to a logic 1 enables the
non-programmable COP watchdog. See 9.5.3 M ask Option
Register 2.
NOTE: Writing a logic 1 to the programmable COP enable bit (PCOPE) in the
COP control register enables the programmable COP watchdog. Setting
the PCOP E bit while the NCOPE bit is programmed to logic 1 enables
both COP watchdogs to operate at the same time.
Table 5-1. Programmable COP Timeout Period Selection
CM1:CM 0 COP
Timeout Rate
Prog ra m m able COP Ti m eout Period
fOSC = 4.0 MHz
fOP = 2.0 MHz fOSC = 3.5795 MHz
fOP = 1.7897 MHz fOSC = 2. 0 MHz
fOP = 1. 0 MHz fOSC = 1.0 MHz
fOP = 0. 5 MHz
00 fOP ÷ 215 16.38 ms 18.31 ms 32. 77 m s 65.54 ms
01 fOP ÷ 217 65.54 ms 73.24 ms 131.07 ms 262.14 ms
10 fOP ÷ 219 262.14 ms 292.95 ms 524. 29 ms 1.048 s
11 fOP ÷ 221 1.048 s 1.172 s 2.097 s 4.194 s
262,144
fOSC
Timeout period =
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Resets
Reset Sou r ces
MC68HC705C8A —Rev. 3 T echnical Data
MOTOROLA Resets
2. COP clear bit (COPC) at address $1FF0
To clear the non-programmable COP watchdog and start a new
COP timeout period, write a logic 0 to bit 0 of address $1FF0.
Reading address $1FF0 returns the mask option register 1
(MOR1) data at that l ocation . S ee 9 .5.2 Mask Op tio n Re gist er 1.
NOTE: T he non-pr ogramma ble watchd og COP is di sabled in bootl oader mo de,
even if the NCOPE bit is programmed.
Figure 5-4 is a diagram of the non-programmable COP.
Figure 5-4. Non- Programm able COP Watchdog Diagram
5.3.4 Clock Monitor Reset
When the CME bit in the COP control register is set, the clock monitor
detects the absence of the inter nal bus clo ck for a certain period of time .
The tim eout peri o d dep ends o n pr ocessing para mete rs an d var ies fro m
5 µs to 100 µs, which implies that systems using a bus clock r a te of
200 kHz or less should not use the clock monitor function.
If a slow or ab sent clock is detected, the clock monitor cau ses a system
reset. The reset is issued to the external system for four bus cycles using
the bidirectional RESET pin.
Special consi d eratio n is requi red when using the S TOP instruction with
the clock monitor. Since STOP causes the system clocks to halt, the
clock monitor issues a system reset when STOP is executed.
÷ 2÷ 2÷ 2÷ 2÷ 2÷ 2÷ 2÷ 2÷ 2÷ 2÷ 2÷ 2÷ 2÷ 2÷ 2÷ 2÷ 2
NCOPE
NON-PRO GRAMMABLE C OP WATCHDO G (MC68HC05C4A T YPE)
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Technical Data MC68HC705C8A —Rev. 3
68 Resets
Resets
The clock monitor is a useful backup to the COP watchdog system.
Because the watchdog timer requires a clock to function, it cannot
indicate a system clock failure. The clock m onitor would detect such a
condition and forc e the MCU to a reset state. Clocks are not required for
the MCU to reach a reset condition. They are, however, required to bring
the MCU through the reset sequence and back to run condition.
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MC68HC705C8A —Rev. 3 Tec hnical Data
MOTOROLA Low-Power Modes
Technical Data — MC68HC705C8 A
Section 6. Low-Power Modes
6.1 Contents
6.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
6.3 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
6.3.1 SCI During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
6.3.2 SPI During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
6.3.3 Programmable COP Watchdog in Stop Mode . . . . . . . . . . .71
6.3.4 Non-Programmable COP Watchdog in Stop Mode . . . . . . .73
6.4 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
6.4.1 Programmable COP Watchdog in Wait Mode . . . . . . . . . . .75
6.4.2 Non-Programmable COP Watchdog in Wait Mode . . . . . . .75
6.5 Data-Retention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
6.2 Introduction
This section describes the three low-power modes:
•Stop mode
•Wait mode
•Data-retention mode
6.3 Stop Mode
The STOP instr uction pl aces th e microcon troller u nit (MCU ) in it s lowest
pow er consumption mode. In stop mo de, the in ternal oscil la tor is turned
off, halting all internal processing including timer, serial communications
interface (SCI), and master mode serial peripheral interface (SPI)
operation. See Figure 6-1.
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70 Low-Power Modes
Low-Power Modes
Figure 6-1. Stop/Wait Mode Function Flowchart
During stop mode, the I bit in the condition code register (CCR) is
cleared to enable external interrupts. All other registers and memory
remain unaltered. All input/output (I/O) lines remain unchanged. The
processor can be brough t o ut of stop mode only by an exter nal interrupt
or reset.
NO
YES
YES
YES
YES
YES
NO
NO
NO
NO
YES
NO
NO
YES
STOP
RESET
EXTERNAL
INTERRUPT
(IRQ)
TURN O N OS CI LL ATOR
WAIT FOR TIME
DELAY TO STABILI Z E
1 . FETCH RE SE T V E CTOR
2. SER V ICE INTERRUP T:
a. STACK
b. SET I BIT
c. VEC TO R TO
INTERRUPT ROUTINE
STOP OSCILLATOR
AND ALL CLO CK S
CLEAR I BI T
WAIT
OSCILLATOR AC TIVE
TIMER, SC I, AND SPI
CLOCKS AC TIVE
CPU CL OC KS STOP PED
RESET
EXTERNAL
INTERRUPT
(IRQ)
INTERNAL TIMER
INTERRUPT
INTERNAL SCI
INTERRUPT
INTERNAL SPI
INTERRUPT
RE STAR T CP U CL OC K
1. FETCH RE SET VECTOR
2. SER VICE INTERR UP T:
a. STACK
b. SET I BIT
c. VEC TO R TO
INTE RRUPT ROUTINE
C LEAR I BIT
OR OR
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Low-Power Modes
Stop Mo de
MC68HC705C8A —Rev. 3 T echnical Data
MOTOROLA Low-Power Modes
6.3.1 SCI During Stop Mode
When the MCU enters stop mode, the baud rate generator stops, halting
all SCI activity. If the STOP instruction is executed during a transmitter
transfer, that transfer is halted. If a low input to the IRQ pin is u sed to exit
stop mode, the transfer resumes.
If the SCI rece iv er is receiv ing data and sto p mode is entered, received
data sampling stops because the baud rate generator stops, and all
subsequent data is lost. Therefore, all SCI transfers should be in the idle
state when the STOP instruction is executed.
6.3.2 SPI During Stop Mode
When the MCU enters stop mode, the baud rate generator stops,
terminating all master mode SPI operations. If the STOP instruction is
executed during an SPI transfer, that transfer halts until the MCU exits
stop mode by a low signal on the IRQ pin. If reset is used to exit stop
mode, the SPI control and status bits are cleared, and the SPI is
disabled.
If the MCU is in slave mode whe n the STOP instruction is execu ted, the
slave SPI continues to opera te and can still accept data and clock
information in addition to transmitting its own data back to a ma ster
device. At the end of a possible transmission with a slave SPI in stop
mode, no flags are set until a low on the IRQ pin wakes up the MCU.
NOTE: Although a slave SPI in stop mode can exchange data with a master SPI,
the status bits of a slave SPI are inactive in stop mode.
6.3.3 Programmable COP Watchdog in Stop Mode
The STOP instruction turns off the in ternal oscillator and suspends the
computer operating properly (COP) watchdog counter. If the RESET pin
bri ngs the MCU out o f stop mode, the reset fun ction clear s and disables
the COP watchdog.
If the IRQ pin brings the MCU out of stop mode, the COP counter
resumes counting from its suspended value after the 4064-tCYC clock
stabilization delay. See Figure 6-2.
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72 Low-Power Modes
Low-Power Modes
NOTE: If the clock monitor is enabled (CME = 1), the ST OP instruction causes
the clock monitor to time out and reset the MCU.
Figure 6-2. Programmable COP Watchdo g
in Stop Mode (PCOPE = 1) Flowchart
STABILIZATION
STOP
EXTERNAL
RESET?
NO
NO
TURN ON INTERNAL OSCILLATOR
YES
YES
END OF
DELAY?
YES
NO
1. LOAD PC WIT H RESET VEC TOR
OR
2. SERVICE INTERRUPT:
a. SAVE CPU REGISTERS ON STACK
b. SET I BIT IN CCR
c. LOAD PC WITH INTERRUPT VECTOR
CLEAR I BIT IN CCR
TURN OF F INTE RNAL OSCIL L ATOR
TURN ON INTERNAL CLOCK
SUS P E ND CO P COUNTER
TURN ON INTERNAL OSCILLATOR
END OF
STABILIZATION
DELAY?
YES
NO
1. LOAD PC WIT H RES ET VECTOR
OR
2. SERVICE INTERRUPT:
a. SAVE C PU REGIST ER S ON STACK
b. SET I BIT IN CCR
c. LOAD PC WITH INTERRUPT VECTOR
TURN ON INTERNAL CLOCK
CLEA R CO P CO UNT ER
CLEA R PCOPE BIT IN COPCR
RESUME COP WATCHDOG COUNT
EXTERNAL
INTERRUPT?
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Low-Power Modes
Wait Mode
MC68HC705C8A —Rev. 3 T echnical Data
MOTOROLA Low-Power Modes
6.3.4 Non-Programmable COP Watchdog in Stop Mode
The S TOP instruction h as these effects o n the non- programm able COP
watchdog:
•Turns off the oscillator and the COP watchdog counter
•Clears the COP watchdog counter
If the RESET pin bring s the MCU out of stop mode, the COP watchdog
begins counting immediately. The reset function clears the COP counter
again after the 4064-tCYC clock stabilization delay.
If the IRQ pin brings the MCU out of stop mode, the COP watchdog
begins counting immediately. The IRQ function does not clear the
COP counter again after the 4064-tCYC clock stabilization delay. See
Figure 6-3.
NOTE: If the clock monitor is enabled (CME = 1), the ST OP instruction causes
it to time out and reset the MCU.
6.4 Wait Mode
The WAIT instruction places the MCU in an intermediate power
consumption mode. All central processor unit (CPU) activity is
suspended, but the oscillator, capture/compare timer, SCI, and SPI
remain active. Any interrupt or reset brings the MCU out of wait mode.
See Figure 6-1 .
The WAIT instruction has these effects on the CPU:
•Clears the I bit in the condition code register, enabling interrupts
•Stops the CPU clock, but allows the internal clock to drive the
capt ure/co mpar e timer, SCI, and SPI
The WAIT instruction does not affect any other registers or I/O lines. The
capt ure/compa re timer, SCI, and S PI can be e nabled to allow a periodic
exit from wait mode.
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Technical Data MC68HC705C8A —Rev. 3
74 Low-Power Modes
Low-Power Modes
Figure 6-3. Non-Programmable COP Watchdog
in St op Mode (NCOPE = 1) Flowchart
STABILIZATION
STOP
EXTERNAL
RESET?
NO
NO
TURN ON INTERNAL OSCILLATOR
YES
YES
END OF
DELAY?
YES
NO
1. LOAD PC WIT H RES ET VECTOR
OR
2. SERVICE INTERRUPT:
a. SAVE CPU REGI STE RS ON STAC K
b. SET I BIT IN CCR
c. LOAD PC WITH INTERRUPT VECTOR
CLEAR I BIT IN CCR
CL E AR COP COUNT E R
TURN ON INTERNAL CLOCK
TURN OF F INTE RNAL OSCIL L ATOR
TURN ON INTERNAL OSCILLATOR
END OF
STABILIZATION
DELAY?
YES
NO
1. LOAD PC WIT H RES ET VECTOR
OR
2. SERVICE INTERRUPT:
a. SAVE C PU REGIST ER S ON STACK
b. SET I BIT IN CCR
c. LOAD PC WITH INTERRUPT VECTOR
CL E AR COP COUNT E R
TURN ON CO P WATCHDOG
EXTERNAL
INTERRUPT?
TURN O FF CO P CO UNT E R
TURN ON CO P WATCHDOG
TURN ON INTERNAL CLOCK
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Low-Power Modes
Data-Retent ion Mode
MC68HC705C8A —Rev. 3 T echnical Data
MOTOROLA Low-Power Modes
6.4.1 Programmable COP Watchdog in Wait Mode
The programmable COP watchdog is active during wait mo de. Software
must periodically bring the MCU out of wait mode to clear the
programmable COP watchdog.
6.4.2 Non-Programmable COP Watchdog in Wait Mo de
The non-programmable COP watchdog is active during wait mode.
Software must periodically bring the MCU out of wait mode to clear the
non-programmable COP watchdog.
6.5 Data-Retention Mode
In data-retention mode, the MCU retains random-access memory (RAM)
contents and CP U registe r conten ts at VDD volta ges as low as 2.0 Vdc.
The data-retention feature allows the MCU to remain in a low
power-consumption state during which it retains data, but the CPU
cannot execute instructions.
To put the MCU in data-retention mode:
1. Drive the RESET pin to logic 0.
2. Lower VDD voltage. The RESET pin must remain low continuously
during data-retention mode.
To take the MCU out of data-retention mode:
1. Return VDD to normal operating voltage.
2. Return the RESET pin to logic 1.
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Technical Data MC68HC705C8A —Rev. 3
76 Low-Power Modes
Low-Power Modes
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MC68HC705C8A —Rev. 3 Tec hnical Data
MOTOROLA Parallel Input/Output (I/O)
Technical Data — MC68HC705C8 A
Section 7. Parallel Input/Output (I/O)
7.1 Contents
7.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
7.3 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
7.3.1 Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
7.3.2 Data Direction Register A. . . . . . . . . . . . . . . . . . . . . . . . . . .7 9
7.3.3 Port A Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
7.4 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
7.4.1 Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
7.4.2 Data Direction Register B. . . . . . . . . . . . . . . . . . . . . . . . . . .8 2
7.4.3 Port B Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
7.5 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
7.5.1 Port C Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
7.5.2 Data Direction Register C. . . . . . . . . . . . . . . . . . . . . . . . . . .86
7.5.3 Port C Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
7.6 Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
7.2 Introduction
This section describes the programming of ports A, B, C, and D.
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Technical Data MC68HC705C8A —Rev. 3
78 Parallel Input/Output (I/O)
Parallel Input/Output (I/O)
7.3 Port A
Port A is an 8-bit, general-purpose, bidirectional input/output (I/O) port.
7.3.1 Port A Data Register
The port A data register (PORTA) shown in Figure 7-1 contains a data
latch for each of the eigh t port A pins. W hen a port A pin i s program med
to be an output, the state of its data register bit determines the state of
the outpu t pin. When a port A pin is programm ed to be an i nput, rea ding
the port A data register returns the logic state of the pin.
PA7–PA0 — Port A Data Bits
These read/write bits are software programmable. Data direction of
each bi t is und er t he control of th e cor respondi ng bit in data direct ion
register A. Reset has no effect on port A data.
Address: $0000
Bit 7654321Bit 0
Read: PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0
Write:
Reset: Unaffected by reset
Figure 7-1. Port A Data Register (PORTA)
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P a r a lle l In pu t/Outp u t (I/O)
Port A
MC68HC705C8A —Rev. 3 T echnical Data
MOTOROLA Parallel Input/Output (I/O)
7.3.2 Data Direction Register A
The contents of data direction register A (DDRA) shown in Figure 7-2
determine whether each port A pin is an input or an output. Writing a
logic 1 to a DDRA bit enables the output buffe r for the associated port A
pin; a logic 0 disables the output bu ffer. A reset clears all DDRA bits,
configuring all port A pins as inputs.
DDRA7–DDRA0 — Port A Data Direction Bits
These read/write bits control port A da ta direction. Reset clears bits
DDRA7–DDRA0.
1 = Corresponding port A pin configured as output
0 = Corresponding port A pin configured as input
NOTE: A void glitch es on port A pi ns by writing to the p ort A data register befo re
changing DDRA bits from logic 0 to logic 1.
Address: $0004
Bit 7654321Bit 0
Read: DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0
Write:
Reset:00000000
Figure 7-2. Data Direction Register A (DDRA)
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Technical Data MC68HC705C8A —Rev. 3
80 Parallel Input/Output (I/O)
Parallel Input/Output (I/O)
7.3.3 Port A Logic
Figure 7-3 is a diagram of the port A I/O logic.
Figure 7-3. Port A I/O Logic
When a port A pin is programmed to be an output, the state of its data
register bit determines the state of the output pin. When a port A pin is
progr amm ed to be an i npu t, read ing the por t A dat a registe r retu rns the
logic state of the pin.
The data latch can always be written, regardless of the state of its DDRA
bit. Table 7-1 summarizes the operation of the port A pins.
NOTE: To avoid excessive current draw, tie all unused input pins to VDD or VSS,
or change I/O pins to outputs by writing to DDRA in user code as early
as possible.
Table 7-1. Port A Pin Functions
DDRA Bit I/O Pin Mode Accesses to DDRA Accesses t o PORTA
Read/Write Read Write
0Input, Hi-Z(1)
1. Hi-Z = high im pedance
DDRA7–DDRA0 Pin PA7–PA0(2)
2. Writ ing affects data register but does no t affect input .
1 Output DDRA7–DDRA0 PA7–PA0 PA7–PA0
DATA DIRECTION
REGISTER A
BIT DDR Ax
PAx
PORT A DATA
REGISTER
BI T PAx
REA D $000 4
WRITE $0000
REA D $000 0
RESET
INTERNAL DATA BUS
WRITE $0004
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P a r a lle l In pu t/Outp u t (I/O)
Port B
MC68HC705C8A —Rev. 3 T echnical Data
MOTOROLA Parallel Input/Output (I/O)
7.4 Port B
Port B is an 8-bit, gen eral-purpose, bidirectional I/O port. Port B pins can
also be configured to function as external interrupts. The port B pullup
devi ces are enable d in mask optio n register 1 (MOR1). Se e 9 .5.2 Mask
Option Register 1 and 4.3.3 Port B Interrupts.
7.4.1 Port B Data Register
The port B data register (PORTB) shown in Figure 7-4 contains a data
latch for each of the eight port B pins.
PB7–PB0 — Port B Data Bits
These read/write bits are software programmable. Data direction of
each bi t is und er t he control of th e cor respondi ng bit in data direct ion
register B. Reset has no effect on port B data.
Address: $0001
Bit 7654321Bit 0
Read: PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0
Write:
Reset: Unaffected by reset
Figure 7-4. Port B Data Register (PORTB)
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Technical Data MC68HC705C8A —Rev. 3
82 Parallel Input/Output (I/O)
Parallel Input/Output (I/O)
7.4.2 Data Direction Register B
The contents of data direction register B (DDRB) shown in Figure 7-5
determine whether each port B pin is an input or an output. Writing a
logic 1 to a DDRB bit enables the output buffe r for the associated port B
pin; a logic 0 disables the output buffer. A reset clears all DDRB bits,
confi guring all port B pins as in puts. If the pullup device s are enabled by
mask option, setting a DDRB bit to a logic 1 turns off the p ullup device
for that pin.
DDRB7–DDRB0 — Port B Data Direction Bits
These read/write bits control port B da ta direction. Reset clears bits
DDRB7–DDRB0.
1 = Corresponding port B pin configured as output
0 = Corresponding port B pin configured as input
NOTE: A void glitch es on port B pi ns by writing to the p ort B data register befo re
changing DDRB bits from logic 0 to logic 1.
Address: $0005
Bit 7654321Bit 0
Read: DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0
Write:
Reset:00000000
Figure 7-5. Data Direction Register B (DDRB)
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P a r a lle l In pu t/Outp u t (I/O)
Port B
MC68HC705C8A —Rev. 3 T echnical Data
MOTOROLA Parallel Input/Output (I/O)
7.4.3 Port B Logic
Figure 7-6 shows the port B I/O logic.
Figure 7-6. Port B I/O Logic
PB7
EXTERNAL
INTERRUPT
REQUEST
DATA DIR ECTION
RE G ISTE R B
BIT DDRB7
PORT B DATA
REGISTER
BIT PB7
READ $0005
WRITE $0001
READ $0001
RESET
INTERNAL DATA BUS
WRITE $0005
PBPU7
FROM OTHE R
VDD
PORT B PINS
D
C
Q
RQ
I BIT
VDD
FROM CCR
RESET
EXTERNAL INTERRUPT VECTOR FETCH
IRQ
IRQ
FROM OPTION
REGISTER
IRQ
LATCH
FROM MOR1
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Technical Data MC68HC705C8A —Rev. 3
84 Parallel Input/Output (I/O)
Parallel Input/Output (I/O)
When a port B pin is programmed as an output, reading the port bit reads
the value of the data latch and not the voltage on the pin itself. When a
port B pin is programmed as an input, reading the port bit reads the
voltage level on the pin. The data latch can always be written, regardless
of the state of its DDRB bit.
NOTE: To avoid excessive current draw, tie all unused input pins to VDD or VSS,
or for I/O pins change to outputs by writing to DDRB in user code as early
as possible.
Table 7-2. Port B Pin Functions
DDRB Bit I/O Pin M ode Accesses to DDRB Accesses to PORTB
Read/Write Read Write
0Input, Hi-Z(1)
1. Hi-Z = high im pedance
DDRB7–DDRB0 Pin PB7–PB0(2)
2. Writ ing affects data register but does no t affect input .
1 Output DDRB7–DDRB0 PB7–PB0 PB7–PB0
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P a r a lle l In pu t/Outp u t (I/O)
Port C
MC68HC705C8A —Rev. 3 T echnical Data
MOTOROLA Parallel Input/Output (I/O)
7.5 Port C
Port C is an 8-bit, general-purpose, bidirectional I/O port. PC7 has a high
current sink and source capability.
7.5.1 Port C Data Register
The port C data register (POR TC) show n in Figure 7-7 conta in s a data
latch for each of the eight port C pins. When a p ort C pin is progr ammed
to be an output, the state of its data register bit determines the state of
the outp ut pin. When a port C pin i s progr ammed to be an input, reading
the port C data regi ster returns the logic state of the pin.
PC7–PC0 — Port C Data Bits
These read/write bits are software programmable. Data direction of
each bi t is und er t he control of th e cor respondi ng bit in data direct ion
register C. PC7 has a high current sink and source capability. Reset
has no effect on port C data.
Address: $0002
Bit 7654321Bit 0
Read: PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
Write:
Reset: Unaffected by reset
Figure 7-7. Port C Data Register (PORTC)
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Technical Data MC68HC705C8A —Rev. 3
86 Parallel Input/Output (I/O)
Parallel Input/Output (I/O)
7.5.2 Data Direction Register C
The contents of data direction register C (DDRC) shown in Figure 7-8
determine whether each port C pin is an input or an output. Writing a
logic 1 to a DDRC bit enable s the output b uffer for the associated po rt C
pin; a logic 0 disables the output buffer. A reset clears all DDRC bits,
configuring all port C pins as inputs.
DDRC7–DDRC0 — Port C Data Direction Bits
These read/write bits control port C data direction. Reset clears bits
DDRC7–DDRC0.
1 = Corresponding port C pin configured as output
0 = Corresponding port C pin configured as input
NOTE: A void glitches on po rt C pins by w riting to t he p ort C data register before
changing DDRC bits from logic 0 to logic 1.
Address: $0006
Bit 7654321Bit 0
Read: DDRC7 DDRC6 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0
Write:
Reset:00000000
Figure 7-8. Data Direction Register C (DDRC)
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P a r a lle l In pu t/Outp u t (I/O)
Port C
MC68HC705C8A —Rev. 3 T echnical Data
MOTOROLA Parallel Input/Output (I/O)
7.5.3 Port C Logic
Figure 7-9 shows port C I/O logic.
Figure 7-9. Port C I/O Logic
When a port C pin is programmed as an output, reading the port bit reads
the val ue of the d ata latc h and not the voltage on th e pin. Whe n a port C
pin is programmed as an input, reading the port bit reads the voltage
leve l on the pin. The da ta latch can al ways be writte n, reg ardle ss of the
state of its DDRC bit. Table 7-3 summarizes the operation of the port C
pins.
NOTE: T o avoid excessi ve current draw , tie all unused i nput pins to VDD or VSS
or change I/O pins to outputs by writing to DDRC in user code as ear ly
as possible.
Table 7-3. Port C Pin Functions
DDRC Bit I/O P in Mode Accesses to DDRC Accesses to PORTC
Read/Write Read Write
0Inpu t, Hi- Z(1)
1. Hi-Z = high im pedance
DDRC7–DDRC0 Pin PC7–PC0(2)
2. Writ ing affects data register but does no t affect input .
1 Output DDRC7–DDRC0 PC7–PC0 PC7–PC0
PCx
DATA DIRECTION
REGISTER C
BIT DDRCx
PORT C DATA
REGISTER
BIT PCx
READ $0006
WRITE $0002
READ $0002
RESET
INTERNAL DATA BUS
WRITE $0006
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Technical Data MC68HC705C8A —Rev. 3
88 Parallel Input/Output (I/O)
Parallel Input/Output (I/O)
7.6 Port D
Port D is a 7-bit, special-purpose, input-only port that has no data
register. Reading address $0003 returns the logic states of the port D
pins.
Port D shares pins PD5 –PD2 with the seri al per ip heral i nterface module
(SPI). When the SPI is enabled, PD5–PD2 read as logic 0s. When the
SPI is disabled, reading address $0003 returns the logic states of the
PD5–PD2 pins.
Port D sha res pins P D1 and PD0 wi th th e S CI m odule. W hen the SCI is
enabled, PD1 and PD0 read as logic 0s. When the SCI is disabled,
reading address $0003 returns the logic states of the PD1 and PD0 pins.
Address: $0003
Bit 7654321Bit 0
Read: PD7 SS SCK MOSI MISO TDO RDI
Write:
Reset: Unaffected by reset
= Unimplemented
Figure 7-10. Port D Fixed Inpu t Register (PORTD)
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MC68HC705C8A —Rev. 3 Tec hnical Data
MOTOROLA Capture/Com pare Timer
Technical Data — MC68HC705C8 A
Section 8. Capture/Compare Timer
8.1 Contents
8.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
8.3 Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
8.3.1 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
8.3.2 Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
8.4 Timer I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
8.4.1 Timer Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
8.4.2 Timer Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
8.4.3 Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
8.4.4 Alternate Timer Registers. . . . . . . . . . . . . . . . . . . . . . . . . . .98
8.4.5 Input Capture Registers . . . . . . . . . . . . . . . . . . . . . . . . . .100
8.4.6 Output Compare Registers. . . . . . . . . . . . . . . . . . . . . . . . .101
8.2 Introduction
This section describes the operation of the 16-bit capture/compare timer.
Figure 8-1 shows the structure of the timer module. Figure 8-2 is a
summary of the timer input/output (I/O) registers.
8.3 Timer Operation
The core of the capture/compare timer is a 16-bit free-running counter.
The counter is the timing reference for the input capture and output
compare functions. The input capture and output compare functions can
latch the times at which external events occur, measure input
waveforms, and generate output waveforms and timing delays. Software
can read the value in the counter at any time without affecting the
counter sequence.
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Technical Data MC68HC705C8A —Rev. 3
90 Capture/Com pare Ti mer
Ca pture/ Compare Timer
Figure 8 -1. Timer Blo ck Diagram
TCAP EDGE
SELECT/
16-BIT COMPARATOR
OCRH ($0016) OCRL ($00 17)
16-BIT COUNTER
AT RH ($001A) ATRL ($0 01B)
TCMP
DETECT
LOGIC
PIN
CONTROL
LOGIC
TRH ($0018) TRL ($00 19)
ICRH ($0014) ICRL ($0015)
INTERNAL DATA BUS
TIMER CONTROL REGISTER TI M ER STAT U S REG ISTER
TIMER
INTERRUPT
REQUEST
INTERNAL CLOCK (XT AL ÷ 2)
TOF
OCF
ICF
$0013
$0012
ICIE
OCIE
TOIE
IEDG
OLVL
OVERFLOW
÷ 4
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Capture/Compare Timer
Time r Operation
MC68HC705C8A —Rev. 3 T echnical Data
MOTOROLA Capture/Com pare Timer
Addr. Regist e r Na me Bi t 7 6 5 4 3 2 1 Bit 0
$0012 Timer Control Register
(TCR)
See page 94 .
Read: ICIE OCIE TOIE 0 0 0 IEDG OLVL
Write:
Reset: 0 0 0 0 0 0 U 0
$0013 Timer Status Register
(TSR)
See page 96 .
Read: ICF OCF TOF 0 0 0 0 0
Write:
Reset: U U U 0 0 0 0 0
$0014 Input C apture Regi ster
High (ICRH)
See page 100 .
Read: Bit 15 Bit 14 Bit 13 Bi t 12 Bit 11 Bit 10 Bit 9 Bit 8
Write:
Reset: Unaff ected by reset
$0015 Input C apture Regi ster
Low (ICRL)
See page 100 .
Read: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Write:
Reset: Unaff ected by reset
$0016
Output Compare R egister
High (OCRH)
See page 101 .
Read: Bi t 1 5 B i t 1 4 Bit 13 Bi t 1 2 Bi t 11 Bi t 1 0 Bit 9 Bit 8
Write:
Reset: Unaffected by reset
$0017 Output Compare Register
Low (OCRL)
See page 101 .
Read: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Write:
Reset: Unaffected by reset
$0018 Timer Regi ster High
(TRH)
See page 97 .
Read: Bit 15 Bit 14 Bit 13 Bi t 12 Bit 11 Bit 10 Bit 9 Bit 8
Write:
Reset: Reset initi alizes TRH to $FF
$0019 Timer Register Low
(TRL)
See page 97 .
Read: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Write:
Reset: R eset initiali zes TRL to $FC
$001A Alternate Timer Register
High (ATRH)
See page 99 .
Read: Bit 15 Bit 14 Bit 13 Bi t 12 Bit 11 Bit 10 Bit 9 Bit 8
Write:
Reset: Reset initi alizes ATRH to $FF
$001B Alternate Timer Register
Low (ATRL)
See page 99 .
Read: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Write:
Reset: Reset initializes ATRL to $FC
= Unimplemented U = Unaffected
Figure 8-2. Timer I/O Register Summary
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Technical Data MC68HC705C8A —Rev. 3
92 Capture/Com pare Ti mer
Ca pture/ Compare Timer
Because of the 16-bit timer architecture, the I/O registers for the input
capture and output compare functions are pairs of 8-bit registers.
Because the counter is 16 bits long and preceded by a fixed
divide-by-four prescaler, the counter rolls over every 262,144 internal
clock cycles. Timer resolution with a 4-MHz crystal is 2 µs.
8.3.1 Input Capture
The input capture function can record the time at which an external event
occurs. When the input capture circuitry detects an active edge on the
input capture pin (TCAP), it latches the contents of the timer registers
into the input capture registers. The polarity of the active edge is
programmable.
Latching values into the input capture registers at successive edges of
the same polarity measures the period of the input signal on the TCAP
pin. Latching the counter values at successive edges of opposite polarity
measures the pulse width of the signal. Figure 8-3 shows the logic of the
input capture function.
Figure 8-3. Input Capture Operation
TCAP EDGE
SELECT/DETECT INPUT CAPTURE REGISTE R HIGH I NPUT CAPTURE REGISTER LOW
TIME R RE GI S TE R HIG H TIMER REGISTER LOW
TIMER
INTERRUPT
REQUEST
LOGIC
15 $0018 8 7$0019 0
15 87 0
$0014 $0015
TIMER STATUS REGISTERTIMER CONTROL REGISTER
LATCH
IEDG
$0012 $0013
ICF
OCF
TOF
ICIE
OCIE
TOIE
OLVL
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Capture/Compare Timer
Time r Operation
MC68HC705C8A —Rev. 3 T echnical Data
MOTOROLA Capture/Com pare Timer
8.3.2 Output Compare
The output compare function can generate an output signal when the
16-bit counter reaches a sele cted value. Software writes the selected
value into the output compare registers. On every fourth internal clock
cycle the output compar e circuitry compar es the value of the coun ter to
the value written in the output compare re gisters. When a match occurs,
the timer transfers the programmable output level bit (OLVL) from the
timer control register to the output compare pin (T CMP).
Softwar e ca n use the outp ut co mpar e r egister to measu re ti me period s,
to generate timing delays, or to generate a pulse of specific duration or
a pulse train of specific frequency and du ty cycle on the TCMP pin.
Figure 8-4 shows the logic of the output compare functi on.
Figure 8-4. Output Compare Operation
16-BIT COMPARATOR
OUTPU T COMPARE REGISTER HIGH OUTPUT COM PARE REGISTER LOW
COUNTE R HIGH BYTE COUNTER LOW BYTE
PIN
CONTROL
LOGIC TCMP
TIME R STATUS REGISTER
TIME R S TATUS REGIST E R
15 0
15 870
TIMER
INTERRUPT
REQUEST
ICIE
OCIE
TOIE
ICF
OCF
TOF
$0012 $0013
$0016 $0017
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Technical Data MC68HC705C8A —Rev. 3
94 Capture/Com pare Ti mer
Ca pture/ Compare Timer
8.4 Timer I/O Registers
These registers control and monitor the timer operation:
•Timer control register (TCR)
•Timer status register (TSR)
•Timer registers (TRH and TRL)
•Alternate timer registers (ATRH and ATRL)
•Input capture registers (ICRH and ICRL)
•Output compare registers (OCRH and OCRL)
8.4.1 Timer Control Register
The ti mer control register ( TCR) as show n in Figur e 8-5 perf orms these
functions:
•Enables input capture interrupts
•Enables output compare interrupts
•Enables timer overflow interrupts
•Controls the active edge polarity of the TCAP signal
•Controls the active level of the TCMP output
Address: $0012
Bit 7654321Bit 0
Read: ICIE OCIE TOIE 0 0 0 IEDG OLVL
Write:
Reset:000000U0
U = Unaffe cted
Fi gu re 8-5. Tim e r Cont ro l Regi ste r (TCR )
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Capture/Compare Timer
Timer I/O Registers
MC68HC705C8A —Rev. 3 T echnical Data
MOTOROLA Capture/Com pare Timer
ICIE — Input Capture Interrupt Enable Bit
This read/write bit enables interrupts caused by an active signal on
the TCAP pin. Reset clears the ICIE bit.
1 = Input capture interrupts enabled
0 = Input capture interrupts disabled
OCIE — Output Compare Interrupt Enable Bit
This read/write bit enables interrupts caused by an active signal on
the TCMP pin. Reset clears the OCIE bit.
1 = Output compare interrupts enabled
0 = Output compare interrupts disabled
TOIE — Timer Overflow Interrupt Enable Bit
This read/write bit enables interrupts caused by a timer overflow.
Reset clears the TOIE bit.
1 = Timer overflow interr upts enabled
0 = Timer overflow interr upts disabled
IEDG — Input Edge Bit
The state of this read/write bit determines whether a positive or
negative transition on the TCAP pin triggers a transfer of the contents
of the timer register to the input capture registers. Reset has no effect
on the IEDG bit.
1 = Positive edge (low-to-high transition) triggers input capture
0 = Negative edge (high-to-low transition) triggers input capture
OLVL — Output Level Bit
The state of this read/write bit determines whether a logic 1 or a
log ic 0 appears on the T C MP pin w hen a successfu l output compa re
occurs. Reset clears the OLVL bit.
1 = TCMP goes high on output compare
0 = TCMP goes low on output compare
Bits 4–2 — Not used; these bits always read 0
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Technical Data MC68HC705C8A —Rev. 3
96 Capture/Com pare Ti mer
Ca pture/ Compare Timer
8.4.2 Timer Status Register
The timer status r egister (TSR ) i s a read- only r egis ter shown in
Figure 8-6 contains flags for these events:
•An active sig nal on th e TCA P pin, tran sferr i ng the co ntents o f the
timer registers to the input capture registers
•A match between the 16-bit counter and the output compare
registers, transferring the OLVL bit to the TCMP pin
•A timer rollover from $FFFF to $0000
ICF — Input Capture Flag
The ICF b it is set automatic ally when an edge of the selected p olarity
occurs on the TC AP pin. Clear th e ICF bit b y r eading th e ti m er statu s
register with ICF set and then reading the low byte ($0015) of the
input capture registers. Reset has no effect on ICF.
1 = Input capture
0 = No input capture
OCF — Output Compare Flag
The OCF bit is se t automaticall y when the value of the timer registers
matches the contents of the output compare registers. Clear the OCF
bit by reading t he tim er status re gister wit h OCF set and then read ing
the low byte ($0017) of the output compare registers. Reset has no
effect on OCF.
1 = O utput compa re
0 = No output compare
Address: $0013
Bit 7654321Bit 0
Read: ICF OCF TOF 00000
Write:
Reset:UUU00000
= Unimplemented U = Unaffected
Figure 8-6. Timer Status Register (TSR)
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Capture/Compare Timer
Timer I/O Registers
MC68HC705C8A —Rev. 3 T echnical Data
MOTOROLA Capture/Com pare Timer
TOF — Timer Overflow Flag
The TOF bit is automatically set when the 16-bit counter rolls over
from $FFFF to $0000. Clear the TOF bit by reading the timer status
register with TOF set and then reading the low byte ($0019) of the
timer registers. Reset has no effect on TOF.
1 = Timer overflow
0 = No timer overflow
Bits 4–0 — Not used; these bits always read 0
8.4.3 Timer Registers
The read-only timer registers (TRH and TRL) shown in Figure 8-7
contain the current high and low bytes of the 16-bit counter. Reading
TRH before reading TRL causes TRL to be latched until TRL is read.
Reading TRL after reading the timer status register clears the timer
overflow flag bit (TOF). Writing to the timer registers has no effect.
Bit 7654321Bit 0
Register Name and Address: Timer Register High — $0018
Read: Bit 15 Bit 14 Bi t 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Write:
Reset: Reset initializes T RH to $FF
Register Name and Address: Timer Register Low — $0019
Read: Bit 7 Bi t 6 Bit 5 Bit 4 Bi t 3 Bit 2 Bit 1 Bit 0
Write:
Reset: R eset initializes TRL to $FC
= Unimplemented
Fi gure 8-7. Tim er Re gis ter s (TRH and TRL)
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Technical Data MC68HC705C8A —Rev. 3
98 Capture/Com pare Ti mer
Ca pture/ Compare Timer
Reading TRH returns the current value of the high byte of the counter
and causes the low byte to be latched into a buffer, as shown in
Figure 8-8. The buffer value remains fixed even if the high byte is read
more than once. Reading TRL rea ds the transparent low byte buffer and
completes the read sequence of the timer registers.
Figure 8-8. Timer Register Reads
NOTE: To prevent interrupts from occurring between readings of TRH and TRL,
set the interrupt mask (I bit) in the condition code register before reading
TRH, and clear the mask after reading TRL.
8.4.4 Alternate Timer Registers
The alternate timer registers (ATRH and ATRL) shown in Figur e 8-9
contain the current high and low bytes of the 16-bit counter. Reading
ATRH before reading ATRL causes AT RL to be latche d unt il ATRL is
read. Reading does not affect the timer overflow flag (TOF). Writing to
the alternate timer register s has no effect.
LOW BYTE BU FF ER
$0018 $0019TIMER REGIS TER HIGH TIMER REGISTER LOW
READ TRH
LATCH
INTE RNAL DAT A BUS
15
70
07
8
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Capture/Compare Timer
Timer I/O Registers
MC68HC705C8A —Rev. 3 T echnical Data
MOTOROLA Capture/Com pare Timer
Reading ATRH returns the current value of the high byte of the counter
and causes the low byte to be latched into a buffer, as shown in
Fi gure 8-10 .
Figure 8-10. Alternate Timer Register Reads
NOTE: To prevent interrupts from occurring between readings of ATRH and
ATRL, set the int erru pt ma sk (I bi t) in the cond ition code registe r before
reading ATRH, and clear the mask after reading ATRL.
Bit 7654321Bit 0
Register Name and Address: Al ternate Timer Regist er High — $001A
Read: Bit 15 Bit 14 Bi t 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Write:
Reset: Reset initi alizes ATRH to $FF
Register Name and Ad dress: Al ternate Timer Register Low — $001B
Read: Bit 7 Bi t 6 Bit 5 Bit 4 Bi t 3 Bit 2 Bit 1 Bit 0
Write:
Reset: Res et initiali zes ATRL to $FC
= Unimplemented
Figure 8-9. Alternate Timer Registers (ATRH and ATRL)
LOW BYTE BUFFER
$001A $001B
READ ATRH
LATCH
INTERNAL DATA BUS
15
70
07
8
ALTERNATE TIMER RE G IS TE R HIG H ALTERNATE TIMER REGIS TE R LO W
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Technical Data MC68HC705C8A —Rev. 3
100 Capture/Com pare Ti mer
Ca pture/ Compare Timer
8.4.5 Input Capture Registers
When a selected edge occurs on the TCAP pin, the current high and low
bytes of the 16-bit counter are latched into the read-only input capture
registers (ICRH and ICRL) shown in Figu re 8-11. Reading ICRH before
readi ng ICRL inhibits fur ther captures unt il ICRL is read. Readi n g ICRL
af ter readin g the timer status registe r clears the input captur e flag (IC F).
Writing to the input capture registers has no effect.
NOTE: To prevent interrupts from occurring between readings of ICRH and
ICRL, set the interrupt mask (I bit) in the condition code register before
reading ICRH and clear the mask after reading ICRL.
Bit 7654321Bit 0
Register Name and Address: Input Capture Register High — $0014
Read: Bit 15 Bit 14 Bi t 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Write:
Reset: Unaffected by reset
Register Name and Address: Input Capture Register Low — $0015
Read: Bit 7 Bi t 6 Bit 5 Bit 4 Bi t 3 Bit 2 Bit 1 Bit 0
Write:
Reset: Unaffected by reset
= Unimplemented
Figure 8-11. Input Captur e Registers (ICRH and ICRL)
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Capture/Compare Timer
Timer I/O Registers
MC68HC705C8A —Rev. 3 T echnical Data
MOTOROLA Capture/Com pare Timer
8.4.6 Output Compare Registers
When the value of the 16-bit counter matches the value in the read/write
output compare registers (OCRH and OCRL) shown in Figure 8-12, the
planned TCMP pin action takes place. Writing to OCRH before writing to
OCRL inhibits time r compa res until OCRL is written. Reading or writing
to OCRL after reading the timer status register clears the output
compare flag (OCF).
To pre v ent OCF from being set bet we en the time it is r ead a nd the ti me
the output compare registers are updated, use this procedure:
1. Disable interrupts b y setting th e I bit in the cond ition code register.
2. Write to OCRH. Compares are now inhibited until OCRL is written.
3. Clear bit OCF by reading the timer status register (TSR).
4. Enable the output compare function by writing to OCRL.
5. Enable interrupts by clearing the I bit in the condition code register.
Bit 7654321Bit 0
Register Name and Address: Output Com pare Register H igh — $0016
Read: Bit 15 Bit 14 Bit 1 3 Bit 12 Bit 11 Bit 10 Bi t 9 B it 8
Write:
Reset: Unaffected by reset
Register Name and Address: Output Compare Register Low — $0017
Read: Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
Write:
Reset: Unaffected by reset
Figure 8-12. Output Com pare Regist ers (OCRH and OCRL)
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Technical Data MC68HC705C8A —Rev. 3
102 Capture/Com pare Ti mer
Ca pture/ Compare Timer
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MC68HC705C8A —Rev. 3 Tec hnical Data
MO TOROLA EP R OM /OTPR OM (PROM )
Technical Data — MC68HC705C8 A
Section 9. EPR OM/OTPROM (PROM)
9.1 Contents
9.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
9.3 EPROM/OTPROM (PROM) Programming. . . . . . . . . . . . . . .104
9.3.1 Program Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
9.3.2 Preprogramming Steps . . . . . . . . . . . . . . . . . . . . . . . . . . .110
9.4 PROM Programming Routines. . . . . . . . . . . . . . . . . . . . . . . .111
9.4.1 Program and Verify PROM. . . . . . . . . . . . . . . . . . . . . . . . .111
9.4.2 Verify PROM Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . .112
9.4.3 Secure PROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
9.4.4 Secure PROM and Verify. . . . . . . . . . . . . . . . . . . . . . . . . .113
9.4.5 Secure PROM and Dump . . . . . . . . . . . . . . . . . . . . . . . . . .113
9.4.6 Load Program into RAM and Execute . . . . . . . . . . . . . . . .114
9.4.7 Execute Program in RAM. . . . . . . . . . . . . . . . . . . . . . . . . .115
9.4.8 Dump PROM Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . .115
9.5 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
9.5.1 Option Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
9.5.2 Mask Option Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . .117
9.5.3 Mask Option Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . .118
9.6 EPROM Erasing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
9.2 Introduction
This section describes erasable, programmable read-only
memory/one-time programmable read-only memory (EPROM/OTPROM
(PROM)) programming.
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Technical Data MC68HC705C8A —Rev. 3
104 EPROM /O TPRO M (PR OM)
EPROM/OTPROM (PROM)
9.3 EPROM/OTPROM (PROM) Programming
The internal PROM can be programmed efficiently using the Motorola
MC 68HC05P GMR- 2 progr amm er boar d, which can be purchased from
a Motorola-authorized distributor. The user can program the
microcontroller unit (MCU) using this printed circuit board (PCB) in
conjunction with an EPROM device already programmed with user code.
Only standalone programming is discussed in this section. For more
info rmation co ncerning the MC68H C05P GMR and i ts usages, contact a
local Motorola representative for a copy of the MC68HC05PGMR
Programmer Board User’s Manual #2, Motorola document number
MC68HC05PGMR2/D1.
Refer to Figure 9-1 for an EPROM programming flowchart. Figure 9-2
provides a schematic of the MC68HC05PGMR PCB with the reference
designators defined in Table 9-1.
Table 9-1. MC68HC05PGMR PCB Reference Designators
Reference
Designators Device
Type Ground +5 V +12 V –12 V VPP Notes
U1 2764 14, 20 1, 26, 27, 28 —— — 8 K x 8-bit EPROM
U2 MCU 20 40 ——3 40-pin DIP socket
U3 MCU 22 44 ——4 44-lead PLCC socket
U4 MC145406 9 16 1 8 — Driver/receiver
VR1 NMA0512S 2.5 1 6 4 — DC-DC converter
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EPROM/OTPROM (PROM)
EPROM /O TPROM (PROM) P rogram ming
MC68HC705C8A —Rev. 3 T echnical Data
MO TOROLA EP R OM /OTPR OM (PROM )
Figure 9-1. EPROM/OTPROM Programming Flowchart
YES
NO
START
APPLY VPP
NTRYS = 0
START AT BEGINNING
OF MEMO RY
LAT = 1
WRITE PR OM DATA
PGM = 1
WAIT 1 ms
PGM = 0
LAT = 0
WRITE
ADDITIONAL
BYTE
NTRYS = NTRYS + 1
NTRYS = 2
VPP OFF
END
YES
NO
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Technical Data MC68HC705C8A —Rev. 3
106 EPROM /O TPRO M (PR OM)
EPROM/OTPROM (PROM)
Figure 9-2. PROM Programming Circuit
1. The asterisk (*) de notes optio n T
4
2
3
5
1
15
64
2
+
3
30
3
3
P3
18
29
2
2
16 9
14
15
5
6
8
20
1
7
1
26
28
20
25
22
24
21
23
2
+12 V
OFF
ON
S1
P1
+5 V
+12 V
–12 V
VPP
GND
RXD
TXD
CTS
DSR
DCD
DTR
GND
GND
U4
MC145406
+12 V –12 V
+5 V
ON
OFF
VR1 NMA 0512S
DC- DC CONVERT E R
(OPTIONAL)
VCC 0 V
+V –VGND
–12 V
D1
1N4001
PD1
PD0
U1
2764
VPP
+5 V
NC
VCC
C5
0.1 µF
PGM
CE
(A10)
(A11)
(A12)
A8
A9
A10
A11
OE GND
14
D0
10
9
8
7
6
5
4
3
(A0)
(A1)
(A2)
(A3)
(A4)
(A5)
(A6)
(A7)
11
12
13
15
16
17
18
19
R15
10 K
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
40
VDD
VPP
PD1
PD0
PA0
11
10
9
8
7
6
5
4
12
13
14
15
16
17
18
19
20
VSS
PB1
PB0
PA7
PA6
PA5
PA4
PA3
PA2
U2
40-PI N DIP
SOCKET
PA1
+5 V
C1
100 µF
OSC1 39
OSC2 38
RESET 1
IRQ 2
TCAP 37
PD7 36
TCMP 35
PD5 34
PD4 33
PD2
32
31
PC5
PC6
PC0
PC1
PC2
PC3
PC4
23
22
28
27
26
25
24
(A8)
(A9)
(A10)
(A11)
(A12)
PC7 21
M
N
L
K
J
I
H
G
F
E
D
C
B
A
(ENABLE)
(A8)
(A9) (D3)
(D2)
(D1)
(D0)
(D4)
(D5)
(D6)
(D7) O
P
Q
R
S
PD3
PB2
PB3
PB4
PB5
PB6
PB7
A0
A1
A2
A3
A4
A5
A6
A7
27
D1
D2
D3
D4
D5
D6
D7
VPP
A12
Notes:
2. Unless otherwise specified, resistors are in ohms,
3. De vice type numbers shown in circuit are for
command only.
±5% 1/4 W; ca pacitors are in µF; voltages are dc.
reference only. Device type number varies
with manufacturer.
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EPROM/OTPROM (PROM)
EPROM /O TPROM (PROM) P rogram ming
MC68HC705C8A —Rev. 3 T echnical Data
MO TOROLA EP R OM /OTPR OM (PROM )
Figure 9-2. PROM Programming Circuit (Continued)
123
12
A
B
C
D
E
F
G
H
I
J
K
L+5 V
R10*
470
DS2*
M
N
VERF
(VERF)
(PROG)
PROG
DS1*
R11*
470
+5 V
O
P
Q
R
S
(D4)
(D3)
(D2)
(D1)
(D0)
(A0)
(A1)
(A2)
(A3)
(A4)
(A5)
17
15
16
14
13
12
11
10
9
8
7
PB4
PB3
PB2
PB1
PB0
PA0
PA1
PA2
PA3
PA4
PA5
C4
22 pF
R5
10 M
C3
22 pF
2.0 MH z
Y1 R13
10 K
+5 V
+5 V R3 10 K
R9
10 K R8
10 K R7
10 K R6
10 K
PA6
PA7
V
PP
NC
IRQ
RESET
V
DD
OSC1
OSC2
TCAP
NC
PD7
TCMP
PD5
PD4
PD3
PD2
PD1
PD0
PC0
PC1
PC2
U3
44-LE AD P LCC
SOCKET
C6
0.1 µF
NC
PB5
PB6
PB7
V
SS
NC
PC7
PC6
PC5
PC4
PC3
39
38
37
36
35
34
33
32
31
30
29
18
NC
19
20
21
22
23
24
25
(PROG)26
27
28
(VERF)
(D5)
(D6)
(D7)
NC
(A12)
(A11)
(A10)
(A9)
(A8)
PD0
PD1
PD2
PD3
PD4
PD5
(A6)6(A7)5
4
3
NC
2
1
44
43
42
41
40
NC
+5 V
PC7
PC6
PC5
PD0
PD1
PC4
PC3
PC2
PC1
PC0
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
TCMP
TCAP 37
35
12
13
14
15
16
17
18
19
11
10
9
8
7
6
5
4
28
27
26
25
24
30
29
23
22
21
R12
10 K
PD7
PD2
PD3
PD4
PD5 34
33
32
31
36
S6S5S4S3
+5 V
J2
+5 V IRQ
RESET
2
+5 V
R4
10 K
40
39
38
3
1
P2
NC
NC
NC
NC
NC
+12 V
R2
10 K
2.7 K
R1
NC
OUT
1.0 µF
C2 S2
J1
20
VSS
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Technical Data MC68HC705C8A —Rev. 3
108 EPROM /O TPRO M (PR OM)
EPROM/OTPROM (PROM)
To program the PROM MCU, the MCU is installed in the PCB, along with
an EPROM device programmed with user code; the MCU is then
subjected to a series of routines. The routines necessary to program,
verify, and secure the PROM MCU are:
•Program and verify PROM
•Verify PROM contents only
•Secure PROM and verify
•Secure PROM and dump through the serial communications
interface (SCI)
Other board routi nes available to the user are:
•Load program into random-access memory (RAM) and execute
•Execute program in RAM
•Dump PROM contents (binary upload)
The user first configures the MCU for the bootstrap mode of operations
by installing a fabricated jumper across pins 1 and 2 of the board’s mode
select header, J1. Next, the board’s mode switches (S3, S4, S5, and S6)
are set to determine the routine to be executed after the next reset, as
shown in Table 9-2.
Table 9-2. PROM Pr ogra mming Routin es
Routine S3S4S5S6
Program an d verify PROM Off Off Off Off
Veri fy PROM cont ents only Off Off On Off
Secure PRO M cont ents and verify On Off O n O ff
Secure PRO M contents and dum p On On On O ff
Load program into RAM and execute Off On Off Off
Execute program in RAM Off Of f Off On
Dump PROM contents Off On On Of f
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EPROM/OTPROM (PROM)
EPROM /O TPROM (PROM) P rogram ming
MC68HC705C8A —Rev. 3 T echnical Data
MO TOROLA EP R OM /OTPR OM (PROM )
9.3.1 Program Register
The program register (PROG) shown in Figure 9-3 is used for PROM
programming.
LAT — Latch Enable Bit
This bit is both readable and writable.
1 = Enables PROM data and address bus latches for programming
on the next byte write cycle
0 = Latch disabled. P ROM dat a and address buses are unla t ched
for normal CPU operations.
PGM — Program Bit
If LAT is cleared, PGM cannot be set.
1 = Enables VPP power to the PROM for programming
0 = VPP is disabled.
Bits 1 and 3−7 — Not used; always read 0
Address: $001C
Bit 7654321Bit 0
Read: 00000LAT0PGM
Write:
Reset:00000000
Figure 9-3. Program Register (PROG)
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Technical Data MC68HC705C8A —Rev. 3
110 EPROM /O TPRO M (PR OM)
EPROM/OTPROM (PROM)
9.3.2 Preprogramming Steps
Before programming the PROM using an MC68HC05PGMR PCB in
standalone mode, the user should ensure that:
•A jumper is installed on pins 1 and 2 of mode select header J1.
•An EPROM is programmed with the necessary user code.
•The erasure window (if any) of the device to be programmed is
covered.
• VDD of +5 Vdc is available on the board.
• VPP is available on the board.
NOTE: If the VPP level at the MCU exceeds +16 Vdc, then the MC68HC705C8A
MCU device will suffer permanent damage.
Once those cond itions are met, the user should take these steps be fore
beginning programming:
1. Remove the VPP power source.
2. Set switch 1 in the OFF position (removes V DD).
3. Place the programmed EPROM in socket U1.
4. Insert the erased PROM MCU device to be programmed in the
proper socket:
–MC68HC705C8S or MC68HC705C8P in socket U2 (40-pin
dual in-line package (DIP)) or
–MC68HC705C8FN in socket U3 (44-pin plastic leaded chip
carrier (P LCC ) ) with the de vice no tch a t th e up per ri gh t co rner
of the socket.
5. Set switch S2 in the RESET position.
NOTE: N o PROM MC U sho uld be inserted in or re moved from i ts bo ard so cket
(U2 or U3) while VPP (P1, slot 5) or VDD (switch 1) is active on the board.
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EPROM/OTPROM (PROM)
PROM Program ming Routines
MC68HC705C8A —Rev. 3 T echnical Data
MO TOROLA EP R OM /OTPR OM (PROM )
9.4 PROM Programming Routines
This subsection describes the routines necessary to program, verify, and
secure the PROM device, and other routines available to the user.
9.4.1 Program and Verify PROM
The program and verify PROM routine copies the contents of the
external EPROM into the MCU PROM with direct correspondence
between the addresses. Memory addresses in the MCU that are not
implemented in PROM are skipped. Unprogrammed addresses in the
EPROM being copied should contain $00 bytes to speed up the
programming process.
To run the program and verify the PROM routine on the PROM MCU,
take these steps:
1. Set switch 1 in the ON position (restores VDD).
2. Restor e the VPP power source.
3. Set switches S3, S4, S5, and S6 in the OFF position (selects
proper routine).
4. Set switch 2 in the OUT position (routine is activated).
The re d light-emitting d iode (LED) is illum inated, showing tha t the
programming part of the routine is running. The LED goes out
whe n pro gram ming is finished. The veri ficatio n par t of the routi ne
now begins. When the green LED is illuminated, verification is
successfully completed and the routine is finished.
5. Set switch 2 in the RESET position.
At this point, if no other MCU is to be programmed or secured, remove
VPP power from the board. If another routine is to be performed on the
MCU being programmed, the user can then set switches S3, S4, S5, and
S6 to the positions necessary to select the next routine, and begin the
routine by setting switch 2 to the OUT positi on. If no other routine is to
be performed, remove VDD from the board and remove the MCU from
the programming socket.
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Technical Data MC68HC705C8A —Rev. 3
112 EPROM /O TPRO M (PR OM)
EPROM/OTPROM (PROM)
9.4.2 Verify PROM Contents
The verify PROM contents routine is normally run automatically after the
PROM is programmed. Direct entry to this routine causes the PROM
contents of the MCU to be compared to the contents of the external
memory locations of the EPROM at the same addresses.
To invoke the verify PROM contents routine of the MCU, take these
steps:
1. Set switch 1 in the ON position (restores VDD).
2. Connect VPP to VDD.
3. Set switches S3, S4, and S6 in the OFF position.
4. Set S5 in the ON position.
5. Set switch 2 in the OUT position (routine is activated).
The red LED is not illuminated during this routine, since no
programming takes place. If verification fails, the routine halts with
the failing address in the external memory bus. When the green
LED is illuminated, verification is completed succe ssfully and the
routi ne is finished.
6. Set switch 2 in the RESET position.
At this point, if another routine is to be performed on the MCU being
programmed, the user can set switches S3, S4, S5, and S6 to the
positions necessary to select the next routine and move switch S2 to the
OUT position to start the routine. If no other routine is to be performed,
remove VDD from the board and remove the MCU from the programming
socket.
9.4.3 Secure PROM
The secure PROM routines are used after the PROM is successfully
programmed and verified. Only the SEC bi t of the option register
($1FDF) is programmed, but VPP is necessary. Once this bit is
progr amm ed, P ROM is se cure a nd can be ne it her verified nor dumped.
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EPROM/OTPROM (PROM)
PROM Program ming Routines
MC68HC705C8A —Rev. 3 T echnical Data
MO TOROLA EP R OM /OTPR OM (PROM )
9.4.4 Secure PROM and Verify
This routine is used after the PROM is programmed successfully to
verify the contents of the MCU PROM against the contents of the
EPRO M and t hen to se cure the PROM . To a ccomplish this routine , take
these steps:
1. Set switch 1 in the ON position (restores VDD).
2. Restor e VPP power to the programming board.
3. Set switches S4 and S6 in the OFF position.
4. Set switches S3 and S5 in the ON position.
5. Set switch 2 in the OUT position (routine is activated).
Execution time for this routine is about one second.
6. Set switch 2 in the RESET po sition when the routine is completed.
No LED is illum inated dur ing this routine. Further, the end of the routine
does not mean that the SEC bit was verified. To ensure that security is
proper l y enab led, at tempt to perfor m another verify r outi ne . If th e gre en
LED does not light, the PROM has been secured properly.
9.4.5 Secure PROM and Dum p
This routine is used after the PROM is successfully programmed to
dump the contents of the MCU PROM through the SCI (binary upload)
and then to secure the PROM. To accomplish this routi ne, take these
steps:
1. Set switch 1 in the ON position (restores VDD).
2. Restor e VPP power to the programming board.
3. Set switch S6 in the OFF position.
4. Set switches S3, S4, and S5 in the ON position.
5. Set switch 2 in the OUT position (routine is activated).
Execution time for this routine is about one second.
6. Set switch 2 in the RESET po sition when the routine is completed.
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Technical Data MC68HC705C8A —Rev. 3
114 EPROM /O TPRO M (PR OM)
EPROM/OTPROM (PROM)
No LED is illum inated dur ing this routine. Further, the end of the routine
does not mean that the SEC bit was verified. To ensure that security is
proper l y enab led, at tempt to perfor m another verify r outi ne . If th e gre en
LED does not light, the PROM has been secured properly.
9.4.6 Load Program into RAM and Execute
In the load program in RAM and execute routine, user programs are
loaded via the SCI port and then executed. Data is loaded sequentially
starting at address $0050. After the last byte is loaded, control is
transfer red to the RAM p rogr am st arti ng at $00 51. T he first byte l oad ed
is the count of the total number of bytes in the program plus the count
byt e. The pr ogram starts at location $0 051 in RAM. During initial ization,
the SCI is configur ed for eigh t data bits and one stop bit. The ba ud rate
is 4800 with a 2-MHz crystal or 9600 with a 4-MHz crystal.
To load a program into RAM and execute it, take these steps:
1. Set switch 1 in the ON position (restores VDD).
2. Connect VPP to VDD.
3. Set switches S3, S5, and S6 in the OFF position.
4. Set switch S4 in the ON position.
5. Set switch 2 in the OUT position (routine is activated).
The downloaded program starts executing as soon as the last byte is
received by the SCI.
Execution of the routine can be held off by setting the byte count in the
count byte (the first byte loaded) to a value greater than the number of
bytes to be loaded. After loading the la st byte, the firmware waits for
more data. Program execution does not begin. At this point, placing
switch 2 in the RESET position resets the MCU with the RAM data intact.
Any other routine can be entered, including the one to execute the
program in RAM, simply by setting switches S3–S6 as ne cessary to
select the desired routine, then setting switch 2 in the OUT position.
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EPROM/OTPROM (PROM)
PROM Program ming Routines
MC68HC705C8A —Rev. 3 T echnical Data
MO TOROLA EP R OM /OTPR OM (PROM )
9.4.7 Execute Program in RAM
This routine allows the MCU to transfer control to a program previously
loaded in RAM. This program is executed once bootstrap mode is
entered, if switch S6 is in the ON position and switch 2 is in the OUT
position, without any firmware initialization. The program must start at
location $0051 to be compatible with the load program in RAM routine.
To run the execute program in RAM routine, take these steps:
1. Set switch 1 in the ON position (restores VDD).
2. Connect VPP to VDD.
3. Set switch S6 in the OFF position.
4. Switches S3, S4, and S5 can be in either position.
5. Set switch 2 in the OUT position (routine is activated).
NOTE: T he non-pr ogramma ble watchd og COP is di sabled in bootl oader mo de,
even if the NCOPE bit is programmed.
9.4.8 Dump PROM Contents
In the dump PROM contents routine, the PROM contents are dumped
sequentially to the S CI output, provided the PROM has not been
secured. The first location sent is $0020 and the last location sent is
$1FFF. Unused lo cations are skipped so that no gaps exist in the data
stream. The external memory address lines indicate the current location
being sent. Data is sent with eight data bits and one stop bit at 4800 baud
with a 2-MHz crystal or 9600 baud with a 4-MHz crystal.
To run the dump PROM contents routine, take these steps:
1. Set switch 1 in the ON position (restores VDD).
2. Connect VPP to VDD.
3. Set switches S3 and S6 in the OFF position.
4. Set switches S4 and S5 in the ON position.
5. Set switch 2 in the OUT position (routine is activated).
6. Once PROM dumping is complete, set switch 2 in the RESET
position.
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Technical Data MC68HC705C8A —Rev. 3
116 EPROM /O TPRO M (PR OM)
EPROM/OTPROM (PROM)
9.5 Control Registers
This subsection describes the three registers that control memory
confi gura tion, PROM security, and IRQ edge or leve l sensitivit y; port B
pullups; and non-programmable COP enable/disable.
9.5.1 Option Register
The option register shown in Figure 9-4 is used to select the IRQ
sensitivity, enable the PROM security, and select the memory
configuration.
RAM0 — Random-Access Memory Control Bit 0
1 = Maps 32 bytes of RAM into page zero starting at address
$0030. Addresse s fr om $ 0020 to $002F a re reser ved. Thi s bit
can be read or written at any time, allowing memory
configuration to be changed during program execution.
0 = Provides 48 bytes of PROM at location $0020–$005F.
RAM1 — Random-Access Memory Control Bit 1
1 = Maps 96 bytes of RAM into page one starting at address $0100.
This bit can be read or written at any time, allowing memory
configuration to be changed during program execution.
0 = Provides 96 bytes of PROM at location $0100.
Address: $1FDF
Bit 7654321Bit 0
Read: RAM0 RAM1 0 0 SEC*IRQ 0
Write:
Reset:0000*U10
*Implemented as an EPROM cell
= Unimplemented U = Unaffected
Figure 9-4. Option Register (Option)
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EPROM/OTPROM (PROM)
Control Registers
MC68HC705C8A —Rev. 3 T echnical Data
MO TOROLA EP R OM /OTPR OM (PROM )
SEC — Security Bit
This bit is implemented as an EPROM cell and is not affected by
reset.
1 = Security enabled
0 = Security off; bootloader able to be enabled
IRQ — Interrupt Request Pin Sensitivit y Bit
IRQ is set only by reset, but can be cleared by software. This bit can
only be written once.
1 = I RQ pin is both negative edge- and level-sensitive.
0 = I RQ pin is negative edge-sensitive only.
Bits 5, 4, and 0 — Not used; always read 0
Bit 2 — Unaffected by reset; reads either 1 or 0
9.5.2 Mask Option Register 1
Mask option register 1 (MOR1) shown in Figure 9-5 is an EPROM
register that enables the port B pullup devices. Data from MOR1 is
latched on the rising edge of the voltage on the RESE T pin.
See 4 . 3.3 Port B Interr up ts.
PBPU7–PBPU0/COPC — Port B Pullup Enable Bits 7–0
These EPROM bits enable the port B pullup devices.
1 = Port B pullups enabled
0 = Port B pullups disabled
Address: $1FF0
Bit 7654321Bit 0
Read: PBPU7 PBPU6 PBPU5 PBPU4 PBPU3 PBPU2 PBPU1 PBPU0/
COPC
Write:
Reset: Unaffected by reset
Erased:00000000
Figure 9-5. Mask Option Register 1 (MOR1)
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Technical Data MC68HC705C8A —Rev. 3
118 EPROM /O TPRO M (PR OM)
EPROM/OTPROM (PROM)
NOTE: P BPU0/COPC program med to a 1 enables the port B pullup bit. T his b it
is also used to clear the non-programmable COP (MC68HC05C4A
type). Writing to th is bit to clear the COP will not affect the stat e of the
port B pull-up (bit 0). See 5.3.3 Programmable and
Non-Programmable COP Watchdog Resets.
When using the MC68HC705C8A in an MC68HC705C8 or
MC68HSC705C8 application, program locations $1FF0 and $1FF1 to
$00.
9.5.3 Mask Option Register 2
Mask option register 2 (MOR2) shown in Figure 9-6 is an EPROM
regi ster that en ables th e non- pro gram mab le C OP wa tchdog . Data fr om
MOR2 is latched on the rising edge of the voltage on the RES ET pin.
See 5.3.3 Programmable and Non- Programmable COP Watchdog
Resets.
NCOPE — Non-Programmable COP Watchdog E nable Bit
This EPROM bit enables the non-programmable COP watchdog.
1 = Non-programmable COP watchdog enabled
0 = Non-programmable COP watchdog disabled
Address: $1FF1
Bit 7654321Bit 0
Read: NCOPE
Write:
Reset: Unaffected by reset
Erased:00000000
= Unimplemented
Figure 9-6. Mask Option Register 2 (MOR2)
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EPROM/OTPROM (PROM)
EPROM Erasing
MC68HC705C8A —Rev. 3 T echnical Data
MO TOROLA EP R OM /OTPR OM (PROM )
9.6 EPROM Erasing
The erased state of an EPROM or OTPROM byte is $00. EPROM
devices can be erased by exposure to a high intensity ultraviolet (UV)
light wi th a wave length of 2537 Å. The recommended erasure dosage
(UV intensity on a given surface area x exposure time) is 15 Ws/cm2. UV
lamps should be used without short-wave filters, and the EPROM device
should be positioned about one inch from the UV source.
OTPROM devices are shipped in an erased state. Once programmed,
they cannot be erased. Electrical erasing procedures cannot be
performed on either EPROM or OTPROM devices.
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Technical Data MC68HC705C8A —Rev. 3
120 EPROM /O TPRO M (PR OM)
EPROM/OTPROM (PROM)
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MC68HC705C8A —Rev. 3 Tec hnical Data
MOTOROLA Serial Communications Interface (SCI)
Technical Data — MC68HC705C8 A
Section 10. Ser ial Comm unications Interface (SCI)
10.1 Contents
10.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
10.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
10.4 SCI Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
10.5 SCI Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
10.5.1 Transmitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
10.5.2 Receiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
10.6 SCI I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
10.6.1 SCI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
10.6.2 SCI Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
10.6.3 SCI Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
10.6.4 SCI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
10.6.5 Baud Rate Regi ster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136
10.2 Introduction
The serial communications interface (SCI) module allows high-speed
asynchronous communication with peripheral devices and other
microcontroller units (MCUs).
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Technical Data MC68HC705C8A —Rev. 3
122 Serial Communications Interface (SCI)
Serial Communications Interface (SCI)
10.3 Features
Features of the SCI module include:
•Standard mark/space non-return-to-zero format
•Full-duplex operation
•32 programmable baud rates
•Programmable 8-bit or 9-bit character length
•Separately enabled transmitter and receiver
•Two receiver wakeup methods:
–Idle line wakeup
–Address mark wakeup
•Interrupt-driven operation capability with five interrupt flags:
–Transmitter data register empty
–Transmission complete
–Receiver data register full
–Receiver over run
–Idle receiver input
•Receiver framing error detection
•1/16 bit-time noise detection
10.4 SCI Data Format
The SCI uses the standard non-return-to-zero mark/space data format
illustrated in Figure 10-1.
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Serial Communica tions Interface (SCI)
SCI Op eration
MC68HC705C8A —Rev. 3 T echnical Data
MOTOROLA Serial Communications Interface (SCI)
Figure 10-1. SCI Data Format
10.5 SCI Operation
The SCI allows full-duplex, asynchronous, RS232 or RS422 serial
communication between the MCU and remote devices, including other
MCUs. The transmitter and receiver of the SCI operate independently,
although they use the same baud-rate generator. This subsection
describes the operation of the SCI transmitter and receiver.
10.5.1 Transmitter
Figure 10-2 shows the st ructure of th e SCI transmi tter. Fig ure 10- 3 is a
summary of the SCI transmitter input/output (I/O) registers.
•Character Length — The transmitter can accommodate either
8-bit or 9-bi t data. The state of the M bit in SCI control register 1
(SCCR1) determines character length. When transmitting 9-bit
data, bit T8 in SCCR1 is the ninth bit (bit 8).
•Character Transmissi on — During tra nsmission, the tra nsmit shift
register shifts a character ou t to the PD1/TDO pin. The SCI data
register (SCDR) is the write-only buffe r between the internal data
bus and the transmit shift register.
8-BI T DAT A FORM AT
(BIT M IN SCCR 1 CLE AR)
9-BI T DAT A FORM AT
(BIT M IN SCCR 1 S E T)
START
BIT B IT 0 B IT 1 B IT 2 B IT 3 BIT 4 BIT 5 B IT 6 B IT 7 B IT 8 STOP
BIT
NEXT
START
BIT
BIT 0 BIT 1 B IT 2 BIT 3 BIT 4 B IT 5 B IT 6 B IT 7
START
BIT STOP
BIT
NEXT
START
BIT
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Technical Data MC68HC705C8A —Rev. 3
124 Serial Communications Interface (SCI)
Serial Communications Interface (SCI)
Figure 10-2. SCI Transmitter
SCDR ($00 11)
TRAN SMIT SHIFT RE GIST ER
7 6 5 4 3 2 1 08H L
TRANSMITTER
CO NTR O L L O GIC
LOAD FROM SC DR
SH IFT ENABL E
PREAMBLE (ALL LOGIC 1s)
BREAK (ALL LOGIC 0s)
PIN BUF FE R
AND CONTROL PD1/
TDO
SC I RECEIV E
REQUESTS
SCI INT E RRUPT
REQUEST
1X
BA UD RATE
CLOCK
SCCR1 ($000E)
SCCR 2 ($ 000 F)
SCSR ($0010)
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
TDRE
TC
RDRF
IDLE
OR
NF
FE
R8
T8
M
WAKE
TIE
TDRE
TC
TCIE
INTERNAL DATA B US
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Serial Communica tions Interface (SCI)
SCI Op eration
MC68HC705C8A —Rev. 3 T echnical Data
MOTOROLA Serial Communications Interface (SCI)
Writing a logic 1 to the TE bit in SCI control register 2 (SCCR2) and
then writing data to the SCDR begins the transmission. At the start
of a transmission , transmitter control logi c automa tically loads the
transmit shift register with a preamble of logic 1s. After the
preamble shifts out, the contro l logic transfers the SCDR data into
the shift register. A logic 0 start bit automatically goes into the least
significant bit (LSB) position of the shift register, and a logic 1 stop
bit goes into the most significant bit (MSB) position.
When th e data in th e SCDR transfers to th e transmit shift re gister ,
the transmit data register empty (TDRE) flag in the SCI status
register (SCS R) becomes set. The TDRE flag indicates that the
SCDR can accept new data from the internal data bus.
When the shift register is not transmitting a character, the
PD1/T DO pi n goes to t he id le condition, logic 1. If softw are clear s
the TE bit during the idle condition, and while TDRE is set, the
transmitter relinquishes control of the PD1/TDO pin.
Addr. Regist e r Na me Bi t 7 6 5 4 3 2 1 Bit 0
$000D Baud Rate Register
(Baud)
See page 136 .
Read: SCP1 SCP0 SCR2 SCR1 SCR0
Write:
Reset: U U 0 0 U U U U
$000E SCI C ontrol Register 1
(SCCR1)
See page 130 .
Read: R8 T8 M WAKE
Write:
Reset: U U U U
$000F SCI C ontrol Register 2
(SCCR2)
See page 131 .
Read: TIE TCIE RIE ILIE TE RE RWU SBK
Write:
Reset: 0 0 0 0 0 0 0 0
$0010 SCI Status Register
(SCSR)
See page 133 .
Read: TDRE TC RDRF IDLE OR NF FE
Write:
Reset: 1 1 0 0 0 0 0 U
$0011 SCI Da ta Register
(SCDR)
See page 129 .
Read: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Write:
Reset: Unaff ected by reset
= Unimplemented U = Unaffected
Figure 10-3. SCI Transmitter I/O Register Summary
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Technical Data MC68HC705C8A —Rev. 3
126 Serial Communications Interface (SCI)
Serial Communications Interface (SCI)
•Break Characters — Writing a logic 1 to the SBK bit in SCCR2
loads the shift register with a break character. A break character
contains all logic 0s and has no start and stop bits. Break
characte r length depe nds on the M bit in SCCR1. A s lo ng as SBK
is at logic 1, transm itter logic con tinuously loads break char acters
into the shift register. After software clears the SBK bit, the shift
register finishes transmitting the last break character and then
transmits at least one logic 1. The automatic logic 1 at the end of
a break char acter is to guarant ee the recogni tion of the start bit of
the next character.
•Idle Characters — An idle character contains all logic 1s and has
no start o r stop bi ts. Idle ch aract er len gth dep ends o n the M bit i n
SCCR1. The preamble is a synchronizing idle character that
begins every transmission.
Clearing the TE bit during a transmission relinquishes the
PD1/TDO pin after the last character to be transmitted is shifted
out. The last character may already be in the shift register, or
waiting in the SCDR, or it may be a break character gen erated by
writ in g to the S BK bit. T oggling TE from logic 0 t o logic 1 while th e
last character is in transmission generates an idle character (a
preamble) that allows the receiver to maintain control of the
PD1/TDO pin.
•Transmitter Interrupts — These sources can generate SCI
transmitter interrupt requests:
–Transm it Data Register Emp ty (TDRE ) — The TDRE bit in the
SCSR indicates that the SCDR has transferred a character to
the transmit shift register. TDRE is a source of SCI interrupt
requests. The transmission complete interr upt enable bit
(TCIE) in SCCR2 is the local mask for TDRE inte rru pts.
–Transmission Complete (TC) — The TC bit in the SCSR
indicates that both the transmit shift register and the SCDR are
empty and that no break or idle character has been gen erated.
TC is a source of SCI interrupt requests. The transmission
complete interrupt enable bit (TCIE) in SCCR2 is the local
mask for T C interrupts.
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Serial Communica tions Interface (SCI)
SCI Op eration
MC68HC705C8A —Rev. 3 T echnical Data
MOTOROLA Serial Communications Interface (SCI)
10.5.2 Receiver
Fi gu re 10-4 shows the structure of the SCI receiver. Refer to
Fi gu re 10-3 for a summary of the SCI receiver I/O registers.
Figu re 10-4 . SCI Re ceive r
RECEI VE SHIFT REGIST ER
7 6 5 4 3 2 1 08
PIN BUF FE R
AND CONTROL
PD0/
RDI
16X
BA UD RATE
CLOCK
DATA
RECOVERY
STOP
START
÷16
IDLE
WAKEUP
LOGIC
SCS R ($00 10)
TDRE
TC
RDRF
IDLE
OR
NF
FE
SCDR ($0011)SCCR1 ($000 E)
R8
T8
M
WAKE
SCCR 2 ($000F )
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
MSB RDRF OR
RDRF
RIE
IDLE
ILIE
OR
RIE
SCI TRANSMIT
REQUESTS
SC I INT E RRU P T
REQUEST
INTE RNAL DAT A BUS
RE
M
DISABLE
DRIVER
INTERNAL DATA BUS
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Technical Data MC68HC705C8A —Rev. 3
128 Serial Communications Interface (SCI)
Serial Communications Interface (SCI)
•Character Length — The receiver can accommodate either 8-bit
or 9-bit data. The state of the M bit in SCI control register 1
(SCCR1) determines cha racter len gth. When receiving 9-bit data ,
bit R8 in SCCR1 is the ninth bit (bit 8).
•Character Reception — During reception, the receive shift register
shifts characters in from the PD0/RDI pin. The SCI data register
(SCDR) is the read-only buffer between th e internal data bus and
the receive shift register.
After a complete character shifts into the receive shift register, the
data portion of the character is transferred to the SCDR, setting
the receive data register full (RDRF) flag. The RDRF flag can be
used to generate an interrupt.
•Receiver Wakeup — So that the MCU can ignore transmissions
intended only f or other rece ivers in multiple-re ceiver systems, the
MC U can be pu t into a st andby state. Setting the receiver wakeup
enable (RWU) bit in SCI control register 2 (SCCR2) p uts the MCU
into a standby state during which receiver interrupts are disabled.
Either of two conditions on the PD0/RDI pin can bring the MCU out
of the standby state:
–Idle input line cond i tion — If the P D0/RD I pin is at l ogic 1 long
enough for 10 or 11 logic 1s to shift into the receive shift
register, receiver interrupts are again enabled.
–Address mark — If a logic 1 occurs in the most significant bit
position of a received character, receiver interrupts are again
enabled.
The state of the WAKE bit in SCCR1 determines which of the two
conditions wakes up the MCU.
•Receiver Noise Immunity — The data recovery logic samples
each bit 16 times to identify and verify the start bit and to detect
noise. Any conflict between noise detection samples sets the
noise flag (NF) in the SCSR. The NF bit is set at the same time
that the RD RF bit is set.
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Serial Communica tions Interface (SCI)
SCI I/O Registers
MC68HC705C8A —Rev. 3 T echnical Data
MOTOROLA Serial Communications Interface (SCI)
•Framing Errors — If the data recovery logic does not detect a logic
1 where the stop bit should be in an incoming character, it sets the
framing error (FE) bit in the SCSR. The FE bit is set at the same
time that th e RDRF bit is set.
•Receiver Inter rupts — These sources can generate SCI receiver
interrupt requests:
–Receive Data Register Full (RDRF) — The RDRF bit in the
SCSR indicates that the receive shift register has transferred a
character to th e SCDR.
–Receiver Overrun ( OR) — The OR bit in the SCSR indicates
that the receiv e shift register shifted i n a new character before
the previous character was read from the SCDR.
–Idle Input (IDLE) — The IDLE bit in the SCSR indicates that 10
or 11 consecutive logic 1s shifted in from the PD0/RDI pin.
10.6 SCI I/O Registers
These I/O registers control and monitor SCI operation:
•SCI data register (SCDR)
•SCI control register 1 (SCCR1)
•SCI control register 2 (SCCR2)
•SC I status register (SCSR)
10.6.1 SCI Data Register
The SCI data register (SCDR) shown in Figure 10-5 is the buffer for
characters received and for characters transmitted.
Address: $0011
Bit 7654321Bit 0
Read: Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
Write:
Reset: Unaffected by reset
Figure 10-5. SCI Data Register (SCDR)
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Technical Data MC68HC705C8A —Rev. 3
130 Serial Communications Interface (SCI)
Serial Communications Interface (SCI)
10.6.2 SCI Control Regist er 1
SCI control register 1 (SCCR1) shown in Figur e 10-6 has these
functions:
•Stores ninth SCI data bit received and ninth SCI data bit
transmitted
•Controls SCI char acter length
•Controls SCI wakeup method
R8 — Bit 8 (Received)
When the SCI is receiving 9-bit characters, R8 is the ninth bit of the
received character. R8 receives the ninth bit at the same time that the
SCDR receives the other eight bits. Reset has no eff ect on the R8 bit.
T8 — Bit 8 (Transmitted)
When the SCI is tra nsmitting 9-bit characters, T8 is the ninth bit of the
transmitted character. T8 is loaded into the transmit shift register at
the same time that SCDR is loaded into the transmit shift register.
Reset has no effect on the T 8 bit.
M — Character Length Bit
This read/write bit determines whether SCI characters are eight or
nine bits long. The ninth bit can be used as an extra stop bit, as a
receiver wakeup signal, or as a mark or space parity bit. Reset has no
effect on the M bit.
1 = 9-bit SCI characters
0 = 8-bit SCI characters
Address: $000E
Bit 7654321Bit 0
Read: R8 T8 MWAKE
Write:
Reset:UU UU
= Unimplemented U = Unaffected
Figure 10-6. SCI Cont ro l Register 1 (SCCR1 )
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Serial Communica tions Interface (SCI)
SCI I/O Registers
MC68HC705C8A —Rev. 3 T echnical Data
MOTOROLA Serial Communications Interface (SCI)
WAKE — Wakeup Bit
This read/write bit determines which condition wakes up the SCI: a
logic 1 (address mark) in the most significant bit position of a received
characte r or an idle condi tion of the PD0/RDI pin. Reset has no effect
on the WAKE bit.
1 = Address mark wakeup
0 = Idle line wakeup
10.6.3 SCI Control Regist er 2
SCI control register 2 (SCCR2) shown in Figur e 10-7 has these
functions:
•Enables the SCI receiver and SCI receiver interrupts
•Enables the SCI transmitter and SCI transmitter interrupts
•Enables SCI receiver idle interr upts
•Enables SCI transmission complete interrupts
•Enables SCI wakeup
•Transmits SCI break characters
TIE — Transmit Interrupt Enable Bit
Thi s read/w rite bit enabl es SCI inter rupt requests w hen the TDRE bit
becomes set. Reset clears the TIE bit.
1 = TDRE interrupt requests enabled
0 = TDRE interrupt requests disabled
Address: $000F
Bit 7654321Bit 0
Read: TIE TCIE RIE ILIE TE RE RWU SBK
Write:
Reset:00000000
Figure 10-7. SCI Cont ro l Register 2 (SCCR2 )
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Technical Data MC68HC705C8A —Rev. 3
132 Serial Communications Interface (SCI)
Serial Communications Interface (SCI)
TCIE — Transmission Complete Interrupt Enable Bit
This read/write bit enables SCI interrupt requests when the TC bit
becomes set. Reset clears the TCIE bit.
1 = TC interr upt requests enabled
0 = TC interr upt requests disabled
RIE — Receive Interrupt Enable Bit
This read /write bit enables SCI interrupt requ ests when the RDRF bit
or the OR bit becomes set. Reset clears the RIE bit.
1 = RDRF interrupt requests enab le d
0 = RDRF interrupt requests disabled
ILIE — Idle Line Interrupt Enable Bit
This read/write bit enables SCI interrupt requests when the IDLE bit
becomes set. Reset clears the ILIE bit.
1 = IDLE interrupt requests enabled
0 = IDLE interrupt requests disabled
TE — Transmit Enable Bit
Setting this read/write bit begins the transmission by sending a
preamble of 10 or 11 logic 1s from the transmit shift register to the
PD1/TDO pin. Reset clears the TE bit.
1 = Transmission enabled
0 = Transmission disabled
RE — Receive Enable Bit
Setting this read/write bit enables the receiver. Clearing the RE bit
disables the receiver and receiver interrupts but does not affect the
receiver interrupt flags. Reset clears the RE bit.
1 = Receiver enabled
0 = Receiver disabled
RWU — Receiver Wakeup Enable Bit
This read/wri te bit p uts the r eceiver in a standb y state. Typically, data
transmitted to the receiver clears the RWU bit and returns the receiver
to normal operation. The WAKE bit in SCCR1 determines whether an
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Serial Communica tions Interface (SCI)
SCI I/O Registers
MC68HC705C8A —Rev. 3 T echnical Data
MOTOROLA Serial Communications Interface (SCI)
idle input or an address mark brings the receiver out of the standby
state. Reset clears the RWU bit.
1 = Standby state
0 = No rma l operati on
SBK — Send Break Bit
Setting this read/write bit continuously transmits break codes in the
form of 10- bi t or 11-bi t groups of logic 0s. Cl earin g the SBK bit stop s
the bre ak codes and transmits a logic 1 as a start bit. Reset clears the
SBK bit.
1 = Break codes being transmitted
0 = No break codes being transmitted
10.6.4 SCI Status Reg ister
The SCI status register (SCSR) shown in Figure 10-8 contains fl ags to
signal these conditions:
•Transfer of SCDR data to tran smit shift register complete
•Transmission complete
•Transfer of receive shift register data to SCDR complete
•Receiver input idle
•Receiver over run
•Noisy data
•Framing error
Address: $0010
Bit 7654321Bit 0
Read: TDRE TC RDRF IDLE OR NF FE
Write:
Reset:1100000U
= Unimplemented U = Unaffected
Figure 10-8. SCI Status Register (SCSR)
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Technical Data MC68HC705C8A —Rev. 3
134 Serial Communications Interface (SCI)
Serial Communications Interface (SCI)
TDRE — Transmit Data Register Empty Bit
This clearable, read-only bit is set when the data in the SCDR
transfers to the transmit shift register. TDRE generates an interrupt
request if the TIE bit in SCCR2 is also set. Clear the TDRE bit by
reading the SCSR with TDRE set and then writing to the SCDR. Reset
sets the TDRE bit. Software must initialize the TDRE bit to logic 0 to
avoid an instant interrupt request when turning on the transmitter.
1 = SCDR data transferred to transmit shift register
0 = SCDR data not transferred to tr ansmit shift reg iste r
TC — Transmission Complete Bit
This clearable, read-only bit is set when the TDRE bit is set and no
data, preamble, or break character is being transmitted. TC generates
an interrupt req uest if the TCIE bit in SCCR2 is also set . Clear the TC
bit by reading the SCSR with TC set and then wr iting to the SCDR.
Reset sets the TC bit. Software must initialize the TC bit to logic 0 to
avoid an instant interrupt request when turning on the transmitter.
1 = No transmission in progress
0 = Transmission in progress
RDRF — Receive Data Register Full Bit
This clearable, read-only bit is set when the data in the receive shift
register transfers to the SCI data register. RDRF generates an
interrupt request if the RIE bit in SCCR2 is also set. Clear the RDRF
bit by rea ding th e SCSR with RDRF set and then read ing the SCDR.
Reset clears the RDRF bit.
1 = Received data avai lable in SCDR
0 = Received data not available in SCDR
IDLE — Rece iver Idle Bit
This clearable, read-only bit is set when 10 or 11 consecutive logic 1s
appear on the receiver input. IDLE generates an interrupt request if
the ILIE bit in SCCR2 is also set. Clear the IDLE bit by reading the
SCSR with IDLE set, and then reading the SCDR. Reset clears the
IDLE bit.
1 = Receiver input idle
0 = Receiver input not idle
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Serial Communica tions Interface (SCI)
SCI I/O Registers
MC68HC705C8A —Rev. 3 T echnical Data
MOTOROLA Serial Communications Interface (SCI)
OR — Receiver Overrun Bit
This clearable, read- only bit is set if the SCDR is not read be fore the
receive shift register receives the next word. OR generates an
interrupt r equest if the RIE bit in SCCR2 is also set. The data in the
shift registe r is l ost, bu t the d ata alr eady in th e S CDR is n ot affec ted.
Clear the OR bit by reading the SCSR with OR set and then reading
the SCDR. Reset clears the OR bit.
1 = Receiver shift register full and RDRF = 1
0 = No receiver overrun
NF — Receiver Noise Flag Bit
This clearable, read-only bit is set when noise is detected in data
received in the SCI data register. Clear the NF bit by reading the
SCSR and then reading the SCDR. Reset clears the NF bit.
1 = Noi se detected in SCDR
0 = No noise detected in SCDR
FE — Receiver Framing Error Bit
This cle arab le, r ead- only fl ag is set w he n a logic 0 i s loca ted wher e a
stop bit should be in the character shifted into the receive shift
register. If the received word causes both a framing error and an
overrun error, the OR bit is set and the F E bi t is not set. C lea r the FE
bit by reading the SCSR and then reading the SCDR. Reset clears the
FE bit.
1 = Framing error
0 = No framing error
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Technical Data MC68HC705C8A —Rev. 3
136 Serial Communications Interface (SCI)
Serial Communications Interface (SCI)
10.6.5 Baud Rate Register
The baud rate register shown in Figure 10-9 selects the baud rate for
both the receiver and the transmitter.
SCP1 and SCP0 — SCI Prescaler Select Bits
These read/write bits control prescaling of the baud rate generator
clock, as shown in Table 10-1. Resets clear both SCP1 and SCP0.
Address: $000D
Bit 7654321Bit 0
Read: SCP1 SCP0 SCR2 SCR1 SCR0
Write:
Reset:UU00UUUU
= Unimplemented U = Unaffected
Figu re 10-9. Baud Rate Register (Baud)
Table 10-1. Baud Rate Generator Clock Prescaling
SCP[1:0] Baud Rate Gen erato r Clock
00 Internal clock ÷ 1
01 Internal clock ÷ 3
10 Internal clock ÷ 4
11 Int ern al cl ock ÷ 13
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Serial Communica tions Interface (SCI)
SCI I/O Registers
MC68HC705C8A —Rev. 3 T echnical Data
MOTOROLA Serial Communications Interface (SCI)
SCR2–SCR0 — SCI Baud Rate Select Bits
These read/write bits select the SCI baud rate, as shown in
Table 10-2. Reset has no effect on the SCR2–SCR0 bits.
Table 10-3 shows all possible SCI baud rates derived from crystal
frequencies of 2 MHz, 4 MHz, and 4.194304 MHz.
Table 10-2. Baud Rate Selection
SCR[2:1:0] SCI Baud Rate (Baud)
000 Prescal e d clock ÷ 1
001 Prescal e d clock ÷ 2
010 Prescal e d clock ÷ 4
011 Prescale d clock ÷ 8
100 Prescal e d clock ÷ 16
101 Prescaled cloc k ÷ 32
110 Prescaled cloc k ÷ 64
111 Prescaled clock ÷ 128
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Technical Data MC68HC705C8A —Rev. 3
138 Serial Communications Interface (SCI)
Serial Communications Interface (SCI)
Table 10-3. Baud Rate Selection Examples
SCP[1:0] SCR[2:1:0] SCI Baud Rate
fOSC = 2 MH z fOSC = 4 MH z fOSC = 4.194304 MHz
00 000 62.50 Kbaud 125 Kbaud 131.1 Kbaud
00 001 31.25 Kbaud 62.50 Kbaud 65.54 Kbaud
00 010 15.63 Kbaud 31.25 Kbaud 32.77 Kbaud
00 011 7813 baud 15. 63 Kbaud 16.38 Kbaud
00 100 3906 baud 7813 baud 8192 baud
00 101 1953 baud 3906 baud 4096 baud
00 110 976.6 baud 1953 baud 2048 baud
00 111 48 8.3 baud 9 76.6 baud 10 24 baud
01 000 20.83 Kbaud 41.67 Kbaud 43.69 Kbaud
01 001 10.42 Kbaud 20.83 Kbaud 21.85 Kbaud
01 010 5208 baud 10.42 Kbaud 10.92 Kbaud
01 011 2604 baud 5208 baud 5461 baud
01 100 1302 baud 2604 baud 2731 baud
01 101 651.0 baud 1302 baud 1365 baud
01 110 325.5 baud 651.0 baud 682.7 baud
01 111 162. 8 baud 325.5 baud 341.3 baud
10 000 15.63 Kbaud 31.25 Kbaud 32.77 Kbaud
10 001 7813 baud 15.63 Kbaud 16.38 Kbaud
10 010 3906 baud 7813 baud 8192 baud
10 011 1953 baud 3906 baud 4906 baud
10 100 976.6 baud 1953 baud 2048 baud
10 101 488.3 baud 976.6 baud 10 24 baud
10 110 244.1 baud 488.3 baud 512.0 baud
10 111 122. 1 baud 244.1 baud 256.0 baud
11 000 4808 baud 9615 baud 10.08 Kbaud
11 001 2404 baud 4808 baud 5041 baud
11 010 1202 baud 2404 baud 2521 baud
11 011 601.0 baud 1202 baud 1260 baud
11 100 300.5 baud 601.0 baud 630.2 baud
11 101 150.2 baud 300.5 baud 315.1 baud
11 110 75.12 baud 150.2 baud 157.5 baud
11 11 1 37.56 baud 75.12 baud 78.77 baud
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MC68HC705C8A —Rev. 3 Tec hnical Data
MOTOROLA Serial Peripheral Interface (SPI)
Technical Data — MC68HC705C8 A
Section 11. Serial Peripheral Interface (SPI)
11.1 Contents
11.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
11.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
11.4 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142
11.4.1 Pin Functions in Master Mode . . . . . . . . . . . . . . . . . . . . . .143
11.4.2 Pin Functions in Slave Mode . . . . . . . . . . . . . . . . . . . . . . .144
11.5 Multiple-SPI Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145
11.6 Serial Clock Polarity and Phase . . . . . . . . . . . . . . . . . . . . . . .146
11.7 SPI Error Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
11.7.1 Mode Fault Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
11.7.2 Write Collision Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
11.7.3 Overrun Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148
11.8 SPI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148
11.9 SPI I/O Regi sters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148
11.9.1 SPI Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
11.9.2 SPI Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
11.9.3 SPI Status Regi ster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151
11.2 Introduction
The serial peripheral interface (SPI) module allows full-duplex,
synchronous, serial communication with peripheral devices.
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Technical Data MC68HC705C8A —Rev. 3
140 Serial Peripheral Interface (SPI)
Seri al Periph eral Interf ace (SPI)
11.3 Features
Features of the SPI include:
•Full-duplex operation
•Master and slave modes
•Four programmable master mode frequencies (1.05 MHz
maximum)
•2.1-MHz maximum slave mode frequency
•Serial clock with programmable polarity and phase
•End of transmission interrupt flag
•Write collision error flag
•Bus contention error flag
Fi gu re 11-1 shows the structure of the SPI module. Figure 11-2 is a
summary of the SPI input/output (I/O) registers.
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Serial Peripheral Interfac e (SPI)
Features
MC68HC705C8A —Rev. 3 T echnical Data
MOTOROLA Serial Peripheral Interface (SPI)
Figure 11-1. SPI Block Diagram
SPI SHIF T REGISTER
DIVIDER
SPCR ($000A)
7 6 5 4 3 2 1 0
PD4/
SCK
PD3/
MOSI
÷2÷32÷6÷4
SELECT
SPI CONT ROL
S
M
M
S
INTERNAL
CLOCK
(XTAL ÷2)
PIN CONTR O L L O GIC
PD2/
MISO
SPSR ($000B)
SPIF
WCOL
MODF
REQUEST
SPR1
SPR0
SPDR ($000C )
SP I INT ER RUPT INTERNAL
DAT A BU S
SPI CLOC K (M AST ER) CLOCK
LOGIC
MSTR
SPE
M
S
MSTR
SPE
DWOM
SPIE
SPE
DWOM
MSTR
CPHA
CPOL
SPR1
SPR0
SHIFT
CLOCK
SPIE
PD5/
SS
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Technical Data MC68HC705C8A —Rev. 3
142 Serial Peripheral Interface (SPI)
Seri al Periph eral Interf ace (SPI)
11.4 Operation
The master/slave SPI allows full-duplex, synchronous, serial
communication between the microcontroller unit (M CU) and peripheral
devices, including other MCUs. As the 8-bit shift register of a master SPI
transmits each byte to another device, a byte from the receiving device
enters the master SPI shift register. A clock signal from the master SPI
synchronizes data transmission.
Only a master SPI can initiate transmissions. Software begins the
transmission from a master SPI by writing to the SPI data register
(SPDR). The SPDR does not buffer data being transmitted from the SPI.
Data written to th e S PDR g oes dir ectly i nto the sh ift reg ister a nd be gi ns
the transmission immedi ately under the control of the serial clock. The
transmission ends after eight cycles of the serial clock when the SPI flag
(SPIF) becom es set. At the same tim e that SPIF b ecome s set, the data
shifted into the master SPI from the receiving device transfers to the
SPDR. The SPDR buffers data being received by the SPI. Before the
master SPI sends the next byte, software must clear the SPIF bit by
reading the SPSR and then accessing the SPDR.
Addr. Registe r Nam e Bit 7 6 5 4 3 2 1 Bit 0
$000A SPI Control Register
(SPCR)
See page 149.
Read: SPIE SPE MSTR CPOL CPHA SPR1 SPR0
Write:
Reset: 0 0 0 U U U U
$000B SPI Status Register
(SPSR)
See page 151.
Read: SPIF WCOL MODF
Write:
Reset: 0 0 0
$000C SPI Data Register
(SPDR)
See page 149.
Read: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 BIt 2 Bit 1 Bit 0
Write:
Reset: Unaffected by reset
= Unimplemented U = Unaff ected
Figure 11-2. SPI I/O Register Summary
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Serial Peripheral Interfac e (SPI)
Operation
MC68HC705C8A —Rev. 3 T echnical Data
MOTOROLA Serial Peripheral Interface (SPI)
In a slave SPI, data enters the shift register under the control of the serial
clock from the master SPI. After a byte e nters the shift registe r of a slave
SPI, it transfers to the SPDR. To prevent an overrun condition, slave
software must then read the byte in the SPDR before another byte enters
the shift register and is ready to transfer to the SPDR.
Fi gure 11- 3 shows how a master SPI excha nges data with a slave SPI.
Figure 11-3. Master/Slave Connections
11.4.1 Pin Functions in Master Mode
Setting the MSTR bit in the SPI control register (SPCR) configures the
SPI for operation in master mode. The master-mode functions of the SPI
pins are:
•PD4/SCK (serial clock) — In master mode, the PD4/SCK pin is the
synchronizing clock output.
•PD3/MOSI (master output, slave input) — In master mode, the
PD3/MOSI pin is the serial output.
•PD2/MISO (master in put, slave output) — In master mode, the
PD2/MISO pin is configured as the serial input.
•PD5/SS (slave select) — In master mode, the PD5/SS pin protects
against driver contention caused by the simultaneous operation of
two SPIs in master mode. A logic 0 on the PD5/SS pin of a master
SPI disables the SPI, clears the MSTR bit, and sets the mode-fault
flag (MODF).
SPI SHIF T REGISTER
7 6 5 4 3 2 1 0
SPI SHIF T REGISTER
7 6 5 4 3 2 1 0
SP DR ($ 000 C) SP DR ($ 000 C)
PD3/MOSI
PD2/MISO
PD5/SS
PD4/SCK
MASTER MCU SLAVE MCU
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Technical Data MC68HC705C8A —Rev. 3
144 Serial Peripheral Interface (SPI)
Seri al Periph eral Interf ace (SPI)
11.4.2 Pin Functions in Slave Mode
Clearing the MSTR bit in the SPCR configures the SP I for operation in
slave mode. The slave-mode functions of the SPI pins are:
•PD4/SC K (serial clock) — In slave mode, the PD4/S CK pin is the
input for the synchronizing clock signal from the master SP I.
•PD3/MOSI (master output, slave input) — In slave mode, the
PD3/MOSI pin is the serial input.
•PD2/MISO (master in put, slave output) — In slave mode, the
PD2/MISO pin is the serial output.
•PD5/SS (sla ve select) — In slave m ode, the PD5/SS pin enables
the SPI for data and serial clock reception from a master SPI.
When CPHA = 0, the shift clock is the OR of SS with SCK. In this clock
phase mo de, SS must go high between successive characters in an SPI
message. When CPHA = 1, SS may be left low for several SPI
characters. In cases with only one SPI slave MCU, the slave MCU SS
line can be tied to V SS as long as CPHA = 1 clock modes are used.
The WCOL flag bit can be improperly set when attempting the first
transmission after a reset if these conditions are present: MSTR = 0,
CPOL = 0, CPHA = 1, SS pin = 0, and SCK pin = 1. The reset states of
the CPOL and CPHA bits are 0 and 1, respectively. Under normal
operating conditions (CPOL = 0, CPHA = 1), the SCK input will be low.
The incorrect setting of the WCOL bit can be prevented in two ways:
1. Send a dummy transmission after reset, clear the WCOL flag, and
then proceed with the real transmission.
2. Use the MSTR bit in the SPCR (SPI control register). This is
accompl ished by setting th e MSTR bit at the sam e time the CPOL
and C PH A bi ts are pr ogra mme d to the de si red logi c levels . Then ,
the data r egi ster can be writte n to i f desir ed. A fter th is, t he MSTR
bit should be set to a logic 0, the SPE (SPI enable bit) should be
set to a logic 1, and the CP OL, CPHA, SPR1, and SPR0 bits set
to the desired logic levels. If this procedure is followed after a reset
and before the first access to the SPDR, the WCOL flag will not be
set.
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Serial Peripheral Interfac e (SPI)
Multiple-SPI Systems
MC68HC705C8A —Rev. 3 T echnical Data
MOTOROLA Serial Peripheral Interface (SPI)
Example:
LDA #$1C ; MSTR = 1, CPOL = 1, CPHA = 1,
; SPR1 = SPR0 = 0
STA SPCR ; SPI control register
LDA #$4C ; MSTR = 0, SPE = 1, CPOL = 1, CPHA = 1,
; SPR1 = SPR0 = 0
STA SPCR ; SPI control register
11.5 Multi ple -S PI Syst em s
In a multiple-SPI system, all PD4/SCK pins are connected together, all
PD3/MOSI pins are connected together, and all PD2/MISO pins are
connected together.
Befor e a transmission, on e SPI is configu red as master and the re st are
configured as slaves. Figure 11-4 is a block diagram showing a single
master SPI and three slave SPIs.
Figure 11-4. One Master and Three Slaves Block Diagram
Fi gu re 11-5 is another block diagram with two master/slave SPIs and
three slave SPIs.
PD2/MISO
PD3/MOSI
PD4/SCK
PD5/SS
I/O 2
1
0
SLAVE MCU 2 SLAVE M CU 1 SLAVE MCU 0
PD5/SS
PD4/SCK
PD3/MOSI
PD2/MISO
MASTER MCU
PORT
PD5/SS
PD4/SCK
PD3/MOSI
PD2/MISO
PD5/SS
PD4/SCK
PD3/MOSI
PD2/MISO
VDD
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Technical Data MC68HC705C8A —Rev. 3
146 Serial Peripheral Interface (SPI)
Seri al Periph eral Interf ace (SPI)
Figure 11-5. Two Master/Slaves and Three Slaves Block Diagram
11.6 Ser ial Clo ck P ola ri ty an d Phas e
To accommodate the different serial communication requirements of
peripheral devices, software can change the phase and polarity of the
SPI serial clock. The clock pol arity bit (CP OL) and the clock phase bit
(CPHA), both in the SPCR, control the timing relationship betwe en the
serial clock and the transmitted data. Figu re 11- 6 shows ho w the CPOL
and CPHA bits affect the clock/data timing.
Figu re 11-6. SPI Clock/Data Timing
SLAVE MCU 2 SLAVE MCU 1 SLAVE MCU 0
PD5/SS
PD4/SCK
PD3/MOSI
PD2/MISO
MASTER/SLAVE
PD5/SS
PD4/SCK
PD3/MOSI
PD2/MISO
PD5/SS
PD4/SCK
PD3/MOSI
PD2/MISO
PD2/MISO
PD3/MOSI
PD4/SCK
PD5/SS
I/O
0
1
2PORT
3
PD2/MISO
PD3/MOSI
PD4/SCK
PD5/SS
I/O
0
1
2
PORT
3
MCU 1 MASTER/SLAVE
MCU 2
MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSBSDO/SDI
1
0
1
0
SS
1
1
0
0
SCK (D)
SCK (C)
SCK (B)
SCK (A)
CPHA CPOL
CAP TUR E STRO B E
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Serial Peripheral Interfac e (SPI)
SPI Error Conditions
MC68HC705C8A —Rev. 3 T echnical Data
MOTOROLA Serial Peripheral Interface (SPI)
11.7 SPI Error Conditions
These conditions produce SP I system errors:
•Bus contention caused by multiple master SPIs (mode fault error)
•Writing to the SPDR during a transmission (write-collision error)
•Failing to read the SPDR before the next incoming byte sets the
SPIF bit (overrun error)
11.7.1 Mode Fault Error
A mo de fa ul t error results wh en a lo gic 0 oc curs on the P D5/S S pin of a
master SPI. The MCU takes these actions when a mode fault error
occurs:
•Puts the SPI in slave mode by clearing the MSTR bit
•Disables the SPI by clearing the SPE bit
•Sets the MODF bit
11.7.2 Write Collision Error
Writing to t he SPDR during a transmission causes a write collision error
and sets the WCO L bit i n the SP SR. Eithe r a ma ster S PI or a sl a ve SPI
can generate a write collision error.
•Master — A master SPI can cause a write collision error by writing
to the SPDR wh ile the previously written b yte is still being shifted
out to the PD3/MOSI pin. The error does not affect the
transmission of the previously written byte, but the byte that
caused the error is lost.
•Slave — A slave SPI can cause a write collision error in either of
two ways, depending on the state of the CPHA bit:
–CPHA = 0 — A slave SPI can cause a write collision error by
writing to the SPDR while the PD5/SS pin is at logic 0. The
error does not affect the byte in the SPDR, but the byte that
caused the error is lost.
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Technical Data MC68HC705C8A —Rev. 3
148 Serial Peripheral Interface (SPI)
Seri al Periph eral Interf ace (SPI)
–CPHA = 1 — A slave SPI can cause a write collision error by
writing to the SPDR while receivin g a transmissio n, that is,
between the first active SCK edge and the end of the eighth
SCK cycle. The error does not affect the transmission from the
master SPI, but the byte that caused the error is lost.
11.7.3 Overrun Error
Failing to read the byte in the SPDR before a subsequent byte enters the
shift register causes an overrun condition. In an overrun condition, all
incoming data is lost until software clears SPIF. The overrun condition
has no flag.
11.8 SPI Interrupts
The SPIF bit in the SPSR indicates a byte has shifted into or out of the
SPDR. The SPIF bit is a source of SPI interrupt requests. The SPI
interrupt enable bit (SPIE) in the SPCR is the local mask for SPIF
interrupts.
The MODF bit in the SPSR indicates a mode error and is a source of SPI
interrupt requests. The MODF bit is set when a logic 0 occurs on the
PD5/SS pin while the MSTR bit is set. The SPI interrupt enable bit (SPIE)
in the SPCR is the local mask for MODF interrupts.
11.9 SPI I/O Registers
These input/output (I/O) register s control and monitor SPI operation:
•SPI data register (SPDR)
•SPI control register (SPCR)
•SPI status register (SPSR)
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Serial Peripheral Interfac e (SPI)
SPI I/O Registers
MC68HC705C8A —Rev. 3 T echnical Data
MOTOROLA Serial Peripheral Interface (SPI)
11.9.1 SPI Data Register
The SPDR shown in Figure 11-7 is the read buffer for characters
receiv ed by the SPI. Wri ting a b yte to the SPDR places the byte dire ctly
into the SPI shift register.
11.9.2 SPI Control Register
•Enables SPI interrupt requests
•Enables the SPI
•Configures the SPI as master or slave
•Selects serial clock polarity, phase, and frequency
SPIE — SPI Interrupt Enable Bit
This read/write bit enables SPI interrupts. Reset clears the SPIE bit.
1 = SPI interrupts enabled
0 = SPI interrupts disabled
Address: $000C
Bit 7654321Bit 0
Read: Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
Write:
Reset: Unaffected by reset
Figure 11-7. SPI Data Register (SPDR)
Address: $000A
Bit 7654321Bit 0
Read: SPIE SPE MSTR CPOL CPHA SPR1 SPR0
Write:
Reset:00 0UUUU
= Unimplemented U = Unaffected
Figure 11-8. SPI Control Register (SPCR)
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Technical Data MC68HC705C8A —Rev. 3
150 Serial Peripheral Interface (SPI)
Seri al Periph eral Interf ace (SPI)
SPI — SPI Enable Bit
This read/write bit enables the SPI. Reset clears the SPE bit.
1 = SPI enabled
0 = SPI disabled
MSTR — M a ster Bit
This read/write bit selects master mode operation or slave mode
operation. Reset clears the MSTR bit.
1 = Master mode
0 = Slave mode
CPOL — Clock Polarity Bit
This read/write bit determines the logic state of the PD4/SCK pin
between transmissions. To transmit data between SPIs, the SPIs
must have identical CPOL bits. Reset has no effect on the CPOL bit.
1 = PD4/SCK pin at logic 1 between transmissions
0 = PD4/SCK pin at logic 0 between transmissions
CPHA — Clock Phase Bit
This read/write bit controls the timing relationship between the serial
clock and SPI data. To transmit data between SPIs, the SPIs must
have identical CPHA bits. When CPHA = 0, the PD5/SS pin of the
slave SPI must be set to logic 1 between bytes. Reset has no effect
on the CPHA bit.
1 = Edge following first active edge on PD4/SCK latches data
0 = First active edge on PD4/SCK latches data
SPR1 and SPR0 — SPI Clock Rate Bits
These read/write bits select the master mode serial clock rate, as
shown in Table 11-1. The SPR1 and SPR0 bits of a slave SPI have
no effect on th e se ri al clock. Rese t has no ef fect on S P R1 a nd SPR0.
Table 11-1. SPI Clock Rate Selection
SPR[1:0] SPI Clock Rate
00 Internal Clock ÷ 2
01 Internal Clock ÷ 4
10 Internal Clock ÷ 16
11 Internal Clock ÷ 32
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Serial Peripheral Interfac e (SPI)
SPI I/O Registers
MC68HC705C8A —Rev. 3 T echnical Data
MOTOROLA Serial Peripheral Interface (SPI)
11.9.3 SPI Status Register
The SPSR shown in F i gu re 11-9 contains flags to signal these
conditions:
•SPI transm ission complete
•Write collision
•Mode fault
SPIF — SPI Flag
This clearable, read-only bit is set each time a byte shifts out of or into
the shift register. SPIF generates an interrupt request if the SPIE bit
in the SPCR is also set. Clear SPIF by reading the SPSR with SPIF
set and then reading or writing the SPDR. Reset clears the SPIF bit.
1 = Transmission complete
0 = Transmission not complete
WCOL — Write Collisio n Bit
This clearable, read-only flag is set when software writes to the SPDR
while a transmission is in progress. Clear the WCOL bit by reading the
SPSR with WCOL set and then reading or writing the SPDR. Reset
clears WCOL.
1 = Invalid write to SPDR
0 = No invalid write to SPDR
Address: $000B
Bit 7654321Bit 0
Read: SPIF WCOL MODF
Write:
Reset: 0 0 0
= Unimplemented
Figure 11-9. SPI Status Register (SPSR)
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Technical Data MC68HC705C8A —Rev. 3
152 Serial Peripheral Interface (SPI)
Seri al Periph eral Interf ace (SPI)
MODF — Mode Fault Bit
This clearable, read-only bit is set when a logic 0 occurs on the
PD5/SS pin while the MSTR bit is set. MODF generates an interrupt
request if the S PIE bit is also set. Cl ear the MO DF bit by reading the
SPSR with MODF set and then writing to the SPCR. Reset clears
MODF.
1 = PD5/S S pulled low while MSTR bit set
0 = PD5/S S not pu lled low while MSTR bit set
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MC68HC705C8A —Rev. 3 Tec hnical Data
MOTOROLA Instruction Set
Technical Data — MC68HC705C8 A
Section 12. Instruction Set
12.1 Contents
12.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154
12.3 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154
12.3.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
12.3.2 Immediate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
12.3.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
12.3.4 Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
12.3.5 Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156
12.3.6 Indexed, 8-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156
12.3.7 Indexed, 16-Bit Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . .156
12.3.8 Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157
12.4 Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157
12.4.1 Register/Memory Instructions. . . . . . . . . . . . . . . . . . . . . . .158
12.4.2 Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . .159
12.4.3 Jump/Branch Instructions. . . . . . . . . . . . . . . . . . . . . . . . . .160
12.4.4 Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . .162
12.4.5 Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163
12.5 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .164
12.6 Opcode Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169
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Technical Data MC68HC705C8A —Rev. 3
154 Instruction Set
Instruction Set
12.2 Introduction
The MCU instruction set has 62 instructions and uses eight addressing
modes. The instructions include all those of the M146805 CMOS Family
plus one more: the unsigned multiply (MUL) instruction. The MUL
instruction allows unsigned multiplication of the contents of the
accumulator (A) and the index regi ster (X). The high-order product is
stored in the index register, and the low-order product is stored in the
accumulator.
12 .3 Addressin g Mo de s
The CPU uses eight addressing modes for flexibility in accessing data.
The addressing modes provide eight different ways for the CPU to find
the data required to execute an instruction.
The eight addressing modes are:
•Inherent
•Immediate
•Direct
•Extended
•Indexed, no offset
•Indexed, 8-bit offset
•Indexed, 16-bit offset
•Relative
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In stru ction Set
Addressing M odes
MC68HC705C8A —Rev. 3 T echnical Data
MOTOROLA Instruction Set
12.3.1 Inherent
Inherent instructions are those that have no operand, such as return
from i nt err upt ( RTI) a nd sto p (S TOP). So me of the i nh eren t instru cti ons
act on data in the CPU registers, such as set carry flag (SEC) and
increment accumulator (INCA). Inherent instructions require no operand
address and are one byte long.
12.3.2 Immediate
Immediate instructions are those that contain a value to be used in an
operat ion wi th the value in the accumul ator o r index reg ister. Immed iate
instructions require no operand address and are two bytes long. The
opcode is the first byte, and the immediate data value is the second byte.
12.3.3 Direct
Direct instructions can access any of the first 256 memory locations with
two bytes. The first byte is the opcod e, and the second is the low byte of
the operan d address. In di rect addr essing, the CPU autom aticall y uses
$00 as the high byte of the operand address.
12.3.4 Extended
Extended instructions use three bytes and can access any address in
memor y. The fir st byte is the opco de; the seco nd and th ird bytes ar e the
high and low bytes of the operand address.
When using the M otor ola assem bl er, th e prog ram mer does not ne ed to
specify whether an instruction is direct or extended. The assembler
automatically selects the shortest form of the instruction.
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Technical Data MC68HC705C8A —Rev. 3
156 Instruction Set
Instruction Set
12.3.5 Indexed, No Offset
Indexed instructions with no offset are 1-byte instructions that can
access data with variable addresses within the first 256 mem ory
locations. The index register contains the low byte of the effective
address of the operand. The CPU automatically uses $00 as the high
byte, so these instructions can address locations $0000–$00FF.
Indexed, no offset instru ctions are often used t o move a point er through
a table or to hold the address of a frequently used RAM or I/O location.
12.3.6 Indexed, 8-Bit Offset
Indexed, 8-bit offset instru ctions ar e 2- byte in structi o ns tha t can a ccess
data w ith varia bl e addresses w ithin the firs t 511 m emory locations. The
CPU adds the unsigned byte in the index register to the unsigned byte
following the opcode. The sum is the effective address of the operand.
These instructions can access locations $0000–$01FE.
Indexed 8-b it offset instructions are usefu l for selecting the kth element
in an n- element table. The ta ble ca n begin anywhe re within the first 256
memor y locations a nd could extend as far as lo cation 510 ($0 1FE). T he
k value is typically in the index register, and the address of the beginning
of the table is in the byte following the opcode.
12.3.7 Indexed, 16-Bit Offset
Indexed, 16-bit offset instructions are 3-byte instructions that can access
data w ith var iable addresses at any l o cation in m emo ry. T he CP U adds
the unsigned byte in the index register to the two unsigned bytes
following the opcode. The sum is the effective address of the operand.
The first byte after the opcode is the high byte of the 16-bit offset; the
second byte is the low byte of the offset.
Indexed, 16-bit offset instructions are useful for selecting the kth element
in an n-element table anywhere in memory.
As with direct and extended addressing, the Motorola assembler
determines the shortest form of indexed addressing.
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In stru ction Set
Instruction Types
MC68HC705C8A —Rev. 3 T echnical Data
MOTOROLA Instruction Set
12.3.8 Relative
Relative addressing is only for branch instructions. If the branch
condition is true, the CPU finds the effective branch destination by
adding the signed byte following the opcode to the contents of the
program counter. If the branch condition is not true, the CPU goes to the
next instruction. The offset is a signed, two’s complement byte that gives
a branchi ng range of –128 to +127 bytes from the address of the next
location after the branch instruction.
When using the M otor ola assem bl er, th e prog ram mer does not ne ed to
calculate the offset, because the assembler determines the proper offset
and veri fies that it is within the span of the branch.
12.4 Instruction Types
The MCU instructions fall into five categories:
•Register/memory instructions
•Read-modify-write instructions
•Jump/branch instructions
•Bit manipulation instructions
•Control instructions
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Technical Data MC68HC705C8A —Rev. 3
158 Instruction Set
Instruction Set
12.4.1 Register/Memory Instru ctions
These instructions operate on CPU registers and memory locations.
Most of them use two operands. One operand is in either the
accumulator or the index register. The CPU finds the other operand in
memory.
Table 12-1. Register/Memory Instructions
Instruction Mnemonic
Add memory byte and carry bit to acc umu lator ADC
Add memory byte to accumulator ADD
AND memory byte with accumulator AND
Bit test accumulator BIT
Compare accu mulator CMP
Compare index register with memory byte CPX
Exclusive OR accumulator with memory byte EOR
Load accumulator with memory byte LDA
Load Index register with memory byte LDX
Multiply MUL
OR accum ulator wi th memo ry byte ORA
Subtract memory byte and carry bit f rom
accumulator SBC
St ore acc umulator in memor y S TA
Store ind ex register i n memory STX
Subtract memory byte from accumulator SUB
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In stru ction Set
Instruction Types
MC68HC705C8A —Rev. 3 T echnical Data
MOTOROLA Instruction Set
12.4.2 Read-Modify-Write Instru ctions
These instructions read a memory location or a register, modify its
contents, and write the modifi ed value b ack to the memory location o r to
the register.
NOTE: Do not use read-modify-write operations on write-only registers.
Table 12-2. Read-Modify-Write Instructions
Instruction Mnemonic
Arithm etic s hift left (same as LS L) ASL
Arithm etic shift right ASR
Bit clear BCLR(1)
1. Unlike other read-modify-write instructions, BCLR and BSET use
only dir ect addressing.
Bit se t BSET(1)
Clear register CLR
Compl ement (one’s comple ment) COM
Decrement DEC
Increment INC
Logical shift left (same as ASL) LSL
Logical shift right LSR
Negate (two’s complement) NEG
Rotate left through carry bit ROL
Rotate right through carry bit R OR
Test for negative or zero TST(2)
2. TST is an except ion to the read-modify-write sequence because it
does not write a replacement value.
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Technical Data MC68HC705C8A —Rev. 3
160 Instruction Set
Instruction Set
12.4.3 Jump/Branc h Instruct ions
Jump instruct ions allow the CPU to interrupt the normal sequence of the
program counter. The unconditional jump instruction (JMP) and the
jump-to-subroutine instruction (JSR) have no register operand. Branch
instructions allow the C PU to interrupt the normal sequence of the
progr am co unter when a test condit ion is met. If the test condi tio n is n ot
met, the branch is not performed.
The BRCLR and BRSET instruction s cause a branch based on the state
of any readable bit in the first 256 memory location s. These 3-byte
instructions use a combination of direct addressing and relative
addressing. The direct address of the byte to be tested is in the byte
following the opcode. The third byte is the signed offset byte. The CPU
finds the effective branch destination by adding the third byte to the
program counter if the specified bit tests true. The bit to be teste d and its
condition (set or clear) is part of the opcode. The span of branching is
from –128 to +1 27 from the addr ess of the next locatio n after the bran ch
instructi on. The CPU also tr ansfe rs the tested b i t to the carry/borr ow bit
of the condition code register.
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In stru ction Set
Instruction Types
MC68HC705C8A —Rev. 3 T echnical Data
MOTOROLA Instruction Set
Table 12-3. Jump and Branch Instructions
Instruction Mnemonic
Branch if carry bit clear BCC
Branch if carry bit set BCS
Branch if equal BEQ
Branch if half-carry bit clear BHCC
Branch if half-carry bit set BHCS
Branch if higher BHI
Branch if higher or same BHS
Branch if IRQ pin high BIH
Branch if IRQ pin low B IL
Branch if lower BLO
Branch if lower or same BLS
Branch if interrupt mask clear BMC
Branch if minus BMI
Branch if interrupt mask set B M S
Branch if not equal BNE
Branch if plus BPL
Branch always BRA
Branch if bit clear BRCLR
Branch nev er BR N
Branch if bit set BRSE T
Branch to subroutine BSR
Unconditional jump JMP
Jump to subroutine J SR
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Technical Data MC68HC705C8A —Rev. 3
162 Instruction Set
Instruction Set
12.4.4 Bit Man ipulation Instructions
The CPU can set or clear any writable bit in the first 256 bytes of
memory, which includes I/O registers and on-chip RAM locations. The
CPU can al so test and br anch based on th e state of any bit in an y o f the
first 256 memory locations.
Table 12-4. Bit Manipu lation Instructions
Instruction Mnemonic
Bit clear BCLR
Branch if bit clear BRCLR
Branch if bit set BRSET
Bit se t BSET
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In stru ction Set
Instruction Types
MC68HC705C8A —Rev. 3 T echnical Data
MOTOROLA Instruction Set
12.4.5 Control Instructions
These instructions act on CPU registers and control CPU operation
during program execution.
Table 12-5. Control Instructions
Instruction Mnemonic
Clear carry bit CLC
Clear int errupt mask CLI
No operation NOP
Rese t st a ck p o i n t e r RSP
Return from interrupt RTI
Return from subroutine RTS
Set carry bit SEC
S e t in terr u pt mask SEI
Stop oscillator and enable IRQ pin STOP
Software inte r r u p t SWI
Trans fer accumula tor to index register TAX
Trans fer i ndex register to accumulator TXA
Stop CPU clock and enable interrupts WAIT
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Technical Data MC68HC705C8A —Rev. 3
164 Instruction Set
Instruction Set
12.5 Instruction Set Summary
Table 12-6. Instruction Set Summary (Sheet 1 of 6)
Source
Form Operation Description Effect on
CCR
Address
Mode
Opcode
Operand
Cycles
HINZC
ADC #opr
ADC opr
ADC opr
ADC opr,X
ADC opr,X
ADC ,X
Add with Ca rry A ← (A) + (M) + (C)
—
IMM
DIR
EXT
IX2
IX1
IX
A9
B9
C9
D9
E9
F9
ii
dd
hh ll
ee ff
ff
2
3
4
5
4
3
ADD #opr
ADD opr
ADD opr
ADD opr,X
ADD opr,X
ADD ,X
Ad d wi th ou t Ca rr y A ← (A) + (M)
—
IMM
DIR
EXT
IX2
IX1
IX
AB
BB
CB
DB
EB
FB
ii
dd
hh ll
ee ff
ff
2
3
4
5
4
3
AND #opr
AND opr
AND opr
AND opr,X
AND opr,X
AND ,X
Logical AND A ← (A) ∧ (M) ——
—
IMM
DIR
EXT
IX2
IX1
IX
A4
B4
C4
D4
E4
F4
ii
dd
hh ll
ee ff
ff
2
3
4
5
4
3
ASL opr
ASLA
ASLX
ASL opr,X
ASL ,X
Arithm etic Shift Left ( Same as LSL) ——
DIR
INH
INH
IX1
IX
38
48
58
68
78
dd
ff
5
3
3
6
5
ASR opr
ASRA
ASRX
ASR opr ,X
ASR ,X
Arithm etic Shift Right ——
DIR
INH
INH
IX1
IX
37
47
57
67
77
dd
ff
5
3
3
6
5
BCC rel Branch if Carry Bit Clear PC ← (PC) + 2 + rel ? C = 0 ————— REL 24 rr 3
BCLR n opr Clear Bi t n Mn ← 0 —————
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
11
13
15
17
19
1B
1D
1F
dd
dd
dd
dd
dd
dd
dd
dd
5
5
5
5
5
5
5
5
BCS rel Branch if Carry Bit Set ( Same as BLO) PC ← (PC) + 2 + rel ? C = 1 ————— REL 25 rr 3
BEQ rel Branch if Equal PC ← (PC) + 2 + rel ? Z = 1 ————— REL 27 rr 3
BHCC rel Branch if Half-Carry Bit Clear PC ← (PC) + 2 + rel ? H = 0 ————— REL 28 rr 3
BHCS rel Branch if Half-Carry Bit Set PC ← (PC) + 2 + rel ? H = 1 ————— REL 29 rr 3
BHI rel Branch if Higher PC ← (PC) + 2 + rel ? C ∨ Z = 0 ————— REL 22 rr 3
BHS rel Branch if Higher or Same PC ← (PC) + 2 + rel ? C = 0 ————— REL 24 rr 3
Cb0
b7 0
b0
b7 C
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In stru ction Set
Instruction Set Summary
MC68HC705C8A —Rev. 3 T echnical Data
MOTOROLA Instruction Set
BIH rel Branch if IRQ Pin High PC ← (PC) + 2 + rel ? IRQ = 1 ————— REL 2F rr 3
BIL rel Branch if IRQ Pin Low PC ← (PC) + 2 + rel ? IRQ = 0 ————— REL 2E rr 3
BIT #opr
BIT opr
BIT opr
BIT opr,X
BIT opr,X
BIT ,X
Bit Test Accumulator with Memory Byte (A) ∧ (M) ——
—
IMM
DIR
EXT
IX2
IX1
IX
A5
B5
C5
D5
E5
F5
ii
dd
hh ll
ee ff
ff
2
3
4
5
4
3
BLO rel Branch if Lower (Same as BCS) PC ← (PC) + 2 + rel ? C = 1 ————— REL 25 rr 3
BLS rel Branch if Low er or Same PC ← (PC) + 2 + rel ? C ∨ Z = 1 ————— REL 23 rr 3
BMC rel Branch if Interrupt Mask Clear PC ← (PC) + 2 + rel ? I = 0 ————— REL 2C rr 3
BMI rel Branch if Minus PC ← (PC) + 2 + rel ? N = 1 ————— REL 2B rr 3
BMS rel Branch if Interrupt Mask Set PC ← (PC) + 2 + rel ? I = 1 ————— REL 2D rr 3
BNE rel Branch if Not Equal PC ← (PC) + 2 + rel ? Z = 0 ————— REL 26 rr 3
BPL rel Branch if Plus PC ← (PC) + 2 + rel ? N = 0 ————— REL 2A rr 3
BRA rel Branch Always PC ← (PC) + 2 + rel ? 1 = 1 ————— REL 20 rr 3
BRCLR n opr rel Branch if Bit n Clear PC ← (PC) + 2 + rel ? Mn = 0 ————
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
01
03
05
07
09
0B
0D
0F
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
BRN rel Branch Never PC ← (PC) + 2 + rel ? 1 = 0 ————— REL 21 rr 3
BRSET n opr rel Branch if Bit n Set PC ← (PC) + 2 + rel ? Mn = 1 ————
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
00
02
04
06
08
0A
0C
0E
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
BSET n opr Set Bit n Mn ← 1 —————
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
10
12
14
16
18
1A
1C
1E
dd
dd
dd
dd
dd
dd
dd
dd
5
5
5
5
5
5
5
5
BSR rel Branch to Subroutine
PC ← (PC) + 2; push (PCL)
SP ← (SP) – 1; push (PCH)
SP ← (SP) – 1
PC ← (PC) + rel
————— REL AD rr 6
CLC Clear Carry Bit C ← 0 ————0INH98 2
CLI Clear Interrupt Mask I ← 0 — 0 ——— INH 9A 2
Table 12-6. Instruction Set Summary (Sheet 2 of 6)
Source
Form Operation Description Effect on
CCR
Address
Mode
Opcode
Operand
Cycles
HINZC
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Technical Data MC68HC705C8A —Rev. 3
166 Instruction Set
Instruction Set
CLR opr
CLRA
CLRX
CLR opr,X
CLR ,X
Clear Byte
M ← $0 0
A ← $0 0
X ← $0 0
M ← $0 0
M ← $0 0
——01—
DIR
INH
INH
IX1
IX
3F
4F
5F
6F
7F
dd
ff
5
3
3
6
5
CMP #opr
CMP opr
CMP opr
CMP opr,X
CMP opr,X
CMP ,X
Compare Accumulator with Memory Byte (A) – (M) ——
IMM
DIR
EXT
IX2
IX1
IX
A1
B1
C1
D1
E1
F1
ii
dd
hh ll
ee ff
ff
2
3
4
5
4
3
COM opr
COMA
COMX
COM opr,X
COM ,X
Complement Byte (One’s Complement)
M ← (M) = $FF – (M )
A ← (A) = $FF – (A)
X ← (X) = $FF – (X)
M ← (M) = $FF – (M )
M ← (M) = $FF – (M )
——
1
DIR
INH
INH
IX1
IX
33
43
53
63
73
dd
ff
5
3
3
6
5
CPX #opr
CPX opr
CPX opr
CPX opr,X
CPX opr,X
CPX ,X
Compare Index Regist er with Memory Byte (X ) – (M) ——
IMM
DIR
EXT
IX2
IX1
IX
A3
B3
C3
D3
E3
F3
ii
dd
hh ll
ee ff
ff
2
3
4
5
4
3
DEC op r
DECA
DECX
DEC op r,X
DEC ,X
Decrement Byte
M ← (M) – 1
A ← (A) – 1
X ← (X) – 1
M ← (M) – 1
M ← (M) – 1
——
—
DIR
INH
INH
IX1
IX
3A
4A
5A
6A
7A
dd
ff
5
3
3
6
5
EOR #opr
EOR op r
EOR op r
EOR op r,X
EOR op r,X
EOR ,X
EXCLUSIVE OR Accumulator with Memory
Byte A ← (A) ⊕ (M) ——
—
IMM
DIR
EXT
IX2
IX1
IX
A8
B8
C8
D8
E8
F8
ii
dd
hh ll
ee ff
ff
2
3
4
5
4
3
INC op r
INCA
INCX
INC op r,X
INC ,X
Increment Byte
M ← (M) + 1
A ← (A) + 1
X ← (X) + 1
M ← (M) + 1
M ← (M) + 1
——
—
DIR
INH
INH
IX1
IX
3C
4C
5C
6C
7C
dd
ff
5
3
3
6
5
JMP opr
JMP opr
JMP opr,X
JMP opr,X
JMP ,X
Unconditional Jump PC ← Jump A ddress —————
DIR
EXT
IX2
IX1
IX
BC
CC
DC
EC
FC
dd
hh ll
ee ff
ff
2
3
4
3
2
Table 12-6. Instruction Set Summary (Sheet 3 of 6)
Source
Form Operation Description Effect on
CCR
Address
Mode
Opcode
Operand
Cycles
HINZC
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In stru ction Set
Instruction Set Summary
MC68HC705C8A —Rev. 3 T echnical Data
MOTOROLA Instruction Set
JSR opr
JSR opr
JSR opr,X
JSR opr,X
JSR ,X
Jump to Subro utine
PC ← (PC) + n (n = 1, 2, or 3)
Pus h (PCL); SP ← (SP) – 1
Push (PCH); SP ← (SP) – 1
PC ← Effective Address
—————
DIR
EXT
IX2
IX1
IX
BD
CD
DD
ED
FD
dd
hh ll
ee ff
ff
5
6
7
6
5
LDA #opr
LDA opr
LDA opr
LDA opr,X
LDA opr,X
LDA ,X
Load Accumulator with Memory Byte A ← (M) ——
—
IMM
DIR
EXT
IX2
IX1
IX
A6
B6
C6
D6
E6
F6
ii
dd
hh ll
ee ff
ff
2
3
4
5
4
3
LDX #opr
LDX opr
LDX opr
LDX opr,X
LDX opr,X
LDX ,X
Load Index Register w ith Memory Byte X ← (M) ——
—
IMM
DIR
EXT
IX2
IX1
IX
AE
BE
CE
DE
EE
FE
ii
dd
hh ll
ee ff
ff
2
3
4
5
4
3
LSL opr
LSLA
LSLX
LSL opr,X
LSL ,X
Logical Shift Left (Same as ASL) ——
DIR
INH
INH
IX1
IX
38
48
58
68
78
dd
ff
5
3
3
6
5
LSR opr
LSRA
LSRX
LSR opr,X
LSR ,X
Logical Shif t Right ——0
DIR
INH
INH
IX1
IX
34
44
54
64
74
dd
ff
5
3
3
6
5
MUL Unsigned Mult iply X : A ← (X) × (A) 0 ——— 0INH42 1
1
NEG opr
NEGA
NEGX
NEG opr,X
NEG ,X
Ne gate By te (Two ’s Complement)
M ← –(M) = $ 00 – (M)
A ← –(A) = $0 0 – (A)
X ← –(X) = $0 0 – (X)
M ← –(M) = $ 00 – (M)
M ← –(M) = $ 00 – (M)
——
DIR
INH
INH
IX1
IX
30
40
50
60
70
dd
ff
5
3
3
6
5
NOP No Operation ————— INH 9D 2
ORA #opr
ORA opr
ORA opr
ORA opr,X
ORA opr,X
ORA ,X
Logical OR Accumulato r with Memory A ← (A) ∨ (M) ——
—
IMM
DIR
EXT
IX2
IX1
IX
AA
BA
CA
DA
EA
FA
ii
dd
hh ll
ee ff
ff
2
3
4
5
4
3
ROL opr
ROLA
ROLX
ROL opr,X
ROL ,X
Rotate Byte Left through Carry Bit ——
DIR
INH
INH
IX1
IX
39
49
59
69
79
dd
ff
5
3
3
6
5
Table 12-6. Instruction Set Summary (Sheet 4 of 6)
Source
Form Operation Description Effect on
CCR
Address
Mode
Opcode
Operand
Cycles
HINZC
Cb0
b7 0
b0
b7 C0
Cb0
b7
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Technical Data MC68HC705C8A —Rev. 3
168 Instruction Set
Instruction Set
ROR op r
RORA
RORX
ROR op r,X
ROR ,X
Rotate Byte Right through Carry Bit ——
DIR
INH
INH
IX1
IX
36
46
56
66
76
dd
ff
5
3
3
6
5
RSP Reset Stack Pointer SP ← $00FF ————— INH 9C 2
RTI Return from I nterrupt
SP ← (SP) + 1; Pull (CCR)
SP ← (SP) + 1; Pull (A)
SP ← (SP) + 1; Pull (X)
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
INH 80 9
RTS Return from Subroutine SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL) ————— INH 81 6
SBC #opr
SBC opr
SBC opr
SBC opr ,X
SBC opr ,X
SBC ,X
Subtract Memory Byte and Carry Bit from
Accumulator A ← (A) – (M) – (C) ——
IMM
DIR
EXT
IX2
IX1
IX
A2
B2
C2
D2
E2
F2
ii
dd
hh ll
ee ff
ff
2
3
4
5
4
3
SEC Set Carry Bit C ← 1 ————1INH99 2
SEI Set Interrupt Mask I ← 1 — 1 ——— INH 9B 2
STA opr
STA opr
STA opr,X
STA opr,X
STA ,X
Store Accumulator in Memory M ← (A) ——
—
DIR
EXT
IX2
IX1
IX
B7
C7
D7
E7
F7
dd
hh ll
ee ff
ff
4
5
6
5
4
STOP Stop Oscillator and Enable IRQ Pin — 0 ——— INH 8E 2
STX opr
STX opr
STX opr,X
STX opr,X
STX ,X
Store Index Register In Memory M ← (X) ——
—
DIR
EXT
IX2
IX1
IX
BF
CF
DF
EF
FF
dd
hh ll
ee ff
ff
4
5
6
5
4
SUB #opr
SUB opr
SUB opr
SUB opr ,X
SUB opr ,X
SUB ,X
Subtract Memory Byte from Accumulator A ← (A) – (M) ——
IMM
DIR
EXT
IX2
IX1
IX
A0
B0
C0
D0
E0
F0
ii
dd
hh ll
ee ff
ff
2
3
4
5
4
3
SWI Softwa re In terr up t
PC ← (PC) + 1; Push (PCL)
SP ← (SP) – 1; Push (PCH)
SP ← (SP) – 1; Push (X)
SP ← (SP) – 1; Push (A)
SP ← (SP) – 1; Push (CCR)
SP ← (SP) – 1; I ← 1
PCH ← Interrupt Vector High Byte
PCL ← Interrupt Ve ctor Low Byte
— 1 ——— INH 83 1
0
TAX Transfer Accumulator to Index Register X ← (A) ————— INH 97 2
Table 12-6. Instruction Set Summary (Sheet 5 of 6)
Source
Form Operation Description Effect on
CCR
Address
Mode
Opcode
Operand
Cycles
HINZC
b0
b7 C
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In stru ction Set
Opc ode M ap
MC68HC705C8A —Rev. 3 T echnical Data
MOTOROLA Instruction Set
12.6 Opcode Map
See Table 12-7.
TST opr
TSTA
TSTX
TST opr,X
TST ,X
Test Memory Byte for Negative or Zero (M) – $00 ——
—
DIR
INH
INH
IX1
IX
3D
4D
5D
6D
7D
dd
ff
4
3
3
5
4
TXA Transfer Index Register to Accumulator A ← (X) ————— INH 9F 2
WAIT Stop CPU Clock and Enable Interrupts —
——— INH 8F 2
A Accumulator opr Oper an d (one or tw o by tes)
C Carry/borrow flag PC Program counter
CCR Conditio n code regist er PCH Program counter high byte
dd Direct address of operand PCL Program count er low byte
dd rr Dir ect addres s of oper and and relative offset of branch instruction REL Relative addressing mode
DIR Direct addressing mode rel Relative program counter offset byte
ee ff High and low bytes of offset in indexed, 16-bit offset addre ssing rr Relati ve program counter offset byte
EXT Extended addressing mode SP S tack pointer
ff Offset byt e in indexed, 8-bit off s et addressing X Index r egister
H H alf-carry flag Z Zer o flag
hh ll High and low bytes of operand address in extended add ressing # Immediate value
I Inte r rupt ma s k ∧Logica l AN D
ii Immediate operand by te ∨Logi ca l O R
IMM Immediate addressing mod e ⊕Logica l EXCLU SIVE OR
INH Inherent addressing mode ( ) Contents of
IX Indexed, no offset addressing mode –( ) Negation (two’s compl ement)
IX1 Indexed, 8-bit offset addressing mode ←Loaded with
IX2 Indexed, 16-bit offset addressing mode ? If
M Memory location : Concatenated with
N N egative flag
Set or cleared
nAny bit —Not affected
Table 12-6. Instruction Set Summary (Sheet 6 of 6)
Source
Form Operation Description Effect on
CCR
Address
Mode
Opcode
Operand
Cycles
HINZC
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Technical Data MC68HC7 05C8A —Rev. 3
170 Instruction Set
Instruction Set
Tab le 12-7. Opcode Map
Bit Manipulation Branch Read-Modify-Write Control Register/Memory
DIR DIR REL DIR INH INH IX1 IX INH INH IMM DIR EXT IX2 IX1 IX
0123456789ABCDEF
05
BRSET0
3DIR
5
BSET0
2DIR
3
BRA
2REL
5
NEG
2DIR
3
NEGA
1INH
3
NEGX
1INH
6
NEG
2IX1
5
NEG
1IX
9
RTI
1INH
2
SUB
2IMM
3
SUB
2DIR
4
SUB
3EXT
5
SUB
3IX2
4
SUB
2IX1
3
SUB
1IX
0
15
BRCLR0
3DIR
5
BCLR0
2DIR
3
BRN
2REL
6
RTS
1INH
2
CMP
2IMM
3
CMP
2DIR
4
CMP
3EXT
5
CMP
3IX2
4
CMP
2IX1
3
CMP
1IX
1
25
BRSET1
3DIR
5
BSET1
2DIR
3
BHI
2REL
11
MUL
1INH
2
SBC
2IMM
3
SBC
2DIR
4
SBC
3EXT
5
SBC
3IX2
4
SBC
2IX1
3
SBC
1IX
2
35
BRCLR1
3DIR
5
BCLR1
2DIR
3
BLS
2REL
5
COM
2DIR
3
COMA
1INH
3
COMX
1INH
6
COM
2IX1
5
COM
1IX
10
SWI
1INH
2
CPX
2IMM
3
CPX
2DIR
4
CPX
3EXT
5
CPX
3IX2
4
CPX
2IX1
3
CPX
1IX
3
45
BRSET2
3DIR
5
BSET2
2DIR
3
BCC
2REL
5
LSR
2DIR
3
LSRA
1INH
3
LSRX
1INH
6
LSR
2IX1
5
LSR
1IX
2
AND
2IMM
3
AND
2DIR
4
AND
3EXT
5
AND
3IX2
4
AND
2IX1
3
AND
1IX
4
55
BRCLR2
3DIR
5
BCLR2
2DIR
3
BCS/BLO
2REL
2
BIT
2IMM
3
BIT
2DIR
4
BIT
3EXT
5
BIT
3IX2
4
BIT
2IX1
3
BIT
1IX
5
65
BRSET3
3DIR
5
BSET3
2DIR
3
BNE
2REL
5
ROR
2DIR
3
RORA
1INH
3
RORX
1INH
6
ROR
2IX1
5
ROR
1IX
2
LDA
2IMM
3
LDA
2DIR
4
LDA
3EXT
5
LDA
3IX2
4
LDA
2IX1
3
LDA
1IX
6
75
BRCLR3
3DIR
5
BCLR3
2DIR
3
BEQ
2REL
5
ASR
2DIR
3
ASRA
1INH
3
ASRX
1INH
6
ASR
2IX1
5
ASR
1IX
2
TAX
1INH
4
STA
2DIR
5
STA
3EXT
6
STA
3IX2
5
STA
2IX1
4
STA
1IX
7
85
BRSET4
3DIR
5
BSET4
2DIR
3
BHCC
2REL
5
ASL/LSL
2DIR
3
ASLA/LSLA
1INH
3
ASLX/LSLX
1INH
6
ASL/LSL
2IX1
5
ASL/LSL
1IX
2
CLC
1INH
2
EOR
2IMM
3
EOR
2DIR
4
EOR
3EXT
5
EOR
3IX2
4
EOR
2IX1
3
EOR
1IX
8
95
BRCLR4
3DIR
5
BCLR4
2DIR
3
BHCS
2REL
5
ROL
2DIR
3
ROLA
1INH
3
ROLX
1INH
6
ROL
2IX1
5
ROL
1IX
2
SEC
1INH
2
ADC
2IMM
3
ADC
2DIR
4
ADC
3EXT
5
ADC
3IX2
4
ADC
2IX1
3
ADC
1IX
9
A5
BRSET5
3DIR
5
BSET5
2DIR
3
BPL
2REL
5
DEC
2DIR
3
DECA
1INH
3
DECX
1INH
6
DEC
2IX1
5
DEC
1IX
2
CLI
1INH
2
ORA
2IMM
3
ORA
2DIR
4
ORA
3EXT
5
ORA
3IX2
4
ORA
2IX1
3
ORA
1IX
A
B5
BRCLR5
3DIR
5
BCLR5
2DIR
3
BMI
2REL
2
SEI
1INH
2
ADD
2IMM
3
ADD
2DIR
4
ADD
3EXT
5
ADD
3IX2
4
ADD
2IX1
3
ADD
1IX
B
C5
BRSET6
3DIR
5
BSET6
2DIR
3
BMC
2REL
5
INC
2DIR
3
INCA
1INH
3
INCX
1INH
6
INC
2IX1
5
INC
1IX
2
RSP
1INH
2
JMP
2DIR
3
JMP
3EXT
4
JMP
3IX2
3
JMP
2IX1
2
JMP
1IX
C
D5
BRCLR6
3DIR
5
BCLR6
2DIR
3
BMS
2REL
4
TST
2DIR
3
TSTA
1INH
3
TSTX
1INH
5
TST
2IX1
4
TST
1IX
2
NOP
1INH
6
BSR
2REL
5
JSR
2DIR
6
JSR
3EXT
7
JSR
3IX2
6
JSR
2IX1
5
JSR
1IX
D
E5
BRSET7
3DIR
5
BSET7
2DIR
3
BIL
2REL
2
STOP
1INH
2
LDX
2IMM
3
LDX
2DIR
4
LDX
3EXT
5
LDX
3IX2
4
LDX
2IX1
3
LDX
1IX
E
F5
BRCLR7
3DIR
5
BCLR7
2DIR
3
BIH
2REL
5
CLR
2DIR
3
CLRA
1INH
3
CLRX
1INH
6
CLR
2IX1
5
CLR
1IX
2
WAIT
1INH
2
TXA
1INH
4
STX
2DIR
5
STX
3EXT
6
STX
3IX2
5
STX
2IX1
4
STX
1IX
F
INH = Inherent REL = Relative
IMM = Immediate IX = Indexed, No Offset
DIR = Direct IX1 = Indexed, 8-Bit Offset
EXT = Extended IX2 = Indexed, 16-Bit Offset
0MSB of Opcode in Hexadecimal
LSB of Opcode in Hexadecimal 05
BRSET0
3DIR
Numb er of Cyc les
Opcode Mnemonic
Numb er of By tes/Add re ssing Mode
LSBMSB LSB
MSB
LSB MSB
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MC68HC705C8A —Rev. 3 Tec hnical Data
MOTO ROLA Electrical Spec ifications
Technical Data — MC68HC705C8 A
Section 13. Electrical Specifications
13.1 Contents
13.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171
13.3 Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172
13.4 Operating Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .173
13.5 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173
13.6 Power Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174
13.7 5.0-Volt DC Electrical Characteristics. . . . . . . . . . . . . . . . . . .175
13.8 3.3-Volt DC Electrical Characteristics . . . . . . . . . . . . . . . . . .176
13.9 5.0-Volt Control Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181
13.10 3.3-Volt Control Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182
13.11 5.0-Volt Serial Peripheral Interface (SPI) Timing . . . . . . . . . .185
13.12 3.3-Volt Serial Peripheral Interface (SPI) Timing . . . . . . . . . .187
13.2 Introduction
This section contains electrical and timing specifications.
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Technical Data MC68HC705C8A —Rev. 3
172 Elect rical Spec ifications
Electrical Specifications
13.3 Maximum Ratings
Maximum ratings are the extreme limits to which the MCU can be
exposed without permanently damaging it.
The MCU contains circuitry to protect the inputs against damage from
high static voltages; however, do not apply voltages higher than those
shown in the table here. Keep VIn and VOut within the range
VSS ≤(VIn or VOut)≤VDD. Connect unused inputs to the appropriate
voltage level, either V SS or VDD.
NOTE: This device is not guaranteed to operate properly at the maximum
ratings. Refer to 13.7 5.0-Volt DC Electrical Characteristics and
13.8 3.3-Volt DC E lectrical Character istics for g uara nteed oper ating
conditions.
Rating(1)
1. Volt ages r eferenced to VSS
Symbol Value Unit
Supply voltage VDD –0.3 to +7.0 V
Input voltage VIn VSS –0.3
to VDD +0.3 V
Programming voltage VPP VDD –0.3 to
16.0
Bootstrap mode (IRQ pin only) VIn VSS – 0.3
to 2 x VDD + 0.3 V
Current drain per pin excluding
VDD and VSS I25mA
Storage temperature range TSTG –65 t o +150 °C
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Ele ctrical Specifications
Operating Temperature Range
MC68HC705C8A —Rev. 3 T echnical Data
MOTO ROLA Electrical Spec ifications
13.4 Operating Temperature Range
13.5 Therm al Chara ct erist ics
Figure 13-1. Equivalent Test Load
Rating(1)
1. Volt ages r eferenced to VSS
Symbol Va lue Un it
Operating temperature range(2)
MC68HC705C8ACB
MC68HC705C8ACFB
MC68HC705C8ACFS
MC68HC705C8ACP
MC68HC705C8ACFN
MC68HC705C8ACFS
2. C = Extended temperature range (– 40°C to + 85°C)
P = Plastic dual in-line package (PDIP)
B = Plastic shrink dual in- li ne package (SDIP)
S = Ceramic dual in-line package (cerdip)
FN = Plastic-leaded chip carrier (PLCC)
FB = Quad flat pack (QFP)
FS = Ceramic- leaded chip carri er (CLCC)
TATL to TH
– 40 to + 85 °C
Characteristic Symbol Value Unit
Therm al resistance
Plastic dual in-line package (DIP)
Ceramic dual in-line pac kage (cerdip)
Plastic leaded chip carrier (P LCC)
Quad flat pack (QFP)
Plastic shrink DIP (SDIP)
θJA
60
50
70
95
60
°C/W
VDD
C
R2
R1
TEST
POINT
(SEE TABLE) (SEE TABLE )
(SEE TABLE)
VDD = 4.5 V
Pins R1 R2 C
PA7–PA0
PB7–PB0
PC7–PC0
PD4–PD1
3.26 kΩ2.3 8 kΩ50 pF
VDD = 3.0 V
Pins R1 R2 C
PA7–PA0
PB7–PB0
PC7–PC0
PD4–PD1
10.91 kΩ6. 32 k Ω50 pF
PD7, PD5, PD0 6 kΩ6 kΩ200 pF
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Technical Data MC68HC705C8A —Rev. 3
174 Elect rical Spec ifications
Electrical Specifications
13.6 Power Considerations
The average chip junction temperature, TJ, in °C can be obtained from:
TJ = TA + (PD x θJA)(1)
Where:
TA = ambient temperature in °C
θJA = package thermal resistance, junction to ambient in °C/W
PD = PINT + PI/O
PINT = ICC × VCC = chip internal power dissipation
PI/O = power dissipation on input and output pins (user-determined)
For most applications, PI/O < P INT and can be neglected.
Ignoring PI/O, the relationship between PD and TJ is approximately:
(2)
Solving equations (1) and (2) for K gives:
= PD x (TA + 273°C) + θJA x (PD)2(3)
where K is a constant pertaining to the particular part. K can be
determined from equation (3) by measuring PD (at equilibrium) for a
known TA. Using this value of K, the values of PD and TJ can be obtained
by solving equations (1) and (2) iteratively for any value of TA.
PD = TJ + 273°C
K
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Ele ctrical Specifications
5.0-Volt DC Electrical Characteris tics
MC68HC705C8A —Rev. 3 T echnical Data
MOTO ROLA Electrical Spec ifications
13.7 5.0-Volt DC Electrical Characteristics
Characteristic(1)
1. VDD = 5 V ± 10%; VSS = 0 Vdc, TA = TL to TH, unless otherwise n oted
Symbol Min Typ(2)
2. Typical values reflect average measurements at midpoint of voltage range at 25°C.
Max Unit
Out put voltage, ILoad ≤ 10.0 µAVOL
VOH
—
VDD – 0.1 —
—0.1
—V
Out put high voltage
ILoad = –0.8 mA, PA7–PA0, PB7–PB0, PC 6 –PC 0 , TCMP
(see Figu re 13 -2 )
ILoad = –1.6 mA, PD4–P D1 (see Figure 13-3)
ILoad = –5.0 mA, PC7
VOH VDD – 0.8 —
—
—
—
—
—
V
Out put low voltage (see Figure 13-4)
ILoad = 1.6 mA
PA7–PA0, PB7–PB0, PC6–PC0, PD4–PD1
ILoad = 20 m A , PC7
VOL —
——
—0.4
0.4
V
Input high volt age
PA7–PA0, PB7–PB0, PC7–PC0, PD5–PD0, PD7 ,
TCAP, IRQ, RESET, OS C 1 VIH 0.7 x VDD —VDD V
Input low voltage
PA7–PA0, PB7–PB0, PC7–PC0, PD5–PD0, PD7 ,
TCAP, IRQ, RESET, OS C 1 VIL VSS —0.2 x VDD V
EPROM programming voltage VPP 14.5 14.75 15.0 V
EPROM/OTPROM programming current IPP —510mA
User mode current IPP ——± 10 mA
Data-retention mode (0°C to 70°C) VRM 2.0 ——V
Supply current (3)
Run(4)
Wait(5)
Stop(6)
25°C
–40°C to +85 °C
3. IDD measured wit h port B pull up devices disabled.
4. Run (oper ati ng) IDD measur ed using external square wa ve clock s ource (fOSC = 4.2 MHz). All inputs 0.2 V from r ail. No dc
loads. Less than 50 pF on all outputs. CL = 20 pF on OSC2. OSC2 capacitance linearly aff ects run IDD.
5. W ait IDD m easure d using ex ter nal squ are wave cl ock s ource ( fOSC = 4.2 MHz). Al l inp uts 0.2 V from r ail. No dc loads . Less
than 50 pF on al l output s. CL = 20 pF on OSC2. V IL = 0.2 V, VIH = VDD – 0.2 V. All por ts configur ed as input s. SPI and SCI
disabled. If SPI and SCI enabl ed, ad d 10% current draw. OSC2 capac it ance linearly aff ects wait IDD.
6. Stop IDD m easured with OSC1 = VDD. All ports configured as inputs. VIL = 0.2 V, VIH = VDD – 0. 2 V.
IDD
—
—
—
—
5.0
1.95
5.0
5.0
7.0
3.0
50
50
mA
mA
µµA
µµA
I/O ports hi-z leakage current
PA7–PA0, PB7–PB0, PC7–PC0, PD4–PD1, PD7 , R ESET IIL ——± 10 µA
Input cu rrent, IRQ, TCAP, OSC1, PD0, PD5 IIn ——± 1 µA
Capacitance
Ports (as input or output)
RESET, IRQ, TCAP, PD 0 –PD5, PD7
COut
CIn
—
——
—12
8pF
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Technical Data MC68HC705C8A —Rev. 3
176 Elect rical Spec ifications
Electrical Specifications
13.8 3.3-Volt DC Electrical Characteristics
Characteristic(1)
1. VDD = 3.3 V ± 10%; VSS = 0 Vdc, TA = TL to TH, unless otherwise noted
Symbol Min Typ(2)
2. Typical values at midpoint of voltage range, 25°C only.
Max Unit
Output voltage, ILoad ≤ 10.0 µAVOL
VOH
—
VDD – 0.1 —
—0.1
—V
Output high voltage
ILoad = –0.2 mA
PA7–PA0, PB7–PB0, PC6–PC0, TCMP
(see Fi gure 1 3-2)
ILoad = –0.4 mA
PD4–PD1 (see Figure 13-3)
ILoad = –1.5 mA
PC7
VOH VDD – 0.3 —
—
—
—
—
—
V
Output low voltage (see Figure 13-4)
ILoad = 0.4 mA
PA7–PA0, PB7–PB0, PC6–PC0, PD4–PD1
ILoad = 6.0 mA
PC7
VOL —
—
—
—
0.3
0.3
V
Inpu t h igh vo l t a ge
PA7–PA0, PB7–PB0, PC7–PC0, PD5–PD0,
PD7, TCAP, IRQ, RESET, OSC1 VIH 0.7 x VDD —VDD V
Inpu t lo w volta g e
PA7–PA0, PB7–PB0, PC7–PC0, PD5–PD0,
PD7, TCAP, IRQ, RESET, OSCI VIL VSS —0.2 x VDD V
Data-retention mode (0°C to 70 °C) VRM 2.0 ——V
Supply current(3)
Run(4)
Wait(5)
Stop(6)
3. IDD me asured with port B pullup devices disabl ed.
4. Run (oper ati ng) IDD measur ed using external square wa ve clock s ource (fOSC = 2.0 MHz). All inputs 0.2 V from r ail. No dc
loads. Less than 50 pF on all outputs. CL = 20 pF on OSC2. OSC2 capacitance linearly aff ects run IDD.
5. W ait IDD m easure d using ex ter nal squ are wave cl ock s ource ( fOSC = 2.0 MHz). Al l inp uts 0.2 V from r ail. No dc loads . Less
than 50 pF on al l output s. CL = 20 pF on OSC2. VIL = 0. 2 V, VIH = VDD – 0.2 V. All port s con figured as in puts. SPI and SCI
disabled. If SPI and SCI enabl ed, ad d 10% current draw. OSC2 capac it ance linearly aff ects wait IDD.
6. Stop IDD m easured with OSC1 = VDD. All ports configured as inputs. VIL = 0.2 V; VIH = VDD – 0. 2 V.
IDD —
—
—
1.53
0.711
2.0
3.0
1.0
20
mA
mA
µA
I/O ports hi-z leakage current
PA7–PA0, PB7–PB0, PC7–PC0, PD4–PD1,
PD7, RESET IIL ——± 10 µA
Inpu t c u rre n t
IRQ, TCA P, O SC 1, PD 5 , PD0 IIn ——± 1 µA
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Ele ctrical Specifications
3.3-Volt DC Electrical Characteris tics
MC68HC705C8A —Rev. 3 T echnical Data
MOTO ROLA Electrical Spec ifications
Figure 13-2. Typical Voltage Compared to Current
0
1.0
2.0
3.0
4.0
5.0
00.60.80.2 0.4
VDD – VOH (VOLTS)
I
OH
(mA)
(a) VOH versus IOH for P orts A, B, PC6–PC0, and TCMP
V
DD
= 5.0 V
SEE NOTE 1
SEE NO TE 2
1. At VDD = 5.0 V, devices are specified and tested for (VDD – VOH)
Notes:
≤ 800 mV @ IOH = –0.8 mA .
V
DD
= 3.0 V
2. At VDD = 3.3 V, devices are specified and tested for (VDD – VOH)
≤ 300 mV @ IOH = –0.2 mA .
0.8
0.2
0
2.0
4.0
6.0
8.0
00.60.2 0.4
VDD – VOH (VOLTS)
I
OH
(mA)
V
DD
= 5.0 V
(b) VOH versus IOH for PD4–PD1
SEE NOTE 1
SEE NOTE 2
V
DD
= 3.0 V
1. At VDD = 5.0 V, dev i ce s ar e spe ci fied an d tes t e d for
Notes:
(VDD – VOH) ≤ 800 mV @ IOH = –1.6 mA.
2. At VDD = 3.3 V, dev i ce s ar e spe ci fied an d tes t e d for
(VDD – VOH) ≤ 300 mV @ IOH = –0.4 mA.
1.6
0.4
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Technical Data MC68HC705C8A —Rev. 3
178 Elect rical Spec ifications
Electrical Specifications
Figure 13-2. Typical Voltage Compared to Current (Continued)
0
1.0
2.0
3.0
4.0
5.0
00.30.40.1 0.2
VOL (VOLTS)
I
OL
(M A)
6.0
V
DD
= 5.0 V
V
DD
= 3.0 V
(c) VOL versus IOL for All Po rts Except PC 7
SEE NOTE 1
SEE NOTE 2
1. At VDD = 5.0 V, devices are sp ecified and tested for
Notes:
VOL ≤ 400 mV @ IOL = 1.6 mA.
2. At VDD = 3.3 V, devices a re specified and tested f or
VOL ≤ 300 mV @ IOL = 0.4 mA.
1.6
0.4
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Ele ctrical Specifications
3.3-Volt DC Electrical Characteris tics
MC68HC705C8A —Rev. 3 T echnical Data
MOTO ROLA Electrical Spec ifications
Figure 13-3. Typical Current versus Internal
Frequency for Run and Wait Modes
I
DD
(mA)
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
0.0 0.5 1.0 1.5 2.0
INTERNAL FREQUENCY 1 tCYC (MHz)
2.0
(a) Wait Mode
V
DD
= 5.0 V
V
DD
= 3.3 V
I
DD
(mA)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
0.0 0.5 1.0 1.5 2.0
INTERNAL FRE QUENCY 1 tCYC (MHz)
5.0
(b) Run Mode
V
DD
= 5.0 V
V
DD
= 3.3 V
5.5
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Technical Data MC68HC705C8A —Rev. 3
180 Elect rical Spec ifications
Electrical Specifications
Figure 13-4. Total Current Drain versus Frequency
SUPPLY CURR EN T (I
DD
)
1.0 mA
1.5 mA
2.0 mA
2.5 mA
3.0 mA
0250 kHz 500 kHz 750 kHz 1 MHz
INTE RNA L CLO CK FRE Q UE NCY (XT AL ÷ 2)
0
500 mA
T = –40°C to 85°C
VDD = 3.3 V ± 10%
STOP IDD (20 µA)
RUN (OPERATING) I
DD
WAIT I
DD
(a) Maximum Current Drain vers us Fre quency @ 3. 3 V ± 10 %
SUPPLY CURRENT (I
DD
)
1.0 mA
2.0 mA
3.0 mA
4.0 mA
5.0 mA
0500 kHz 1 MHz 1.5 MHz 2 MHz
INTERNAL CL OCK FREQUENCY (XTAL ÷ 2)
0
T = –40°C to 8 5 °C
VDD = 5.0 V ± 10%
STOP IDD (50 µA)
6.0 mA
7.0 mA
RUN (OPERATING) I
DD
WAIT I
DD
(b) M axi m um Cu rren t Drain versus Fre quency @ 5 V ± 10%
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Ele ctrical Specifications
5.0-Volt Control Timing
MC68HC705C8A —Rev. 3 T echnical Data
MOTO ROLA Electrical Spec ifications
13.9 5.0-Volt Control Timing
Characteristic(1)
1. VDD = 5.0 Vdc ± 10% , VSS = 0 Vdc; TA = TL to TH
Symbo l Min Max Unit
Frequenc y of operation
Cry st al o pt io n
External clock option fOSC —
dc 4.2
4.2 MHz
Internal operating frequency
Crystal (fOSC ÷ 2)
Exte rn a l cl ock ( fOSC ÷ 2) fOP —
dc 2.1
2.1 MHz
Cycle time (s ee Figure 1 3-7)tCYC 480 —ns
Cry st al o s c illator s tar t up time (see Fi gure 13- 7)tOXOV —100 ms
Stop recovery startup time (crystal osci llator)
(see Fi gure 1 3-6)tILCH —100 ms
RESET pulse width (see Figure 13-7)tRL 8 — tCYC
Timer
Resolution(2)
Input capture pulse width (see Figure 1 3- 5)
Input capture pulse period (see Fi gure 1 3-5)
2. Since a 2- bit pres caler in the timer m u st count f our inte rnal cycl es (tCYC), this is the limiting minimum factor in determining
the timer resolution.
tRESL
tTH, tTL
tTLTL
4.0
125
(3)
3. The mini m um period, tTLTL, should not be l ess than the nu mb er of cy cle times it takes to execute the captur e interrupt ser -
vice routine plus 24 tCYC.
—
—
—
tCYC
ns
tCYC
Interrupt pulse width low (edge-triggered )
(see Figure 4-2. External Interrupt Timing)tILIH 125 —ns
Interrupt pulse period
(see Figure 4-2. External Interrupt Timing)tILIL (4)
4. The minim um pe riod, tILIL, should not be less th an the number of cycle times it takes to execu te t he interrup t service rou tine
plus 19 tCYC.
—tCYC
OSC1 pulse width tOH, tOL 90 —ns
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Technical Data MC68HC705C8A —Rev. 3
182 Elect rical Spec ifications
Electrical Specifications
13.10 3.3-Volt Control Timing
Figure 13-5. Timer Relationships
Characteristic(1) Symb ol Min Max U nit
Frequenc y of operation
Cry st al o pt io n
External clock option fOSC —
dc 2.0
2.0 MHz
Internal operating frequency
Crystal (fOSC ÷ 2)
Exte rn a l cl ock ( fOSC ÷ 2) fOP —
dc 1.0
1.0 MHz
Cycle time (see Figu re 13 -7 )tCYC 1000 —ns
Cry st a l o s c illator s tar t u p time (see Fi gure 13- 7)tOXOV —100 ms
Stop recovery startup time (crystal oscillator)
(see Fi gure 1 3-6)tILCH —100 ms
RESET pulse width, excluding power- up
(see Fi gure 1 3-7)tRL 8 — tCYC
Timer
Resolution(2)
Input capture pulse width (see Figure 1 3- 5)
Input capture pulse period (see Fi gure 1 3-5)
tRESL
tTH, t TL
tTLTL
4.0
250
(3)
—
—
—
tCYC
ns
tCYC
Interrupt pulse width low (edge-triggered)
(see Figure 4-2. External Interrupt Timing)tILIH 250 —ns
Interrupt pulse period
(see Figure 4-2. External Interrupt Timing)tILIL (4) —tCYC
OSC1 pulse width tOH, tOL 200 —ns
1. VDD = 3.3 Vdc ± 0.3 Vdc, VSS = 0 Vdc; TA = TL to TH
2. Since a 2- bit pres caler in the timer m u st count f our inte rnal cycl es (tCYC), this is the limiting minimum factor in determining
the timer resolution.
3. The mini m um period, tTLTL, should not be l ess than the nu mb er of cy cle times it takes to execute the captur e interrupt ser -
vice routine plus 24 tCYC.
4. The minim um pe riod, tILIL, should not be less th an the number of cycle times it takes to execu te t he interrup t service rou tine
plus 19 tCYC.
tTLTL*
EXTERN AL SIGNAL
tTH*tTL*
*Refer to timer resolution data in Figure 13-6 and Figur e 13-7.
(TCAP PIN 37)
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Ele ctrical Specifications
3.3-Volt Control Timing
MC68HC705C8A —Rev. 3 T echnical Data
MOTO ROLA Electrical Spec ifications
Figure 13-6. Stop Recovery Timing Diagram
1FFE 1FFE 1FFE 1FFE 1FFF(4)
tILCH 4 064 tCYC
tILIH
tRL
Notes:
1. Represents the internal gating of the OSC1 pin
2. IRQ pin edge-sensitive option
3. IRQ pin level and edge-sensiti ve option
4. RESET vector address shown for timing example
RESET OR IN TE RRU PT
VECTOR FETCH
OSC1(1)
RESET
IRQ(2)
IRQ(3)
INTERNAL
CLOCK
INTERNAL
ADDRESS
BUS
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Technical Data MC68HC7 05C8A —Rev. 3
184 Elect rical Spec ifications
Electrical Specifications
Figure 13-7. Power-On Reset and External Reset Timing Diagram
PCH PCL
OSC1
RESET
INTERNAL
PROCESSOR
INTERNAL
ADDRESS
BUS 1FFE 1FFF
VDD VDD THRESHOLD (1-2 V TYPICAL)
tVDDR
tRL
INTERNAL
DATA
BUS
1FFE
1FFE
1FFE 1FFE NE W PC1FFF
*OSC1 line is not meant to represent frequency. It is only used to represent time.
** Intern al t iming signal and b us infor mation are not av ailable externally.
***The next rising edge of the intern al processor clock following the ri sing edge of RESET initiates the reset sequence.
NEW NEW
PCL
PCH
NEW PC
CLOCK
OP
CODE OP
CODE
tCYC
tOXOV
* **
*
**
***
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Ele ctrical Specifications
5.0-Volt Serial Peripheral Inte rface (SPI) Timing
MC68HC705C8A —Rev. 3 T echnical Data
MOTO ROLA Electrical Spec ifications
13.11 5.0-Volt Serial Peripheral Interface (SPI) Timing
Number(1) Characteristic(2) Symbol Min Max Unit
Operat ing frequenc y
Master
Slave fOP(M)
fOP(S)
dc
dc 0.5
2.1 fOP
MHz
1Cycle time
Master
Slave tCYC(M)
tCYC(S)
2.0
480 —
—tCYC
ns
2Enable lead t i me
Master
Slave tLead(M)
tLead(S)
(3)
240 —
—ns
3Enable lag time
Master
Slave tLag(M)
tLag(S)
(2)
720 —
—ns
4Clock (SCK) high time
Master
Slave tW(SCKH)M
tW(SCKH)S
340
190 —
—ns
5Clock (SCK) low t ime
Master
Slave tW(SCKL)M
tW(SCKL)S
340
190 —
—ns
6Dat a setup time (inputs)
Master
Slave tSU(M)
tSU(S)
100
100 —
—ns
7D ata hold time (inputs)
Master
Slave tH(M)
tH(S)
100
100 —
—ns
8Access time(4)
Slave tA0 120 ns
9D isable time(5)
Slave tDIS —240 ns
10 Data valid time
Master (before capture edge)
Slave (after enable edge)(6) tV(M)
tV(S)
0.25
——
240 tCYC(M)
ns
Continued
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Technical Data MC68HC705C8A —Rev. 3
186 Elect rical Spec ifications
Electrical Specifications
11 D ata hold time (output s)
Master (after capture edge)
Slave (after enable edge) tHO(M)
tHO(S)
0.25
0—
—tCYC(M)
ns
12 Rise time(7)
SPI outputs (SCK, MOSI , MISO)
SPI inputs (SCK, MO SI, M ISO, SS)tR(M)
tR(S)
—
—100
2.0 ns
µs
13 Fall time(8)
SPI outputs (SCK, MOSI , MISO)
SPI inputs (SCK, MO SI, M ISO, SS)tF(M)
tF(S)
—
—100
2.0 ns
µs
1. Numbers refer to dimensions in Figure 13-8 and Figure 13-9.
2. VDD = 5.0 Vdc ± 10 %
3. Signal pr oduction depe nds on software.
4. Time to data active from high-impedance state
5. Hold time t o high-impedan ce state
6. W ith 200 pF on all SPI pins
7. 20% of VDD to 70% of VDD; CL = 200 pF
8. 70% of VDD to 20% of VDD; CL = 200 pF
Number(1) Characteristic(2) Symbol Min Max Unit
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Ele ctrical Specifications
3.3-Volt Serial Peripheral Inte rface (SPI) Timing
MC68HC705C8A —Rev. 3 T echnical Data
MOTO ROLA Electrical Spec ifications
13.12 3.3-Volt Serial Peripheral Interface (SPI) Timing
Number(1) Characteristic(2) Symbol Min Max Unit
Operat ing frequenc y
Master
Slave fOP(M)
fOP(S) dc 0.5
2.1 fOP
MHz
1Cycle time
Master
Slave tCYC(M)
tCYC(S)
2.0
1—
—tCYC
ns
2Enab le l ead time
Master
Slave tLead(M)
tLead(S)
(3)
500 —
—ns
3Enable lag time
Master
Slave tLag(M)
tLag(S)
(2)
1500 —
—ns
4Clock (SCK) high time
Master
Slave tW(SCKH)M
tW(SCKH)S
720
400 —
—ns
5Clock (SCK) low time
Master
Slave tW(SCKL)M
tW(SCKL)S
720
400 —
—ns
6Data setup time ( i n p uts )
Master
Slave tSU(M)
tSU(S)
200
200 —
—ns
7Data hold time (inputs)
Master
Slave tH(M)
tH(S)
200
200 —
—ns
8Access time(4)
Slave tA0 250 ns
9Disable time(5)
Slave tDIS —500 ns
10 Data valid time
Master (before capture edge)
Slave (after enable edge)(6) tV(M)
tV(S)
0.25
——
500 tCYC(M)
ns
Continued
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Technical Data MC68HC705C8A —Rev. 3
188 Elect rical Spec ifications
Electrical Specifications
11 Data hold time (outputs)
Master (after capture edge)
Slave (after enable edge) tHO(M)
tHO(S)
0.25
0—
—tCYC(M)
ns
12 Rise time(7)
SPI outputs (SCK, MOSI, MISO)
SPI inputs (SCK, MOSI, MISO, SS)tR(M)
tR(S)
—
—200
2.0 ns
µs
13 F all t ime(8)
SPI outputs (SCK, MOSI, MISO)
SPI inputs (SCK, MOSI, MISO, SS)tF(M)
tF(S)
—
—200
2.0 ns
µs
1. Numbers refer to dimensions in Figure 13-8 and Figure 13-9.
2. VDD = 3.3 Vdc ± 10 %
3. Signal production depends on so ftware.
4. Time to data active from high-impedance state
5. Hold time t o high-impedan ce state
6. W ith 200 pF on all SPI pins
7. 20% of VDD to 70% of VDD; CL = 200 pF
8. 70% of VDD to 20% of VDD; CL = 200 pF
Number(1) Characteristic(2) Symbol Min Max Unit
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Ele ctrical Specifications
3.3-Volt Serial Peripheral Inte rface (SPI) Timing
MC68HC705C8A —Rev. 3 T echnical Data
MOTO ROLA Electrical Spec ifications
Figure 13-8. SPI Master Timing
NOTE
Note: This fir s t clock edge is generated interna lly, but is not seen at the SCK pin.
SS pin of master held high.
MSB IN
SS
INPUT
SCK (CPOL = 0)
OUTPUT
SCK (CPOL = 1)
OUTPUT
MISO
INPUT
MOSI
OUTPUT
NOTE
4
5
5
113 12
4
12 13
BITS 6–1LSB IN
MASTER MSB OUT BITS 6–1MASTER LSB OUT
10
13
11 10
12
11
76
NOTE
Not e: This last clock edge is generated internally, but is not seen at the SCK pin.
SS p in of master held high.
MSB IN
SS
INPUT
SCK (CPOL = 0)
OUTPUT
SCK (CPOL = 1)
OUTPUT
MISO
INPUT
MOSI
OUTPUT
NOTE
4
5
5
113 12
4
13
BITS 6–1LSB IN
MASTER MSB OUT BITS 6–1MASTER LSB OUT
10
13
11 10
12
11
76
12
a) SPI Master Timing (CPHA = 0)
b) SPI Master Timing (CPHA = 1)
12
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Technical Data MC68HC705C8A —Rev. 3
190 Elect rical Spec ifications
Electrical Specifications
Figure 13-9. SPI Slave Timing
Note: Not defined, but normally MSB of character just received
SLAVE
SS
INPUT
SCK (CPOL = 0)
(INPUT
SCK (CPOL = 1)
INPUT
MISO
INPUT
MOSI
OUTPUT
4
5
5
113 12
4
13
MSB IN
BITS 6–1
8
610
11
11
12
NOTESLAVE LSB OUT
9
3
LSB IN
2
7
BITS 6–1
MSB OUT
Note: Not defined, but normally LSB of character previously transmitted
SLAVE
SS
INPUT
SCK (CPOL = 0)
INPUT
SCK (CPOL = 1)
INPUT
MISO
OUTPUT
MOSI
INPUT
4
5
5
113 12
4
13
MSB IN
BITS 6–1
8
610 11
12
NOTE SLAVE LSB OUT
9
3
LSB IN
2
7
BITS 6–1
MSB OUT
10
a) SPI Slave Timing (CPHA = 0)
b) SPI Slave Timing (CPHA = 1)
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MC68HC705C8A —Rev. 3 Tec hnical Data
MOTOROLA Mechanical Specifi cations
Technical Data — MC68HC705C8 A
Section 14. Mechanical Specifications
14.1 Contents
14.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191
14.3 40-Pin Pl astic Dual In-Line Package (PDIP). . . . . . . . . . . . . .192
14.4 40-Pin Ceramic Dual In-Line Package (Cerdip) . . . . . . . . . . .193
14.5 44-Lead Plastic-Leaded C hip Carrier (PLCC) . . . . . . . . . . . .194
14.6 44-Lead Ceramic-Leaded Chip Carr ier (CLCC) . . . . . . . . . . .195
14.7 44-Pin Quad Flat Pack (QFP). . . . . . . . . . . . . . . . . . . . . . . . .196
14.8 42-Pin Shrink Dual In-Line Package (SDIP). . . . . . . . . . . . . .197
14.2 Introduction
Package dimensions available at the time of this publication for the
MC68HC705C8A are provided in this section. The packages are:
•40-pin plastic dual in-line package (PDIP)
•40-pin ceramic dual-in-line package (cerdip)
•44-lead plastic-leaded chip carrier (PLCC)
•44-lead ceramic-leaded chip carrier (CLCC)
•44-pin quad flat pack (QFP)
•42-pin shrink dual in-line package (SDIP)
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Technical Data MC68HC705C8A —Rev. 3
192 Mechanical Specifications
Mechanical Specifications
14.3 40-Pin Plastic Dual In-Line Package (PDIP)
Figure 14-1. MC68HC705C8AP Package Dimensions (Case #711)
120
40 21
B
AC
SEATING
PLANE
DFGH K
N
M
J
L
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A51.69 52.45 2.035 2.065
B13.72 14.22 0.540 0.560
C3.94 5.08 0.155 0.200
D0.36 0.56 0.014 0.022
F1.02 1.52 0.040 0.060
G2.54 BSC 0.100 BSC
H1.65 2.16 0.065 0.085
J0.20 0.38 0.008 0.015
K2.92 3.43 0.115 0.135
L15. 2 4 B SC 0.60 0 B SC
M1°
N0.51 1.02 0.020 0.040
NOTES:
1.POSITION TOLERANCE OF LEADS (D), SHALL
BEWITHIN 0. 25 ( 0. 010) A T M A X IMUM MAT E RIAL
CONDITIONS, IN RELATION TO SEATING PLANE
AND EACH OT HER.
2.DIMENSION L T O CENTER OF LEADS WHEN
FORMED PARALLEL.
3.DIMENSION B DOES NOT I NCLUDE MOLD FLASH.
1°0°0°
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Mechanical Spec ifications
40-Pin Ceramic Dual In-Line Package (Cerdip)
MC68HC705C8A —Rev. 3 T echnical Data
MOTOROLA Mechanical Specifi cations
14.4 40-Pin C eramic Dual In-Line Package (Cerdip)
Figure 14-2. MC68HC705C8AS Package Dimensions (Case #734A)
M
L
JDIM MIN MAX MIN MAX
MILLIMETERSINCHES
A 2.020 2.096 51.31 53.23
B 0.500 0.610 12.70 15.94
C 0.160 0.240 4.06 6.09
D 0.015 0.022 0.38 0.55
F 0.050 0.065 1.27 1.65
G 0.100 BSC 2.54 BSC
J 0.008 0.012 0.20 0.30
K 0.125 0.160 3.17 4.06
L 0.600 BSC 15.24 BSC
M0° 15° 0° 15°
N 0.020 0.050 0.51 1.27
A
φ 0.25(0.010) T
T
40 PLD
1
40
20
21
A
B
GF
KC
N
SEATING
PLANE
DATUM
PLANE
M
M
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Technical Data MC68HC705C8A —Rev. 3
194 Mechanical Specifications
Mechanical Specifications
14.5 44-Lead Plastic-Leaded Chip Carrier (PLCC)
Figure 14-3. MC68HC705C8AF N Package Dimensions (Case #777)
-N-
-L- -M-
D
Y
D
K
VW
144
BRK
B
Z
U
X
VIEW D-D
S
L-M
M
0.007(0.180) N S
T
S
L-M
M
0.007(0.180) N S
T
G1 S
L-M
S
0.010 (0.25) N S
T
K1
F
H
S
L-M
M
0.007(0.180) N S
T
Z
G
G1
R
A
EJ
VIEW S
C
S
L-M
M
0.007(0.180) N S
T
S
L-M
M
0.007(0.180) N S
T
0.004 (0. 10)
-T- SEATING
PLANE
VIEW S
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A0.685 0.695 17.40 17.65
B0.685 0.695 17.40 17.65
C0.165 0.180 4.20 4.57
E0.090 0.110 2.29 2.79
F0.013 0.019 0.33 0.48
G0. 05 0 B SC 1.27 BS C
H0.026 0.032 0.66 0.81
J0.020 0.51
K0.025 0.64
R0.650 0.656 16.51 16.66
U0.650 0.656 16.51 16.66
V0.042 0.048 1.07 1.21
W0.042 0.048 1.07 1.21
X0.042 0.056 1.07 1.42
Y0.020 0.50
Z2°10°
G1 0.610 0.630 15.50 16.00
K1 0.040 1.02
S
L-M
S
0.010 (0. 25) N S
T
S
L-M
M
0.007(0.180) N S
T
2°10°
NOTES:
1.DA TUMS -L-, -M-, AND -N- ARE DETERMINED
WHERE TO P OF LEAD SHOLDERS EXITS
PLASTIC BODY AT MOLD PARTING LINE.
2.DIMENSION G1, TRUE POSITION TO BE
MEASURED AT DATUM -T-, SEATING PLANE.
3.DIMENSION R AND U DO NOT INCLUDE MOLD
FLASH. ALL OWABL E MOLD FLASH IS 0.010
(0.25 ) PER SIDE.
4.DIMENSIONING AND TOLERANCING PER ANSI
Y1 4.5M, 1982.
5.CONTROLLING DIMENSION: INCH.
6.THE PACKAGE TOP MAY BE SMALLER THAN
T HE P ACK AGE BOT T OM BY UP TO 0 .012
(0.300). DIMENSIONS R AND U ARE DETERMINED
AT THE OUTERMOST EXTREMES OF THE
PLASTIC BODY EXCLUSIVE OF THE MOLD
FLASH, TIE BAR BURRS, GATE BURRS AND
INTERLEAD FLASH, BUT INCLUDING ANY
MISMATCH BETWEEN THE TOP AND BOTTOM
OF THE PLASTIC BODY.
7.DIMINSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTUSION(S) SHALL NOT CAUSE THE H
DIMINSION TO BE GREATER THAN 0.037
(0.940198). T HE DAMBAR INTRUSION(S) SHALL
NOT CAUSE THE H DIMINISION TO SMALLER
THAN 0.025 (0.635).
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Mechanical Spec ifications
44-Lead Cerami c-Leaded Chip Carrier (CLCC)
MC68HC705C8A —Rev. 3 T echnical Data
MOTOROLA Mechanical Specifi cations
14.6 44-Lead Ceramic-Leaded Chip Carrier (CLCC)
Figure 14-4. MC68HC705C8AFS Package Dimensions (Case #777B)
17.40
17.40
4.20
2.29
0.33
0.66
0.51
0.64
16.51
6.94
16.51
1.07
1.07
---
14.99
1.02
S
L
M
0.18 (0.007) N -P
S S
T
B
U
G1
S
L
M
0.18 (0.007) N -P
S S
T
S
L
MN -P
S S
T
DETAIL D-D
-N-
M
L
M
0.20 (0. 008) N -P
M M
T
-L-
-P- 144
V
D
W
S
D
YBRK
S
L
M
0.18 (0. 007) N -P
S S
T
S
L
M
0.18 (0. 007) N -P
S S
T
0.10 (0.004)
SEATING
PLANE
-T-
J
E
R
A
G
G1
S
L
S
0.25 (0. 010) N -P
S S
T
DETAIL S
C
S
L
M
0.18 (0. 007) N -P
S S
TS
L
M
0.18 (0.007) N -P
S S
T
FS
L
M
0.18 (0. 007) N -P
S S
TS
L
M
0 .1 8 (0.007 ) N - P
S S
T
H
K
K1
DETAIL S
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A17.65 0.685 0.695
B 17.65 0.685 0.695
C 4.57 0.165 0.180
E 2.79 0.090 0.110
F 0.48 0.013 0.019
G 1.27 BSC 0.050 BSC
H 0.81 0.026 0.032
J --- 0.020 ---
K --- 0.025 ---
R 16.66 0.650 0.656
S 7.26 0.273 0.286
U 16.66 0.650 0.656
V 1.21 0.042 0.048
W 1.21 0.042 0.048
Y 0.50 --- 0.020
G1 16.00 0.590 0.630
K1 --- 0.040 ---
NOTES:
1. DATUMS -L-, -N-, AND -P- DETERMINED
WHERE TO P OF LE AD SHOU L DER EXI T
BODY.
2. DIMINSION G1, TRUE POSITION TO B E
MEASURED AT DATUM -T-, SEATING
PLANE.
3. DIMINSIONS R AND U DO NOT INCLUDE
GLASS MENISCUS. ALLOWABLE GLASS
RUNOUT IS 0.25 (0 .010) PER SIDE.
4. DIMINSIONING AND TOLERANCING PER
AN SI Y14. 5M, 1982.
0.25 (0. 010)
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Technical Data MC68HC705C8A —Rev. 3
196 Mechanical Specifications
Mechanical Specifications
14.7 44-Pin Quad Flat Pack (QFP)
Figure 14-5. MC68HC705C8AF B Package Dimensions (Case #824A)
NOTES:
1. 1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. 2. CONTROLLING DIMENSION: MILLIMETER.
3. 3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD WHERE
THE LEAD EXITS THE PLASTIC BODY AT THE
BOTTOM OF THE PARTING LINE.
4. 4. DATUMS -A-, -B- AND -D- TO BE DETERMINED A T
DATUM PLANE -H-.
5. 5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE -C-.
6. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS 0.25
(0.010) PER SIDE . DIMENSIONS A AND B DO
INCLUDE MOLD MISMATCH AND ARE DETERMINED
AT DATUM PLANE -H-.
7. 7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHA LL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE D DIMENSION AT MAXIMUM
MATERIAL CONDITION. DAMBAR CANNOT BE
LOCATED ON THE LOWER RADIUS OR THE FOOT.
L
33
34
23
22
44
111
12
DETAIL A
-D-
-A-
A
S
A-B
M
0.20 (0.008) D S
C
S
A-B
M
0.20 ( 0.008) D S
H
0.05 ( 0.002) A-B
S
B
S
A-B
M
0.20 ( 0.008) D
S
C
S
A-B
M
0.20 (0. 008) D
S
H
0.05 (0.002) A-B
V
L
-B-
-C-
SEATING
PLANE
M
M
E
HG
C-H- DATUM
PLANE
DETAIL C
0.01 (0.004)
M
-H-
DATUM
PLANE
T
R
KQ
WX
DETAIL C
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A9.90 10.10 0.390 0.398
B9.90 10.10 0.390 0.398
C2.10 2.45 0.083 0.096
D0.30 0.45 0.012 0.018
E2.00 2.10 0.079 0.083
F0.30 0.40 0.012 0.016
G0.80 BSC 0.031 BSC
H--- 0.25 --- 0.010
J0.013 0.23 0.005 0.009
K0.65 0.95 0.026 0.037
L8.00 REF 0.315 REF
M5 10 5 10
N0.13 0.17 0.005 0.007
Q0 7 0 7
R0.13 0.30 0.005 0.012
S12.95 13.45 0.510 0.530
T0.13 --- 0.005 ---
U0 --- 0 ---
V12.95 13.45 0.510 0.530
W0.40 --- 0.016 ---
X1.6 REF 0.063 REF
DETAIL A
B
B
-A-, -B-, -D-
S
A-B
M
0.20 ( 0.008) D S
C
F
N
SECTION B-B
J
D
BASE METAL
°°°°
°°°°
°°
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Mechanical Spec ifications
42-Pin Shr ink Dual In-Line Package (SDIP)
MC68HC705C8A —Rev. 3 T echnical Data
MOTOROLA Mechanical Specifi cations
14.8 42-Pin Shrink Dual In-Line Package (SDIP)
Figure 14-6. MC68HC705C8AB Package Dimensions (Case #858)
1.435
0.540
0.155
0.014
0.032
0.008
0.115
0°
0.020
1.465
0.560
0.200
0.022
0.046
0.015
0.135
15°
0.040
37.21
14.22
5.08
0.56
1.17
0.38
3.43
15°
1.02
36.45
13.72
3.94
0.36
0.81
0.20
2.92
0°
0.51
-B-
-A-
C
D 42 PL
FK
GN
J 42 PL M
MIN MINMAX MAX
INCHES MILLIMETERS
DIM
A
B
C
D
F
G
H
J
K
L
M
N
H
L
1.778 BSC0.070 BSC
7.62 BSC0.300 BSC
15.24 BSC0.600 BSC
0.25 (0.010) T A
MS0.25 (0.010) T B
MS
NOTES:
1. DIMENSIONS AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSIONS A AND B DO NOT INCLUDE MOLD
FLASH. MAXIMUM MOLD FLASH 0.25 (0.010).
121
42 22
SEATING
PLANE
-T-
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Technical Data MC68HC705C8A —Rev. 3
198 Mechanical Specifications
Mechanical Specifications
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MC68HC705C8A —Rev. 3 Tec hnical Data
MOTOROLA Ordering Information
Technical Data — MC68HC705C8 A
Section 15. Orde ring Information
15.1 Contents
15.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199
15.3 MCU Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199
15.2 Introduction
This section contains ordering information for the available package
types.
15.3 MCU Order Numb ers
Table 15-1 lists the MC order numbers.
Ta ble 15-1. MC68HC7 05C8A Orde r Nu mb ers
Package Type Temperature Range Order Number
40-pin plastic dual in-li ne pac kage (PDIP ) –40°C to +85°CMC68HC705C8AC(1)P(2)
44-lead plastic-leaded chip carrier (P LCC) –40°C to +85°CMC68HC705C8ACFN(3)
44-lead ceramic-leaded chip carrier (CLCC) –40°C to + 85°CMC68HC705C8ACFS(4)
40-pin windowed ceramic DIP (Cerdip) –40°C to +85°CMC68HC705C8ACS(5)
44-pin quad flat pack (QFP) –40°C to +85°CMC68HC705C8ACFB(6)
42-pin shrink dual in-line package (SDIP) –40°C to +85°CMC68HC705C8ACB(7)
1. C = Extended temperature range (–40°C to +85 °C)
2. P = Plastic dual i n-l ine package (PDIP)
3. FN = Plastic-leaded chip carrier ( PLCC)
4. FS = Cerami c-leaded chip carrier (CLCC)
5. S = Windowed ceramic dual in-line package (Cerdip)
6. FB = Quad flat pack ( QFP)
7. B = Shrink dual in- li ne package (SDIP)
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Technical Data MC68HC705C8A —Rev. 3
200 Ordering Information
Ordering Information
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MC68HC705C8A —Rev. 3 Tec hnical Data
MOTOROLA MC68HSC705C8A
Technical Data — MC68HC705C8 A
Appendix A. MC68HSC705C8A
A.1 Co ntents
A.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .201
A.3 5.0-Volt High-Speed DC Electrical Characteristics. . . . . . . . .202
A.4 3.3-Volt High-Speed DC Electrical Characteristics . . . . . . . .203
A.5 5.0-Volt High-Speed Control Timing. . . . . . . . . . . . . . . . . . . .204
A.6 3.3-Volt High-Speed Control Timing. . . . . . . . . . . . . . . . . . . .204
A.7 5.0-Volt High-Speed SPI Timing . . . . . . . . . . . . . . . . . . . . . .205
A.8 3.3-Volt High-Speed SPI Timing. . . . . . . . . . . . . . . . . . . . . . .207
A.9 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209
A.2 Introdu ct ion
The MC68HSC705C8A is an enhanced, high-speed version of the
MC68HC705C8A, featuring a 4-MHz bus speed.
The data in this document, MC68HC705C8A Technical Data Rev. 3,
applies to the MC68HSC705C8A with the exceptions given in this
appendix.
The computer operating properly (COP) mode bits (CM1 and CM0 in th e
COP control register) select the timeout period of the programmable
COP watchdog, as shown in Table A-1. See Figure 5-3.
Programmable COP Control Register (COPCR).
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Technical Data MC68HC705C8A —Rev. 3
202 MC68HSC705C8A
MC68HSC705C8A
A.3 5.0-Volt High-Speed DC Electrical Characteristics
Table A-1. Programm able COP Timeout Period Selection
CM1:CM0 COP
Timeout
Rate
Programm a bl e C OP Ti m e ou t Peri od
fOSC = 8.0 MHz
fOP = 4.0 MHz fOSC = 4.0 MHz
fOP = 2.0 MHz fOSC = 3. 5795 MHz
fOP = 1.7897 MHz fOSC = 2.0 MHz
fOP = 1.0 MHz
00 fOP ÷ 215 8.192 ms 16.38 ms 18.31 ms 32.77 ms
01 fOP ÷ 217 32.77 ms 65.54 ms 73.24 ms 131.07 ms
10 fOP ÷ 219 131.07 ms 262.14 ms 292.95 ms 524. 29 m s
11 fOP ÷ ÷221 524. 29 ms 1.048 s 1. 172 s 2. 097 s
Characteristic(1)
1. VDD = 5 V ± 10%; VSS = 0 Vdc, TA = TL to TH, unless otherwise n oted
Symbol Min Typ(2)
2. Typical values reflect aver age m easurements at midpoint of voltag e range at 25°C.
Max Unit
Output high voltage
ILoad = –0.8 mA
PA7–PA0, PB7–PB0, PC6–PC0, TCMP
ILoad = –1.6 mA
PD4–PD1
ILoad = –5.0 mA
PC7
VOH VDD – 0.8 —
—
—
—
—
—
V
Output l ow voltage
ILoad = 1.6 mA
PA7–PA0, PB7–PB0, PC6–PC0, PD4–PD1
ILoad = 20 mA
PC7
VOL —
—
—
—
0.4
0.4
V
Supply current(3)
Run(4)
Wait(5)
Stop(6)
25°C
–40°C to +85°C
3. IDD measured wit h port B pull up devices disabled.
4. Run (oper ati ng) IDD measur ed using external square wa ve clock s ource (fOSC = 8.0 MHz). All inputs 0.2 V from r ail. No dc
loads. Less than 50 pF on all outputs. CL = 20 pF on OSC2. OSC2 capacitance linearly affects run IDD.
5. W ait IDD m easure d using ex ter nal squ are wave cl ock s ource ( fOSC = 8.0 MHz). Al l inp uts 0.2 V from r ail. No dc loads . Less
than 50 pF on al l output s. CL = 20 pF on OSC2. VIL = 0.2 V, VIH = VDD – 0.2 V. All ports co nfigur ed as input s. SPI and SCI
disabled. If SPI and SCI enabl ed, ad d 10% current draw. OSC2 capac it ance linearly aff ects wait IDD.
6. Stop IDD measured with OSC1 = VDD. All ports configur ed as inputs. VIL = 0.2 V, VIH = VDD – 0. 2 V.
IDD
—
—
—
—
5.92
2.27
5
2.0
14
7.0
50
50
mA
mA
µA
µA
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MC68HSC705C8A
MC68HC705C8A —Rev. 3 T echnical Data
MOTOROLA MC68HSC705C8A
A.4 3.3-Volt High-Speed DC Electrical Characteristics
Characteristic(1)
1. VDD = 3.3 V ± 10%; VSS = 0 Vdc, TA = TL to TH, unless otherwise noted
Symbol Min Typ(2)
2. Typical values reflect aver age m easurements at midpoint of voltag e range at 25°C.
Max Unit
Output high voltage
ILoad = –0.2 mA
PA7–PA0, PB7–PB0, PC6–PC0, TCMP
ILoad = –0.4 mA
PD4–PD1
ILoad = –1.5 mA
PC7
VOH VDD – 0.3 —
—
—
—
—
—
V
Output low voltage
ILoad = 0.4 mA
PA7–PA0, PB7–PB0, PC6–PC0, PD 4 –PD1
ILoad = 6.0 mA
PC7
VOL —
—
—
—
0.3
0.3
V
Supply cu rre nt(3)
Run(4)
Wait(5)
Stop(6)
3. IDD me asured with port B pullup devices disabl ed.
4. Run (oper ati ng) IDD m easured usi ng externa l square wa ve clock s ource (fOSC = 4.2 MH z). All inputs 0.2 V from rail. No dc
loads. Less than 50 pF on all outputs. CL = 20 pF on OSC2. OSC2 capacitance linearly aff ects run IDD.
5. W ait IDD m easure d using ex ter nal squ are wave cl ock s ource ( fOSC = 4.2 MHz). Al l inp uts 0.2 V from r ail. No dc loads . Less
than 50 pF on al l output s. CL = 20 pF on OSC2. VIL = 0.2 V, VIH = VDD – 0.2 V. Al l ports con figur ed as input s. SPI and SCI
disabled. If SPI and SCI enabl ed, ad d 10% current draw. OSC2 capac it ance linearly aff ects wait IDD.
6. Stop IDD measured with OSC1 = VDD. All ports configur ed as inputs. VIL = 0.2 V; VIH = VDD – 0.2 V.
IDD —
—
—
1.91
0.915
2.0
6.0
2.0
20
mA
mA
µA
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Technical Data MC68HC705C8A —Rev. 3
204 MC68HSC705C8A
MC68HSC705C8A
A.5 5.0-Volt High-Speed Control Timing
A.6 3.3-Volt High-Speed Control Timing
Characteristic(1) Symbol Min Max Unit
Oscillator freq uenc y
Cry st al o s c illator
External clock fOSC —
dc 8.0
8.0 MHz
Internal operating frequency (f OSC ÷ 2)
Cry st al o s c illator
External clock fOP —
dc 4.0
4.0 MHz
Cycle time tCYC 250 —ns
Input capture pulse width tTH, tTL 65 —ns
Interrupt pulse width low (edge-triggered ) tILIH 65 —ns
OSC1 pulse width tOH, tOL 45 —ns
1. VDD = 5 V ± 10%; VSS = 0 Vdc, TA = TL to TH, unless otherwise n oted
Characteristic(1) Symbol Min Max Unit
Oscillator frequency
Cry st al oscillator
External clock fOSC —
dc 4.0
4.0 MHz
Internal operating frequenc y (fOSC ÷ 2)
Cry st al o s c illator
External clock fOP —
dc 2.0
2.0 MHz
Cycle time tCYC 476 —ns
Input capture pulse width tTH, tTL 125 —ns
Interrupt pulse width low (edge-triggered) tILIH 125 —ns
OSC1 pulse width tOH, tOL 90 —ns
1. VDD = 3.3 V ± 10%; VSS = 0 Vdc, TA = TL to TH, unless otherwise noted
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MC68HSC705C8A
MC68HC705C8A —Rev. 3 T echnical Data
MOTOROLA MC68HSC705C8A
A.7 5.0-Volt High-Speed SPI Timing
Diagram
Number(1) Characteristic(2) Symbol Min Max Unit
Operating frequency
Master
Slave fOP(S)
fOP(S)
dc
dc 0.5
4.0 fOP
MHz
1Cycle time
Master
Slave tCYC(M)
tCYC(S)
2.0
250 —
—tCYC
ns
2Enable lead time
Master
Slave tLead(M)
tLead(S) No te (3)
125 —
—ns
3Enable lag time
Master
Slave tLag(M)
tLag(S) Note(2)
375 —
—ns
4Clock (SCK) high ti me
Master
Slave tW(SCKH)M
tW(SCKH)S
170
95 —
—ns
5Clock (SCK) low time
Master
Slave tW(SCKL)M
tW(SCKL)S
170
95 —
—ns
6Data setup t i me (inputs)
Master
Slave tSU(M)
tSU(S)
50
50 —
—ns
7Data hold time (input s)
Master
Slave tH(M)
tH(S)
50
50 —
—ns
8Acce ss time(4)
Slave tA060ns
9Disable time(5)
Slave tDIS —120 ns
10 Data valid time
Master (before capture edge)
Slave (after enable edge)(6) tV(M)
tV(S)
0.25
——
120 tCYC(M)
ns
Continued
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Technical Data MC68HC705C8A —Rev. 3
206 MC68HSC705C8A
MC68HSC705C8A
11 Data hold time (outputs)
Master (after capture edge)
Slave (after enable edge) tHO(M)
tHO(S)
0.25
0—
—tCYC(M)
ns
12 Rise ti me(7)
SPI outputs (SCK, MOSI, MISO)
SPI inputs (SCK, MO SI, MISO, SS)tRM
tRS
—
—50
2.0 ns
µs
13 Fall time(8)
SPI outputs (SCK, MOSI, MISO)
SPI inputs (SCK, MO SI, MISO, SS)tFM
tFS
—
—50
2.0 ns
µs
1. Diagram numbers refer to dimensions in Figure 13-8. SPI Master Timing and Figure 13-9. SPI Slave Ti ming.
2. VDD = 5 V ± 10%; VSS = 0 Vdc, TA = TL to TH, unless otherwise n oted
3. Signal production depends on software.
4. Time to data active from high-impedance st ate
5. Hold time to high- impedance state
6. With 200 pF on all SPI pins.
7. 20% of VDD to 70% of VDD; C L = 200 pF
8. 70% of VDD to 20% of VDD; C L = 200 pF
Diagram
Number(1) Characteristic(2) Symbol Min Max Unit
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MC68HSC705C8A
MC68HC705C8A —Rev. 3 T echnical Data
MOTOROLA MC68HSC705C8A
A.8 3.3-Volt High-Speed SPI Timing
Diagram
Number(1) Characteristic(2) Symbol Min Max Unit
Operati ng frequency
Master
Slave fOP(S)
fOP(S)
dc
dc 0.5
2.1 fOP
MHz
1Cycle time
Master
Slave tCYC(M)
tCYC(S)
2.0
480 —
—tCYC
ns
2Enable lead time
Master
Slave tLead(M)
tLead(S) Note (3)
240 —
—ns
3Enable lag time
Master
Slave tLag(M)
tLag(S) Note(2)
720 —
—ns
4Clock (SCK) high time
Master
Slave tW(SCKH)M
tW(SCKH)S
340
190 —
—ns
5Clock (SCK) low time
Master
Slave tW(SCKL)M
tW(SCKL)S
340
190 —
—ns
6Data setup t i me (inputs)
Master
Slave tSU(M)
tSU(S)
100
100 —
—ns
7Data ho ld time (inputs)
Master
Slave tH(M)
tH(S)
100
100 —
—ns
8Access time(4)
Slave tA0 120 ns
9Disable t ime(5)
Slave tDIS —240 ns
10 Data valid ti me
Master (before capture edge)
Slave (a fter enable edge)(6) tV(M)
tV(S)
0.25
——
240 tCYC(M)
ns
Continued
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Technical Data MC68HC705C8A —Rev. 3
208 MC68HSC705C8A
MC68HSC705C8A
11 Data ho ld tim e (output s)
Master (after c ap ture edge )
Slave (a fter enable edge) tHO(M)
tHO(S)
0.25
0—
—tCYC(M)
ns
12 Rise time (7)
SPI outputs (SCK, MOSI, MISO)
SPI inputs (SCK, MOSI, M ISO , SS)tRM
tRS
—
—100
2.0 ns
µs
13 Fall time(8)
SPI outputs (SCK, MOSI, MISO)
SPI inputs (SCK, MOSI, M ISO , SS)tFM
tFS
—
—100
2.0 ns
µs
1. Diagram numbers refer to dimensions in Figur e 13-8. SPI Master Timing and Figure 13-9. SPI Slave Ti ming.
2. VDD = 3.3 V ± 10%; VSS = 0 Vdc, TA = TL to TH, unless otherwise noted
3. Signal pr oduction depe nds on software.
4. Time to data active from high-impedance st ate
5. Hold time to high- impedance state
6. With 200 pF on all SPI pins
7. 20% of VDD to 70% of VDD; C L = 200 pF
8. 70% of VDD to 20% of VDD; C L = 200 pF
Diagram
Number(1) Characteristic(2) Symbol Min Max Unit
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MC68HSC705C8A
MC68HC705C8A —Rev. 3 T echnical Data
MOTOROLA MC68HSC705C8A
A. 9 Or dering Information
Tabl e A-2 provides ordering information for the MC68HSC705C8A.
Ta ble A-2. M C68HSC705C8A Order Numbers
Package Type Temperature Range Order Number
40-pin plastic dual i n-l ine package (PDIP) –40°C to +85°CMC68HSC705C8AC(1)P(2)
44-lead plastic-leaded chip carri er (PLCC) –40°C to +85°CMC68HSC705C8ACFN(3)
44-lead ceramic-l eaded chip carrier (CLCC) –40°C to +85°CMC68HSC705C8ACFS(4)
40-pin ceramic DIP (cerdip) –40°C to +8 5°CMC68HSC705C8ACS(5)
44-pin quad f lat pack ( Q FP) –40°C to +85°CMC68HSC705C8ACFB(6)
42-pin shrink dual in- li ne package (SDIP) –40°C to +85°CMC68HSC705C8ACB(7)
1. C = Extended temperature range (–40°C to +8 5 °C)
2. P = Plastic dual in-li ne package (PDIP)
3. FN = Plastic- leaded chip car rier (PLCC)
4. FS = Ceramic-leaded chip carrier (CLCC)
5. S = Wind owed ceramic dual in-l ine package (cerdi p)
6. FB = Quad f lat pack ( QFP)
7. B = Shrink dual in-line package (SDIP)
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Technical Data MC68HC705C8A —Rev. 3
210 MC68HSC705C8A
MC68HSC705C8A
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MC68HC705C8A —Rev. 3 Tec hnical Data
MOTOROLA Index
Technical Data — MC68HC705C8 A
Index
A
accumulator (A). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45, 154, 155, 158
addressing modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
arithmetic/logic unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
B
block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
bootloader ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
C
C bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
condition code register (CCR). . . . . . . . . . . . . . . . . . . . . . . . . . 47, 160
COP watchdog (non-programmable)
diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
in stop mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
timeout period formula . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6
when clock monitor enabled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
COP watchdog (programmable)
COP control register (COPCR) . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4
COP reset register (COPRST). . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4
diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
in stop mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
timeout period selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
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Technical Data MC68HC705C8A —Rev. 3
212 Index
Index
CPU
instruction set summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
instructi on types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
programming model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155, 158, 163
accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154, 155, 158
condition code register (CCR) . . . . . . . . . . . . . . . . . . . . . . . . . . 160
index register (X) . . . . . . . . . . . . . . . . . . . . . . . . 154, 155, 156, 158
program counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157, 160
D
data-retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
E
electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
DC electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
power considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
electrical specifications (high-speed part)
control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
DC electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
orderi ng inform ation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
SPI timin g. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
EPROM/OTPROM (PROM) . . . . . . . . . . . . . . . . . . . . . . . . . . . 37, 103
control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
EPROM erasing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
mask option register 1 (MOR1) . . . . . . . . . . . . . . . . . . . . . . . . . 117
mask option register 2 (MOR2) . . . . . . . . . . . . . . . . . . . . . . . . . 118
option register (option). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
preprogramming steps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
program register (PROG). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
MC68HC05PGMR programmer board. . . . . . . . . . . . . . . . . 104
programming circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
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Index
MC68HC705C8A —Rev. 3 T echnical Data
MOTOROLA Index
programming flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
programming routines . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108, 111
F
features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
H
high-speed part (MC68HSC705C8A) . . . . . . . . . . . . . . . . . . . . . . . 201
I
I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6, 77
data direction register A (DDRA) . . . . . . . . . . . . . . . . . . . . . . . . . 79
data direction register B (DDRB) . . . . . . . . . . . . . . . . . . . . . . . . . 82
data direction register C (DDRC). . . . . . . . . . . . . . . . . . . . . . . . . 86
port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
port A data register (PORTA). . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
port A I/O logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
port A pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
port B data register (PORTB). . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
port B I/O logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
port B pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
port C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
port C data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
port C I/O logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
port C pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
port D. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
I/O bits
C bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
I/O register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
index register (X). . . . . . . . . . . . . . . . . . . . . . . . 45, 154, 155, 156, 158
instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
instruction set summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
instructi on types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
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Technical Data MC68HC705C8A —Rev. 3
214 Index
Index
interrupt processing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
reset/interr upt vector addresses. . . . . . . . . . . . . . . . . . . . . . . . . . 57
stacking order. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
interrupts
ext erna l in terr upt (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
internal function diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
masking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
port B interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
enabling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
port B I/O logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
SCI interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5
software interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 9
SPI interrup ts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
timer interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
IRQ pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
J
junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
L
low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
data-retention mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
stop mode
non-programmable COP in stop mode flowchart . . . . . . . . . . 74
non-programmable COP watchdog in stop mode. . . . . . . . . . 73
programmable COP in stop mode flowchart. . . . . . . . . . . . . . 72
programmable COP watchdog in stop mode . . . . . . . . . . . . . 71
SCI during stop mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
SPI during stop mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
stop/wait mode function flowchart. . . . . . . . . . . . . . . . . . . . . . 70
wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
non-programmable COP watchdog in wait mode. . . . . . . . . . 75
programmable COP watchdog in wait mode . . . . . . . . . . . . . 7 5
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Index
MC68HC705C8A —Rev. 3 T echnical Data
MOTOROLA Index
M
mask option registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23, 117, 118
MC68HSC705C8A (high-speed part) . . . . . . . . . . . . . . . . . . . . . . . 201
control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
DC electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
orderi ng inform ation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
programmable COP timeout period selection . . . . . . . . . . . . . . 202
SPI timin g. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
mechanica l specification s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
memory
bootloader ROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
I/O register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
memo ry m ap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35, 38
PROM (E PROM/OTPROM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
memo ry m ap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35, 38
O
on-chip memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
opcode map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
option register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3
orderi ng inform ation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
OSC1 pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
OSC2 pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
oscillator
ceramic resonator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
crystal resonator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
externa l clock signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
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Technical Data MC68HC705C8A —Rev. 3
216 Index
Index
P
pin assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
port A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33, 78
data direction register A (DDRA) . . . . . . . . . . . . . . . . . . . . . . . . . 79
port A data register (PORT A) . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
port A I/O logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
port A pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
port B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33, 81
data direction register B (DDRB) . . . . . . . . . . . . . . . . . . . . . . . . . 82
port B data register (PORTB). . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
port B I/O logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
port B pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
port C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33, 85
data direction register C (DDRC). . . . . . . . . . . . . . . . . . . . . . . . . 86
port C data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
port C I/O logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
port C pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
port D. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33, 88
power dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
program counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46, 157, 160
programmable options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3
programming model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
PROM (E PROM/OTPROM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
R
RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
registers
I/O register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
reset and interrupt processing flowchart . . . . . . . . . . . . . . . . . . . . . . 59
RESET pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
clock monitor reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65, 67
with STOP instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
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Index
MC68HC705C8A —Rev. 3 T echnical Data
MOTOROLA Index
COP watchdog resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
non-programmable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
non-programmable COP watchdog diagram . . . . . . . . . . . . . 6 7
programmable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
programmable COP watchdog diagram . . . . . . . . . . . . . . . . . 63
enabling both programmable and non-programmable COPs . . . 65
ext erna l reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
power-on reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
reset sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
ROM (bootloader) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
S
serial communications interface (SCI). . . . . . . . . . . . . . . . . . . . . . . 121
baud rate generator clock prescaling. . . . . . . . . . . . . . . . . . . . . 136
baud rate register (baud) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
baud rate selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
baud rate selection examples . . . . . . . . . . . . . . . . . . . . . . . . . . 138
during stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
SCI control register 1 (SCCR1) . . . . . . . . . . . . . . . . . . . . . . . . . 130
SCI control register 2 (SCCR2) . . . . . . . . . . . . . . . . . . . . . . . . . 131
SCI data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
SCI data register (SCDR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
SCI I/O registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
SCI interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
SCI operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
SCI receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
SCI status register (SCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
SCI transmitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
serial peripheral interface (SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
during stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
master/slave connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
multiple-SPI systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
pin functions in master mode. . . . . . . . . . . . . . . . . . . . . . . . . . . 143
pin functions in slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
serial clock polarity and phase. . . . . . . . . . . . . . . . . . . . . . . . . . 146
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Technical Data MC68HC705C8A —Rev. 3
218 Index
Index
SPI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
SPI clock/data timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
SPI control register (SPCR). . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
SPI data register (SPDR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
SPI error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
SPI I/O register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
SPI I/O registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
SPI interrup ts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
SPI operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
SPI status register (SPSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
stack pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
stop mode
non-programmable COP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
non-programmable COP flowchart . . . . . . . . . . . . . . . . . . . . . . . . 74
programmable COP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
programmable COP flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
SCI during stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
SPI during stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
stop/wait mode function flowchart . . . . . . . . . . . . . . . . . . . . . . . . 70
T
TCAP pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
TCMP pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
thermal resistance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
alternate timer registers (A TRH and ATRL). . . . . . . . . . . . . . . . . 9 9
I/O registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4
input capture registers (ICRH and ICRL). . . . . . . . . . . . . . . . . . 100
output compare registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
timer control register (TCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
timer I/O register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
timer interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
timer operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
timer registers (TRH and TRL). . . . . . . . . . . . . . . . . . . . . . . . . . . 97
timer status register (TSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
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Index
MC68HC705C8A —Rev. 3 T echnical Data
MOTOROLA Index
V
VDD pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
VSS pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 9
VPP pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 9
W
wait mode
non-programmable COP watchdog in wait mode . . . . . . . . . . . . 75
programmable COP watchdog in wait mode . . . . . . . . . . . . . . . . 75
stop/wait mode function flowchart . . . . . . . . . . . . . . . . . . . . . . . . 70
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Technical Data MC68HC705C8A —Rev. 3
220 Index
Index
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MC68HC705C8A/D
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