© Semiconductor Components Industries, LLC, 2019
April, 2018 − Rev. 0
1Publication Order Number:
ONA10IV/D
ONA10IV
16 Watt Digital Input
Class-D Audio Amplifier
with Speaker Sense Digital
Output
Description
The ONA10IV is a digital input, mono Class−D audio amplifier
with real time, integrated current and voltage sensing of the
loudspeaker it’s driving. This sense data is transmitted to the host
through a separate digital output.
The ONA10IV can be directly connected to a 2−cell (2S) or 3−cell
(3S) battery and offers a fast automatic gain control (AGC) for
brownout protection that can react within 10 s.
Up to eight devices can share the digital audio interfaces through
I2C control. A separate bus (MAGC) is used to synchronize gain
across multiple ONA10IV instantiations during a brownout protection
event.
Key Features
•Filter−less, Mono Class−D Amplifier
♦16 W into 4 / 14 V Supply (1% THD+N)
♦13.8 W into 4 / 12 V Supply (1% THD+N)
♦500 V “Click and Pop” Suppression
♦42 VRMS Noise Floor (A−Weighted)
♦No Boost Capacitors Required
•Speaker Voltage & Current Sense
♦Up to 20 kHz Bandwidth
♦81 / 71 dBA Dynamic Range (Voltage / Current)
♦0.5% V/I Gain Error Variation
•Digital Audio / Sense Configurations
♦16 kHz to 96 kHz Audio Sampling Rates
♦16−, 24−, and 32−Bit I2S Data
♦16−, 24−, and 32−Bit TDM Data (up to 8 Slots)
♦Selectable PCM or PDM Format
•I2C Fast Mode (up to 1 MHz) Control
•EMI Reduction Controls
•Over Current and Thermal Protection
•PVDD Power Supply: 5.5 V to 14 V
•DVDD Power Supply: 1.62 V to 1.98 V
•30−Bump WLCSP
♦2.31 mm x 2.89 mm, 0.4mm pitch
•This is a Pb−Free Device
Applications
•Laptops, Smart Speakers, Portable Speakers, and Other IoT Devices
www.onsemi.com
WLCSP30
CASE 567VB
MARKING DIAGRAM
VD = Specific Device Code
ZZ = Wafer Lot
YW = Date Code
A = Assembly Location
VDZZ
D YWA
Device Package Shipping†
ORDERING INFORMATION
NCA−
ONA10IVUCX
WLCSP30
(Pb−Free)
3000 Units /
Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
ONA10IV
www.onsemi.com
2
Capabilities
•Filter−less Class D Amplifier: Capable of operating off of
direct 2−cell (2S) or 3−cell (3S) battery connection or a
regulated supply from 5.5 V to 14 V.
•Current and Voltage Speaker Sensing: Able to sense up to
20 kHz with low gain error variation.
•TDM / I2S Digital Audio Input: Programmable interface
that can support 16 kHz to 96 kHz sample rates with up
to eight 16− to 32−bit input slots. Ability to select CKI
active edge as well as FRCK polarity, delay, and pulse
mode.
•PDM Digital Audio Input/Output: Ability to bypass
embedded digital filters and drive/sense the speaker using
pulse density modulation (PDM) interface.
•TDM / I2S Digital Sense Path Output: Can provide die
temperature, current and voltage speaker sense data in up
to 8 slots.
•Volume Control: Ability to adjust volume in 0.375 dB
steps and automatically ramp on start up or shut down
using 4 different rates.
•Amplifier Gain: Independently adjustable for PCM or
PDM mode.
•EMI Reduction Controls: 4 selectable edge rates and 8
spread spectrum modes to accommodate EMI reduction
per system needs.
•Brownout Protection: Fast reaction of less than 10 s with
ability to customize attack threshold for a 2−cell or 3−cell
battery. Maximum attenuation as well as attack, hold, and
release timing programming available to adjust the
dynamic response to a brownout event.
•MAGC Synchronous Gain Adjustments: Dedicated bus to
synchronize multiple chip instantiations to within 0.5 dB.
•Fatal Protections: Includes output over−current, supply
under−voltage, clock error, and chip over−temperature
protections that are always on when the amplifier is
active. The ONA10IV can recover from each fatal
protection automatically without host intervention.
•Interrupt Flags: Indicate when a fatal protection,
brownout protection, or thermal foldback is active.
•Thermal Foldback: Ability to customize the chip’s
thermal response to elevated die temperature using four
programmable thresholds. Attack, hold, and release
timing customization also available.
•Power Reduction Options: Ability to disable features like
IV sensing, brownout protection, and thermal foldback to
reduce power consumption.
ONA10IV
www.onsemi.com
3
OUT+
OUT−
AGND
DAC
Digital Audio
Interface
PCM or PDM
DATAI
FRCK
MCK
VSNS+
VSNS−
ADC
Analog
Gain
Adjust
& PWM
H−Bridge
Speaker
Driver
ADC
Speaker
IV Sense
PGND
DATAO
MAGC Interface
SCL
SDA I2C Interface
DVDD
DVDD (1.62 V to 1.98 V)
PVDD
CPVDD
PVDD (5.5 V to 14 V)
VREG
CREF
Digital Sense
Interface
PCM or PDM
INT_N
SD_N
VREF
CREG
ADDR
CDVDD
MAGC
ADC
Die
Temp
Sense
& AGC
To Digital Sense Interface
AGC
CKI
Digital
Filtering
DGND
Digital Filtering &
Calibration
(PCM only)
Volume Control,
Digital Filtering, &
Calibration (PCM only)
LDO
1.1 F1 F1 F22 F
Figure 1. Functional Diagram
Figure 2. System Diagram
Digital Audio
Processor
w/ Speaker
Algorithms
ONA10IV
Digital Audio Data Out
Digital Sense Data In
DATAO
DATAI
Speaker
OUT+
VSNS+
VSNS−
OUT−
Speaker
OUT+
VSNS+
VSNS−
OUT−
Speaker
OUT+
VSNS+
VSNS−
OUT−
Speaker
OUT+
VSNS+
VSNS−
OUT−
DATAO
DATAI
DATAI
DATAO
DATAI
DATAO
ONA10IV
ONA10IV
ONA10IV
ONA10IV
www.onsemi.com
4
PIN CONFIGURATION
DATAI MCK CKI
DVDD SCL FRCK
VREG ADDR SDA
PGND PGND DGND
A
B
C
D
123
MAGC
INT_N
SD_N
PGND
4
OUT−OUT−VSNS+
EOUT+
DATAO
AGND
VREF
PGND
5
OUT+
PVDD PVDD VSNS−
FPVDD PVDD
DATAI
MCK
CKI
DVDDSCLFRCK
VREG
ADDRSDA
PGNDPGND
DGND
A
B
C
D
1
23
MAGC
INT_N
SD_N
PGND
4
OUT−OUT−
VSNS+ E
OUT+
DATAO
AGND
VREF
PGND
5
OUT+
PVDDPVDDVSNS−F
PVDD
PVDD
Figure 3. Top Through View (Balls Down) Figure 4. Bottom View (Balls Up)
PIN DESCRIPTION
Pin No. Name Type Description
A1 DATAI Data Input DAI – Serial Digital Audio Data (either I2S or PDM)
A2 MCK Clock Input DAI − Master Clock
A3 CKI Clock Input DAI – Bit Clock (PCM Mode) / PDM Clock (PDM Mode) Input
A4 MAGC Control Bidirectional Multi−speaker automatic gain control (MAGC) to synchronize multiple ONA10IV
instantiations
A5 DATAO Data Output PDM or Serial PCM Speaker Sense Data Output
B1 DVDD Power Digital Power Supply
B2 SCL Clock Input I2C − Clock Signal
B3 FRCK Clock Input DAI − Frame Clock (PCM Mode)
B4 INT_N Control Output Interrupt Request Signal
B5 AGND Ground Analog Ground
C1 VREG Analog Output Internal LDO Regulator Output
C2 ADDR Control Input Hardware selection of I2C address to allow multiple ONA10IV instantiations.
C3 SDA Data Bidirectional I2C − Data Signal
C4 SD_N Control Input Shutdown (Active Low)
C5 VREF Analog Output Internally Generated Reference
D1, D2, D4, D5 PGND Ground High Power Ground
D3 DGND Ground Digital Ground
E1,E2 OUT−Analog Output Inverting Class D Amplifier Output
E3 VSNS+ Analog Input Positive Analog Input for Voltage Sense
E4, E5 OUT+ Analog Output Non−inverting Class D Amplifier Output
F1,F2,F4,F5 PVDD Power Output Driver Power Supply
F3 VSNS−Analog Input Negative Analog Input for Voltage Sense
ONA10IV
www.onsemi.com
5
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Min Max Unit
PVDD Voltage on PVDD Pin −0.3 17.0 V
DVDD Voltage on DVDD Pin −0.3 2.2 V
VOUT Voltage on OUT− and OUT+ Pins (Output Disabled) −0.3 PVDD + 0.3 V
Voltage on INT_N, DATAO, and MAGC Pins (Output Disabled) −0.3 6.0
VIN Voltage on VSNS− and VSNS+ Pins −0.3 PVDD + 0.3
VCNTRL Control Input Voltage SCL, SDA, ADDR, CKI, DATAI,
MCK, FRCK, MAGC, SD_N
−0.3 6.0 V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
THERMAL RATINGS
Symbol Parameter Min Typ Max Unit
TJJunction Temperature − − 150 °C
TSTG Storage Temperature Range −65 −150 °C
TLLead Temperature (Soldering, 10 s) − − 300 °C
JA Thermal Resistance, JEDEC Standard, Still Air 4−layer Board −55 (Note 1) −°C/W
4−layer Board w/ vias −33 (Note 2) −
PDMaximum continuous on−chip power dissipation (TA = 25°C) for multi−layer board −3.0 −W
1. More layers can provide a lower JA.
2. JEDEC standard board utilizes a via for each ball.
ESD PROTECTION
Symbol Parameter Condition Min Unit
ESD Human Body Model (HBM) ANSI/ESDA/ JEDEC JS−001−2012 2 kV
Charged Device Model (CDM) According to “EIA/JESD22−C101 Level III” 500 V
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min (Note 3) Typ Max Unit
TAOperating Temperature Range −40 −85 °C
DVDD Digital Supply Voltage Range 1.62 −1.98 V
PVDD Power Supply Voltage Range (2S− Battery Configuration) 5.5 −9.0 V
Power Supply Voltage Range (3S− Battery Configuration) 7.5 −14.0 V
CREF Reference Capacitor 0.85 − − F
CREG Regulator Capacitor 0.85 − − F
CPVDD PVDD Capacitor (s) 20 − − F
CDVDD DVDD Capacitor (s) 0.85 − − F
RPD_DATAO Pull down resistor; Only 1 required per DATAO bus − − 10 k
ZLLoad Inductance −10 −H
Load Resistance 4− −
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
3. Minimum passive component values include temperature, tolerance, and aging.
ONA10IV
www.onsemi.com
6
ELECTRICAL CHARACTERISTICS (PVDD = 12 V, DVDD = 1.8 V, fS= FRCK = 48 kHz, 24−bit digital audio data, ZL=∞,T
A=25°C,
SD_N = H, Default I2C registers, and audio measurement bandwidth = 20 Hz to 20 kHz (AES17) unless otherwise noted)
Symbol Parameter Conditions Min Typ Max Unit
SPEAKER DRIVER PATH
POMaximum Continuous
Output Power
THD+N ≤ 10%, f = 1 kHz ZL = 4 + 10 H
PVDD = 12 V
−16.0 −W
THD+N ≤ 1%, f = 1 kHz ZL = 4 + 10 H
PVDD = 12 V
−13.8 −
ZL = 8 + 10 H
PVDD = 14 V
−10.9 −
ZL = 8 + 10 H
PVDD = 12 V
−8.1 −
ZL = 8 + 10 H
PVDD = 10.8 V
−6.5 −
ZL = 8 + 10 H
PVDD = 7.2 V
−2.9 −
RON On Resistance of Output
Stage
IO = 500 mA
High Side + Low Side Resistance
−435 −m
Efficiency f = 1 kHz, PVDD = 14 V POUT = 14 W,
ZL = 4 + 10 H
−84 −%
POUT = = 10 W,
ZL = 8 + 10 H
−90 −
PSRR PVDD Power Supply
Rejection Ratio
PVDD = 5.5 V to 14V , Digitally Silent Input −74 −dB
fRIPPLE = 217 Hz, Square Wave on PVDD
10 s Rise/Fall Time
PVDD = 12 V w/ 200 mV Drop
Digitally Silent Input
−74 −
fRIPPLE = 10 kHz, VRIPPLE = 200 mVPP
Digitally Silent Input
−74 −
fRIPPLE = 20 kHz, VRIPPLE = 200 mVPP
Digitally Silent Input
−70 −
KCP Click−And−Pop Level
(Note 10)
Digitally Silent Input
Peak Output Voltage
A−weighted, TA = 25°C
ZL = 4 + 10 H
Into Shutdown −±0.5 −mV
Out of Shutdown −±0.5 −
VOS Differential Output Offset
Voltage
TA = 25°C, Digitally Silent Input
ZL =4 + 10 H
−±0.5 ±1.5 mV
eNOutput Noise Digitally Silent Input,
16 dB Gain
ZL = 4 + 10 H
A−weighted −42 − VRMS
Un−weighted −57 −
DR Dynamic Range 16 dB Gain, −60 dBFS Input
ZL = 4 + 10 H, A−weighted
Relative to 1% THD+N Driver Path Output Power
−105 −dB
THD+N Total Harmonic Distortion
Plus Noise
f = 1 kHz POUT = 4 W,
ZL = 8 + 10 H
−0.012 −%
POUT = 8 W,
ZL = 4 + 10 H
−0.015 −
f = Up to 8 kHz POUT = 4 W,
ZL = 8 + 10 H
−0.080 −
POUT = 8 W,
ZL = 4 + 10 H
−0.090 −
ONA10IV
www.onsemi.com
7
ELECTRICAL CHARACTERISTICS (PVDD = 12 V, DVDD = 1.8 V, fS= FRCK = 48 kHz, 24−bit digital audio data, ZL=∞,T
A=25°C,
SD_N = H, Default I2C registers, and audio measurement bandwidth = 20 Hz to 20 kHz (AES17) unless otherwise noted) (continued)
Symbol UnitMaxTypMinConditionsParameter
SPEAKER DRIVER PATH
AVAmplifier Gain Selected through AGC response or I2C
programming.
ZL = 8 + 10 H or ZL = 4 + 10 H
15.4 16.0 16.6 dB
11.4 12.0 12.6
8.3 9.0 9.6
5.2 6.0 6.7
2.1 3.0 3.9
DACMAP Typical DAC Mapping 0 dBFS PCM Input −4.22 −dBV
0 dBFS PDM Input
85.35% Ones Density Maximum
−9.68 −0.13 7.23
DAC Digital Filter Characteristics (fs = 16, 22.05, 44.1, or 48kHz) (Note 5)
fPB Passband −0.1 dB Cutoff −0.43* fs−Hz
−3 dB Cutoff −0.504* fs−Hz
−6 dB Cutoff −0.524* fs−Hz
PPassband Ripple −0.052 −dB
fSB Stopband −0.62* fs−Hz
SStopband Attenuation f > fSB −58 −dB
tgGroup Delay −8.25 −S
DAC Digital Filter Characteristics (fs = 32 or 96 kHz) (Note 5)
fPB Passband −0.1 dB Cutoff −0.43* fs−Hz
−3 dB Cutoff −0.485* fs−Hz
−6 dB Cutoff −0.494* fs−Hz
PPassband Ripple −0.054 −dB
fSB Stopband −0.54* fs−Hz
SStopband Attenuation f > fSB −58 −dB
tgGroup Delay −8.25 −S
Driver References (Note 5)
fSW(AMP) Class−D Switching
Frequency
MCK = 12.2880 MHz −646.7 −kHz
MCK = 11.2986 MHz −519.2 −
DDigital Volume Control
(Note 4)
Programmable in 0.375 dB steps from MUTE to
0dB
−95.25 −0 dB
SPEAKER SENSE PATH
GERRVI Gain Error Variation, Voltage
Over Current (Note 10)
TA = 0°C to 60°C, −40 dBFS Input at 40 Hz −±0.50 −%
Current Sense
IIN Current Sense Range − − 3.50 AP
BWIConverter Bandwidth HPF Enabled 0.014 −20 kHz
DRIDynamic Range −60 dBFS Input
16 dB Gain, A−weighted
Relative to 1% THD+N Driver Path Output Power
−71 −dB
Voltage Sense
VIN Voltage Sense Range − − 14 VP
BWVConverter Bandwidth HPF Enabled 0.014 −20 kHz
ONA10IV
www.onsemi.com
8
ELECTRICAL CHARACTERISTICS (PVDD = 12 V, DVDD = 1.8 V, fS= FRCK = 48 kHz, 24−bit digital audio data, ZL=∞,T
A=25°C,
SD_N = H, Default I2C registers, and audio measurement bandwidth = 20 Hz to 20 kHz (AES17) unless otherwise noted) (continued)
Symbol UnitMaxTypMinConditionsParameter
SPEAKER SENSE PATH
Voltage Sense
DRVDynamic Range −60 dBFS Input
16 dB Gain, A−weighted
Relative to 1% THD+N Driver Path Output Power
−81 −dB
POWER SUPPLY
VREG Regulator Voltage IREG = 100 A, Standby Bit Set −5.00 −V
IPVDD Supply Current, PVDD Digital Silence PVDD = 14 V −13.8 −mA
PVDD = 12 V −13.5 −
PVDD = 10.8 V −13.2 −mA
PVDD = 7.2 V −12.6 −mA
IDVDD Supply Current, DVDD Digital Silence −1.5 2.0 mA
ISB_PVDD Standby Current, PVDD STBY bit set in I2C
register or CKI static
(Note 6)
PVDD = 12 V −2.9 −mA
PVDD = 7.2 V −2.9 −
ISB_DVDD Standby Current, DVDD STBY bit set in I2C register or CKI static (Note 6) −0.3 −mA
IDRV_PVDD Driver Path Only Supply
Current, PVDD
Digital Silence, IVSNS_PD bit active. −9.9 −mA
IDRV_DVDD Driver Path Only Supply
Current, DVDD
Digital Silence, IVSNS_PD bit active. −1.0 −mA
ISD Shutdown Current SD_N = L PVDD = 12 V −2.0 −A
DVDD = 1.8 V −0.3 2.0
ENVIRONMENT SENSE & PROTECTION CHARACTERISTICS
Chip Protection Thresholds
VLMT Under−Voltage Limit, PVDD Threshold 2.5 −4.5 V
Hysteresis −0.2 −
Under−Voltage Limit, DVDD Threshold 0.5 −1.5
Hysteresis −0.5 −
ILMT Output Current Limit Shutdown Threshold 3.6 5.0 −A
TLMT Thermal Limit Shutdown Threshold −145 −°C
Recovery Threshold −115 −
Automatic Gain Control (AGC) for Brownout Protection
VATH Attack Threshold Range Programmable through I2C2S Battery
Configuration
(48 mV Steps)
6.511 −7.999 V
3S Battery
Configuration
(72 mV Steps)
9.763 −11.995
ACCPAbsolute Accuracy 2S Battery Configuration −±70 −mV
3S Battery Configuration −±104 −
tAAttack Time
(Gain Decrease)
Programmable through I2C in 35 s steps 5−530 s/dB
tHHold Time Programmable through I2C in 35 ms steps 10 −Infinite ms
tRRelease Time
(Gain Increase)
Programmable through I2C in 70 ms steps 5−1055 ms/dB
ONA10IV
www.onsemi.com
9
ELECTRICAL CHARACTERISTICS (PVDD = 12 V, DVDD = 1.8 V, fS= FRCK = 48 kHz, 24−bit digital audio data, ZL=∞,T
A=25°C,
SD_N = H, Default I2C registers, and audio measurement bandwidth = 20 Hz to 20 kHz (AES17) unless otherwise noted) (continued)
Symbol UnitMaxTypMinConditionsParameter
ENVIRONMENT SENSE & PROTECTION CHARACTERISTICS
Automatic Gain Control (AGC) for Brownout Protection
tLAGC Attenuation Latency Attack Time set to 5 s. Measured from PVDD to
initial response on OUT±
− − 10 s
AGC Maximum AGC Attenuation Gain setting is 16 dB or 12 dB (Note 7) −2− −9 dB
AGC AGC Attenuation Step Size −0.5 −dB
tD2D MAGC Device−to−Device
Latency
−1−Sample
AD2D MAGC Device−to−Device
Gain Delta
−0.5 −dB
Die Temperature Sense
BWTConverter Bandwidth −500 −Sps
TIN Temperature Sense Range −40 −150 °C
DIGITAL INTERFACE (Includes SCL, SDA, CKI, FRCK, MCK, SD_N, MAGC, ADDR, DATAI, DATAO, and INT_N)
I/O Characteristics
VIH Input High Voltage 0.7 x
DVDD
−DVDD V
VIL Input Low Voltage −0.5 −0.3 x
DVDD
V
VHYST Input Hysteresis SCL, SDA, and ADDR −0.20 −V
All other inputs (Note 8) −0.40 −
IIH Input High Leakage Input Voltage = VIH to DVDD −1−1A
IIL Input Low Leakage Input Voltage = VIL to DGND −1−1A
IOFF Off Leakage DVDD = 0 V Any I/O from 0 V to
2.2 V
−10 −10 A
SCL, SDA, and AD-
DR from 0 V to 5.5 V
−10 −10 A
IOZ Disable Leakage DATAO & MAGC Pins, Across all DVDD
VIN on pin from 0 V to 2.2 V.
−5−5A
CIN Input Capacitance 5−pF
VOH Output High Voltage All Outputs; IOH = 4 mA 1.2 − − V
For MAGC/DATAO, 50% Drive; IOH = 2 mA 1.2 − −
VOL Output Low Voltage For MAGC/DATAO IOL = 4 mA 0−0.2 x
DVDD
V
50% Drive;
IOL = 2 mA
0−0.2 x
DVDD
For SDA, SCL, & INT_N; IOL= 3 mA 0−0.4
IOL Output Low Current For SDA, SCL, & INT_N; VOL = 0.4 V 3− − mA
Shutdown and Standby Timing
tWU Wake−Up Time SD_N = L → H to I2C Communication 10 − − s
Shutdown condition removed (OUT+/− active)
through I2C. MCK is present
− − 17.0 ms
Standby condition removed (OUT+/− active)
through I2C.
− − 11.0 ms
ONA10IV
www.onsemi.com
10
ELECTRICAL CHARACTERISTICS (PVDD = 12 V, DVDD = 1.8 V, fS= FRCK = 48 kHz, 24−bit digital audio data, ZL=∞,T
A=25°C,
SD_N = H, Default I2C registers, and audio measurement bandwidth = 20 Hz to 20 kHz (AES17) unless otherwise noted) (continued)
Symbol UnitMaxTypMinConditionsParameter
DIGITAL INTERFACE (Includes SCL, SDA, CKI, FRCK, MCK, SD_N, MAGC, ADDR, DATAI, DATAO, and INT_N)
Shutdown and Standby Timing
tSD Shutdown/Standby Time Time required after volume ramp down. MCK must
be present during this period.
5.0 5.1 −ms
Global Timing Requirements (Regardless of Mode or Interface)
fFRCK FRCK Input Frequency
Range
16 −96 kHz
fMCK MCK Input Frequency
Range
fS = 16, 24, 32, 48, or 96 kHz −12.2880 −MHz
fS = 44.1 kHz −11.2896 −
tjit, MCK MCK Jitter Allowable RMS jitter with minimal performance
degradation.
− − 0.1 ns
tSETUP FRCK or DATAI to CKI
Setup Time
10 − − ns
tHOLD FRCK or DATAI to CKI Hold
Time
0− − ns
PCM Mode − I2S
fCKI CKI Frequency Range CKI must be 32, 48, and 64x of FRCK. 0.512 −6.144 MHz
PCM Mode – TDM (Used for DATAI & DATAO)
Number of Slots Supported 2−8 Slots
fCKI CKI Frequency Range 0.512 −12.288 MHz
PDM Mode (Used for DATAI & DATAO)
fCKI Clock Frequency −3.072 −MHz
tPDM_SETUP DATAI to CKI Setup Time 10 − − ns
tPDM_HOLD DATAI to CKI Hold Time 0− − ns
tPDM_VALID Time from CKI Transition to
DATAO Remaining Valid
CLOAD = 15 pF −17 −ns
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. This value is programmable through I2C.
5. These specs are intended as reference and are guaranteed by design.
6. CKI is static based upon it not meeting the criteria as outlined in the Clock Requirements section.
7. Absolute minimum gain setting is 3 dB.
8. Does not include MCK
9. In the recommended implementation, VDDEXT is DVDD.
10.Validated by characterization.
CKI
3.072 MHz
DATAO I or V V or I I or V V or I
tPDM_VALID
DATAI AUDIO AUDIO
tPDM_HOLD tPDM_SETUP
tPDM_VALID
Figure 5. PDM Timing Parameters
ONA10IV
www.onsemi.com
11
FAST MODE I2C SPECIFICATION
Symbol Parameter
Fast Mode
Min Max Unit
fSCL SCL Clock Frequency 0 1000 kHz
tHD;STA Hold Time (Repeated) START Condition 0.26 −s
tLOW Low Period of SCL Clock 0.5 −s
tHIGH High Period of SCL Clock 0.26 −s
tSU;STA Set−up Time for Repeated START Condition 0.26 −s
tHD;DAT Data Hold Time 0−s
tSU;DAT Data Set−up Time 50 −s
trRise Time of SDA and SCL Signals −120 ns
tfFall Time of SDA and SCL Signals 20* (VDDEXT /
5.5 V) (Note 11)
120 ns
tSU;STO Set−up Time for STOP Condition 0.26 −s
tBUF Bus−Free Time between STOP and START Conditions 0.5 −s
tSP Pulse Width of Spikes that Must Be Suppressed by the Input Filter 0 50 ns
CbCapacitive Load for each Bus Line −550 pF
tVD−DAT Data Valid Time for Data from SCL LOW to SDA HIGH or LOW Output 0 0.45 s
tVD−ACK Data Valid Time for acknowledge from SCL LOW to SDA HIGH or LOW Output 0 0.45 s
VnL Noise Margin at the LOW Level 0.1* VDDEXT
(Note 11)
−V
VnH Noise Margin at the HIGH Level 0.2* VDDEXT
(Note 11)
−V
11. In the recommended implementation, VDDEXT is DVDD.
12.Validated by characterization.
Figure 6. Definition of Timing for Full−Speed Mode Devices on the I2C Bus
ONA10IV
www.onsemi.com
12
Table 1. I2C SLAVE ADDRESS
Name Size (Bits) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Slave Address 8See Table 5 in I2C Slave Address Selection R/W
TYPICAL PERFORMANCE CHARACTERISTICS
(Unless otherwise noted: ZL = 8 + 10 H, f = 1 kHz, Audio measurement bandwidth 20 Hz to 20 KHz (AES17), PVDD = 12 V, TA = 25°C,
Typical external component values)
Figure 7. THD+N vs. Output Power Figure 8. THD+N vs. Output Power
Figure 9. THD+N vs. Frequency Figure 10. THD+N vs. Frequency
Figure 11. Efficiency vs. Output Power Figure 12. Efficiency vs Output Power
ONA10IV
www.onsemi.com
13
TYPICAL PERFORMANCE CHARACTERISTICS
(Unless otherwise noted: ZL = 8 + 10 H, f = 1 kHz, Audio measurement bandwidth 20 Hz to 20 KHz (AES17), PVDD = 12 V, TA = 25°C,
Typical external component values) (continued)
Figure 13. PVDD Idle Current vs. PVDD Figure 14. DVDD Idle Current vs. DVDD
Figure 15. Idle Channel Noise (A−Weighed) vs. PVDD Figure 16. Vsense Gain Deviation vs. Temperature
Figure 17. Isense Gain Deviation vs. Temperature
ONA10IV
www.onsemi.com
14
THEORY OF OPERATION
The ONA10IV is an audio endpoint, meaning that it
includes the converters and amplifiers that translate the
digital audio input into an analog audio output across the
speaker and then senses that analog signal, amplifies,
converts it to digital, and communicates what it senses to the
host. This driver/sensor loop allows the host to optimize the
audio speaker system.
While the theory of operation does not vary, there are
multiple interface formats and device configurations that the
ONA10IV can support. The remainder of this section
describes the operating requirements and configurations.
The list below summarizes the interface options available to
the host:
Pulse Code Modulated (PCM)
•Formats: I2S, Left−Justified, and TDM
•Sampling (fFRCK): 16 kHz to 96 kHz
•Slot Width: 16−, 24, or 32 bits
•fCKI: 512 kHz to 6.144 (I2S)/12.288 MHz (TDM)
•fMCK: 12.288 MHz or 11.2896 MHz (can be phase
asynchronous to CKI/FRCK)
•TDM configuration can be adjusted so long as:
♦fCKI = # of slots * slot width * sampling frequency
•The digital formats are all clocked using MCK, CKI and
FRCK. The digital input clocking is also applicable to the
following interfaces:
♦Digital Audio Input (DATAI Pin)
♦Digital Sense Output (DATAO Pin)
♦MAGC Bidirectional Bus (MAGC Pin)
Pulse Density Modulated (PDM)
•fCKI: 3.072 MHz
•fMCK: 12.288 MHz
•This modulation scheme is simpler and only clocked with
CKI. The MAGC signal does not support PDM output
and, if the MAGC feature is utilized, a FRCK is still
required.
Power Supplies
The ONA10IV uses two power supplies, DVDD (1.8 V
regulated supply) and PVDD, (can be a regulated supply
between 5.5 V to 14 V or a stacked cell battery (2S, 5.5 V to
9 V or 3S, 7.5 V to 13.5 V)) and generates a third, VREG (5 V
internally regulated supply).
DVDD [1.62 V to 1.98 V]
DVDD is intended to match the I/O supply of the host such
that no translators are required in the board design. It
provides power to the digital interface and device controls.
If DVDD is 0 V, the chip cannot be communicated with, the
I2C registers are in reset, the PVDD supply current is below
ISD (max.), and the I/O leakage current is less than
IOFF_DVDD (max.).
PVDD [5.50 V to 14.00 V]
PVDD provides a high voltage rail that supplies the
H−Bridge of the amplifier to drive the speaker. It is also used
to generate the VREG supply.
If PVDD is below VLIM (shutdown) and not in shutdown,
the chip enables only circuitry associated with detecting
PVDD. DVDD supply current is IDVDD (typ.), and the
speaker interface pins (OUT+, OUT−, VSNS+, VSNS−)
each have leakage less than IOFF_PVDD (max.).
VREG [~5.00 V]
VREG is an internally generated supply that provides
power to most of the analog circuitry. It is 0 V when the part
is in shutdown (SD_N or SD_N bit low), PVDD is below
VLIM (shutdown), or DVDD is below VLIM (shutdown).
POWER/ENABLE SEQUENCING
The following power sequence is required on power−up:
1. PVDD is the first power supply applied to the device.
2. With SD_N low and PVDD above VLIM (recovery),
DVDD is applied with SCL and SDA always above
VIH.*
3. Wait until DVDD is above VLIM (recovery).
4. Remove chip from a hard shutdown by driving the
SD_N pin high.
5. I2C communication is available after 10 s.
6. Remove chip from a soft shutdown by writing a 1 to
the SD_N bit in register 0x01: PWR_CTRL.
7. With MCK applied any time prior to this point, wait
tWU before transmitting digital audio.
*In the above sequence, SD_N does not have to be an
independent signal − it can be tied to DVDD.
Power States
The ONA10IV has three power states when DVDD is
present: SHUTDOWN, STANDBY, and ACTIVE. These
are described below.
SHUTDOWN Power State
(“Hard”: SD_N < VIL or “Soft”: SD_N bit is 0)
The SHUTDOWN power state provides the lowest
possible supply current, ISD. In shutdown, all non−I2C
digital I/Os and the speaker interface pins are all below their
IOZ (max) specifications. SHUTDOWN can be accessed
through a “soft” shutdown (SD_N bit is 0) or a “hard”
shutdown (SD_N < VIL).
In “Hard” shutdown, the I2C registers are reset and I2C is
not operational. The minimum time for SD_N to be low is
indicated by “Soft” shutdown will not reset the registers and
allow I2C communication, but will have slightly higher
leakage current on DVDD (adds 5 − 10 A at higher
temperatures).
ONA10IV
www.onsemi.com
15
STANDBY Power State
A STANDBY power state can be entered through I2C
(from the PWR_CTRL register), if CKI is not toggling, or
after a timeout period from an AGC or error state. If
STANDBY is entered into from a timeout period, the part
can recover by entering RESET or exiting the automatic
mode that triggered the timeout period (i.e. – disable
AGC_TIMEOUT or ARCV setting). This mode is not as
low−power as shutdown, but disables the DAC, mutes the
amplifier, and disables all sense circuitry.
Table 2. POWER STATE CONDITIONS AND AVAILABLE OPERATIONS
Power State Error State Condition to Enter State Available Operation
RESET N/A DVDD < VLIM None
SD_N Input < VIL
Writing 1 to RST bit
SHUTDOWN N/A SD_N Input < VIL I2C Communication when
SD_N Input > VIH
SD_N bit is 0
Under−Voltage (VERR) PVDD < VLIM
(Note, IPVDD > ISD)
STANDBY N/A STBY bit is 1 I2C Communication Only
Exceeding ARVC attempts or
AGC_TIMEOUT Time
ACTIVE None N/A All
AGC Active PVDD < BATT_ATH Register
Setting
Speaker Drive Gain Limited by
AGC_MAX_ATT
Thermal Foldback Active TJ ≥ T_ATH Register Setting Maximum Volume Limited
Over−Temperature Error (TERR) TJ ≥ TLIM I2C Communication Only
Over−Current Error (IERR) IOUT± > ILIM I2C Communication Only
The following sections describe operation in the
“ACTIVE Power State”…
DIGITAL AUDIO INPUT
The digital audio input can be configured for a single−bit
Pulse Density Modulation (PDM) stream or in a Pulse Code
Modulation (PCM) format such as: I2S, Left Justified (LJ),
or Time Divided Multiplexing (TDM). Examples of these
digital audio formats are shown in the diagrams in Figure 18
(I2S) and Figure 19 (TDM).
CKI
FRCK
I2S – Standard
(Default)
32/24/16 CKIs (SLOTW)
16/24/32 CKIs (SAMPW)
Left−Justified
(FRM_DLY = 00b)
Slot 1 Slot 2 Slot N (up to 8)
Slot 1 Slot 2 Slot N (up to 8)
TDM DATAI
16/24/32 CKIs (SAMPW)
32/24/16 CKIs (SLOTW)
One Frame
Any number of CKIs
CKI
FRCK
I2S – Standard
(Default)
16/24/32 CKIs (SAMPW)
Left−Justified
(FRM_DLY = 00b,
FRCK_MODE = 1)
16/24/32 CKIs (SLOTW)
Slot 1: Left Channel
Slot 2: Right Channel
Slot 2: Right Channel
Slot 1: Left Channel
I2SDATAI
Figure 18. I2S Digital Audio Input (I2S and LJ Formats Shown)
Figure 19. TDM Digital Audio Input (I2S and LJ Formats Shown)
ONA10IV
www.onsemi.com
16
PDM Digital Audio Operation
In PDM mode, audio data on the DATAI pin is clocked in
by CKI. Pulse Density Modulation (PDM) is a common
output of ADCs and, in essence, is the audio signal
oversampled by fCKI. An example of this format is shown
below:
CKI
3.072 MHz
DATAI
3.072 MHz 0
Sine Wave
Equivalent
110000
1
−1
PDM
Figure 20. PDM Digital Audio Input
The PDM data that is received on DATAI is mapped into
the DAC. This mapping is configurable via I2C in the
register under PDM_DAC_MAP. Additionally, a separate
amplifier gain for PDM mode can be set in the same register
under PDM_AMP_GAIN. When switching into PDM mode
this value will be used rather than the PCM_AMP_GAIN
setting. A time of tSW_MOD, is required to switch between
the PCM and PDM interfaces. It is expected that the host will
manage any sequencing required between digital audio
formats to avoid undesirable audible effects.
PCM Digital Audio Operation
Audio data on the DATAI pin is clocked in by CKI with
the most significant bit appearing first. Audio samples are
two’s complement Pulse Code Modulation (PCM) and are
16 bits, 24 bits, or 32 bits in width as defined by the SAMPW
register bits. SLOTW defines the number of CKI periods
between each sample. For example, sample width may be 24
bits (SAMPW = 01b), while slot width may be 32 bits
(SLOTW = 10b). After every 24 bit sample, there are an
additional 8 bits (that are ignored by the DAC) before the
next sample begins. Sample length must be equal to or less
than slot width.
Sample rate, fs, is equal to the FRCK frequency. In
addition, one data “frame” is equal to one FRCK period.
PCM audio data is internally buffered and fed to the DAC
at the end of the audio frame. This is done to keep separate
amplifiers in phase with each other in multi−slot systems.
The slot that the ONA10IV responds to can be selected using
the A_SLOT setting in the register.
I2S Digital Audio Interface
For I2S or left justified data (DAI = 00b), each frame
contains 2 separate slots of audio – left channel and right
channel. In each frame, the left channel is always
transmitted first, and the right channel is always second.
FRCK’s duty cycle is always 50%.
Figure 18 shows the I2S digital audio interface with two
different formats on DATAI: I2S (traditional) and
left−justified. For “left justified”, FRCK is high during left
channel audio data and low during right slot audio data
(FRCK_MODE = 1). Audio samples are left justified so that
the first data bit appears at the first CKI period after a FRCK
edge (FRM_DLY = 00b). Data is valid on the rising edges
of CKI (BEDGE_DAI = 1). If the audio sample width is 24
bits (SAMPW = 01b), but the data slot width is 32 bits
(SLOTW = 10b) the 8 bits after the audio sample are ignored
and one FRCK period is 64 CKI periods. The chip will
respond to left or right channel audio data based on the
A_SLOT setting in the register.
For “I2S” formatted I2S digital audio, it is similar to left
justified except that the frame is delayed by one CKI
(FRM_DLY = 01) and FRCK is low for left slot audio data
and high for right slot audio data (FRM_POL = 0). Note that
the frame still begins with left channel audio data. If the
frame were to begin with right channel audio data, left and
right audio would be out of phase with each other by 1/2 fS.
In this example, audio sample width is 16 bits wide
(SAMPW = 00b) but the slot width is still 32 bits
(SLOTW = 10b) and FRCK period is still 64 CKI periods.
Only right channel audio data is used (A_SLOT = 0000b).
TDM Digital Audio Interface
One TDM “frame” can contain 2, 4, or 8 separate slots of
audio. In each frame, slot 1 is transmitted first; slot 2 is
transmitted second, and so on. FRCK signals the beginning
of a frame with a single pulse that is 1 CKI period wide. This
can also be changed in I2C through the FRCK_MODE
settings.
PCM audio data is internally buffered and fed to the DAC
at the end of the audio frame. This is done to keep separate
amplifiers in phase with each other in multi−slot systems.
The data slot that the ONA10IV receives can be selected
using the A_SLOT register.
Clock Requirements
The ONA10IV requires a master clock that is
12.288 MHz or 11.2896 MHz (depending on if the sample
rate is 44.1 kHz).
The bit (CKI) and frame (FRCK) clock need to match
what has been programmed in the FS register (0x06) such
that the following equation is valid:
fS+fFRCK +
fCKI
NChannels @SlotWidth (eq. 1)
In addition, FRCK frequency must always be within
recommended operating conditions. If FRCK fails to meet
these criteria, a clock error is detected (CERR) and the
class−D amplifier will shutdown (see Interrupts & Fault
Recovery section).
ONA10IV
www.onsemi.com
17
Volume Control
Volume can be ramped anytime the driving path is enabled
or the volume setting changed. This minimizes pop if audio
data is nonzero. If AVOLUP is set to 1 and the driving path
is enabled, then the volume is ramped from mute up to
MAX_VOL in VOL_RAMP. If the thermal fold back limit
is reached before the volume reaches the MAX_VOL
setting, the startup ramp releases control of MAX_VOL. If
AVOLUP = 0, the volume is immediately set to MAX_VOL
upon enable.
If AVOLDN is set to 1 and the driving path is disabled, the
volume is ramped from its present value down to mute in
VOL_RAMP. During the ramp, the detection of a thermal
error is allowed to accelerate the downward ramp, but it is
not allowed to increase the volume. If AVOLDN = 0, volume
is immediately set to mute upon disable.
Further, if the maximum volume setting is changed, then
the volume will also be ramped up or down as necessary.
Shutdown conditions caused by PVDD < VLIM or
class−D amplifier over−current are immediate and
unaffected by the VOL_RAMP setting.
Interrupts & Fault Recovery
The ONA10IV contains multiple fault flags that will drive
the INT_N pin low when the status of the flag changes to
alert the host and prevent a system failure. The flags are
contained in the register and can be cleared by writing a “1”
in the flagged bit. The following faults are detected and
flagged:
•Under−Voltage Limit (VERR_I)
•Over Output current Limit (IERR_I)
•Over−Temperature Limit (TERR_I)
•Absent or Insufficient Clocks (CERR_I)
Additionally, there are interrupts to communicate that
Automatic gain correction (AGC_I) or thermal
foldback(TFB_I) is active.
Where the interrupt flag is sent to indicate a change in an
error state, the error status register always shows the active
status of the error.
If PVDD falls below VLIM (shutdown), the device goes
into an under−voltage error state that is similar to shutdown.
The device remains off until PVDD rises above VLIM
(recovery). I2C registers are reset to default values.
If the output current of the class−D amplifier exceeds ILIM
(shutdown), OUT+ and OUT− are high impedance and the
IERR bit is set to 1. The I2C port remains active and I2C
register values are preserved. If ARCV = 1, the class−D
amplifier attempts to restart every 1 s until the fault
condition is removed. If ARCV = 0, the class−D amplifier
remains off until SD_N or MRCV are toggled to
successfully restart the amplifier without an over−current
event.
If the junction temperature meets or exceeds TLIM
(shutdown), OUT+ and OUT− are disabled, and the TERR
bit is set to 1. The I2C port remains active and I2C register
values are preserved. If ARCV = 1, the class−D amplifier
will restart after the die temperature meets or falls below
TLIM (recovery). If the MAX_ARCV is limited, then every
1 s period is counted as a recovery attempt. If ARCV = 0, the
class−D amplifier remains off and the TERR status bit is set
to 1 until SD_N or MRCV are toggled to successfully restart
the amplifier without an over−temperature event. See the
“Thermal Foldback” section for more detail.
If a clock error is detected (see the Clock Requirements
section), OUT+ and OUT− are high impedance, and the
CERR bit is set to 1. The I2C port remains active and I2C
register values are preserved. If ARCV = 1, the class−D
amplifier will turn on when all clocks are valid. If
ARCV = 0, the class−D amplifier will remain off until
SD_N or MRCV are toggled to successfully restart the
amplifier without a clock error event.
During a CERR, the DATAO and MAGC buses will
maintain their last driving state.
Low EMI
The class−D amplifier’s low EMI design allows the
OUT+ and OUT− pins to be connected directly to a speaker
without an output filter.
Edge Rate Control minimizes EMI generated by the
high−current switching waveform of the Class−D amplifier
output. One of the main contributors to EMI generated by
Class−D amplifiers is the high−frequency energy produced
by rapid (large dV/dt) transitions at the edges of the
switching waveform. ERC suppresses the high−frequency
component of the switching waveform by extending the rise
and fall times of the output FET transitions at all power
levels. Rise and fall rates are set to a default of 3.5 V/ns and
can be reprogrammed through I2C.
Spread spectrum switching can also be adjusted through
I2C.
ONA10IV
www.onsemi.com
18
Thermal Foldback
Compared to thermal protection (Figure 22; described in
Interrupts & Fault Recovery), the thermal foldback feature
(Figure 21) is a pre−emptive attempt to avoid the
over−temperature fault (TERR). The following describes
the sequence that it conducts to limit the volume. All
configurations are set in the 0x15: SENSE_CNTRL register.
1. Unless thermal foldback is disabled (TFB_PD = 1),
at any time the die temperature reaches the attack
threshold (set in register bits, T_ATH) the thermal
foldback sequence initiates. The thermal foldback
attacks at a rate of T_ATTACK to a target output
attenuation of −12 dB from the current MAX_VOL
setting and is applied to all signal amplitudes. The
reduction in gain does not track with temperature,
but reduces gain until the temperature has reached a
recovery threshold that is 10°C below the attach
threshold (T_ATH) or has reached the maximum
attenuation.
2. While in foldback, any time the die temperature has
gone below the recovery threshold then the chip
waits a hold time (T_HOLD) until it begins ramping
the volume (using the settings in volume control
register, VOL_CTRL).
3. If the ONA10IV remains in foldback at maximum
attenuation (−12 dB from MAX_VOL) without
reaching the recovery threshold for an extended
period of time, the TFB_PD bit can be set to 1 to
remove the foldback and rely on thermal protection
only.
4. When the die temperature is below the temperature
attack threshold, the thermal foldback feature has no
effect on the signal path.
Time
Digital Volume
Die Temperature
Attack Time / Step
(T_ATTACK)
Release Time / Step
(set by AGC_RELEASE)
Hold Time
(T_HOLD)
Maximum Allowable Attenuation
(−12 dB from current MAX_VOL)
Temperature Threshold
(T_ATH)
The recovery threshold
Time
Power State
Die Temperature
Temperature Protection
Threshold
(1455C)
ACTIVEACTIVE Disable Amplifier and check for recovery
(When MAX_ARCV limit is set, 1 recovery period is 1 sec)
Temperature Recovery
Threshold
(1155C)
is always 105C lower than T_ATH
105C
Figure 21. Thermal Foldback: Die Temperature Changes vs. Time
Figure 22. Thermal Protection: Die Temperature Changes vs. Time
ONA10IV
www.onsemi.com
19
Automatic Gain Control (AGC) for Brownout Protection
The AGC eases low−PVDD current demands by reducing
the maximum volume when PVDD voltage drops below an
“attack” threshold. The AGC attack threshold can be set by
the AGC_CTRL register. The following is an example AGC
sequence that would automatically control the system gain
1. At any time the battery (PVDD) crosses below the
attack threshold (BATT_ATH), the AGC sequence
initiates. The AGC attacks (AGC_ATTACK) to the
target output attenuation (AGC_MAX_ATT) that is
applied to all signal amplitudes. The latency from
PVDD dropping below BATT_ATH to the output
changing is 10 s (maximum). The reduction in gain
does not track the battery, but attacks until PVDD has
gone above the attack threshold (BATT_ATH).
The timing values are set in and registers.
2. At any time the battery has gone above the attack
threshold (BATT_ATH), the chip waits a hold time
(AGC_HOLD) until it begins its release timing
(AGC_RELEASE) from the automatic gain control.
3. If the ONA10IV remains at AGC_MAX_ATT for a
programmable timeout period, AGC_TIMEOUT,
then the device will go into standby. The AGC error
status will be maintained. To exit, the part can be
reset (through a hard or soft shutdown) or the
AGC_TIMEOUT can be disabled to begin searching
for a recovery of PVDD.
4. When PVDD is above the AGC attack threshold, the
AGC has no effect on the signal path.
Time
System Gain
PV
DD
Attack Time / dB Step
(AGC_ATTACK)
Release Time / dB Step
(AGC_RELEASE)
Hold Time
(AGC_HOLD)
10 ms Fast Latency
to output original
Maximum Allowable
Attenuation
(AGC_MAX_ATT)
Figure 23. AGC Changes vs. Time
Multi−amplifier Automatic Gain Control (MAGC) Bus
In order to maintain a balanced multi−speaker /
multi−amplifier system, it is necessary to have a means of
synchronizing and matching the gain of each instantiation of
ONA10IV (up to 8) quickly (within tD2D; typically one
sample), accurately (within AD2D; typically 0.5 dB), and
despite its current environment.
To do this, each ONA10IV is programmed through I2C to
transmit on a particular slot (up to 8) on the MAGC bus.
Additionally, it can be programmed to listen to as many of
the other slots as desired. When the chip detects an AGC
event, it transmits the current gain setting within its slot onto
the MAGC bus and then releases the bus into high
impedance immediately after transmission (as shown in
Figure 24). All other ONA10IVs synchronize their amplifier
gain to the lowest setting on the MAGC bus (whether
transmitted (measured on−chip) or received). The MAGC
setting does not affect the active operation of AGC, only the
amplifier gain setting.
If any ONA10IV on the host exceeds the
AGC_TIMEOUT period and goes into STANDBY, it sends
a 0x1F code to other instantiations to go into STANDBY.
Entering STANDBY through a MAGC command will not
set an interrupt flag. Only the instance of ONA10IV that
flagged the AGC, we have set an interrupt flag.
If MAGC is enabled (via MAGC_EN register bit) and
AGC is disabled (AGC_PD), the ONA10IV will still react
to what it receives on the MAGC bus.
If a more rapid response is required, then the gain data can
be sent out on multiple slots for systems with 4 or less
instantiations of the ONA10IV.
ONA10IV
www.onsemi.com
20
CKI
FRCK 32/24/16 CKIs (SLOTW)
MAGC HiZ
Gain Data
5 CKIs
16 to 32 CKIs (SAMPW) 16 CKIs
Slot 1: HiZ
16 to 32 CKIs (SLOTW)
Slot 3 Slot N
Slot 2: I2C Selected Tx Slot
Figure 24. MAGC Gain Transmission
Speaker Sense
The ONA10IV includes two analog−to−digital converters
that aid in allowing the host to drive the speakers at the
maximum possible volume. Speaker impedances vary
considerable over frequency and knowing what the speaker
voltage and current allows the host to optimize the audio
system without damaging the speaker. Based on the I2C
settings in the register, the output can be sent out in a PDM
format or in a PCM format within a selected slot determined
by register.
For PCM, the results of these ADCs are sent out in 2 s
complement out of the DATAO output. Example timing
diagram of the PCM format is shown in the Digital Sense
Interface section. A summary of the code is found below:
Table 3. SPEAKER SENSE
MSB Speaker Sense Encoding LSB Unit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Voltage
Sense
−(24) 232221202−12−22−32−42−52−62−72−82−92−10 2−11 Volts
Current
Sense
−(22) 21202−12−22−32−42−52−62−72−82−92−10 2−11 2−12 2−13 Amps
Die Temperature Sense
While speaker protection is provided by the current and
voltage sense paths, the environmental conditions of the
chip (and system) are measured by another ADC used for
monitoring the die temperature. These values can be read
through I2C or streaming concurrently (through TDM) on
DATAO in PCM mode. A summary of the code is found
below:
Table 4. TEMPERATURE SENSE
MSB Speaker Sense Encoding LSB Unit
10 9 8 7 6 5 4 3 2 1 0
Temperature Sense −(28) 27262524232221202−12−2°C
Digital Sense Interface (DATAO)
The DATAO output is used communicate the output of the
sense ADCs to the host. It can be configured for either PDM
Mode (as shown in Figure 25) or as a TDM interface (as
shown in Figure 26) in the register. In TDM mode, the data
is sent out from MSB to LSB. In PDM mode, data can be sent
on both edges of the clock if both current and voltage sense
paths are enabled. Or, if one path is enabled, both edges will
transmit the enabled sense path data. Temperature cannot be
sent out through DATAO in PDM mode
VIVIVIVIVIVIVI
Figure 25. Digital Sense Interface with PDM
CKI
3.072 MHz
DATAO
3.072 MHz
TDM with Sense
CKI
FRCK 32/24/16 CKIs (SLOTW)
DATAO HiZ
Current Sense Data Voltage Sense Data HiZ
16 CKIs
Slot 1: Left or Right Audio
DATAI
16 to 32 CKIs (SAMPW)
16 CKIs
Slot 2 Slot 3
Slot 1: HiZ Temp Sense Data
8 CKIs
Slot 4 Right Audio
Slot 1
Slot 3
HiZ
16 to 32 CKIs (SLOTW) 16 to 32 BCKs (SLOTW)
Figure 26. Digital Sense Interface with TDM
ONA10IV
www.onsemi.com
21
I2C Interface
The ONA10IV includes a full I2C slave controller. The
I2C slave fully complies with the I2C specification version
6 requirements. This block is designed for Fast Mode traffic
with up to 1 MHz SCL operation.
SWR AA A A A
NOTE: Single Byte read is initiated by Master with P immediately following first data byte
8bits 8bits 8bits
Write Data K+2Slave Address Register Address K Write Data Write Data K+1 Write Data K+N−1
SWR A RD AA NA
Register address to Read specified
8bits
NOTE: If Register is not specified Master will begin read from current register. In this case only sequence showing in Red
bracket is needed
Read Data K+1 Read Data K+N−1
8bits 8bits 8bits
Slave Address Register Address K Read Data KSlave Address
From Master to Slave S Start Condition NA NOT Acknowledge (SDA High) RD Read = 1
From Slave to Master A Acknowledge (SDA Low) WR Write = 0 S Stop Condition
Figure 27. I2C Write Example
Figure 28. I2C Read Example
A P
ASA P
Single or multi byte read executed from current register location (Single Byte read
is initiated by Master with NA immediately following first data byte)
I2C Slave Address Selection
The ONA10IV includes a fast−mode (up to 1 MHz) I2C
slave controller with 4 slave addresses selectable through
shorting the DGND, SCL, SDA, or DVDD pins to the ADDR
pin. An additional 4 slave addresses can be attained from
swapping the SCL and SDA signals to the SCL and SDA
pins. All possible slave address configurations are shown in
Table 5. The slave address is determined using the start
condition of the first I2C transaction after a power up. It is
required that I2C traffic to the chip during power−up be held
high or at DVDD to insure that the desired slave address is
selected.
Table 5. I2C SLAVE ADDRESS SELECTION (ONA10IV)
DR Pin SCL Pin SDA Pin
I2C Slave Address (Binary)
I2C Slave
Address (Hex)
B6 B5 B4 B3 B2 B1 B0 R/W Write Read
DGND SCL Signal SDA Signal 0 1 0 0 0 1 1 R/W 46 47
SCL Pin SCL Signal SDA Signal 0 1 0 0 1 0 0 R/W 48 49
SDA Pin SCL Signal SDA Signal 0 1 0 0 1 0 1 R/W 4A 4B
DVDD SCL Signal SDA Signal 0 1 0 0 1 1 0 R/W 4C 4D
DGND SDA Signal SCL Signal 1 0 0 1 0 0 0 R/W 90 91
SCL Pin SDA Signal SCL Signal 1 0 0 1 0 0 1 R/W 92 93
SDA Pin SDA Signal SCL Signal 1 0 0 1 0 1 0 R/W 94 95
DVDD SDA Signal SCL Signal 1 0 0 1 0 1 1 R/W 96 97
Hard−wired to SCL, SDA, DV
DD , or GND
Slave Address RW ACK
Start bit used for I2C slave address selection
DV
DD
SDA
signal
SCL
signal
ADDR
No I2C traffic allowed during ramp
High or DV
DD
High or DV
DD
Figure 29. I2C Slave Address Selection on Power−up (ONA10IV)
ONA10IV
www.onsemi.com
22
PCB LAYOUT GUIDELINES &
RECOMMENDATIONS
When designing audio applications using the
ON Semiconductor ONA10IV 16 W Class−D amplifier
with digital inputs, there are PCB layout and design
guidelines that should be implemented for optimum
performance and reliability in the end application. This
section will address the following key topics:
•PCB stackup recommendations
•Grounding layout & considerations
•Key components − bill of materials
•Decoupling capacitor size and placement
•DVDD & digital signal layout
•PVDD & Class−D signal layout
•Thermal management
•Design for EMI considerations
PCB Stackup Recommendations
The ONA10IV is a versatile device that can be
incorporated into designs of various sizes, form−factors and
layouts. The following stackup recommendations are based
on the ONA10IV evaluation kit PCB. This proven design
can act as a basis for modifications to meet your specific
application requirements:
Table 6.
PCB Thickness 0.063”
PCB Material High TG FR4
Layer Count 6
Layer Stackup Top − Signal & output traces, decoupling
Layer 2 − GND
Layer 3 − Power (PVDD, DVDD)
Layer 4 Signal routing
Layer 5 − GND
Bottom − Signal & decoupling w/ GND fill
Cu Weight 1 oz.
Grounding Layout & Considerations
ONA10IV grounding layout is extremely important for
proper operation and performance. The ground layout
guidelines listed here must be followed to ensure good
performance and proper device operation.
•Figure 30 and Figure 31 illustrate a suitable ONA10IV
layout scheme for a multi−layer PCB design.
•As noted in these figures, decoupling capacitors for all
supplies and reference voltages are placed as close as
possible to the ONA10IV and on the same PCB layer
where practical.
•Top−layer ground flooding and multiple vias to inner
ground planes should be used to minimize parasitic
inductance.
•Use a minimum of 1 oz Cu, or the equivalent, for ground
planes.
•The ground reference for VREG and VREF is AGND.
Route AGND back to the system ground separately from
PGND routing. Failure to properly decouple VREG &
VREF or to isolate AGND from noise may result in
Decoupling Capacitors
•1 F (min), low−ESR capacitors are recommended for
DVDD, VREG & VREF. VREF and VREG capacitors
should be placed close to the ONA10IV and connected to
AGND through a low−impedance path.
•Due to the potential for large voltage and current
transients during operation at high output power, multiple
PVDD decoupling capacitors are recommended. These
should include a bulk, low−ESR storage capacitor with
stable capacitance at higher DC working voltages
(tantalum or electrolytic, for example) of at least 22 F, as
well as additional smaller value capacitors as needed for
high−frequency noise decoupling.
•Refer to Figure 30 and Figure 31 for examples.
NOTE: when selecting MLCC capacitors for PVDD
decoupling, make sure the capacitance rating vs.
DC offset voltage is suitable for your intended
application. Generally, capacity of MLCC
capacitors derates significantly as DC bias
increases, especially for larger capacitance values
in smaller package sizes.
DVDD & Digital Signal Layout
•Place a low−ESR 1 F decoupling capacitor as close as
possible to DVDD. Minimize trace inductance.
•Layout all digital audio interface signals using 50
characteristic trace impedance where possible.
•Use pull−up resistors on SD_N & INT_N. These are
open−drain I/Os and require an external pull−up to
DVDD. Noisy environments may require a lower value
pull−up resistor.
•Nominal I2C pull−up resistor values will be dependent
upon several factors, including the I2C frequency, output
drive current of the I2C master and the capacitive load of
the I2C bus. The
•Refer to Figure 30 and Figure 31 for examples.
PVDD & Class−D Signal Layout
•Refer to Figure 30 & Figure 31 for examples of top−layer
trace routing and layout for power, output and signal
traces.
ONA10IV
www.onsemi.com
23
Thermal Management
For applications that use the ONA10IV at high continuous
power ratings or at elevated ambient temperatures, layout
techniques must be incorporated to ensure the ONA10IV
does not exceed its designed thermal operating range in
normal operation and operates as close to nominal operating
temperature as possible for best reliability.
Often excessive heat is removed, by careful use of ground
planes on various layers.
EMI Considerations
Designing for adequate EMI (Electro−Magnetic
Interference) mitigation in Class−D audio applications is a
necessity for electronic devices. Although the ONA10IV
has I2C programmable options for assisting with EMI
mitigation in an application (edge−rate control and
spread−spectrum modulation of the Class−D output
waveform), the most effective methods for EMI
management are incorporated in the board design and
layout.
•Output trace lengths and shielding/routing
•Output ferrite beads can also be considered but they have
some audio performance trade−offs
D1 D2D3 D4 D5 B5
F1 F2 F4 F5 B1
PVDD DVDD
A1
A2
A3
A4
DATAI
MCK
CKI
MAGC
B2
C3
SCL
SDA
A5 DATAO
B3 FRCK
C2 ADDR
OUT+
OUT+
OUT−
OUT−
VSNS+
VSNS−F3
E3
B4
C4
INT_N
SD _N
VREG C1
VREF C5
C8
1 mF
R1
10 k
R2
10 k
DVDD
C9
0.1 mF
C10
1 mF
C2
1 mF
C4
0.1 mF
C3
1 mF
C5
0.1 mF
C1
22 mF C7
1 mF
C6
0.1 mF
DAI_DATAO
DAI_MCK
DAI_CKI
DAI_FRCK
R3
1 k
R4
1 k
DVDD
DVDD
INT_N
DAI_DATAI
SD _N
SCL
SDA
U1
ONA10IV
MAGC
PGND
DGND AGND
ADDR
E4
E5
E1
E2
FB1
FB2
AGND
PGND
R5
4.7 k
PVDD
DGND
DGND AGND
DGND
Figure 30. Key Signal Connection Schematic
C11
0.1 mF
PGND PGND PGND
ONA10IV
www.onsemi.com
24
Table 7. KEY COMPONENT − BILL OF MATERIALS
Ref Des Qty Description Package Manufacturer Mfg P/N
U1 1 ONA10IV Digital Input Class−D Audio Amplifier WLCSP30−330 ON Semiconductor ONA10IVUCX
C1 1 22 F capacitor, SMT, Tantalum, ±10%, 50 V 2924 AVX TAJV226K050RNJ
C2, C3, C7,
C8, C10
5Capacitor, 1 F, 0603, X7R, ±10%, 50 V 0603 Taiyo Yuden UMK107AB7105KA−T
C4, C5, C9, C11 4Capacitor, 0.1 F, 0402, X7R, ±10%, 50 V 0402 Taiyo Yuden UMK105B7104KV−FR
C6 1 Capacitor, 0.1 F, 0402, X7R, ±10%, 6.3 V 0402 Samsung CL05B104KQ5NNNC
FB1, FB2 2Ferrite bead, 90 @ 100 MHz, 5 ADC 0805 Vishay ILHB0805ER900V
R1, R2 2Resistor, 0402, 10 k, 1% 0402 Yageo AT0402FRE0710KL
R3, R4 2Resistor, 0402, 1 k, 1% 0402 Yageo AT0402BRD071KL
R5 1 Resistor, 0402, 4.7 k, 5% 0402 Yageo AC0402JR−074K7L
ONA10IV
www.onsemi.com
25
C2
C3
C4
C5
C9
C8
C6
C7
FB1
FB2
C11
C10
Output −
Output +
PGND Island
VREG
VREF
DVDD
PVDD Island
AGND
AGND
(Direct connected to B5 on another Layer) (Duplicated on Bottom Layer for C1)
(Duplicated on Bottom Layer for C1)
(Direct connected to D1 − D5 on another Layer)
Figure 31. Top Copper Placement of Key Components
ONA10IV
www.onsemi.com
26
C1
C9
C8
C6
C7
FB1
FB2
C11
C10
Output −
Output +
PGND Island
VREG
VREF
DVDD
PVDD Island
AGND
AGND
(Direct connected to B5 on another Layer) (Duplicated on Bottom Layer for C1)
(Duplicated on Bottom Layer for C1)
(Direct connected to D1 − D5 on another Layer
Located on Bottom Side of the Board
NOTE : C2 – C5 are removed for Clarity
Figure 32. Location for the C1 Bulk Capacitor (Bottom Side of the Board)
ONA10IV
www.onsemi.com
28
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
ONA10IV/D
ON Semiconductor is licensed by the Philips Corporation to carry the I2C bus protocol.
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
19521 E. 32nd Pkwy, Aurora, Colorado 80011 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
◊
