1 of 12 101100
DESCRIPTION
This application note discusses the extended features for the following Real Time Clocks (RTCs):
DS1685/87, DS1688/91, DS1689/93, DS17285/87, DS17485/87 and DS17885/87. Also included is an
initialization flow chart. All of these devices incorporate these extended features unless otherwise noted.
EXTENDED FEATURES
AUXILIARY BATTERY INPUT (VBAUX)
The auxiliary battery input, VBAUX, provides the power required to use the and the 32 kHz square wave in
the absence of system power. The timekeeping and RAM data can also be maintained by this power
source. The ABE bit, Bit 7 in control register 48h must be set to a logic 1, to enable VBAUX to power the
32 kHz square wave and kickstart input in the absence of VCC. If this input is not going to be used then
ABE must be set to a logic 0 and the VBAUX input tied to ground.
KICKSTART INPUT (KS)
The kickstart pin is intended to be used in the battery-backed mode in conjunction with the PWR signal
providing systems with power management control. A signal providing a ground closure will force the
PWR signal to transition low. The KS pin can also be used as an interrupt input while VCC is applied.
POWER–ON OUTPUT (PW
R
)
This output is open drain and requires an external pull–up resistor for proper operation. This signal is
intended to be used in conjunction with KS and the wakeup alarm for power management features.
32 KHz SQUARE WAVE OUTPUT (SQW)
The SQW output pin can provide a 32 kHz square waves for power management purposes. The
DS1685/87, DS1688/91, DS17285/87, DS17485/87, and DS17885/87 will provide the 32 kHz each time
the system power, VCC, is applied. The DS1689/93 must be programmed to output the 32 kHz after the
system power is applied.
SILICON SERIAL NUMBER
A unique 64–bit silicon serial number is located in bank 1 registers 40h – 47h. The serial number is
divided into three separate parts. The first byte, location 40h, contains a model number to identify the
device type and revision. The following is a list of the model numbers currently assigned for the devices
mentioned above:
Application Note 90
Using the Multiplex Bus RTC
Extended Features
www.dalsemi.com
APPLICATION NOTE 90
2 of 12
Model # Part #
71h DS1685/87
72h DS17285/87
73h DS1688/91
73h DS1689/93
74h DS17485/87
78h DS17885/87
The second part of the serial number is a unique 48–bit binary number located in registers 41h – 46h. The
third part of the serial number is located in register 47h and contains a CRC number used to validate the
data in registers 40h – 46h. This 8-byte serial number is read only.
CENTURY BYTE
The century byte, located in bank 1 register 48h, will update every 100 years keeping track of the century.
DATE ALARM BYTE
The date alarm byte, located in bank 1 register 49h, can be used in conjunction with the time of day alarm
providing a system with a wakeup alarm programmable to any day within a month.
CONTROL REGISTERS 4 Ah and 4 Bh
See the Register Description section.
EXTENDED RAM SOFTWARE PORT
The extended user RAM can be accessed through software via three internal registers located in bank 1
locations 50h, 51h, and 53h. Locations 50h and 51h are used for the RAM address and location 53h is
used for the data transfer. This unique feature eliminates the need for external hardware and at the same
time provides the ability to switch RAM densities without any hardware modification required. This
feature is not available on the DS1688/91 or DS1689/93.
VCC ELAPSED TIME COUNTER
A 32–bit VCC powered elapsed time counter, located in bank 1 registers 54h (LSB) through 57h (MSB),
will keep track of how long system power has been applied. This counter will update once per second as
long as VCC is within nominal limits and the oscillator and countdown chain are enabled. When VCC falls
outside of the nominal limits the counter is halted and the elapsed time is retained. This counter can be
read or written at the user’s discretion. This feature is available only on the DS1688/91 and DS1689/93.
VBAT ELAPSED TIME COUNTER
A 32–bit VBAT powered elapsed time counter, located in bank 1 registers 58h (LSB) through 5 Bh (MSB)
will keep track of how long the system has been in service. This counter will run continuously and
update once per second as long as VBAT or VBAUX is within nominal limits and the oscillator and
countdown chain are enabled. This counter can be read or written at the user’s discretion. This feature is
available only on the DS1688/91 and DS1689/93.
POWER CYCLE COUNTER
A 16–bit power cycle counter, located in bank 1 registers 5 Ch (LSB) and 5 Dh (MSB), will keep track of
the number of times a system is powered on and off. Each time system power, VCC, is applied within
nominal limits, the counter will be incremented by one. This counter can be read and written at the user’s
discretion. This feature is available only on the DS1688/91 and DS1689/93.
APPLICATION NOTE 90
3 of 12
ADDITIONAL SERIAL NUMBER
An additional 64–bit customer specific serial number or ROM is located in bank 1 registers 60h through
67h. This feature is available only on the DS1688/91 and DS1689/93.
BURST MODE
The DS17285/87, DS17485/87, and DS17885/87 are the only devices which provide the burst mode
option. The model byte uniquely identifies these devices as having burst mode.
REGISTER DESCRIPTION
LOCATION DESCRIPTION
0 Ah Control Register A
Bit 7 Update In Progress (UIP) – (read only)
0=time/date can be read
1=update in progress
Bits 6 – 4 Oscillator Control (DV2-DV0)
DV2=countdown chain
0=countdown chain enabled
1=resets countdown chain only if DV1=1
DV1=oscillator enable
0=oscillator off
1=oscillator on
DV0=bank select
0=original bank
1=extended registers
Bits 3 – 0 Rate Selection (RS3-RS0)
These bits define the square wave output frequency
and the periodic interrupt rate.
APPLICATION NOTE 90
4 of 12
LOCATION DESCRIPTION
0 Bh Control Register B
Bit 7 Halt Clock Updates (SET)
0=updates time/date once per second
1=time/date updates are inhibited
Bit 6 Periodic Interrupt Enable (PIE)
0=disabled
1=enabled
Bit 5 Alarm Interrupt Enable (AIE)
0=disabled
1=enabled
Bit 4 Update-Ended Interrupt Enable (UIE)
0=disabled
1=enabled
Bit 3 Square Wave Enable (SQWE)
0=disabled
1=enabled
Bit 2 Time and Date Data Mode (DM)
0=binary coded decimal (BDC) format
1=binary format
Bit 1 Hour Format (24/12)
0=12 hour mode
1= 24 hour mode
Bit 0 Daylight Savings Time Enable (DSE)
0=disabled
1=enabled
0 Ch Status Register C (read only)
Bit 7 Interrupt Request Flag (IRQF) – (read only)
Bit 6 Periodic Interrupt (PF) – (read only)
Bit 5 Alarm Interrupt Flag (AG) – (read only)
Bit 4 Update-Ended Interrupt Flag (UF) – (read only)
Bit 3 – 0 Reserved (read only logic 0)
APPLICATION NOTE 90
5 of 12
LOCATION DESCRIPTION
0 Dh Status Register D (read only)
Bit 7 Valid RAM and Time (VRT) – (read only)
0=battery low; CMOS RAM invalid
1=battery good; CMOS RAM valid
Bit 6 – 0 Reserved (read only logic 0)
04 Ah Extended Control Register 4A
Bit 7 Valid RAM and Time 2 (VRT2) – (read only)
0=auxiliary battery is low
1=auxiliary battery is good
Bit 6 Increment in Progress (INCR) – (read only)
0=time/date has been updated
1=time/date is incrementing and checking alarms
Bit 5 Burst Mode Enable (BME) – See Note 1
0=single-byte extended RAM reads and writes
1=auto-increments address for extended RAM reads
and writes
Bit 4 Reserved
Bit 3 Power Active Bar (PAB)
0= PWR pin is in the active low state
1= PWR pin is in the inactive high state
Bit 2 RAM Clear Flag (RF)
0=cleared state (must be written)
1=high to low transition detected on RCLR if RCE=1
Bit 1 Wakeup Alarm Flag (WF)
0=cleared state (must be written)
1=wakeup alarm condition has occurred
Bit 0 Kickstart Flag (KF)
0=cleared state (must be written)
1=high to low transition detected on KS input
APPLICATION NOTE 90
6 of 12
LOCATION DESCRIPTION
04Bh Extended Control Register 4B
Bit 7 Auxiliary Battery Enable (ABE)
0=auxiliary battery input not being used
1=auxiliary battery input used for extended features
Bit 6 Enable 32 kHz (E32K)
0=32 kHz disabled
1=32 kHz enabled to be output on the SQW pin
Bit 5 Crystal Selection (CS)
0=oscillator configured for a crystal with a load
capacitance of 6 pF
1=oscillator configured for a crystal with a load
capacitance of 12.5 pF
Bit 4 RAM Clear Enable (RCE)
0=RAM clear function is disabled
1=allows RCLR pin to clear user RAM
Bit 3 Power Active Bar Reset Select (PRS)
0= PWR pin will go High-Z when entering power fail
1= PWR pin remains active when entering power fail
Bit 2 RAM Clear Interrupt Enable (RIE)
0=disabled
1=enables RAM clear function to generate interrupts
Bit 1 Wakeup Alarm Interrupt Enable (WIE)
0=disabled
1=enables wakeup alarm to generate interrupts
Bit 0 Kickstart Interrupt Enable (KSE)
0=disabled
1=enables KS to generate interrupts
NOTES:
1. Burst Mode Enable (BME) is available only on the DS17285/87, DS17485/87, and DS17885/87
devices.
APPLICATION NOTE 90
7 of 12
INITIALIZATION PROCEDURE
APPLICATION NOTE 90
8 of 12
APPLICATION NOTE 90
9 of 12
APPLICATION NOTE 90
10 of 12
APPLICATION NOTE 90
11 of 12
APPLICATION NOTE 90
12 of 12
