© 2005 Fairchild Semiconductor Corporation DS005366 www.fairchildsemi.com
Februa ry 198 4
Revised May 2005
MM74HCT245 Octal 3-STATE Transceiver
MM74HCT245
Octal 3-STATE Transceiver
General Descript ion
The MM74HCT245 3-STATE bi-directional buffer utilizes
advanced silicon-gate CMOS technology and is intended
for two-way asynchronous communication between data
buses. It has hi gh drive current outp uts which ena ble high
speed operation even when driving large bus capaci-
tances. Thi s circuit pos sesses the l ow power consumpt ion
of CMOS circuitry, yet has speeds comparable to low
power Schottky TTL circuits.
This de vice is TTL i npu t co mpat ib le a nd can dr i ve up to 15
LS-TTL loads, and all inputs are protected from damage
due to static discharge by diodes to VCC and ground.
The MM74HCT245 has one active low enable input (G),
and a di r ectio n co ntr ol ( D IR) . W he n the DIR input i s HIGH ,
data flows from the A inputs to the B out puts. When DI R is
LOW, data flows from B to A.
MM74HCT devices ar e intended to interfa ce betwe en TTL
and NMOS components and standard CMOS devices.
These parts are also plug-in replacements for LS-TTL
devices and can be used to red uce power consump tion in
existing designs.
Features
■TTL input compatible
■3-STATE outputs for connection to system busses
■High output drive current: 6 mA (min)
■High speed: 16 ns typi cal pro pagat i on dela y
■Low power: 80
P
A (74HCT Series)
Ordering Code:
Devices also available in Tape and R eel. Specify by appending the suffix let t er “X” to the or dering code.
Connection Diagram
Pin Assignments for DIP, SOIC, SOP and TSSOP
Top View
Truth Table
H
HIGH Level
L
LOW Le vel
X
Irrelevant
Order Number Package Number Package Description
MM74HCT245WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
MM74HCT245SJ M20D 20-Lead Small Outline Package (SOP) , EIAJ TYPE II, 5.3mm Wide
MM7 4HC T 24 5M TC MTC2 0 20-Le ad T hin S hr in k Sm al l Ou t li n e Pac ka ge ( TS S OP ), J E DE C MO - 15 3 , 4.4 mm W id e
MM74HCT245N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Control Operation
Inputs
GDIR 245
L L B data to A bus
L H A data to B bus
H X isolation
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MM74HCT245
Logic Diagram
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MM74HCT245
Absolute Maximum Ratings(Note 1)
(Note 2) Recommended Operating
Conditions
Note 1: Absolute Maximum Ratings are those values beyond which dam-
age to the device may occur.
Note 2: Unl es s ot herwise s pecified all v olt ages are ref erenced t o ground.
Note 3: Power Dis sipation tem perature d erating — plastic “N” package :
12 mW/
q
C from 65
q
C to 85
q
C.
DC Electrical Characteristics
(VCC
5V
r
10%, unless otherwise specified.)
Note 4: Measured per input. All other inputs at VCC or ground.
Supply Voltage (VCC)
0.5 to
7.0V
DC Input Voltage (VIN)
1.5 to VCC
1.5V
DC Output Voltage (VOUT)
0.5 to VCC
0.5V
Clamp Diode Current (IIK, IOK)
r
20 mA
DC Output Current,
r
35 mA
DC VCC or GND Current, per pin (ICC)
r
70 mA
Storage Temperature Range (TSTG)
65
q
C to
150
q
C
Power Dissipation (PD)
(Note 3) 600 mW
S.O. Package only 500 mW
Lead Temperature (TL)
(Soldering 10 seconds) 260
q
C
Min Max Units
Supply Voltage (VCC)4.55.5V
DC Input or Output Voltage
(VIN, VOUT)0V
CC V
Operati ng Tem per ature Range (TA)
40
85
q
C
Input Rise or Fall Times
(tr, tf) 500 ns
Symbol Parameter Conditions TA
25
q
CT
A
40 to 85
q
CT
A
55 to 125
q
CUnits
Typ Guaranteed Limits
VIH Minimum HIGH Level 2.0 2.0 2.0 V
Input Voltage
VIL Maximum LOW Level 0.8 0.8 0.8 V
Input Voltage
VOH Minimum HIGH Level VIN
VIH or VIL
Output Voltage |IOUT|
20
P
AV
CC VCC
0.1 VCC
0.1 VCC
0.1 V
|IOUT|
6.0 mA, VCC
4.5V 4.2 3.98 3.84 3.7 V
|IOUT|
7.2 mA, VCC
5.5V 5.2 4.98 4.84 4.7 V
VOL Maximum LOW Level VIN
VIH or VIL
Voltage |IOUT|
20
P
A00.10.10.1V
|IOUT|
6.0 mA, VCC
4.5V 0.2 0.26 0.33 0.4 V
|IOUT|
7.2 mA, VCC
5.5V 0.2 0.26 0.33 0.4 V
IIN Maximum Input VIN
VCC or GND,
r
0.1
r
1.0
r
1.0
P
A
Current VIH or VIL, Pin 1 or 19
IOZ Maximum 3-STATE VOUT
VCC or GND
r
0.5
r
5.0
r
10
P
A
Output Leakage G
VIH
Current
ICC Maximum Quiescent VIN
VCC or GND 8 80 160
P
A
Supply Current IOUT
0
P
A
VIN
2.4V or 0.5V (Note 4) 0.6 1.0 1.3 1.5 mA
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MM74HCT245
AC Electrical Characteristics
VCC
5.0V, tr
tf
6 ns, TA
25
q
C (unless otherwise specified)
AC Electrical Characteristics
VCC
5.0V
r
10%, tr
tf
6 ns (unless otherwise specified)
Note 5: CPD determines the no load pow er con su m pt ion, PD
CPD VCC2 f
ICCVCC, and the no load dynamic current consumption,
IS
CPD VCC f
ICC.
Symbol Parameter Conditions Typ Guaranteed Units
Limit
tPHL, tPLH Maximum Output CL
45 pF 16 20 ns
Propagation Delay
tPZL, tPZH Maximum Output CL
45 pF 29 40 ns
Enable T i me RL
1 k
:
tPLZ, tPHZ Maximum Output CL
5 pF 20 25 ns
Disable Time RL
1 k
:
Symbol Parameter Conditions TA
25
q
CT
A
40 to 85
q
CT
A
55 to 125
q
CUnits
Ty p Guar ant eed Lim i ts
tPHL, tPLH Maximum Output CL
50 pF 17 23 29 34 ns
Propagation Delay CL
150 pF 24 30 38 45 ns
tPZL Maximum Output RL
1 k
:
31 42 53 63 ns
Enable Time CL
50 pF
tPZH Maximum Output RL
1 k
:
23 33 41 49 ns
Enable Time CL
50 pF
tPHZ, tPLZ Maximum Output RL
1 k
:
21 30 38 45 ns
Disable Time CL
50 pF
tTHL, tTLH Maximum Output CL
50 pF 8 12 15 18 ns
Rise and Fall Time
CIN Maximum Input 10 15 15 15 pF
Capacitance
COUT Maximum Output/Input 20 25 25 25 pF
Capacitance
CPD Power Dissipation G
VCC (Note 5) 7 pF
Capacitance G
GND 100 pF
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MM74HCT245
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M20B
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MM74HCT245
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Small Outline Pack age (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
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MM74HCT245
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lea d Th in S hri nk Sm all Ou tlin e Pack age (TSSOP ), JED EC MO-1 53, 4.4mm Wide
Package Number MTC20
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MM74HCT245 Octal 3-STATE Transceiver
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N20A
Fairchild does no t assume any responsibility for use of any circui try described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life suppor t de vices o r systems a re devices or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical compon ent in any componen t of a life support
device or system whose failure to perform can be rea-
sonabl y ex pect ed to cause the fa ilu re of the li fe su pp ort
device or system, or to affect its safety or effectiveness.
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